diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst index 160e710d992f3a363d8f39314b0a04b9d658d07f..8267675ea95c4102bccbca904f5e4b07665c0513 100644 --- a/Documentation/core-api/printk-formats.rst +++ b/Documentation/core-api/printk-formats.rst @@ -567,6 +567,24 @@ For printing netdev_features_t. Passed by reference. +V4L2 and DRM FourCC code (pixel format) +--------------------------------------- + +:: + + %p4cc + +Print a FourCC code used by V4L2 or DRM, including format endianness and +its numerical value as hexadecimal. + +Passed by reference. + +Examples:: + + %p4cc BG12 little-endian (0x32314742) + %p4cc Y10 little-endian (0x20303159) + %p4cc NV12 big-endian (0xb231564e) + Thanks ====== diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index b3e9992525c2ae4f5a0c2ac306074857faa34997..907fb47cc84aa5e68b3dca9ea8382b678676b3f7 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -12,8 +12,8 @@ description: | and CEC. These DT bindings follow the Synopsys DWC HDMI TX bindings defined - in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with - the following device-specific properties. + in bridge/synopsys,dw-hdmi.yaml with the following device-specific + properties. maintainers: - Chen-Yu Tsai diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml index a1d5a32660e0d27dc8555efdb302a4240f1e39db..57324a5f0271e1b8ca371bd15a4fbfa9bf8c9f05 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml @@ -109,7 +109,7 @@ required: - resets - ddc -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml index c789784efe3062fcee91adcdd7b80d64b6418f10..ab48ab2f4240d58510267efc1061e6a02e8aad57 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml @@ -34,6 +34,15 @@ properties: description: used for reset chip control, RESET_N pin B7. maxItems: 1 + vdd10-supply: + description: Regulator that provides the supply 1.0V power. + + vdd18-supply: + description: Regulator that provides the supply 1.8V power. + + vdd33-supply: + description: Regulator that provides the supply 3.3V power. + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -55,6 +64,9 @@ properties: required: - compatible - reg + - vdd10-supply + - vdd18-supply + - vdd33-supply - ports additionalProperties: false @@ -72,6 +84,9 @@ examples: reg = <0x58>; enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&pp3300_mipibrdg>; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml new file mode 100644 index 0000000000000000000000000000000000000000..62c3bd4cb28d89f36d994fce9dd58292c68ec801 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge + +maintainers: + - Jagan Teki + +description: | + ICN6211 is MIPI-DSI to RGB Converter bridge from chipone. + + It has a flexible configuration of MIPI DSI signal input and + produce RGB565, RGB666, RGB888 output format. + +properties: + compatible: + enum: + - chipone,icn6211 + + reg: + maxItems: 1 + description: virtual channel number of a DSI peripheral + + enable-gpios: + description: Bridge EN pin, chip is reset when EN is low. + + vdd1-supply: + description: A 1.8V/2.5V/3.3V supply that power the MIPI RX. + + vdd2-supply: + description: A 1.8V/2.5V/3.3V supply that power the PLL. + + vdd3-supply: + description: A 1.8V/2.5V/3.3V supply that power the RGB output. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DSI input + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DPI output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + bridge@0 { + compatible = "chipone,icn6211"; + reg = <0>; + enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt deleted file mode 100644 index 33bf981fbe3348877d52da4301f96696f1c7927b..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Synopsys DesignWare HDMI TX Encoder -=================================== - -This document defines device tree properties for the Synopsys DesignWare HDMI -TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding -specification by itself but is meant to be referenced by platform-specific -device tree bindings. - -When referenced from platform device tree bindings the properties defined in -this document are defined as follows. The platform device tree bindings are -responsible for defining whether each property is required or optional. - -- reg: Memory mapped base address and length of the DWC HDMI TX registers. - -- reg-io-width: Width of the registers specified by the reg property. The - value is expressed in bytes and must be equal to 1 or 4 if specified. The - register width defaults to 1 if the property is not present. - -- interrupts: Reference to the DWC HDMI TX interrupt. - -- clocks: References to all the clocks specified in the clock-names property - as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt. - -- clock-names: The DWC HDMI TX uses the following clocks. - - - "iahb" is the bus clock for either AHB and APB (mandatory). - - "isfr" is the internal register configuration clock (mandatory). - - "cec" is the HDMI CEC controller main clock (optional). - -- ports: The connectivity of the DWC HDMI TX with the rest of the system is - expressed in using ports as specified in the device graph bindings defined - in Documentation/devicetree/bindings/graph.txt. The numbering of the ports - is platform-specific. diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml new file mode 100644 index 0000000000000000000000000000000000000000..735d0233a7d63f0d14a68d7dd43cd25b040d6b27 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lontium LT8912B MIPI to HDMI Bridge + +maintainers: + - Adrien Grassein + +description: | + The LT8912B is a bridge device which convert DSI to HDMI + +properties: + compatible: + enum: + - lontium,lt8912b + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: GPIO connected to active high RESET pin. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Primary MIPI port for MIPI input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: true + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + HDMI port, should be connected to a node compatible with the + hdmi-connector binding. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include + + i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48>; + reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_out_in: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt deleted file mode 100644 index 3f6072651182862f3c7e875d4de6ace495daac00..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +++ /dev/null @@ -1,88 +0,0 @@ -Renesas Gen3 DWC HDMI TX Encoder -================================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall contain one or more of - - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX - - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX - - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX - - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible - HDMI TX - - When compatible with generic versions, nodes must list the SoC-specific - version corresponding to the platform first, followed by the - family-specific version. - -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0 - corresponding to the video input of the controller and one port numbered 1 - corresponding to its HDMI output, and one port numbered 2 corresponding to - sound input of the controller. Each port shall have a single endpoint. - -Optional properties: - -- power-domains: Shall reference the power domain that contains the DWC HDMI, - if any. - - -Example: - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - rcar_dw_hdmi0_sound_in: endpoint { - remote-endpoint = <&hdmi_sound_out>; - }; - }; - }; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - label = "HDMI0 OUT"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0c9785c8db515a8ba37a6c99b8db47516ce40e33 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car DWC HDMI TX Encoder + +maintainers: + - Laurent Pinchart + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: synopsys,dw-hdmi.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX + - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX + - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX + - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX + - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX + - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX + - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX + - const: renesas,rcar-gen3-hdmi + + reg-io-width: + const: 1 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Sound input port + + required: + - port@0 + - port@1 + - port@2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + hdmi@fead0000 { + compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; + reg = <0xfead0000 0x10000>; + interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + port@2 { + reg = <2>; + rcar_dw_hdmi0_sound_in: endpoint { + remote-endpoint = <&hdmi_sound_out>; + }; + }; + }; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + label = "HDMI0 OUT"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9be44a682e67aaea7d3ca46f92f7fca89ae62ca0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Synopsys DesignWare HDMI TX Controller + +maintainers: + - Laurent Pinchart + +description: | + This document defines device tree properties for the Synopsys DesignWare HDMI + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree + binding specification by itself but is meant to be referenced by device tree + bindings for the platform-specific integrations of the DWC HDMI TX. + + When referenced from platform device tree bindings the properties defined in + this document are defined as follows. The platform device tree bindings are + responsible for defining whether each property is required or optional. + +properties: + reg: + maxItems: 1 + + reg-io-width: + description: + Width (in bytes) of the registers specified by the reg property. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 4] + default: 1 + + clocks: + minItems: 2 + maxItems: 5 + items: + - description: The bus clock for either AHB and APB + - description: The internal register configuration clock + additionalItems: true + + clock-names: + minItems: 2 + maxItems: 5 + items: + - const: iahb + - const: isfr + additionalItems: true + + interrupts: + maxItems: 1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a4c3064c778cd5aaae48b06effbe4b443245fd87 --- /dev/null +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/fsl,lcdif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX LCD Interface (LCDIF) + +maintainers: + - Marek Vasut + - Stefan Agner + +description: | + (e)LCDIF display controller found in the Freescale/NXP i.MX SoCs. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx23-lcdif + - fsl,imx28-lcdif + - fsl,imx6sx-lcdif + - items: + - enum: + - fsl,imx6sl-lcdif + - fsl,imx6sll-lcdif + - fsl,imx6ul-lcdif + - fsl,imx7d-lcdif + - fsl,imx8mm-lcdif + - fsl,imx8mq-lcdif + - const: fsl,imx6sx-lcdif + + reg: + maxItems: 1 + + clocks: + items: + - description: Pixel clock + - description: Bus clock + - description: Display AXI clock + minItems: 1 + + clock-names: + items: + - const: pix + - const: axi + - const: disp_axi + minItems: 1 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: The LCDIF output port + +required: + - compatible + - reg + - clocks + - interrupts + - port + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-lcdif + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + maxItems: 3 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +examples: + - | + #include + #include + + display-controller@2220000 { + compatible = "fsl,imx6sx-lcdif"; + reg = <0x02220000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + + port { + endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..af7fe9c4d1963b6cd3789236c4cfe1c2ef4b09ca --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 DWC HDMI TX Encoder + +maintainers: + - Philipp Zabel + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx6dl-hdmi + - fsl,imx6q-hdmi + + reg-io-width: + const: 1 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The HDMI DDC bus can be connected to either a system I2C master or the + functionally-reduced I2C master contained in the DWC HDMI. When connected + to a system I2C master this property contains a phandle to that I2C + master controller. + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the iomuxc-gpr region containing the HDMI multiplexer control + register. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + This device has four video ports, corresponding to the four inputs of the + HDMI multiplexer. Each port shall have a single endpoint. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: First input of the HDMI multiplexer + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Second input of the HDMI multiplexer + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Third input of the HDMI multiplexer + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Fourth input of the HDMI multiplexer + + anyOf: + - required: + - port@0 + - required: + - port@1 + - required: + - port@2 + - required: + - port@3 + +required: + - compatible + - reg + - clocks + - clock-names + - gpr + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + + hdmi: hdmi@120000 { + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HDMI_ISFR>; + clock-names = "iahb", "isfr"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_hdmi>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt deleted file mode 100644 index 6d021e71c9cf1d745a04e068a4f90b8b117d3921..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale i.MX6 DWC HDMI TX Encoder -=================================== - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi". -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports, - numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer. - Each port shall have a single endpoint. -- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI - multiplexer control register. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. - - -Example: - - gpr: iomuxc-gpr@20e0000 { - /* ... */ - }; - - hdmi: hdmi@120000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-hdmi"; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks 123>, <&clks 124>; - clock-names = "iahb", "isfr"; - ddc-i2c-bus = <&i2c2>; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6cdb734c91a936f7fcb65f8988cbc511650ef313..dd2896a40ff080bcb708a7957f4d1c601a27dff3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi + - mediatek,mt8192-dpi reg: maxItems: 1 @@ -50,15 +51,10 @@ properties: - const: sleep port: - type: object + $ref: /schemas/graph.yaml#/properties/port description: - Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached HDMI or LVDS encoder chip. - - properties: - endpoint: - type: object + Output port node. This port should be connected to the input port of an + attached HDMI or LVDS encoder chip. required: - compatible diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt deleted file mode 100644 index c985871c46b372cec4a8e2bf3c969dfca601dad4..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ /dev/null @@ -1,87 +0,0 @@ -* Freescale MXS LCD Interface (LCDIF) - -New bindings: -============= -Required properties: -- compatible: Should be "fsl,imx23-lcdif" for i.MX23. - Should be "fsl,imx28-lcdif" for i.MX28. - Should be "fsl,imx6sx-lcdif" for i.MX6SX. - Should be "fsl,imx8mq-lcdif" for i.MX8MQ. -- reg: Address and length of the register set for LCDIF -- interrupts: Should contain LCDIF interrupt -- clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. -- clock-names: A list of clock names. For MXSFB it should contain: - - "pix" for the LCDIF block clock - - (MX6SX-only) "axi", "disp_axi" for the bus interface clock - -Required sub-nodes: - - port: The connection to an encoder chip. - -Example: - - lcdif1: display-controller@2220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02220000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - - port { - parallel_out: endpoint { - remote-endpoint = <&panel_in_parallel>; - }; - }; - }; - -Deprecated bindings: -==================== -Required properties: -- compatible: Should be "fsl,imx23-lcdif" for i.MX23. - Should be "fsl,imx28-lcdif" for i.MX28. -- reg: Address and length of the register set for LCDIF -- interrupts: Should contain LCDIF interrupts -- display: phandle to display node (see below for details) - -* display node - -Required properties: -- bits-per-pixel: <16> for RGB565, <32> for RGB888/666. -- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>. - -Required sub-node: -- display-timings: Refer to binding doc display-timing.txt for details. - -Examples: - -lcdif@80030000 { - compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 2000>; - interrupts = <38 86>; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <164>; - hback-porch = <89>; - hsync-len = <10>; - vback-porch = <23>; - vfront-porch = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 62b0d54d87b7f0e2c6c32c3cd7320da1640a9bad..b3797ba2698b1b30c6cc7f41dff3f27fbdfd5ee8 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -161,6 +161,8 @@ properties: # Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel - innolux,g121x1-l03 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel + - innolux,n116bca-ea1 + # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel - innolux,n116bge # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel - innolux,n125hce-gn1 diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt deleted file mode 100644 index 7d65c24fcda87cd493e1227f67da5971ca6bc65f..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ /dev/null @@ -1,145 +0,0 @@ -* Renesas R-Car Display Unit (DU) - -Required Properties: - - - compatible: must be one of the following. - - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU - - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU - - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU - - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU - - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU - - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU - - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU - - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU - - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU - - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU - - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU - - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU - - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU - - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU - - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU - - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU - - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU - - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU - - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU - - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU - - - reg: the memory-mapped I/O registers base address and length - - - interrupts: Interrupt specifiers for the DU interrupts. - - - clocks: A list of phandles + clock-specifier pairs, one for each entry in - the clock-names property. - - clock-names: Name of the clocks. This property is model-dependent. - - R8A7779 uses a single functional clock. The clock doesn't need to be - named. - - All other DU instances use one functional clock per channel The - functional clocks must be named "du.x" with "x" being the channel - numerical index. - - In addition to the functional clocks, all DU versions also support - externally supplied pixel clocks. Those clocks are optional. When - supplied they must be named "dclkin.x" with "x" being the input clock - numerical index. - - - renesas,cmms: A list of phandles to the CMM instances present in the SoC, - one for each available DU channel. The property shall not be specified for - SoCs that do not provide any CMM (such as V3M and V3H). - - - renesas,vsps: A list of phandle and channel index tuples to the VSPs that - handle the memory interfaces for the DU channels. The phandle identifies the - VSP instance that serves the DU channel, and the channel index identifies - the LIF instance in that VSP. - -Optional properties: - - resets: A list of phandle + reset-specifier pairs, one for each entry in - the reset-names property. - - reset-names: Names of the resets. This property is model-dependent. - - All but R8A7779 use one reset for a group of one or more successive - channels. The resets must be named "du.x" with "x" being the numerical - index of the lowest channel in the group. - -Required nodes: - -The connections to the DU output video ports are modeled using the OF graph -bindings specified in Documentation/devicetree/bindings/graph.txt. - -The following table lists for each supported model the port number -corresponding to each DU output. - - Port0 Port1 Port2 Port3 ------------------------------------------------------------------------------ - R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 - - R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - - R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - - R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - - R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - - R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - - R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - - R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 - - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - - R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - - R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - - R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - - R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - - R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 - R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - - R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 - - R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - - R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - - R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - - R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - - R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - - - -Example: R8A7795 (R-Car H3) ES2.0 DU - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml new file mode 100644 index 0000000000000000000000000000000000000000..552a99ce4f1280d757f75eb1657b3424ddc4ad1f --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -0,0 +1,831 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Display Unit (DU) + +maintainers: + - Laurent Pinchart + +description: | + These DT bindings describe the Display Unit embedded in the Renesas R-Car + Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs. + +properties: + compatible: + enum: + - renesas,du-r8a7742 # for RZ/G1H compatible DU + - renesas,du-r8a7743 # for RZ/G1M compatible DU + - renesas,du-r8a7744 # for RZ/G1N compatible DU + - renesas,du-r8a7745 # for RZ/G1E compatible DU + - renesas,du-r8a77470 # for RZ/G1C compatible DU + - renesas,du-r8a774a1 # for RZ/G2M compatible DU + - renesas,du-r8a774b1 # for RZ/G2N compatible DU + - renesas,du-r8a774c0 # for RZ/G2E compatible DU + - renesas,du-r8a774e1 # for RZ/G2H compatible DU + - renesas,du-r8a7779 # for R-Car H1 compatible DU + - renesas,du-r8a7790 # for R-Car H2 compatible DU + - renesas,du-r8a7791 # for R-Car M2-W compatible DU + - renesas,du-r8a7792 # for R-Car V2H compatible DU + - renesas,du-r8a7793 # for R-Car M2-N compatible DU + - renesas,du-r8a7794 # for R-Car E2 compatible DU + - renesas,du-r8a7795 # for R-Car H3 compatible DU + - renesas,du-r8a7796 # for R-Car M3-W compatible DU + - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU + - renesas,du-r8a77965 # for R-Car M3-N compatible DU + - renesas,du-r8a77970 # for R-Car V3M compatible DU + - renesas,du-r8a77980 # for R-Car V3H compatible DU + - renesas,du-r8a77990 # for R-Car E3 compatible DU + - renesas,du-r8a77995 # for R-Car D3 compatible DU + + reg: + maxItems: 1 + + # See compatible-specific constraints below. + clocks: true + clock-names: true + interrupts: + description: Interrupt specifiers, one per DU channel + resets: true + reset-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/port + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings specified in Documentation/devicetree/bindings/graph.txt. + The number of ports and their assignment are model-dependent. Each port + shall have a single endpoint. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + - port@1 + + unevaluatedProperties: false + + renesas,cmms: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of phandles to the CMM instances present in the SoC, one for each + available DU channel. + + renesas,vsps: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. The phandle identifies the VSP + instance that serves the DU channel, and the channel index identifies + the LIF instance in that VSP. + +required: + - compatible + - reg + - clocks + - interrupts + - resets + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,du-r8a7779 + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + items: + - description: Functional clock + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 1 + maxItems: 3 + items: + - const: du.0 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7743 + - renesas,du-r8a7744 + - renesas,du-r8a7791 + - renesas,du-r8a7793 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7745 + - renesas,du-r8a7792 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7794 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a77470 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + port@2: + description: LVDS 0 + # port@3 is DVENC, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7742 + - renesas,du-r8a7790 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: + description: LVDS 1 + # port@3 is TCON, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7795 + then: + properties: + clocks: + minItems: 4 + maxItems: 8 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: Functional clock for DU4 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + - description: DU_DOTCLKIN3 input clock + + clock-names: + minItems: 4 + maxItems: 8 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - const: du.3 + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + + interrupts: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.2 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: HDMI 1 + port@3: + description: LVDS 0 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + + renesas,cmms: + minItems: 4 + + renesas,vsps: + minItems: 4 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774a1 + - renesas,du-r8a7796 + - renesas,du-r8a77961 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.2 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: LVDS 0 + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 3 + + renesas,vsps: + minItems: 3 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774b1 + - renesas,du-r8a774e1 + - renesas,du-r8a77965 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU3 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN3 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.3 + - pattern: '^dclkin\.[013]$' + - pattern: '^dclkin\.[013]$' + - pattern: '^dclkin\.[013]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.3 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: LVDS 0 + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 3 + + renesas,vsps: + minItems: 3 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a77970 + - renesas,du-r8a77980 + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Functional clock for DU0 + - description: DU_DOTCLKIN0 input clock + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: du.0 + - const: dclkin.0 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + renesas,vsps: + minItems: 1 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774c0 + - renesas,du-r8a77990 + - renesas,du-r8a77995 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: + description: LVDS 1 + # port@3 is TCON, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 2 + + renesas,vsps: + minItems: 2 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + +additionalProperties: false + +examples: + # R-Car H3 ES2.0 DU + - | + #include + #include + + display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0xfeb00000 0x80000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.2", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; + + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dw_hdmi1_in>; + }; + }; + port@3 { + reg = <3>; + endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt deleted file mode 100644 index 3d32ce137e7f40883426e1b9a3e3db29eddd2527..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip DWC HDMI TX Encoder -============================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible: should be one of the following: - "rockchip,rk3228-dw-hdmi" - "rockchip,rk3288-dw-hdmi" - "rockchip,rk3328-dw-hdmi" - "rockchip,rk3399-dw-hdmi" -- reg: See dw_hdmi.txt. -- reg-io-width: See dw_hdmi.txt. Shall be 4. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 - corresponding to the video input of the controller. The port shall have two - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. -- clock-names: May contain "cec" as defined in dw_hdmi.txt. -- clock-names: May contain "grf", power for grf io. -- clock-names: May contain "vpll", external clock for some hdmi phy. -- phys: from general PHY binding: the phandle for the PHY device. -- phy-names: Should be "hdmi" if phys references an external phy. - -Optional pinctrl entry: -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi - will switch to the unwedge pinctrl state for 10ms if it ever gets an - i2c timeout. It's intended that this unwedge pinctrl entry will - cause the SDA line to be driven low to work around a hardware - errata. - -Example: - -hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..75cd9c686e98514b9cbd1dac834cd44e27265e27 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DWC HDMI TX Encoder + +maintainers: + - Mark Yao + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - rockchip,rk3228-dw-hdmi + - rockchip,rk3288-dw-hdmi + - rockchip,rk3328-dw-hdmi + - rockchip,rk3399-dw-hdmi + + reg-io-width: + const: 4 + + clocks: + minItems: 2 + maxItems: 5 + items: + - {} + - {} + # The next three clocks are all optional, but shall be specified in this + # order when present. + - description: The HDMI CEC controller main clock + - description: Power for GRF IO + - description: External clock for some HDMI PHY + + clock-names: + minItems: 2 + maxItems: 5 + items: + - {} + - {} + - enum: + - cec + - grf + - vpll + - enum: + - grf + - vpll + - const: vpll + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The HDMI DDC bus can be connected to either a system I2C master or the + functionally-reduced I2C master contained in the DWC HDMI. When connected + to a system I2C master this property contains a phandle to that I2C + master controller. + + phys: + maxItems: 1 + description: The HDMI PHY + + phy-names: + const: hdmi + + pinctrl-names: + description: + The unwedge pinctrl entry shall drive the DDC SDA line low. This is + intended to work around a hardware errata that can cause the DDC I2C + bus to be wedged. + items: + - const: default + - const: unwedge + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input of the DWC HDMI TX + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPB + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPL + + required: + - endpoint@0 + - endpoint@1 + + required: + - port + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the GRF to mux vopl/vopb. + +required: + - compatible + - reg + - reg-io-width + - clocks + - clock-names + - interrupts + - ports + - rockchip,grf + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "iahb", "isfr"; + + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.yaml index 0a046be8d1cdae5fd7689c7d6d8c2796c7e215fd..0358a7739c8e273b6ab8e95bb9b410df6aff2380 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.yaml @@ -23,6 +23,7 @@ properties: - enum: - ingenic,jz4775-intc - ingenic,jz4770-intc + - ingenic,jz4760b-intc - const: ingenic,jz4760-intc - items: - const: ingenic,x1000-intc diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index a2133d69872c658a8aa2bf216cc1a8fcbc3e68a4..7f37ec30d9fd721404b5db65d249a98a6ef6aaf9 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -257,3 +257,79 @@ fences in the kernel. This means: userspace is allowed to use userspace fencing or long running compute workloads. This also means no implicit fencing for shared buffers in these cases. + +Recoverable Hardware Page Faults Implications +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Modern hardware supports recoverable page faults, which has a lot of +implications for DMA fences. + +First, a pending page fault obviously holds up the work that's running on the +accelerator and a memory allocation is usually required to resolve the fault. +But memory allocations are not allowed to gate completion of DMA fences, which +means any workload using recoverable page faults cannot use DMA fences for +synchronization. Synchronization fences controlled by userspace must be used +instead. + +On GPUs this poses a problem, because current desktop compositor protocols on +Linux rely on DMA fences, which means without an entirely new userspace stack +built on top of userspace fences, they cannot benefit from recoverable page +faults. Specifically this means implicit synchronization will not be possible. +The exception is when page faults are only used as migration hints and never to +on-demand fill a memory request. For now this means recoverable page +faults on GPUs are limited to pure compute workloads. + +Furthermore GPUs usually have shared resources between the 3D rendering and +compute side, like compute units or command submission engines. If both a 3D +job with a DMA fence and a compute workload using recoverable page faults are +pending they could deadlock: + +- The 3D workload might need to wait for the compute job to finish and release + hardware resources first. + +- The compute workload might be stuck in a page fault, because the memory + allocation is waiting for the DMA fence of the 3D workload to complete. + +There are a few options to prevent this problem, one of which drivers need to +ensure: + +- Compute workloads can always be preempted, even when a page fault is pending + and not yet repaired. Not all hardware supports this. + +- DMA fence workloads and workloads which need page fault handling have + independent hardware resources to guarantee forward progress. This could be + achieved through e.g. through dedicated engines and minimal compute unit + reservations for DMA fence workloads. + +- The reservation approach could be further refined by only reserving the + hardware resources for DMA fence workloads when they are in-flight. This must + cover the time from when the DMA fence is visible to other threads up to + moment when fence is completed through dma_fence_signal(). + +- As a last resort, if the hardware provides no useful reservation mechanics, + all workloads must be flushed from the GPU when switching between jobs + requiring DMA fences or jobs requiring page fault handling: This means all DMA + fences must complete before a compute job with page fault handling can be + inserted into the scheduler queue. And vice versa, before a DMA fence can be + made visible anywhere in the system, all compute workloads must be preempted + to guarantee all pending GPU page faults are flushed. + +- Only a fairly theoretical option would be to untangle these dependencies when + allocating memory to repair hardware page faults, either through separate + memory blocks or runtime tracking of the full dependency graph of all DMA + fences. This results very wide impact on the kernel, since resolving the page + on the CPU side can itself involve a page fault. It is much more feasible and + robust to limit the impact of handling hardware page faults to the specific + driver. + +Note that workloads that run on independent hardware like copy engines or other +GPUs do not have any impact. This allows us to keep using DMA fences internally +in the kernel even for resolving hardware page faults, e.g. by using copy +engines to clear or copy memory needed to resolve the page fault. + +In some ways this page fault problem is a special case of the `Infinite DMA +Fences` discussions: Infinite fences from compute workloads are allowed to +depend on DMA fences, but not the other way around. And not even the page fault +problem is new, because some other CPU thread in userspace might +hit a page fault which holds up a userspace fence - supporting page faults on +GPUs doesn't anything fundamentally new. diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index b89ddd06dabb2498aa5074616ec660ac2626f46f..389892f361850b193c606a76474cd4116cc7591c 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -80,6 +80,18 @@ Atomic State Helper Reference .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c :export: +GEM Atomic Helper Reference +--------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c + :doc: overview + +.. kernel-doc:: include/drm/drm_gem_atomic_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c + :export: + Simple KMS Helper Reference =========================== diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst index c9a51e3bfb5a596c3b449f3528cea98152a170eb..ec4bc72438e4ab72312cc101e6e5cff04779991a 100644 --- a/Documentation/gpu/index.rst +++ b/Documentation/gpu/index.rst @@ -16,6 +16,7 @@ Linux GPU Driver Developer's Guide vga-switcheroo vgaarbiter todo + rfc/index .. only:: subproject and html diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..a8621f7dab8bd8156a080dd884f7231776e1109c --- /dev/null +++ b/Documentation/gpu/rfc/index.rst @@ -0,0 +1,17 @@ +=============== +GPU RFC Section +=============== + +For complex work, especially new uapi, it is often good to nail the high level +design issues before getting lost in the code details. This section is meant to +host such documentation: + +* Each RFC should be a section in this file, explaining the goal and main design + considerations. Especially for uapi make sure you Cc: all relevant project + mailing lists and involved people outside of dri-devel. + +* For uapi structures add a file to this directory with and then pull the + kerneldoc in like with real uapi headers. + +* Once the code has landed move all the documentation to the right places in + the main core, helper or driver sections. diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 40ccac61137e27f936128d037e1fe4c52dc721fd..7ff9fac10d8b3d09144563252641a78231951efa 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -459,52 +459,6 @@ Contact: Emil Velikov, respective driver maintainers Level: Intermediate -Plumb drm_atomic_state all over -------------------------------- - -Currently various atomic functions take just a single or a handful of -object states (eg. plane state). While that single object state can -suffice for some simple cases, we often have to dig out additional -object states for dealing with various dependencies between the individual -objects or the hardware they represent. The process of digging out the -additional states is rather non-intuitive and error prone. - -To fix that most functions should rather take the overall -drm_atomic_state as one of their parameters. The other parameters -would generally be the object(s) we mainly want to interact with. - -For example, instead of - -.. code-block:: c - - int (*atomic_check)(struct drm_plane *plane, struct drm_plane_state *state); - -we would have something like - -.. code-block:: c - - int (*atomic_check)(struct drm_plane *plane, struct drm_atomic_state *state); - -The implementation can then trivially gain access to any required object -state(s) via drm_atomic_get_plane_state(), drm_atomic_get_new_plane_state(), -drm_atomic_get_old_plane_state(), and their equivalents for -other object types. - -Additionally many drivers currently access the object->state pointer -directly in their commit functions. That is not going to work if we -eg. want to allow deeper commit pipelines as those pointers could -then point to the states corresponding to a future commit instead of -the current commit we're trying to process. Also non-blocking commits -execute locklessly so there are serious concerns with dereferencing -the object->state pointers without holding the locks that protect them. -Use of drm_atomic_get_new_plane_state(), drm_atomic_get_old_plane_state(), -etc. avoids these problems as well since they relate to a specific -commit via the passed in drm_atomic_state. - -Contact: Ville Syrjälä, Daniel Vetter - -Level: Intermediate - Use struct dma_buf_map throughout codebase ------------------------------------------ @@ -596,23 +550,48 @@ Contact: Daniel Vetter Level: Intermediate -KMS cleanups ------------- +Object lifetime fixes +--------------------- + +There's two related issues here -Some of these date from the very introduction of KMS in 2008 ... +- Cleanup up the various ->destroy callbacks, which often are all the same + simple code. -- Make ->funcs and ->helper_private vtables optional. There's a bunch of empty - function tables in drivers, but before we can remove them we need to make sure - that all the users in helpers and drivers do correctly check for a NULL - vtable. +- Lots of drivers erroneously allocate DRM modeset objects using devm_kzalloc, + which results in use-after free issues on driver unload. This can be serious + trouble even for drivers for hardware integrated on the SoC due to + EPROBE_DEFERRED backoff. -- Cleanup up the various ->destroy callbacks. A lot of them just wrapt the - drm_*_cleanup implementations and can be removed. Some tack a kfree() at the - end, for which we could add drm_*_cleanup_kfree(). And then there's the (for - historical reasons) misnamed drm_primary_helper_destroy() function. +Both these problems can be solved by switching over to drmm_kzalloc(), and the +various convenience wrappers provided, e.g. drmm_crtc_alloc_with_planes(), +drmm_universal_plane_alloc(), ... and so on. + +Contact: Daniel Vetter Level: Intermediate +Remove automatic page mapping from dma-buf importing +---------------------------------------------------- + +When importing dma-bufs, the dma-buf and PRIME frameworks automatically map +imported pages into the importer's DMA area. drm_gem_prime_fd_to_handle() and +drm_gem_prime_handle_to_fd() require that importers call dma_buf_attach() +even if they never do actual device DMA, but only CPU access through +dma_buf_vmap(). This is a problem for USB devices, which do not support DMA +operations. + +To fix the issue, automatic page mappings should be removed from the +buffer-sharing code. Fixing this is a bit more involved, since the import/export +cache is also tied to &drm_gem_object.import_attach. Meanwhile we paper over +this problem for USB devices by fishing out the USB host controller device, as +long as that supports DMA. Otherwise importing can still needlessly fail. + +Contact: Thomas Zimmermann , Daniel Vetter + +Level: Advanced + + Better Testing ============== @@ -645,8 +624,6 @@ See the documentation of :ref:`VKMS ` for more details. This is an ideal internship task, since it only requires a virtual machine and can be sized to fit the available time. -Contact: Daniel Vetter - Level: See details Backlight Refactoring @@ -700,7 +677,7 @@ Outside DRM Convert fbdev drivers to DRM ---------------------------- -There are plenty of fbdev drivers for older hardware. Some hwardware has +There are plenty of fbdev drivers for older hardware. Some hardware has become obsolete, but some still provides good(-enough) framebuffers. The drivers that are still useful should be converted to DRM and afterwards removed from fbdev. diff --git a/Documentation/networking/bonding.rst b/Documentation/networking/bonding.rst index 5f690f0ad0e4f136b29da05e4475af0830eabf4f..62f2aab8eaec0b65a7c4be0178241a74562bd93f 100644 --- a/Documentation/networking/bonding.rst +++ b/Documentation/networking/bonding.rst @@ -1988,7 +1988,7 @@ netif_carrier. If use_carrier is 0, then the MII monitor will first query the device's (via ioctl) MII registers and check the link state. If that request fails (not just that it returns carrier down), then the MII -monitor will make an ethtool ETHOOL_GLINK request to attempt to obtain +monitor will make an ethtool ETHTOOL_GLINK request to attempt to obtain the same information. If both methods fail (i.e., the driver either does not support or had some error in processing both the MII register and ethtool requests), then the MII monitor will assume the link is diff --git a/Documentation/networking/netdev-FAQ.rst b/Documentation/networking/netdev-FAQ.rst index a64c01b52b4c55286632a05b1578c4b6b833d8be..91b2cf7128012826ea3cddf526b8aafbd7955abf 100644 --- a/Documentation/networking/netdev-FAQ.rst +++ b/Documentation/networking/netdev-FAQ.rst @@ -142,73 +142,13 @@ Please send incremental versions on top of what has been merged in order to fix the patches the way they would look like if your latest patch series was to be merged. -How can I tell what patches are queued up for backporting to the various stable releases? ------------------------------------------------------------------------------------------ -Normally Greg Kroah-Hartman collects stable commits himself, but for -networking, Dave collects up patches he deems critical for the -networking subsystem, and then hands them off to Greg. - -There is a patchworks queue that you can see here: - - https://patchwork.kernel.org/bundle/netdev/stable/?state=* - -It contains the patches which Dave has selected, but not yet handed off -to Greg. If Greg already has the patch, then it will be here: - - https://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git - -A quick way to find whether the patch is in this stable-queue is to -simply clone the repo, and then git grep the mainline commit ID, e.g. -:: - - stable-queue$ git grep -l 284041ef21fdf2e - releases/3.0.84/ipv6-fix-possible-crashes-in-ip6_cork_release.patch - releases/3.4.51/ipv6-fix-possible-crashes-in-ip6_cork_release.patch - releases/3.9.8/ipv6-fix-possible-crashes-in-ip6_cork_release.patch - stable/stable-queue$ - -I see a network patch and I think it should be backported to stable. Should I request it via stable@vger.kernel.org like the references in the kernel's Documentation/process/stable-kernel-rules.rst file say? ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -No, not for networking. Check the stable queues as per above first -to see if it is already queued. If not, then send a mail to netdev, -listing the upstream commit ID and why you think it should be a stable -candidate. - -Before you jump to go do the above, do note that the normal stable rules -in :ref:`Documentation/process/stable-kernel-rules.rst ` -still apply. So you need to explicitly indicate why it is a critical -fix and exactly what users are impacted. In addition, you need to -convince yourself that you *really* think it has been overlooked, -vs. having been considered and rejected. - -Generally speaking, the longer it has had a chance to "soak" in -mainline, the better the odds that it is an OK candidate for stable. So -scrambling to request a commit be added the day after it appears should -be avoided. - -I have created a network patch and I think it should be backported to stable. Should I add a Cc: stable@vger.kernel.org like the references in the kernel's Documentation/ directory say? ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -No. See above answer. In short, if you think it really belongs in -stable, then ensure you write a decent commit log that describes who -gets impacted by the bug fix and how it manifests itself, and when the -bug was introduced. If you do that properly, then the commit will get -handled appropriately and most likely get put in the patchworks stable -queue if it really warrants it. - -If you think there is some valid information relating to it being in -stable that does *not* belong in the commit log, then use the three dash -marker line as described in -:ref:`Documentation/process/submitting-patches.rst ` -to temporarily embed that information into the patch that you send. - -Are all networking bug fixes backported to all stable releases? +Are there special rules regarding stable submissions on netdev? --------------------------------------------------------------- -Due to capacity, Dave could only take care of the backports for the -last two stable releases. For earlier stable releases, each stable -branch maintainer is supposed to take care of them. If you find any -patch is missing from an earlier stable branch, please notify -stable@vger.kernel.org with either a commit ID or a formal patch -backported, and CC Dave and other relevant networking developers. +While it used to be the case that netdev submissions were not supposed +to carry explicit ``CC: stable@vger.kernel.org`` tags that is no longer +the case today. Please follow the standard stable rules in +:ref:`Documentation/process/stable-kernel-rules.rst `, +and make sure you include appropriate Fixes tags! Is the comment style convention different for the networking content? --------------------------------------------------------------------- diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index 3973556250e17050a32309edd7b225554c81e394..003c865e9c212342ecac53c42eddd6848077de4f 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -35,12 +35,6 @@ Rules on what kind of patches are accepted, and which ones are not, into the Procedure for submitting patches to the -stable tree ---------------------------------------------------- - - If the patch covers files in net/ or drivers/net please follow netdev stable - submission guidelines as described in - :ref:`Documentation/networking/netdev-FAQ.rst ` - after first checking the stable networking queue at - https://patchwork.kernel.org/bundle/netdev/stable/?state=* - to ensure the requested patch is not already queued up. - Security patches should not be handled (solely) by the -stable review process but should follow the procedures in :ref:`Documentation/admin-guide/security-bugs.rst `. diff --git a/Documentation/process/submitting-patches.rst b/Documentation/process/submitting-patches.rst index 8c991c8636280e47fc80be27f08479b3e13f5b56..91de63b201c126ed19551cb2a35c9c29f9d55fe4 100644 --- a/Documentation/process/submitting-patches.rst +++ b/Documentation/process/submitting-patches.rst @@ -250,11 +250,6 @@ should also read :ref:`Documentation/process/stable-kernel-rules.rst ` in addition to this file. -Note, however, that some subsystem maintainers want to come to their own -conclusions on which patches should go to the stable trees. The networking -maintainer, in particular, would rather not see individual developers -adding lines like the above to their patches. - If changes affect userland-kernel interfaces, please send the MAN-PAGES maintainer (as listed in the MAINTAINERS file) a man-pages patch, or at least a notification of the change, so that some information makes its way diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 1a2b5210cdbf58508c047a5b64d908a3da0e1d99..38e327d4b479037e0dfcd9ace47ea59b6c50cb22 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -182,6 +182,9 @@ is dependent on the CPU capability and the kernel configuration. The limit can be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the KVM_CHECK_EXTENSION ioctl() at run-time. +Creation of the VM will fail if the requested IPA size (whether it is +implicit or explicit) is unsupported on the host. + Please note that configuring the IPA size does not affect the capability exposed by the guest CPUs in ID_AA64MMFR0_EL1[PARange]. It only affects size of the address translated by the stage2 level (guest physical to diff --git a/MAINTAINERS b/MAINTAINERS index d92f85ca831d30d658fef768575ba538be4d4b93..2086492e262b5a2f256f8954c8e697cc2dd2aaf3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -261,8 +261,8 @@ ABI/API L: linux-api@vger.kernel.org F: include/linux/syscalls.h F: kernel/sys_ni.c -F: include/uapi/ -F: arch/*/include/uapi/ +X: include/uapi/ +X: arch/*/include/uapi/ ABIT UGURU 1,2 HARDWARE MONITOR DRIVER M: Hans de Goede @@ -1323,7 +1323,7 @@ ARC PGU DRM DRIVER M: Alexey Brodkin S: Supported F: Documentation/devicetree/bindings/display/snps,arcpgu.txt -F: drivers/gpu/drm/arc/ +F: drivers/gpu/drm/tiny/arcpgu.c ARCNET NETWORK LAYER M: Michael Grzeschik @@ -5568,6 +5568,12 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml F: drivers/gpu/drm/panel/panel-boe-himax8279d.c +DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE +M: Jagan Teki +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml +F: drivers/gpu/drm/bridge/chipone-icn6211.c + DRM DRIVER FOR FARADAY TVE200 TV ENCODER M: Linus Walleij S: Maintained @@ -5586,6 +5592,14 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c +DRM DRIVER FOR GENERIC USB DISPLAY +M: Noralf Trønnes +S: Maintained +W: https://github.com/notro/gud/wiki +T: git git://anongit.freedesktop.org/drm/drm-misc +F: drivers/gpu/drm/gud/ +F: include/drm/gud.h + DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS M: Hans de Goede S: Maintained @@ -5835,7 +5849,7 @@ M: David Airlie M: Daniel Vetter L: dri-devel@lists.freedesktop.org S: Maintained -B: https://bugs.freedesktop.org/ +B: https://gitlab.freedesktop.org/drm C: irc://chat.freenode.net/dri-devel T: git git://anongit.freedesktop.org/drm/drm F: Documentation/devicetree/bindings/display/ @@ -5894,6 +5908,7 @@ F: drivers/gpu/drm/atmel-hlcdc/ DRM DRIVERS FOR BRIDGE CHIPS M: Andrzej Hajda M: Neil Armstrong +M: Robert Foss R: Laurent Pinchart R: Jonas Karlman R: Jernej Skrabec @@ -5963,6 +5978,7 @@ DRM DRIVERS FOR MEDIATEK M: Chun-Kuang Hu M: Philipp Zabel L: dri-devel@lists.freedesktop.org +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ @@ -5988,9 +6004,9 @@ L: dri-devel@lists.freedesktop.org L: linux-renesas-soc@vger.kernel.org S: Supported T: git git://linuxtv.org/pinchartl/media drm/du/next -F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml -F: Documentation/devicetree/bindings/display/renesas,du.txt +F: Documentation/devicetree/bindings/display/renesas,du.yaml F: drivers/gpu/drm/rcar-du/ F: drivers/gpu/drm/shmobile/ F: include/linux/platform_data/shmob_drm.h @@ -10460,6 +10476,12 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git F: drivers/hid/hid-lg-g15.c +LONTIUM LT8912B MIPI TO HDMI BRIDGE +M: Adrien Grassein +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml +F: drivers/gpu/drm/bridge/lontium-lt8912b.c + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Sreekanth Reddy @@ -10716,7 +10738,8 @@ F: drivers/net/ethernet/marvell/mvpp2/ MARVELL MWIFIEX WIRELESS DRIVER M: Amitkumar Karwar -M: Ganapathi Bhat +M: Ganapathi Bhat +M: Sharvari Harisangam M: Xinming Hu L: linux-wireless@vger.kernel.org S: Maintained @@ -12266,7 +12289,7 @@ M: Stefan Agner L: dri-devel@lists.freedesktop.org S: Supported T: git git://anongit.freedesktop.org/drm/drm-misc -F: Documentation/devicetree/bindings/display/mxsfb.txt +F: Documentation/devicetree/bindings/display/fsl,lcdif.yaml F: drivers/gpu/drm/mxsfb/ MYLEX DAC960 PCI RAID Controller @@ -19165,7 +19188,7 @@ S: Maintained F: drivers/infiniband/hw/vmw_pvrdma/ VMware PVSCSI driver -M: Jim Gill +M: Vishal Bhakta M: VMware PV-Drivers L: linux-scsi@vger.kernel.org S: Maintained diff --git a/Makefile b/Makefile index 31dcdb3d61fa5a32514ef3281efb4524439f9e07..a28bb374663d2cb0ae7f462370bb0173b0ef1388 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 5 PATCHLEVEL = 12 SUBLEVEL = 0 -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = Frozen Wasteland # *DOCUMENTATION* @@ -264,7 +264,8 @@ no-dot-config-targets := $(clean-targets) \ $(version_h) headers headers_% archheaders archscripts \ %asm-generic kernelversion %src-pkg dt_binding_check \ outputmakefile -no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease +no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease \ + image_name single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/ config-build := @@ -478,6 +479,7 @@ USERINCLUDE := \ -I$(objtree)/arch/$(SRCARCH)/include/generated/uapi \ -I$(srctree)/include/uapi \ -I$(objtree)/include/generated/uapi \ + -include $(srctree)/include/linux/compiler-version.h \ -include $(srctree)/include/linux/kconfig.h # Use LINUXINCLUDE when you must reference the include/ directory. diff --git a/arch/Kconfig b/arch/Kconfig index 2bb30673d8e6fbd5e7c3d41e8fe0800020c0f779..ecfd3520b676b014ee9d1dbddd181b4fd37e73bb 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -632,13 +632,12 @@ config HAS_LTO_CLANG def_bool y # Clang >= 11: https://github.com/ClangBuiltLinux/linux/issues/510 depends on CC_IS_CLANG && CLANG_VERSION >= 110000 && LD_IS_LLD - depends on $(success,test $(LLVM) -eq 1) depends on $(success,test $(LLVM_IAS) -eq 1) depends on $(success,$(NM) --help | head -n 1 | grep -qi llvm) depends on $(success,$(AR) --help | head -n 1 | grep -qi llvm) depends on ARCH_SUPPORTS_LTO_CLANG depends on !FTRACE_MCOUNT_USE_RECORDMCOUNT - depends on !KASAN + depends on !KASAN || KASAN_HW_TAGS depends on !GCOV_KERNEL help The compiler and Kconfig options support building with Clang's diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 853aab5ab327a430c250d4d77552e1d99ebe6071..5da96f5df48f356b39e40dc8e5b8bf1b84d72e76 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -348,6 +348,7 @@ config ARCH_EP93XX select ARM_AMBA imply ARM_PATCH_PHYS_VIRT select ARM_VIC + select GENERIC_IRQ_MULTI_HANDLER select AUTO_ZRELADDR select CLKDEV_LOOKUP select CLKSRC_MMIO diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c index acb464547a54f45d90a05437517ce14e5448f21a..84a1cea1f43b9a3331b35093e4c57cb78d670815 100644 --- a/arch/arm/xen/p2m.c +++ b/arch/arm/xen/p2m.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -109,7 +110,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, map_ops[i].status = GNTST_general_error; unmap.host_addr = map_ops[i].host_addr, unmap.handle = map_ops[i].handle; - map_ops[i].handle = ~0; + map_ops[i].handle = INVALID_GRANT_HANDLE; if (map_ops[i].flags & GNTMAP_device_map) unmap.dev_bus_addr = map_ops[i].dev_bus_addr; else @@ -130,7 +131,6 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, return 0; } -EXPORT_SYMBOL_GPL(set_foreign_p2m_mapping); int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops, struct gnttab_unmap_grant_ref *kunmap_ops, @@ -145,7 +145,6 @@ int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops, return 0; } -EXPORT_SYMBOL_GPL(clear_foreign_p2m_mapping); bool __set_phys_to_machine_multi(unsigned long pfn, unsigned long mfn, unsigned long nr_pages) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1f212b47a48a1033d1799c946f0bb0b9dca96fd2..5656e7aacd698436c8b8046d9d01280ea02fda3e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1055,8 +1055,6 @@ config HW_PERF_EVENTS config SYS_SUPPORTS_HUGETLBFS def_bool y -config ARCH_WANT_HUGE_PMD_SHARE - config ARCH_HAS_CACHE_LINE_SIZE def_bool y @@ -1157,8 +1155,8 @@ config XEN config FORCE_MAX_ZONEORDER int - default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) - default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) + default "14" if ARM64_64K_PAGES + default "12" if ARM64_16K_PAGES default "11" help The kernel memory allocator divides physically contiguous memory @@ -1855,12 +1853,6 @@ config CMDLINE_FROM_BOOTLOADER the boot loader doesn't provide any, the default kernel command string provided in CMDLINE will be used. -config CMDLINE_EXTEND - bool "Extend bootloader kernel arguments" - help - The command-line arguments provided by the boot loader will be - appended to the default kernel command string. - config CMDLINE_FORCE bool "Always use the default kernel command string" help diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 22d933e9b59e524cdef76eeb7fa98f69e0211a90..a7ab84f781f73d96006ff1cd4b66bffc97aa31bd 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -47,10 +47,10 @@ #define __KVM_HOST_SMCCC_FUNC___kvm_flush_vm_context 2 #define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa 3 #define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid 4 -#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_local_vmid 5 +#define __KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context 5 #define __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff 6 #define __KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs 7 -#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_ich_vtr_el2 8 +#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config 8 #define __KVM_HOST_SMCCC_FUNC___vgic_v3_read_vmcr 9 #define __KVM_HOST_SMCCC_FUNC___vgic_v3_write_vmcr 10 #define __KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs 11 @@ -183,16 +183,16 @@ DECLARE_KVM_HYP_SYM(__bp_harden_hyp_vecs); #define __bp_harden_hyp_vecs CHOOSE_HYP_SYM(__bp_harden_hyp_vecs) extern void __kvm_flush_vm_context(void); +extern void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu); extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa, int level); extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu); -extern void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu); extern void __kvm_timer_set_cntvoff(u64 cntvoff); extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); -extern u64 __vgic_v3_get_ich_vtr_el2(void); +extern u64 __vgic_v3_get_gic_config(void); extern u64 __vgic_v3_read_vmcr(void); extern void __vgic_v3_write_vmcr(u32 vmcr); extern void __vgic_v3_init_lrs(void); diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index c0450828378b528280f4dcc2f472e5694fc462c2..32ae676236b6b4dc85d101be97976fecc3f2fcf8 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -83,6 +83,11 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); void __debug_switch_to_guest(struct kvm_vcpu *vcpu); void __debug_switch_to_host(struct kvm_vcpu *vcpu); +#ifdef __KVM_NVHE_HYPERVISOR__ +void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu); +void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu); +#endif + void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); @@ -97,7 +102,8 @@ bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt); void __noreturn hyp_panic(void); #ifdef __KVM_NVHE_HYPERVISOR__ -void __noreturn __hyp_do_panic(bool restore_host, u64 spsr, u64 elr, u64 par); +void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr, + u64 elr, u64 par); #endif #endif /* __ARM64_KVM_HYP_H__ */ diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index c759faf7a1ff9a59299e4aad27af246f4c228cec..0aabc3be9a75953fe02b48d535198cc9eed7f6bf 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -328,6 +328,11 @@ static inline void *phys_to_virt(phys_addr_t x) #define ARCH_PFN_OFFSET ((unsigned long)PHYS_PFN_OFFSET) #if !defined(CONFIG_SPARSEMEM_VMEMMAP) || defined(CONFIG_DEBUG_VIRTUAL) +#define page_to_virt(x) ({ \ + __typeof__(x) __page = x; \ + void *__addr = __va(page_to_phys(__page)); \ + (void *)__tag_set((const void *)__addr, page_kasan_tag(__page));\ +}) #define virt_to_page(x) pfn_to_page(virt_to_pfn(x)) #else #define page_to_virt(x) ({ \ diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 70ce8c1d2b078b0431d7e4ce519b386a1a5f3c0f..bd02e99b1a4c54972f871ebe4d0c81650b965abb 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -63,23 +63,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) extern u64 idmap_t0sz; extern u64 idmap_ptrs_per_pgd; -static inline bool __cpu_uses_extended_idmap(void) -{ - if (IS_ENABLED(CONFIG_ARM64_VA_BITS_52)) - return false; - - return unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)); -} - -/* - * True if the extended ID map requires an extra level of translation table - * to be configured. - */ -static inline bool __cpu_uses_extended_idmap_level(void) -{ - return ARM64_HW_PGTABLE_LEVELS(64 - idmap_t0sz) > CONFIG_PGTABLE_LEVELS; -} - /* * Ensure TCR.T0SZ is set to the provided value. */ diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index 046be789fbb479967067cbc13e55693701f394fd..9a65fb5281100a7e08b29ee380c91b84cd887ca6 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -66,7 +66,6 @@ extern bool arm64_use_ng_mappings; #define _PAGE_DEFAULT (_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) #define PAGE_KERNEL __pgprot(PROT_NORMAL) -#define PAGE_KERNEL_TAGGED __pgprot(PROT_NORMAL_TAGGED) #define PAGE_KERNEL_RO __pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY) #define PAGE_KERNEL_ROX __pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY) #define PAGE_KERNEL_EXEC __pgprot(PROT_NORMAL & ~PTE_PXN) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index e17b96d0e4b59845f293cb3f3a050b90fc596520..47027796c2f934a0207013044dcaee2f9e58078c 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -486,6 +486,9 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) #define pgprot_device(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) +#define pgprot_tagged(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) +#define pgprot_mhp pgprot_tagged /* * DMA allocations for non-coherent devices use what the Arm architecture calls * "Normal non-cacheable" memory, which permits speculation, unaligned accesses diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index dfd4edbfe36086df7c67bafe532929970c73dcb7..d4a5fca984c3e228594e19a80fa68bc37e43e16c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -796,6 +796,11 @@ #define ID_AA64MMFR0_PARANGE_48 0x5 #define ID_AA64MMFR0_PARANGE_52 0x6 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 + #ifdef CONFIG_ARM64_PA_BITS_52 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 #else @@ -961,14 +966,17 @@ #define ID_PFR1_PROGMOD_SHIFT 0 #if defined(CONFIG_ARM64_4K_PAGES) -#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 #elif defined(CONFIG_ARM64_16K_PAGES) -#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF #elif defined(CONFIG_ARM64_64K_PAGES) -#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 #endif #define MVFR2_FPMISC_SHIFT 4 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 66b0e0b66e3122a9ba94a7ce648525b7f048bdca..840bda1869e9ccb0d88b2e6bb0cb63ea1eb1f0c6 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -319,7 +319,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables) */ adrp x5, __idmap_text_end clz x5, x5 - cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? + cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? b.ge 1f // .. then skip VA range extension adr_l x6, idmap_t0sz @@ -655,8 +655,10 @@ SYM_FUNC_END(__secondary_too_slow) SYM_FUNC_START(__enable_mmu) mrs x2, ID_AA64MMFR0_EL1 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 - cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED - b.ne __no_granule_support + cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN + b.lt __no_granule_support + cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX + b.gt __no_granule_support update_early_cpu_boot_status 0, x2, x3 adrp x2, idmap_pg_dir phys_to_ttbr x1, x1 diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index dffb16682330e657c6ce3d80f495c7bae48a8425..83f1c4b92095e9a6acf0c2eac454f965228bf040 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -163,33 +163,36 @@ static __init void __parse_cmdline(const char *cmdline, bool parse_aliases) } while (1); } -static __init void parse_cmdline(void) +static __init const u8 *get_bootargs_cmdline(void) { - if (!IS_ENABLED(CONFIG_CMDLINE_FORCE)) { - const u8 *prop; - void *fdt; - int node; + const u8 *prop; + void *fdt; + int node; - fdt = get_early_fdt_ptr(); - if (!fdt) - goto out; + fdt = get_early_fdt_ptr(); + if (!fdt) + return NULL; - node = fdt_path_offset(fdt, "/chosen"); - if (node < 0) - goto out; + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) + return NULL; - prop = fdt_getprop(fdt, node, "bootargs", NULL); - if (!prop) - goto out; + prop = fdt_getprop(fdt, node, "bootargs", NULL); + if (!prop) + return NULL; - __parse_cmdline(prop, true); + return strlen(prop) ? prop : NULL; +} - if (!IS_ENABLED(CONFIG_CMDLINE_EXTEND)) - return; - } +static __init void parse_cmdline(void) +{ + const u8 *prop = get_bootargs_cmdline(); -out: - __parse_cmdline(CONFIG_CMDLINE, true); + if (IS_ENABLED(CONFIG_CMDLINE_FORCE) || !prop) + __parse_cmdline(CONFIG_CMDLINE, true); + + if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && prop) + __parse_cmdline(prop, true); } /* Keep checkers quiet */ diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h index 23f1a557bd9f04fb61c90d2428fcc12ecca127ac..5aa9ed1e9ec6189af9beede0488e9e982044da0d 100644 --- a/arch/arm64/kernel/image-vars.h +++ b/arch/arm64/kernel/image-vars.h @@ -101,6 +101,9 @@ KVM_NVHE_ALIAS(__stop___kvm_ex_table); /* Array containing bases of nVHE per-CPU memory regions. */ KVM_NVHE_ALIAS(kvm_arm_hyp_percpu_base); +/* PMU available static key */ +KVM_NVHE_ALIAS(kvm_arm_pmu_available); + #endif /* CONFIG_KVM */ #endif /* __ARM64_KERNEL_IMAGE_VARS_H */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 7d2318f80955cc8ae7d9891edd0e5b06a3b6fe73..4658fcf88c2b4ddff069e3f47858c6443eac0198 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -460,7 +460,7 @@ static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); } -static inline u32 armv8pmu_read_evcntr(int idx) +static inline u64 armv8pmu_read_evcntr(int idx) { u32 counter = ARMV8_IDX_TO_COUNTER(idx); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index fc4c95dd2d26172cf6ae4a9bd7d401bed5a7b6be..7f06ba76698d843d3b4696c98970865536013a48 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -385,11 +385,16 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) last_ran = this_cpu_ptr(mmu->last_vcpu_ran); /* + * We guarantee that both TLBs and I-cache are private to each + * vcpu. If detecting that a vcpu from the same VM has + * previously run on the same physical CPU, call into the + * hypervisor code to nuke the relevant contexts. + * * We might get preempted before the vCPU actually runs, but * over-invalidation doesn't affect correctness. */ if (*last_ran != vcpu->vcpu_id) { - kvm_call_hyp(__kvm_tlb_flush_local_vmid, mmu); + kvm_call_hyp(__kvm_flush_cpu_context, mmu); *last_ran = vcpu->vcpu_id; } diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index b0afad7a99c6e81c0f5f8bfb70cd9acfc67ff68c..e831d3dfd50d7cee211d915a7e39f9468ceff154 100644 --- a/arch/arm64/kvm/hyp/entry.S +++ b/arch/arm64/kvm/hyp/entry.S @@ -85,8 +85,10 @@ SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL) // If the hyp context is loaded, go straight to hyp_panic get_loaded_vcpu x0, x1 - cbz x0, hyp_panic + cbnz x0, 1f + b hyp_panic +1: // The hyp context is saved so make sure it is restored to allow // hyp_panic to run at hyp and, subsequently, panic to run in the host. // This makes use of __guest_exit to avoid duplication but sets the @@ -94,7 +96,7 @@ SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL) // current state is saved to the guest context but it will only be // accurate if the guest had been completely restored. adr_this_cpu x0, kvm_hyp_ctxt, x1 - adr x1, hyp_panic + adr_l x1, hyp_panic str x1, [x0, #CPU_XREG_OFFSET(30)] get_vcpu_ptr x1, x0 @@ -146,7 +148,7 @@ SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL) // Now restore the hyp regs restore_callee_saved_regs x2 - set_loaded_vcpu xzr, x1, x2 + set_loaded_vcpu xzr, x2, x3 alternative_if ARM64_HAS_RAS_EXTN // If we have the RAS extensions we can consume a pending error diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 54f4860cd87c06b1ed701eb3f2664176b6458806..6c1f51f25eb340154247b6381b6b482e1c76ccd4 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -90,15 +90,18 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) * counter, which could make a PMXEVCNTR_EL0 access UNDEF at * EL1 instead of being trapped to EL2. */ - write_sysreg(0, pmselr_el0); - write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); + if (kvm_arm_support_pmu_v3()) { + write_sysreg(0, pmselr_el0); + write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); + } write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); } static inline void __deactivate_traps_common(void) { write_sysreg(0, hstr_el2); - write_sysreg(0, pmuserenr_el0); + if (kvm_arm_support_pmu_v3()) + write_sysreg(0, pmuserenr_el0); } static inline void ___activate_traps(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index 91a711aa8382e1dcb4811a77e55edafd8ea0af50..f401724f12ef754a184c861e08c2b4ad4a4935a0 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -58,16 +58,24 @@ static void __debug_restore_spe(u64 pmscr_el1) write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); } -void __debug_switch_to_guest(struct kvm_vcpu *vcpu) +void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) { /* Disable and flush SPE data generation */ __debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1); +} + +void __debug_switch_to_guest(struct kvm_vcpu *vcpu) +{ __debug_switch_to_guest_common(vcpu); } -void __debug_switch_to_host(struct kvm_vcpu *vcpu) +void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu) { __debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1); +} + +void __debug_switch_to_host(struct kvm_vcpu *vcpu) +{ __debug_switch_to_host_common(vcpu); } diff --git a/arch/arm64/kvm/hyp/nvhe/host.S b/arch/arm64/kvm/hyp/nvhe/host.S index 6585a7cbbc566212fab4e9409c47a5b96643d708..5d94584840ccfe06b0e11945eeed5bbba7252f50 100644 --- a/arch/arm64/kvm/hyp/nvhe/host.S +++ b/arch/arm64/kvm/hyp/nvhe/host.S @@ -71,7 +71,8 @@ SYM_FUNC_START(__host_enter) SYM_FUNC_END(__host_enter) /* - * void __noreturn __hyp_do_panic(bool restore_host, u64 spsr, u64 elr, u64 par); + * void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr, + * u64 elr, u64 par); */ SYM_FUNC_START(__hyp_do_panic) /* Prepare and exit to the host's panic funciton. */ @@ -82,9 +83,11 @@ SYM_FUNC_START(__hyp_do_panic) hyp_kimg_va lr, x6 msr elr_el2, lr - /* Set the panic format string. Use the, now free, LR as scratch. */ - ldr lr, =__hyp_panic_string - hyp_kimg_va lr, x6 + mov x29, x0 + + /* Load the format string into x0 and arguments into x1-7 */ + ldr x0, =__hyp_panic_string + hyp_kimg_va x0, x6 /* Load the format arguments into x1-7. */ mov x6, x3 @@ -94,9 +97,7 @@ SYM_FUNC_START(__hyp_do_panic) mrs x5, hpfar_el2 /* Enter the host, conditionally restoring the host context. */ - cmp x0, xzr - mov x0, lr - b.eq __host_enter_without_restoring + cbz x29, __host_enter_without_restoring b __host_enter_for_panic SYM_FUNC_END(__hyp_do_panic) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index f012f8665ecc1c6a0510bf25705b738f5660a077..936328207bde02b9e868f3e19153d95aa1fcdfb8 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -46,11 +46,11 @@ static void handle___kvm_tlb_flush_vmid(struct kvm_cpu_context *host_ctxt) __kvm_tlb_flush_vmid(kern_hyp_va(mmu)); } -static void handle___kvm_tlb_flush_local_vmid(struct kvm_cpu_context *host_ctxt) +static void handle___kvm_flush_cpu_context(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1); - __kvm_tlb_flush_local_vmid(kern_hyp_va(mmu)); + __kvm_flush_cpu_context(kern_hyp_va(mmu)); } static void handle___kvm_timer_set_cntvoff(struct kvm_cpu_context *host_ctxt) @@ -67,9 +67,9 @@ static void handle___kvm_enable_ssbs(struct kvm_cpu_context *host_ctxt) write_sysreg_el2(tmp, SYS_SCTLR); } -static void handle___vgic_v3_get_ich_vtr_el2(struct kvm_cpu_context *host_ctxt) +static void handle___vgic_v3_get_gic_config(struct kvm_cpu_context *host_ctxt) { - cpu_reg(host_ctxt, 1) = __vgic_v3_get_ich_vtr_el2(); + cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); } static void handle___vgic_v3_read_vmcr(struct kvm_cpu_context *host_ctxt) @@ -115,10 +115,10 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__kvm_flush_vm_context), HANDLE_FUNC(__kvm_tlb_flush_vmid_ipa), HANDLE_FUNC(__kvm_tlb_flush_vmid), - HANDLE_FUNC(__kvm_tlb_flush_local_vmid), + HANDLE_FUNC(__kvm_flush_cpu_context), HANDLE_FUNC(__kvm_timer_set_cntvoff), HANDLE_FUNC(__kvm_enable_ssbs), - HANDLE_FUNC(__vgic_v3_get_ich_vtr_el2), + HANDLE_FUNC(__vgic_v3_get_gic_config), HANDLE_FUNC(__vgic_v3_read_vmcr), HANDLE_FUNC(__vgic_v3_write_vmcr), HANDLE_FUNC(__vgic_v3_init_lrs), diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index f3d0e9eca56cd2a62de3f31a77926ee8c478390a..68ab6b4d5141401346bcf4247f05e159f0262a20 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -192,6 +192,14 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); __sysreg_save_state_nvhe(host_ctxt); + /* + * We must flush and disable the SPE buffer for nVHE, as + * the translation regime(EL1&0) is going to be loaded with + * that of the guest. And we must do this before we change the + * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and + * before we load guest Stage1. + */ + __debug_save_host_buffers_nvhe(vcpu); __adjust_pc(vcpu); @@ -234,11 +242,12 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) __fpsimd_save_fpexc32(vcpu); + __debug_switch_to_host(vcpu); /* * This must come after restoring the host sysregs, since a non-VHE * system may enable SPE here and make use of the TTBRs. */ - __debug_switch_to_host(vcpu); + __debug_restore_host_buffers_nvhe(vcpu); if (pmu_switch_needed) __pmu_switch_to_host(host_ctxt); @@ -257,7 +266,6 @@ void __noreturn hyp_panic(void) u64 spsr = read_sysreg_el2(SYS_SPSR); u64 elr = read_sysreg_el2(SYS_ELR); u64 par = read_sysreg_par(); - bool restore_host = true; struct kvm_cpu_context *host_ctxt; struct kvm_vcpu *vcpu; @@ -271,7 +279,7 @@ void __noreturn hyp_panic(void) __sysreg_restore_state_nvhe(host_ctxt); } - __hyp_do_panic(restore_host, spsr, elr, par); + __hyp_do_panic(host_ctxt, spsr, elr, par); unreachable(); } diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c index fbde89a2c6e838d0ad9cbcb9029130b789bf2360..229b06748c20849df4b85c6d656eea2f3403853d 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c @@ -123,7 +123,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) __tlb_switch_to_host(&cxt); } -void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu) +void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu) { struct tlb_inv_context cxt; @@ -131,6 +131,7 @@ void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu) __tlb_switch_to_guest(mmu, &cxt); __tlbi(vmalle1); + asm volatile("ic iallu"); dsb(nsh); isb(); diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 4d177ce1d536f3d719887a3e69d08fc2dd3dec22..926fc07074f57b27294082cf2a274abe4c0bc983 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -223,6 +223,7 @@ static inline int __kvm_pgtable_visit(struct kvm_pgtable_walk_data *data, goto out; if (!table) { + data->addr = ALIGN_DOWN(data->addr, kvm_granule_size(level)); data->addr += kvm_granule_size(level); goto out; } diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c index 80406f463c28fdebad45a1c4d4b09cf3e1bf8144..ee3682b9873c44f00c3a2c965987289610caf5d5 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -405,9 +405,45 @@ void __vgic_v3_init_lrs(void) __gic_v3_set_lr(0, i); } -u64 __vgic_v3_get_ich_vtr_el2(void) +/* + * Return the GIC CPU configuration: + * - [31:0] ICH_VTR_EL2 + * - [62:32] RES0 + * - [63] MMIO (GICv2) capable + */ +u64 __vgic_v3_get_gic_config(void) { - return read_gicreg(ICH_VTR_EL2); + u64 val, sre = read_gicreg(ICC_SRE_EL1); + unsigned long flags = 0; + + /* + * To check whether we have a MMIO-based (GICv2 compatible) + * CPU interface, we need to disable the system register + * view. To do that safely, we have to prevent any interrupt + * from firing (which would be deadly). + * + * Note that this only makes sense on VHE, as interrupts are + * already masked for nVHE as part of the exception entry to + * EL2. + */ + if (has_vhe()) + flags = local_daif_save(); + + write_gicreg(0, ICC_SRE_EL1); + isb(); + + val = read_gicreg(ICC_SRE_EL1); + + write_gicreg(sre, ICC_SRE_EL1); + isb(); + + if (has_vhe()) + local_daif_restore(flags); + + val = (val & ICC_SRE_EL1_SRE) ? 0 : (1ULL << 63); + val |= read_gicreg(ICH_VTR_EL2); + + return val; } u64 __vgic_v3_read_vmcr(void) diff --git a/arch/arm64/kvm/hyp/vhe/tlb.c b/arch/arm64/kvm/hyp/vhe/tlb.c index fd7895945bbc6f22b5c687220781a177e7af709a..66f17349f0c36923266b60ca03318e4729d7b1f7 100644 --- a/arch/arm64/kvm/hyp/vhe/tlb.c +++ b/arch/arm64/kvm/hyp/vhe/tlb.c @@ -127,7 +127,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) __tlb_switch_to_host(&cxt); } -void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu) +void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu) { struct tlb_inv_context cxt; @@ -135,6 +135,7 @@ void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu) __tlb_switch_to_guest(mmu, &cxt); __tlbi(vmalle1); + asm volatile("ic iallu"); dsb(nsh); isb(); diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 77cb2d28f2a43a96dd0114ef7d10f2fa60a48b96..8711894db8c2248e3b9953d6550ec81230e490da 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1312,8 +1312,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, * Prevent userspace from creating a memory region outside of the IPA * space addressable by the KVM guest IPA space. */ - if (memslot->base_gfn + memslot->npages >= - (kvm_phys_size(kvm) >> PAGE_SHIFT)) + if ((memslot->base_gfn + memslot->npages) > (kvm_phys_size(kvm) >> PAGE_SHIFT)) return -EFAULT; mmap_read_lock(current->mm); diff --git a/arch/arm64/kvm/perf.c b/arch/arm64/kvm/perf.c index d45b8b9a44151810e1ac9e4ba77c41b7053c6375..739164324afedb9dc54b87c131761abff6d7b72f 100644 --- a/arch/arm64/kvm/perf.c +++ b/arch/arm64/kvm/perf.c @@ -11,6 +11,8 @@ #include +DEFINE_STATIC_KEY_FALSE(kvm_arm_pmu_available); + static int kvm_is_in_guest(void) { return kvm_get_running_vcpu() != NULL; @@ -48,6 +50,14 @@ static struct perf_guest_info_callbacks kvm_guest_cbs = { int kvm_perf_init(void) { + /* + * Check if HW_PERF_EVENTS are supported by checking the number of + * hardware performance counters. This could ensure the presence of + * a physical PMU and CONFIG_PERF_EVENT is selected. + */ + if (IS_ENABLED(CONFIG_ARM_PMU) && perf_num_counters() > 0) + static_branch_enable(&kvm_arm_pmu_available); + return perf_register_guest_info_callbacks(&kvm_guest_cbs); } diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index e9ec08b0b070337d476ec0d00a28d62efa0af89e..e32c6e139a09d39f2d904f1aca8c2648ab097238 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -823,16 +823,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) return val & mask; } -bool kvm_arm_support_pmu_v3(void) -{ - /* - * Check if HW_PERF_EVENTS are supported by checking the number of - * hardware performance counters. This could ensure the presence of - * a physical PMU and CONFIG_PERF_EVENT is selected. - */ - return (perf_num_counters() > 0); -} - int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) { if (!kvm_vcpu_has_pmu(vcpu)) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 47f3f035f3eac5aaf9b4d590e25ebbff7eb8dd95..bd354cd45d2860e4595109c3375395f716f6c911 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -311,23 +311,24 @@ int kvm_set_ipa_limit(void) } switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) { - default: - case 1: + case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE: kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); return -EINVAL; - case 0: + case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT: kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); break; - case 2: + case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX: kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); break; + default: + kvm_err("Unsupported value for TGRAN_2, giving up\n"); + return -EINVAL; } kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); - WARN(kvm_ipa_limit < KVM_PHYS_SHIFT, - "KVM IPA Size Limit (%d bits) is smaller than default size\n", - kvm_ipa_limit); - kvm_info("IPA Size Limit: %d bits\n", kvm_ipa_limit); + kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit, + ((kvm_ipa_limit < KVM_PHYS_SHIFT) ? + " (Reduced IPA size, limited VM/VMM compatibility)" : "")); return 0; } @@ -356,6 +357,11 @@ int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) return -EINVAL; } else { phys_shift = KVM_PHYS_SHIFT; + if (phys_shift > kvm_ipa_limit) { + pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n", + current->comm); + return -EINVAL; + } } mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index 52915b34235143a3248ec2f958f9a6dc7c486f2c..6f530925a23144dca5159f579e709da1119fcac0 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -574,9 +574,13 @@ early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable); */ int vgic_v3_probe(const struct gic_kvm_info *info) { - u32 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_ich_vtr_el2); + u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config); + bool has_v2; int ret; + has_v2 = ich_vtr_el2 >> 63; + ich_vtr_el2 = (u32)ich_vtr_el2; + /* * The ListRegs field is 5 bits, but there is an architectural * maximum of 16 list registers. Just ignore bit 4... @@ -594,13 +598,15 @@ int vgic_v3_probe(const struct gic_kvm_info *info) gicv4_enable ? "en" : "dis"); } + kvm_vgic_global_state.vcpu_base = 0; + if (!info->vcpu.start) { kvm_info("GICv3: no GICV resource entry\n"); - kvm_vgic_global_state.vcpu_base = 0; + } else if (!has_v2) { + pr_warn(FW_BUG "CPU interface incapable of MMIO access\n"); } else if (!PAGE_ALIGNED(info->vcpu.start)) { pr_warn("GICV physical address 0x%llx not page aligned\n", (unsigned long long)info->vcpu.start); - kvm_vgic_global_state.vcpu_base = 0; } else { kvm_vgic_global_state.vcpu_base = info->vcpu.start; kvm_vgic_global_state.can_emulate_gicv2 = true; diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 0ace5e68efba0ea05b32c989ac6ae987364fc89c..3685e12aba9b62b170cbd285dae412c339cae350 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -219,17 +219,40 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max) int pfn_valid(unsigned long pfn) { - phys_addr_t addr = pfn << PAGE_SHIFT; + phys_addr_t addr = PFN_PHYS(pfn); - if ((addr >> PAGE_SHIFT) != pfn) + /* + * Ensure the upper PAGE_SHIFT bits are clear in the + * pfn. Else it might lead to false positives when + * some of the upper bits are set, but the lower bits + * match a valid pfn. + */ + if (PHYS_PFN(addr) != pfn) return 0; #ifdef CONFIG_SPARSEMEM +{ + struct mem_section *ms; + if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS) return 0; - if (!valid_section(__pfn_to_section(pfn))) + ms = __pfn_to_section(pfn); + if (!valid_section(ms)) return 0; + + /* + * ZONE_DEVICE memory does not have the memblock entries. + * memblock_is_map_memory() check for ZONE_DEVICE based + * addresses will always fail. Even the normal hotplugged + * memory will never have MEMBLOCK_NOMAP flag set in their + * memblock entries. Skip memblock search for all non early + * memory sections covering all of hotplug memory including + * both normal and ZONE_DEVICE based. + */ + if (!early_section(ms)) + return pfn_section_valid(ms, pfn); +} #endif return memblock_is_map_memory(addr); } diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 3802cfbdd20d12e93388cb8f5f2029eafdc9f60f..7484ea4f6ba07300a25a4c0689309f9332e9913a 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -40,7 +40,7 @@ #define NO_BLOCK_MAPPINGS BIT(0) #define NO_CONT_MAPPINGS BIT(1) -u64 idmap_t0sz = TCR_T0SZ(VA_BITS); +u64 idmap_t0sz = TCR_T0SZ(VA_BITS_MIN); u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; u64 __section(".mmuoff.data.write") vabits_actual; @@ -512,7 +512,8 @@ static void __init map_mem(pgd_t *pgdp) * if MTE is present. Otherwise, it has the same attributes as * PAGE_KERNEL. */ - __map_memblock(pgdp, start, end, PAGE_KERNEL_TAGGED, flags); + __map_memblock(pgdp, start, end, pgprot_tagged(PAGE_KERNEL), + flags); } /* diff --git a/arch/ia64/include/asm/syscall.h b/arch/ia64/include/asm/syscall.h index 6c6f16e409a877722269841162a4c7e8bc68b7eb..0d23c00493018951e6d8e691fcc7016a80d4c447 100644 --- a/arch/ia64/include/asm/syscall.h +++ b/arch/ia64/include/asm/syscall.h @@ -32,7 +32,7 @@ static inline void syscall_rollback(struct task_struct *task, static inline long syscall_get_error(struct task_struct *task, struct pt_regs *regs) { - return regs->r10 == -1 ? regs->r8:0; + return regs->r10 == -1 ? -regs->r8:0; } static inline long syscall_get_return_value(struct task_struct *task, diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c index c3490ee2daa58642a9b83eeb9daefc6e942962c3..e14f5653393ac865ffd0f144352befec2f932c74 100644 --- a/arch/ia64/kernel/ptrace.c +++ b/arch/ia64/kernel/ptrace.c @@ -2013,27 +2013,39 @@ static void syscall_get_set_args_cb(struct unw_frame_info *info, void *data) { struct syscall_get_set_args *args = data; struct pt_regs *pt = args->regs; - unsigned long *krbs, cfm, ndirty; + unsigned long *krbs, cfm, ndirty, nlocals, nouts; int i, count; if (unw_unwind_to_user(info) < 0) return; + /* + * We get here via a few paths: + * - break instruction: cfm is shared with caller. + * syscall args are in out= regs, locals are non-empty. + * - epsinstruction: cfm is set by br.call + * locals don't exist. + * + * For both cases argguments are reachable in cfm.sof - cfm.sol. + * CFM: [ ... | sor: 17..14 | sol : 13..7 | sof : 6..0 ] + */ cfm = pt->cr_ifs; + nlocals = (cfm >> 7) & 0x7f; /* aka sol */ + nouts = (cfm & 0x7f) - nlocals; /* aka sof - sol */ krbs = (unsigned long *)info->task + IA64_RBS_OFFSET/8; ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19)); count = 0; if (in_syscall(pt)) - count = min_t(int, args->n, cfm & 0x7f); + count = min_t(int, args->n, nouts); + /* Iterate over outs. */ for (i = 0; i < count; i++) { + int j = ndirty + nlocals + i + args->i; if (args->rw) - *ia64_rse_skip_regs(krbs, ndirty + i + args->i) = - args->args[i]; + *ia64_rse_skip_regs(krbs, j) = args->args[i]; else - args->args[i] = *ia64_rse_skip_regs(krbs, - ndirty + i + args->i); + args->args[i] = *ia64_rse_skip_regs(krbs, j); } if (!args->rw) { diff --git a/arch/m68k/include/asm/page_mm.h b/arch/m68k/include/asm/page_mm.h index 7f5912af2a52ea0a033ca4155d8604d2fc53df51..9e8f0cc30a2ccb9d2459228f1fef4ae28d4ca0ff 100644 --- a/arch/m68k/include/asm/page_mm.h +++ b/arch/m68k/include/asm/page_mm.h @@ -171,7 +171,7 @@ static inline __attribute_const__ int __virt_to_node_shift(void) #include #endif -#define virt_addr_valid(kaddr) ((void *)(kaddr) >= (void *)PAGE_OFFSET && (void *)(kaddr) < high_memory) +#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) #define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn)) #endif /* __ASSEMBLY__ */ diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h index 6bbe52025de3c5c68518371a7d41e23003b6ece1..8d0f862ee9d7953236fc315f840e5c98db21d36c 100644 --- a/arch/m68k/include/asm/page_no.h +++ b/arch/m68k/include/asm/page_no.h @@ -30,8 +30,8 @@ extern unsigned long memory_end; #define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) #define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ - ((void *)(kaddr) < (void *)memory_end)) +#define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET) && \ + ((unsigned long)(kaddr) < memory_end)) #endif /* __ASSEMBLY__ */ diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index e3946b06e840a6b2e6c5a297e81f16db50a4c914..3d70d15ada286cbb8928befdcf966e1723c380f8 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -14,6 +14,7 @@ #include #include +#include /* * These two variables specify the free mem region @@ -120,6 +121,13 @@ void decompress_kernel(unsigned long boot_heap_start) /* last four bytes is always image size in little endian */ image_size = get_unaligned_le32((void *)&__image_end - 4); + /* The device tree's address must be properly aligned */ + image_size = ALIGN(image_size, STRUCT_ALIGNMENT); + + puts("Copy device tree to address "); + puthex(VMLINUX_LOAD_ADDRESS_ULL + image_size); + puts("\n"); + /* copy dtb to where the booted kernel will expect it */ memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size, __appended_dtb, dtb_size); diff --git a/arch/mips/crypto/Makefile b/arch/mips/crypto/Makefile index 8e1deaf00e0c0b7722ba48b5b9bf1d9582b03298..5e4105cccf9fa9dde2b3f495b89156e3700c04de 100644 --- a/arch/mips/crypto/Makefile +++ b/arch/mips/crypto/Makefile @@ -12,8 +12,8 @@ AFLAGS_chacha-core.o += -O2 # needed to fill branch delay slots obj-$(CONFIG_CRYPTO_POLY1305_MIPS) += poly1305-mips.o poly1305-mips-y := poly1305-core.o poly1305-glue.o -perlasm-flavour-$(CONFIG_CPU_MIPS32) := o32 -perlasm-flavour-$(CONFIG_CPU_MIPS64) := 64 +perlasm-flavour-$(CONFIG_32BIT) := o32 +perlasm-flavour-$(CONFIG_64BIT) := 64 quiet_cmd_perlasm = PERLASM $@ cmd_perlasm = $(PERL) $(<) $(perlasm-flavour-y) $(@) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 6aa8f126a43d89b3e71747a4ce3a295c798025c4..b710e76c9c658f7baaef01601cef79277020d7ef 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,8 +24,11 @@ extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); +extern void reserve_exception_space(phys_addr_t addr, unsigned long size); extern char except_vec_nmi[]; +#define VECTORSPACING 0x100 /* for EI/VI mode */ + #define nmi_notifier(fn, pri) \ ({ \ static struct notifier_block fn##_nb = { \ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9a89637b4ecfa8331a496f89c653ba1d1fcd6d68..b71892064f2733cfad153c4834e89f29517cb231 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "fpu-probe.h" @@ -1628,6 +1629,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_BMIPS3300; __cpu_name[cpu] = "Broadcom BMIPS3300"; set_elf_platform(cpu, "bmips3300"); + reserve_exception_space(0x400, VECTORSPACING * 64); break; case PRID_IMP_BMIPS43XX: { int rev = c->processor_id & PRID_REV_MASK; @@ -1638,6 +1640,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS4380"; set_elf_platform(cpu, "bmips4380"); c->options |= MIPS_CPU_RIXI; + reserve_exception_space(0x400, VECTORSPACING * 64); } else { c->cputype = CPU_BMIPS4350; __cpu_name[cpu] = "Broadcom BMIPS4350"; @@ -1654,6 +1657,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS5000"; set_elf_platform(cpu, "bmips5000"); c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; + reserve_exception_space(0x1000, VECTORSPACING * 64); break; } } @@ -2133,6 +2137,8 @@ void cpu_probe(void) if (cpu == 0) __ua_limit = ~((1ull << cpu_vmbits) - 1); #endif + + reserve_exception_space(0, 0x1000); } void cpu_report(void) diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c index abdbbe8c5a43a98b3c41474f33f3a240aba668aa..af654771918cdd0873b5046310c5a0fc77253075 100644 --- a/arch/mips/kernel/cpu-r3k-probe.c +++ b/arch/mips/kernel/cpu-r3k-probe.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "fpu-probe.h" @@ -158,6 +159,8 @@ void cpu_probe(void) cpu_set_fpu_opts(c); else cpu_set_nofpu_opts(c); + + reserve_exception_space(0, 0x400); } void cpu_report(void) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e0352958e2f720be5b9bd407e208f249716f7cad..808b8b61ded155195f57d6b21140beaaa30fc746 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2009,13 +2009,16 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) nmi_exit(); } -#define VECTORSPACING 0x100 /* for EI/VI mode */ - unsigned long ebase; EXPORT_SYMBOL_GPL(ebase); unsigned long exception_handlers[32]; unsigned long vi_handlers[64]; +void reserve_exception_space(phys_addr_t addr, unsigned long size) +{ + memblock_reserve(addr, size); +} + void __init *set_except_vector(int n, void *addr) { unsigned long handler = (unsigned long) addr; @@ -2367,10 +2370,7 @@ void __init trap_init(void) if (!cpu_has_mips_r2_r6) { ebase = CAC_BASE; - ebase_pa = virt_to_phys((void *)ebase); vec_size = 0x400; - - memblock_reserve(ebase_pa, vec_size); } else { if (cpu_has_veic || cpu_has_vint) vec_size = 0x200 + VECTORSPACING*64; diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index c1c345be04ffd5c08e47ab0c474341c57c1eb225..1234834cc4c44d55d2efc3ed9a8701935b5f4054 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -145,6 +145,7 @@ SECTIONS } #ifdef CONFIG_MIPS_ELF_APPENDED_DTB + STRUCT_ALIGN(); .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) { *(.appended_dtb) KEEP(*(.appended_dtb)) @@ -172,6 +173,11 @@ SECTIONS #endif #ifdef CONFIG_MIPS_RAW_APPENDED_DTB + .fill : { + FILL(0); + BYTE(0); + . = ALIGN(8); + } __appended_dtb = .; /* leave space for appended DTB */ . += 0x100000; diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 4e53ac46e857e5d9485ce8fcd2d011eea5cd0dae..afc3b8d03572684d649e7fe82ef88839c0e0714e 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -203,9 +203,12 @@ config PREFETCH def_bool y depends on PA8X00 || PA7200 +config PARISC_HUGE_KERNEL + def_bool y if !MODULES || UBSAN || FTRACE || COMPILE_TEST + config MLONGCALLS - def_bool y if !MODULES || UBSAN || FTRACE - bool "Enable the -mlong-calls compiler option for big kernels" if MODULES && !UBSAN && !FTRACE + def_bool y if PARISC_HUGE_KERNEL + bool "Enable the -mlong-calls compiler option for big kernels" if !PARISC_HUGE_KERNEL depends on PA8X00 help If you configure the kernel to include many drivers built-in instead diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c index 2127974982df9a029b9c8819a257debb30bb5f0c..65de6c4c9354d6754091435943146acc8a726483 100644 --- a/arch/parisc/kernel/ptrace.c +++ b/arch/parisc/kernel/ptrace.c @@ -567,8 +567,6 @@ static const struct user_regset_view user_parisc_native_view = { }; #ifdef CONFIG_64BIT -#include - static int gpr32_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h index eacc9102c2515cdc3eaab8d7447a4971c6282df0..f1d029bf906e59b52506624eb77539d90d652726 100644 --- a/arch/powerpc/include/asm/code-patching.h +++ b/arch/powerpc/include/asm/code-patching.h @@ -73,9 +73,10 @@ void __patch_exception(int exc, unsigned long addr); #endif #define OP_RT_RA_MASK 0xffff0000UL -#define LIS_R2 0x3c020000UL -#define ADDIS_R2_R12 0x3c4c0000UL -#define ADDI_R2_R2 0x38420000UL +#define LIS_R2 (PPC_INST_ADDIS | __PPC_RT(R2)) +#define ADDIS_R2_R12 (PPC_INST_ADDIS | __PPC_RT(R2) | __PPC_RA(R12)) +#define ADDI_R2_R2 (PPC_INST_ADDI | __PPC_RT(R2) | __PPC_RA(R2)) + static inline unsigned long ppc_function_entry(void *func) { diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h index 7141ccea8c94e6b2ba571607999a0384ce60a7bd..a92059964579b877334e683177593588b7144429 100644 --- a/arch/powerpc/include/asm/dcr-native.h +++ b/arch/powerpc/include/asm/dcr-native.h @@ -53,8 +53,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val) #define mfdcr(rn) \ ({unsigned int rval; \ if (__builtin_constant_p(rn) && rn < 1024) \ - asm volatile("mfdcr %0," __stringify(rn) \ - : "=r" (rval)); \ + asm volatile("mfdcr %0, %1" : "=r" (rval) \ + : "n" (rn)); \ else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \ rval = mfdcrx(rn); \ else \ @@ -64,8 +64,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val) #define mtdcr(rn, v) \ do { \ if (__builtin_constant_p(rn) && rn < 1024) \ - asm volatile("mtdcr " __stringify(rn) ",%0" \ - : : "r" (v)); \ + asm volatile("mtdcr %0, %1" \ + : : "n" (rn), "r" (v)); \ else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \ mtdcrx(rn, v); \ else \ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h index aedfba29e43a5e0a39b52fa406eabf4dcda82e2e..e8d09a841373b708c729e6ea4d4d63cf62654b48 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -410,7 +410,6 @@ DECLARE_INTERRUPT_HANDLER(altivec_assist_exception); DECLARE_INTERRUPT_HANDLER(CacheLockingException); DECLARE_INTERRUPT_HANDLER(SPEFloatingPointException); DECLARE_INTERRUPT_HANDLER(SPEFloatingPointRoundException); -DECLARE_INTERRUPT_HANDLER(unrecoverable_exception); DECLARE_INTERRUPT_HANDLER(WatchdogException); DECLARE_INTERRUPT_HANDLER(kernel_bad_stack); @@ -437,6 +436,8 @@ DECLARE_INTERRUPT_HANDLER_NMI(hmi_exception_realmode); DECLARE_INTERRUPT_HANDLER_ASYNC(TAUException); +void unrecoverable_exception(struct pt_regs *regs); + void replay_system_reset(void); void replay_soft_interrupts(void); diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 80b27f5d96486227206c4503d388892821e569cd..607168b1aef46a936540a43601960ae6b17eb5bb 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -228,7 +228,7 @@ enum { #define MMU_FTRS_ALWAYS 0 #endif -static inline bool early_mmu_has_feature(unsigned long feature) +static __always_inline bool early_mmu_has_feature(unsigned long feature) { if (MMU_FTRS_ALWAYS & feature) return true; @@ -286,7 +286,7 @@ static inline void mmu_feature_keys_init(void) } -static inline bool mmu_has_feature(unsigned long feature) +static __always_inline bool mmu_has_feature(unsigned long feature) { return early_mmu_has_feature(feature); } diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index 975ba260006a46755670884e9f15363ac4683c30..1499e928ea6a62663b44d8116c2114a974e4b235 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -195,7 +195,7 @@ static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) #define TRAP_FLAGS_MASK 0x11 #define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK) #define FULL_REGS(regs) (((regs)->trap & 1) == 0) -#define SET_FULL_REGS(regs) ((regs)->trap |= 1) +#define SET_FULL_REGS(regs) ((regs)->trap &= ~1) #endif #define CHECK_FULL_REGS(regs) BUG_ON(!FULL_REGS(regs)) #define NV_REG_POISON 0xdeadbeefdeadbeefUL @@ -210,7 +210,7 @@ static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) #define TRAP_FLAGS_MASK 0x1F #define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK) #define FULL_REGS(regs) (((regs)->trap & 1) == 0) -#define SET_FULL_REGS(regs) ((regs)->trap |= 1) +#define SET_FULL_REGS(regs) ((regs)->trap &= ~1) #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) #define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h index fdab934283721f3033304a646fe44636425765c1..9d1fbd8be1c74277ce69c3c095755659aa8a3340 100644 --- a/arch/powerpc/include/asm/switch_to.h +++ b/arch/powerpc/include/asm/switch_to.h @@ -71,6 +71,16 @@ static inline void disable_kernel_vsx(void) { msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); } +#else +static inline void enable_kernel_vsx(void) +{ + BUILD_BUG(); +} + +static inline void disable_kernel_vsx(void) +{ + BUILD_BUG(); +} #endif #ifdef CONFIG_SPE diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h index 0cf52746531bedb28ae6b0b439ea483b3b06f3fa..721c0d6715ac8f7599740355b312d397adc28894 100644 --- a/arch/powerpc/include/asm/vio.h +++ b/arch/powerpc/include/asm/vio.h @@ -113,7 +113,7 @@ struct vio_driver { const char *name; const struct vio_device_id *id_table; int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); - int (*remove)(struct vio_dev *dev); + void (*remove)(struct vio_dev *dev); /* A driver must have a get_desired_dma() function to * be loaded in a CMO environment if it uses DMA. */ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 60d3051a8bc8ad3638d9d0696441311f08fd9e89..8082b690e87468b92b33238549ea50426560202c 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -466,7 +466,7 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) ld r10,PACAKMSR(r13) /* get MSR value for kernel */ /* MSR[RI] is clear iff using SRR regs */ - .if IHSRR == EXC_HV_OR_STD + .if IHSRR_IF_HVMODE BEGIN_FTR_SECTION xori r10,r10,MSR_RI END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/head_book3s_32.S index 727fdab557c9b70ab6c2dc350b8ba9b786da0adb..565e84e20a7214c5485fa143b33755e22ab0542a 100644 --- a/arch/powerpc/kernel/head_book3s_32.S +++ b/arch/powerpc/kernel/head_book3s_32.S @@ -457,11 +457,12 @@ InstructionTLBMiss: cmplw 0,r1,r3 #endif mfspr r2, SPRN_SDR1 - li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC + li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | _PAGE_USER rlwinm r2, r2, 28, 0xfffff000 #ifdef CONFIG_MODULES bgt- 112f lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ + li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */ #endif 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ @@ -520,10 +521,11 @@ DataLoadTLBMiss: lis r1, TASK_SIZE@h /* check if kernel address */ cmplw 0,r1,r3 mfspr r2, SPRN_SDR1 - li r1, _PAGE_PRESENT | _PAGE_ACCESSED + li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER rlwinm r2, r2, 28, 0xfffff000 bgt- 112f lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ + li r1, _PAGE_PRESENT | _PAGE_ACCESSED addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */ 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ lwz r2,0(r2) /* get pmd entry */ @@ -597,10 +599,11 @@ DataStoreTLBMiss: lis r1, TASK_SIZE@h /* check if kernel address */ cmplw 0,r1,r3 mfspr r2, SPRN_SDR1 - li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED + li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER rlwinm r2, r2, 28, 0xfffff000 bgt- 112f lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ + li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */ 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ lwz r2,0(r2) /* get pmd entry */ diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c index 398cd86b6ada15514774666dbcfcebc7bd178a33..c475a229a42ac492298313b485684e8d541a4139 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -149,7 +149,7 @@ notrace long system_call_exception(long r3, long r4, long r5, * enabled when the interrupt handler returns (indicating a process-context / * synchronous interrupt) then irqs_enabled should be true. */ -static notrace inline bool __prep_irq_for_enabled_exit(bool clear_ri) +static notrace __always_inline bool __prep_irq_for_enabled_exit(bool clear_ri) { /* This must be done with RI=1 because tracing may touch vmaps */ trace_hardirqs_on(); @@ -436,7 +436,6 @@ notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned return ret; } -void unrecoverable_exception(struct pt_regs *regs); void preempt_schedule_irq(void); notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsigned long msr) diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 1583fd1c60103c2d2a230fff481b8d81fa147260..a44a30b0688ca5957a8a1265ab23a0add1ebc13e 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -2170,7 +2170,7 @@ DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) * in the MSR is 0. This indicates that SRR0/1 are live, and that * we therefore lost state by taking this exception. */ -DEFINE_INTERRUPT_HANDLER(unrecoverable_exception) +void unrecoverable_exception(struct pt_regs *regs) { pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", regs->trap, regs->nip, regs->msr); diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index bb5c20d4ca91c2423869372306d3d12e95d576fe..c6aebc149d14129ca17a23a1d289bb8cde827131 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -904,7 +904,7 @@ static nokprobe_inline int do_vsx_load(struct instruction_op *op, if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) return -EFAULT; - nr_vsx_regs = size / sizeof(__vector128); + nr_vsx_regs = max(1ul, size / sizeof(__vector128)); emulate_vsx_load(op, buf, mem, cross_endian); preempt_disable(); if (reg < 32) { @@ -951,7 +951,7 @@ static nokprobe_inline int do_vsx_store(struct instruction_op *op, if (!address_ok(regs, ea, size)) return -EFAULT; - nr_vsx_regs = size / sizeof(__vector128); + nr_vsx_regs = max(1ul, size / sizeof(__vector128)); preempt_disable(); if (reg < 32) { /* FP regs + extensions */ diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 6817331e22ffcbea822fa293fbe122c73e5fbd02..766f064f00fbf25322016546e2bd0c81fe3466eb 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -222,7 +222,7 @@ static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs * if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) *addrp = mfspr(SPRN_SDAR); - if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0) + if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel) *addrp = 0; } @@ -507,7 +507,7 @@ static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events * * addresses, hence include a check before filtering code */ if (!(ppmu->flags & PPMU_ARCH_31) && - is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0) + is_kernel_addr(addr) && event->attr.exclude_kernel) continue; /* Branches are read most recent first (ie. mfbhrb 0 is diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index b3ac2455faadc51cdfcb45a251dc112d1df0a5d4..637300330507fe5a678a5f98d28c94ec5d8e8c77 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c @@ -4,6 +4,7 @@ * Copyright 2006-2007 Michael Ellerman, IBM Corp. */ +#include #include #include #include @@ -458,8 +459,28 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type) return hwirq; } - virq = irq_create_mapping_affinity(NULL, hwirq, - entry->affinity); + /* + * Depending on the number of online CPUs in the original + * kernel, it is likely for CPU #0 to be offline in a kdump + * kernel. The associated IRQs in the affinity mappings + * provided by irq_create_affinity_masks() are thus not + * started by irq_startup(), as per-design for managed IRQs. + * This can be a problem with multi-queue block devices driven + * by blk-mq : such a non-started IRQ is very likely paired + * with the single queue enforced by blk-mq during kdump (see + * blk_mq_alloc_tag_set()). This causes the device to remain + * silent and likely hangs the guest at some point. + * + * We don't really care for fine-grained affinity when doing + * kdump actually : simply ignore the pre-computed affinity + * masks in this case and let the default mask with all CPUs + * be used when creating the IRQ mappings. + */ + if (is_kdump_kernel()) + virq = irq_create_mapping(NULL, hwirq); + else + virq = irq_create_mapping_affinity(NULL, hwirq, + entry->affinity); if (!virq) { pr_debug("rtas_msi: Failed mapping hwirq %d\n", hwirq); diff --git a/arch/powerpc/platforms/pseries/vio.c b/arch/powerpc/platforms/pseries/vio.c index b2797cfe4e2b087535a23c13b2132f4e08324419..9cb4fc839fd5d89b3ec9426cfce7fe82742757d6 100644 --- a/arch/powerpc/platforms/pseries/vio.c +++ b/arch/powerpc/platforms/pseries/vio.c @@ -1261,7 +1261,6 @@ static int vio_bus_remove(struct device *dev) struct vio_dev *viodev = to_vio_dev(dev); struct vio_driver *viodrv = to_vio_driver(dev->driver); struct device *devptr; - int ret = 1; /* * Hold a reference to the device after the remove function is called @@ -1270,13 +1269,13 @@ static int vio_bus_remove(struct device *dev) devptr = get_device(dev); if (viodrv->remove) - ret = viodrv->remove(viodev); + viodrv->remove(viodev); - if (!ret && firmware_has_feature(FW_FEATURE_CMO)) + if (firmware_has_feature(FW_FEATURE_CMO)) vio_cmo_bus_remove(viodev); put_device(devptr); - return ret; + return 0; } /** diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig index 02056b024091eb95ade5612922fa1616e9077b3d..dc0b69058ac47556b91846f1aae702d05b8e52e6 100644 --- a/arch/s390/configs/debug_defconfig +++ b/arch/s390/configs/debug_defconfig @@ -275,9 +275,9 @@ CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m -CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y CONFIG_IP_NF_IPTABLES=m @@ -298,7 +298,6 @@ CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_FIB_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m @@ -481,7 +480,6 @@ CONFIG_NLMON=m # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set @@ -581,7 +579,6 @@ CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=y CONFIG_VHOST_NET=m CONFIG_VHOST_VSOCK=m -# CONFIG_SURFACE_PLATFORMS is not set CONFIG_S390_CCW_IOMMU=y CONFIG_S390_AP_IOMMU=y CONFIG_EXT4_FS=y @@ -635,6 +632,7 @@ CONFIG_NTFS_RW=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y CONFIG_HUGETLBFS=y CONFIG_CONFIGFS_FS=m CONFIG_ECRYPT_FS=m @@ -714,12 +712,8 @@ CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_CRC32=m CONFIG_CRYPTO_BLAKE2S=m CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m @@ -731,7 +725,6 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m @@ -796,12 +789,9 @@ CONFIG_DEBUG_OBJECTS_RCU_HEAD=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_SLUB_DEBUG_ON=y CONFIG_SLUB_STATS=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_VMACACHE=y -CONFIG_DEBUG_VM_RB=y CONFIG_DEBUG_VM_PGFLAGS=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m @@ -838,6 +828,7 @@ CONFIG_BPF_KPROBE_OVERRIDE=y CONFIG_HIST_TRIGGERS=y CONFIG_FTRACE_STARTUP_TEST=y # CONFIG_EVENT_TRACE_STARTUP_TEST is not set +CONFIG_DEBUG_ENTRY=y CONFIG_NOTIFIER_ERROR_INJECTION=m CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m CONFIG_FAULT_INJECTION=y @@ -861,4 +852,3 @@ CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_TEST_BITOPS=m CONFIG_TEST_BPF=m -CONFIG_DEBUG_ENTRY=y diff --git a/arch/s390/configs/defconfig b/arch/s390/configs/defconfig index bac721a501da16a47313922369f4a61fff427a18..320379da96d97536fe563a5c09c0aa53acc642ef 100644 --- a/arch/s390/configs/defconfig +++ b/arch/s390/configs/defconfig @@ -266,9 +266,9 @@ CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m -CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y CONFIG_IP_NF_IPTABLES=m @@ -289,7 +289,6 @@ CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_FIB_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m @@ -473,7 +472,6 @@ CONFIG_NLMON=m # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set @@ -573,7 +571,6 @@ CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=y CONFIG_VHOST_NET=m CONFIG_VHOST_VSOCK=m -# CONFIG_SURFACE_PLATFORMS is not set CONFIG_S390_CCW_IOMMU=y CONFIG_S390_AP_IOMMU=y CONFIG_EXT4_FS=y @@ -623,6 +620,7 @@ CONFIG_NTFS_RW=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y CONFIG_HUGETLBFS=y CONFIG_CONFIGFS_FS=m CONFIG_ECRYPT_FS=m @@ -703,12 +701,8 @@ CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_CRC32=m CONFIG_CRYPTO_BLAKE2S=m CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m @@ -720,7 +714,6 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m diff --git a/arch/s390/configs/zfcpdump_defconfig b/arch/s390/configs/zfcpdump_defconfig index acf982a2ae4c5eb1e86bdc837243adfa6da41274..76123a4b26ab06f221c209734b1b97b38cc1e46a 100644 --- a/arch/s390/configs/zfcpdump_defconfig +++ b/arch/s390/configs/zfcpdump_defconfig @@ -26,7 +26,6 @@ CONFIG_CRASH_DUMP=y # CONFIG_SECCOMP is not set # CONFIG_GCC_PLUGINS is not set CONFIG_PARTITION_ADVANCED=y -CONFIG_IBM_PARTITION=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPACTION is not set # CONFIG_MIGRATION is not set @@ -61,11 +60,9 @@ CONFIG_RAW_DRIVER=y # CONFIG_HID is not set # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set -# CONFIG_SURFACE_PLATFORMS is not set # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set -CONFIG_CONFIGFS_FS=y # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_LSM="yama,loadpin,safesetid,integrity" diff --git a/arch/s390/include/asm/idle.h b/arch/s390/include/asm/idle.h index b04f6a794cdfb5d696c9c9dc29e9e35f66e3a00b..5cea629c548e2d53635b4a1a6e175e98e38ca908 100644 --- a/arch/s390/include/asm/idle.h +++ b/arch/s390/include/asm/idle.h @@ -14,12 +14,12 @@ struct s390_idle_data { seqcount_t seqcount; - unsigned long long idle_count; - unsigned long long idle_time; - unsigned long long clock_idle_enter; - unsigned long long clock_idle_exit; - unsigned long long timer_idle_enter; - unsigned long long timer_idle_exit; + unsigned long idle_count; + unsigned long idle_time; + unsigned long clock_idle_enter; + unsigned long clock_idle_exit; + unsigned long timer_idle_enter; + unsigned long timer_idle_exit; unsigned long mt_cycles_enter[8]; }; diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index c4e23e92566546ffe7d082202e33c3fc576d6bc5..f6326c6d2abe83536a340f0829b95cdd6cdb4f7b 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -98,10 +98,10 @@ extern unsigned char ptff_function_mask[16]; /* Query TOD offset result */ struct ptff_qto { - unsigned long long physical_clock; - unsigned long long tod_offset; - unsigned long long logical_tod_offset; - unsigned long long tod_epoch_difference; + unsigned long physical_clock; + unsigned long tod_offset; + unsigned long logical_tod_offset; + unsigned long tod_epoch_difference; } __packed; static inline int ptff_query(unsigned int nr) @@ -151,9 +151,9 @@ struct ptff_qui { rc; \ }) -static inline unsigned long long local_tick_disable(void) +static inline unsigned long local_tick_disable(void) { - unsigned long long old; + unsigned long old; old = S390_lowcore.clock_comparator; S390_lowcore.clock_comparator = clock_comparator_max; @@ -161,7 +161,7 @@ static inline unsigned long long local_tick_disable(void) return old; } -static inline void local_tick_enable(unsigned long long comp) +static inline void local_tick_enable(unsigned long comp) { S390_lowcore.clock_comparator = comp; set_clock_comparator(S390_lowcore.clock_comparator); @@ -169,9 +169,9 @@ static inline void local_tick_enable(unsigned long long comp) #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ -typedef unsigned long long cycles_t; +typedef unsigned long cycles_t; -static inline unsigned long long get_tod_clock(void) +static inline unsigned long get_tod_clock(void) { union tod_clock clk; @@ -179,10 +179,10 @@ static inline unsigned long long get_tod_clock(void) return clk.tod; } -static inline unsigned long long get_tod_clock_fast(void) +static inline unsigned long get_tod_clock_fast(void) { #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES - unsigned long long clk; + unsigned long clk; asm volatile("stckf %0" : "=Q" (clk) : : "cc"); return clk; @@ -208,9 +208,9 @@ extern union tod_clock tod_clock_base; * Therefore preemption must be disabled, otherwise the returned * value is not guaranteed to be monotonic. */ -static inline unsigned long long get_tod_clock_monotonic(void) +static inline unsigned long get_tod_clock_monotonic(void) { - unsigned long long tod; + unsigned long tod; preempt_disable_notrace(); tod = get_tod_clock() - tod_clock_base.tod; @@ -237,7 +237,7 @@ static inline unsigned long long get_tod_clock_monotonic(void) * -> ns = (th * 125) + ((tl * 125) >> 9); * */ -static inline unsigned long long tod_to_ns(unsigned long long todval) +static inline unsigned long tod_to_ns(unsigned long todval) { return ((todval >> 9) * 125) + (((todval & 0x1ff) * 125) >> 9); } @@ -249,10 +249,10 @@ static inline unsigned long long tod_to_ns(unsigned long long todval) * * Returns: true if a is later than b */ -static inline int tod_after(unsigned long long a, unsigned long long b) +static inline int tod_after(unsigned long a, unsigned long b) { if (MACHINE_HAS_SCC) - return (long long) a > (long long) b; + return (long) a > (long) b; return a > b; } @@ -263,10 +263,10 @@ static inline int tod_after(unsigned long long a, unsigned long long b) * * Returns: true if a is later than b */ -static inline int tod_after_eq(unsigned long long a, unsigned long long b) +static inline int tod_after_eq(unsigned long a, unsigned long b) { if (MACHINE_HAS_SCC) - return (long long) a >= (long long) b; + return (long) a >= (long) b; return a >= b; } diff --git a/arch/s390/include/uapi/asm/perf_cpum_cf_diag.h b/arch/s390/include/uapi/asm/hwctrset.h similarity index 100% rename from arch/s390/include/uapi/asm/perf_cpum_cf_diag.h rename to arch/s390/include/uapi/asm/hwctrset.h diff --git a/arch/s390/kernel/idle.c b/arch/s390/kernel/idle.c index 812073ea073ee23e571041d12e528ab2769c4395..4bf1ee293f2b31ee3d5ae06cbe9afd7baa6d37db 100644 --- a/arch/s390/kernel/idle.c +++ b/arch/s390/kernel/idle.c @@ -47,7 +47,7 @@ void account_idle_time_irq(void) void arch_cpu_idle(void) { struct s390_idle_data *idle = this_cpu_ptr(&s390_idle); - unsigned long long idle_time; + unsigned long idle_time; unsigned long psw_mask; /* Wait for external, I/O or machine check interrupt. */ @@ -73,7 +73,7 @@ static ssize_t show_idle_count(struct device *dev, struct device_attribute *attr, char *buf) { struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); - unsigned long long idle_count; + unsigned long idle_count; unsigned int seq; do { @@ -82,14 +82,14 @@ static ssize_t show_idle_count(struct device *dev, if (READ_ONCE(idle->clock_idle_enter)) idle_count++; } while (read_seqcount_retry(&idle->seqcount, seq)); - return sprintf(buf, "%llu\n", idle_count); + return sprintf(buf, "%lu\n", idle_count); } DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); static ssize_t show_idle_time(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long long now, idle_time, idle_enter, idle_exit, in_idle; + unsigned long now, idle_time, idle_enter, idle_exit, in_idle; struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); unsigned int seq; @@ -109,14 +109,14 @@ static ssize_t show_idle_time(struct device *dev, } } idle_time += in_idle; - return sprintf(buf, "%llu\n", idle_time >> 12); + return sprintf(buf, "%lu\n", idle_time >> 12); } DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); u64 arch_cpu_idle_time(int cpu) { struct s390_idle_data *idle = &per_cpu(s390_idle, cpu); - unsigned long long now, idle_enter, idle_exit, in_idle; + unsigned long now, idle_enter, idle_exit, in_idle; unsigned int seq; do { diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 0eb1d1cc53a88380421468f5daa6ec1f842328e2..b3beef64d3d48776667c5d8d851d83ff98f545d2 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -269,7 +269,7 @@ static int __hw_perf_event_init(struct perf_event *event, unsigned int type) case CPUMF_CTR_SET_MAX: /* The counter could not be associated to a counter set */ return -EINVAL; - }; + } /* Initialize for using the CPU-measurement counter facility */ if (!atomic_inc_not_zero(&num_events)) { diff --git a/arch/s390/kernel/perf_cpum_cf_diag.c b/arch/s390/kernel/perf_cpum_cf_diag.c index db4877bbb9aa5626702bf6068de92accdaa9e81a..bc302b86ce28fcd88cd5341d390a6360ce3d265b 100644 --- a/arch/s390/kernel/perf_cpum_cf_diag.c +++ b/arch/s390/kernel/perf_cpum_cf_diag.c @@ -26,12 +26,10 @@ #include #include -#include +#include #define CF_DIAG_CTRSET_DEF 0xfeef /* Counter set header mark */ -#define CF_DIAG_MIN_INTERVAL 60 /* Minimum counter set read */ /* interval in seconds */ -static unsigned long cf_diag_interval = CF_DIAG_MIN_INTERVAL; static unsigned int cf_diag_cpu_speed; static debug_info_t *cf_diag_dbg; @@ -729,7 +727,6 @@ static DEFINE_MUTEX(cf_diag_ctrset_mutex); static struct cf_diag_ctrset { unsigned long ctrset; /* Bit mask of counter set to read */ cpumask_t mask; /* CPU mask to read from */ - time64_t lastread; /* Epoch counter set last read */ } cf_diag_ctrset; static void cf_diag_ctrset_clear(void) @@ -866,27 +863,16 @@ static int cf_diag_all_read(unsigned long arg) { struct cf_diag_call_on_cpu_parm p; cpumask_var_t mask; - time64_t now; - int rc = 0; + int rc; debug_sprintf_event(cf_diag_dbg, 5, "%s\n", __func__); if (!alloc_cpumask_var(&mask, GFP_KERNEL)) return -ENOMEM; - now = ktime_get_seconds(); - if (cf_diag_ctrset.lastread + cf_diag_interval > now) { - debug_sprintf_event(cf_diag_dbg, 5, "%s now %lld " - " lastread %lld\n", __func__, now, - cf_diag_ctrset.lastread); - rc = -EAGAIN; - goto out; - } else { - cf_diag_ctrset.lastread = now; - } + p.sets = cf_diag_ctrset.ctrset; cpumask_and(mask, &cf_diag_ctrset.mask, cpu_online_mask); on_each_cpu_mask(mask, cf_diag_cpu_read, &p, 1); rc = cf_diag_all_copy(arg, mask); -out: free_cpumask_var(mask); debug_sprintf_event(cf_diag_dbg, 5, "%s rc %d\n", __func__, rc); return rc; diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 06bcfa6366384e3145e4dd469d4dfa6641a7d924..165da961f9019adf641c6568a2cc4c853862a007 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -68,10 +68,10 @@ EXPORT_SYMBOL(s390_epoch_delta_notifier); unsigned char ptff_function_mask[16]; -static unsigned long long lpar_offset; -static unsigned long long initial_leap_seconds; -static unsigned long long tod_steering_end; -static long long tod_steering_delta; +static unsigned long lpar_offset; +static unsigned long initial_leap_seconds; +static unsigned long tod_steering_end; +static long tod_steering_delta; /* * Get time offsets with PTFF @@ -96,7 +96,7 @@ void __init time_early_init(void) /* get initial leap seconds */ if (ptff_query(PTFF_QUI) && ptff(&qui, sizeof(qui), PTFF_QUI) == 0) - initial_leap_seconds = (unsigned long long) + initial_leap_seconds = (unsigned long) ((long) qui.old_leap * 4096000000L); } @@ -222,7 +222,7 @@ void __init read_persistent_wall_and_boot_offset(struct timespec64 *wall_time, static u64 read_tod_clock(struct clocksource *cs) { - unsigned long long now, adj; + unsigned long now, adj; preempt_disable(); /* protect from changes to steering parameters */ now = get_tod_clock(); @@ -362,7 +362,7 @@ static inline int check_sync_clock(void) * Apply clock delta to the global data structures. * This is called once on the CPU that performed the clock sync. */ -static void clock_sync_global(unsigned long long delta) +static void clock_sync_global(unsigned long delta) { unsigned long now, adj; struct ptff_qto qto; @@ -378,7 +378,7 @@ static void clock_sync_global(unsigned long long delta) -(adj >> 15) : (adj >> 15); tod_steering_delta += delta; if ((abs(tod_steering_delta) >> 48) != 0) - panic("TOD clock sync offset %lli is too large to drift\n", + panic("TOD clock sync offset %li is too large to drift\n", tod_steering_delta); tod_steering_end = now + (abs(tod_steering_delta) << 15); vdso_data->arch_data.tod_steering_end = tod_steering_end; @@ -394,7 +394,7 @@ static void clock_sync_global(unsigned long long delta) * Apply clock delta to the per-CPU data structures of this CPU. * This is called for each online CPU after the call to clock_sync_global. */ -static void clock_sync_local(unsigned long long delta) +static void clock_sync_local(unsigned long delta) { /* Add the delta to the clock comparator. */ if (S390_lowcore.clock_comparator != clock_comparator_max) { @@ -418,7 +418,7 @@ static void __init time_init_wq(void) struct clock_sync_data { atomic_t cpus; int in_sync; - unsigned long long clock_delta; + unsigned long clock_delta; }; /* @@ -538,7 +538,7 @@ static int stpinfo_valid(void) static int stp_sync_clock(void *data) { struct clock_sync_data *sync = data; - unsigned long long clock_delta, flags; + u64 clock_delta, flags; static int first; int rc; @@ -720,8 +720,8 @@ static ssize_t ctn_id_show(struct device *dev, mutex_lock(&stp_mutex); if (stpinfo_valid()) - ret = sprintf(buf, "%016llx\n", - *(unsigned long long *) stp_info.ctnid); + ret = sprintf(buf, "%016lx\n", + *(unsigned long *) stp_info.ctnid); mutex_unlock(&stp_mutex); return ret; } @@ -794,7 +794,7 @@ static ssize_t leap_seconds_scheduled_show(struct device *dev, if (!stzi.lsoib.p) return sprintf(buf, "0,0\n"); - return sprintf(buf, "%llu,%d\n", + return sprintf(buf, "%lu,%d\n", tod_to_ns(stzi.lsoib.nlsout - TOD_UNIX_EPOCH) / NSEC_PER_SEC, stzi.lsoib.nlso - stzi.lsoib.also); } diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index e7ce447651b905c20dce60dfc41555ee359d5d55..bfcc327acc6b2ebfec38f7fe0e3a3bd39e73f4f6 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -76,8 +76,6 @@ static void cpu_group_map(cpumask_t *dst, struct mask_info *info, unsigned int c } info = info->next; } - if (cpumask_empty(&mask)) - cpumask_copy(&mask, cpumask_of(cpu)); break; case TOPOLOGY_MODE_PACKAGE: cpumask_copy(&mask, cpu_present_mask); diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index e3183bd059107a04f7695ee707da18f1bea2153d..d548d60caed252021c6abb532e546a79184741fb 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -1287,7 +1287,7 @@ static u64 __calculate_sltime(struct kvm_vcpu *vcpu) /* already expired? */ if (cputm >> 63) return 0; - return min(sltime, tod_to_ns(cputm)); + return min_t(u64, sltime, tod_to_ns(cputm)); } } else if (cpu_timer_interrupts_enabled(vcpu)) { sltime = kvm_s390_get_cpu_timer(vcpu); diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig index 148f44b33890e220039f1f345b8ccfaf4a9f0006..12a4fb0bd52aa41d2865e49450b7c4b6ad4b1656 100644 --- a/arch/sparc/configs/sparc64_defconfig +++ b/arch/sparc/configs/sparc64_defconfig @@ -93,7 +93,7 @@ CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_MII=m CONFIG_SUNLANCE=m -CONFIG_HAPPYMEAL=m +CONFIG_HAPPYMEAL=y CONFIG_SUNGEM=m CONFIG_SUNVNET=m CONFIG_LDMVSW=m @@ -234,9 +234,7 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRC16=m CONFIG_LIBCRC32C=m CONFIG_VCC=m -CONFIG_ATA=y CONFIG_PATA_CMD64X=y -CONFIG_HAPPYMEAL=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_DEVTMPFS=y diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h index 7e078bc73ef5616d8f0a94f070246d203c4f6e14..8fb09eec8c3e796a9a79aa0a7877842ceb7ea6d3 100644 --- a/arch/sparc/include/asm/elf_64.h +++ b/arch/sparc/include/asm/elf_64.h @@ -8,7 +8,6 @@ #include #include -#include #include #include diff --git a/arch/sparc/include/asm/extable_64.h b/arch/sparc/include/asm/extable.h similarity index 92% rename from arch/sparc/include/asm/extable_64.h rename to arch/sparc/include/asm/extable.h index 5a0171907b7e5dac71055aba5d48d7ef591f901b..554a9dc376fc8efabf4ee0aaf884bd90ece5abc8 100644 --- a/arch/sparc/include/asm/extable_64.h +++ b/arch/sparc/include/asm/extable.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_EXTABLE64_H -#define __ASM_EXTABLE64_H +#ifndef __ASM_EXTABLE_H +#define __ASM_EXTABLE_H /* * The exception table consists of pairs of addresses: the first is the * address of an instruction that is allowed to fault, and the second is diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm/processor_32.h index 3c4bc2189092d350b7b6e2c794714f6c7249f692..b6242f7771e9e845ab9a24720e99f66a86c8ae51 100644 --- a/arch/sparc/include/asm/processor_32.h +++ b/arch/sparc/include/asm/processor_32.h @@ -50,16 +50,12 @@ struct thread_struct { unsigned long fsr; unsigned long fpqdepth; struct fpq fpqueue[16]; - unsigned long flags; mm_segment_t current_ds; }; -#define SPARC_FLAG_KTHREAD 0x1 /* task is a kernel thread */ -#define SPARC_FLAG_UNALIGNED 0x2 /* is allowed to do unaligned accesses */ - #define INIT_THREAD { \ - .flags = SPARC_FLAG_KTHREAD, \ .current_ds = KERNEL_DS, \ + .kregs = (struct pt_regs *)(init_stack+THREAD_SIZE)-1 \ } /* Do necessary setup to start up a newly executed thread. */ diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h index 42cd4cd3892e32a9adacad7ba1d4fb208369691c..8047a9caab2fc86a35e684a98e2c1deff54e923a 100644 --- a/arch/sparc/include/asm/thread_info_64.h +++ b/arch/sparc/include/asm/thread_info_64.h @@ -118,6 +118,7 @@ struct thread_info { .task = &tsk, \ .current_ds = ASI_P, \ .preempt_count = INIT_PREEMPT_COUNT, \ + .kregs = (struct pt_regs *)(init_stack+THREAD_SIZE)-1 \ } /* how to get the thread information struct from C */ diff --git a/arch/sparc/include/asm/uaccess.h b/arch/sparc/include/asm/uaccess.h index dd85bc2c2cad5211c19695362bba874e0ce17b3c..390094200fc44212187f7909d74b3079ed639d6e 100644 --- a/arch/sparc/include/asm/uaccess.h +++ b/arch/sparc/include/asm/uaccess.h @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef ___ASM_SPARC_UACCESS_H #define ___ASM_SPARC_UACCESS_H + +#include + #if defined(__sparc__) && defined(__arch64__) #include #else diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h index 0a2d3ebc4bb86d349bf5455bc05d7868f6da495e..4a12346bb69c335d06bc4e30b98244ced13a46e3 100644 --- a/arch/sparc/include/asm/uaccess_32.h +++ b/arch/sparc/include/asm/uaccess_32.h @@ -13,9 +13,6 @@ #include -#define ARCH_HAS_SORT_EXTABLE -#define ARCH_HAS_SEARCH_EXTABLE - /* Sparc is not segmented, however we need to be able to fool access_ok() * when doing system calls from kernel mode legitimately. * @@ -40,36 +37,6 @@ #define __access_ok(addr, size) (__user_ok((addr) & get_fs().seg, (size))) #define access_ok(addr, size) __access_ok((unsigned long)(addr), size) -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - * - * There is a special way how to put a range of potentially faulting - * insns (like twenty ldd/std's with now intervening other instructions) - * You specify address of first in insn and 0 in fixup and in the next - * exception_table_entry you specify last potentially faulting insn + 1 - * and in fixup the routine which should handle the fault. - * That fixup code will get - * (faulting_insn_address - first_insn_in_the_range_address)/4 - * in %g2 (ie. index of the faulting instruction in the range). - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -/* Returns 0 if exception not found and fixup otherwise. */ -unsigned long search_extables_range(unsigned long addr, unsigned long *g2); - /* Uh, these should become the main single-value transfer routines.. * They automatically use the right size if we just have the right * pointer type.. @@ -252,12 +219,7 @@ static inline unsigned long __clear_user(void __user *addr, unsigned long size) unsigned long ret; __asm__ __volatile__ ( - ".section __ex_table,#alloc\n\t" - ".align 4\n\t" - ".word 1f,3\n\t" - ".previous\n\t" "mov %2, %%o1\n" - "1:\n\t" "call __bzero\n\t" " mov %1, %%o0\n\t" "mov %%o0, %0\n" diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h index 698cf69f74e9984d54bca056bcd6470df7b88c1e..30eb4c6414d1baf9ae792726bf8c652d6085e61e 100644 --- a/arch/sparc/include/asm/uaccess_64.h +++ b/arch/sparc/include/asm/uaccess_64.h @@ -10,7 +10,6 @@ #include #include #include -#include #include diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S index be30c8d4cc7373490ed5f8c2ff716aae22f56574..6044b82b976751a8ccbe43ac424bafe8de36af42 100644 --- a/arch/sparc/kernel/head_32.S +++ b/arch/sparc/kernel/head_32.S @@ -515,7 +515,7 @@ continue_boot: /* I want a kernel stack NOW! */ set init_thread_union, %g1 - set (THREAD_SIZE - STACKFRAME_SZ), %g2 + set (THREAD_SIZE - STACKFRAME_SZ - TRACEREG_SZ), %g2 add %g1, %g2, %sp mov 0, %fp /* And for good luck */ diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index c5ff2472b3d9d4e53385da0536802b387f123f75..72a5bdc833ea22f0800663c354cba188fad83243 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -706,7 +706,7 @@ tlb_fixup_done: wr %g0, ASI_P, %asi mov 1, %g1 sllx %g1, THREAD_SHIFT, %g1 - sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 + sub %g1, (STACKFRAME_SZ + STACK_BIAS + TRACEREG_SZ), %g1 add %g6, %g1, %sp /* Set per-cpu pointer initially to zero, this makes diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c index b91e88058e0ce39675eb095c9c4876e4ea44ad97..3b9794978e5bc97c3cc4c536dc43e2dacb6d5a58 100644 --- a/arch/sparc/kernel/process_32.c +++ b/arch/sparc/kernel/process_32.c @@ -216,16 +216,6 @@ void flush_thread(void) clear_thread_flag(TIF_USEDFPU); #endif } - - /* This task is no longer a kernel thread. */ - if (current->thread.flags & SPARC_FLAG_KTHREAD) { - current->thread.flags &= ~SPARC_FLAG_KTHREAD; - - /* We must fixup kregs as well. */ - /* XXX This was not fixed for ti for a while, worked. Unused? */ - current->thread.kregs = (struct pt_regs *) - (task_stack_page(current) + (THREAD_SIZE - TRACEREG_SZ)); - } } static inline struct sparc_stackf __user * @@ -313,7 +303,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, extern int nwindows; unsigned long psr; memset(new_stack, 0, STACKFRAME_SZ + TRACEREG_SZ); - p->thread.flags |= SPARC_FLAG_KTHREAD; p->thread.current_ds = KERNEL_DS; ti->kpc = (((unsigned long) ret_from_kernel_thread) - 0x8); childregs->u_regs[UREG_G1] = sp; /* function */ @@ -325,7 +314,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, } memcpy(new_stack, (char *)regs - STACKFRAME_SZ, STACKFRAME_SZ + TRACEREG_SZ); childregs->u_regs[UREG_FP] = sp; - p->thread.flags &= ~SPARC_FLAG_KTHREAD; p->thread.current_ds = USER_DS; ti->kpc = (((unsigned long) ret_from_fork) - 0x8); ti->kpsr = current->thread.fork_kpsr | PSR_PIL; diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index eea43a1aef1b9a6fd1e4139dbf118d8e4eafc2ee..c8e0dd99f3700e73851878ca44102f1c7d24fe8f 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c @@ -266,7 +266,6 @@ static __init void leon_patch(void) } struct tt_entry *sparc_ttable; -static struct pt_regs fake_swapper_regs; /* Called from head_32.S - before we have setup anything * in the kernel. Be very careful with what you do here. @@ -363,8 +362,6 @@ void __init setup_arch(char **cmdline_p) (*(linux_dbvec->teach_debugger))(); } - init_task.thread.kregs = &fake_swapper_regs; - /* Run-time patch instructions to match the cpu model */ per_cpu_patch(); diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index d87244197d5cbb56fec92223c3b5c7ead0352b63..48abee4eee29d8589d9452029f109e102f63f91a 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c @@ -165,8 +165,6 @@ extern int root_mountflags; char reboot_command[COMMAND_LINE_SIZE]; -static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; - static void __init per_cpu_patch(void) { struct cpuid_patch_entry *p; @@ -661,8 +659,6 @@ void __init setup_arch(char **cmdline_p) rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; #endif - task_thread_info(&init_task)->kregs = &fake_swapper_regs; - #ifdef CONFIG_IP_PNP if (!ic_set_manually) { phandle chosen = prom_finddevice("/chosen"); diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c index d92e5eaa4c1d704be7115f3ab23785153fde1194..a850dccd78ea19c8a9e30f9140884d3d0091b82a 100644 --- a/arch/sparc/kernel/traps_64.c +++ b/arch/sparc/kernel/traps_64.c @@ -275,14 +275,13 @@ bool is_no_fault_exception(struct pt_regs *regs) asi = (regs->tstate >> 24); /* saved %asi */ else asi = (insn >> 5); /* immediate asi */ - if ((asi & 0xf2) == ASI_PNF) { - if (insn & 0x1000000) { /* op3[5:4]=3 */ - handle_ldf_stq(insn, regs); - return true; - } else if (insn & 0x200000) { /* op3[2], stores */ + if ((asi & 0xf6) == ASI_PNF) { + if (insn & 0x200000) /* op3[2], stores */ return false; - } - handle_ld_nf(insn, regs); + if (insn & 0x1000000) /* op3[5:4]=3 (fp) */ + handle_ldf_stq(insn, regs); + else + handle_ld_nf(insn, regs); return true; } } diff --git a/arch/sparc/kernel/unaligned_32.c b/arch/sparc/kernel/unaligned_32.c index 83db94c0b43189e4c938d30878368ee2cbf41c08..ef5c5207c9ffbbee5ef2b339cb0d073d1cc55d2a 100644 --- a/arch/sparc/kernel/unaligned_32.c +++ b/arch/sparc/kernel/unaligned_32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -213,10 +214,10 @@ static inline int ok_for_kernel(unsigned int insn) static void kernel_mna_trap_fault(struct pt_regs *regs, unsigned int insn) { - unsigned long g2 = regs->u_regs [UREG_G2]; - unsigned long fixup = search_extables_range(regs->pc, &g2); + const struct exception_table_entry *entry; - if (!fixup) { + entry = search_exception_tables(regs->pc); + if (!entry) { unsigned long address = compute_effective_address(regs, insn); if(address < PAGE_SIZE) { printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference in mna handler"); @@ -232,9 +233,8 @@ static void kernel_mna_trap_fault(struct pt_regs *regs, unsigned int insn) die_if_kernel("Oops", regs); /* Not reached */ } - regs->pc = fixup; + regs->pc = entry->fixup; regs->npc = regs->pc + 4; - regs->u_regs [UREG_G2] = g2; } asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn) @@ -274,103 +274,9 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn) } } -static inline int ok_for_user(struct pt_regs *regs, unsigned int insn, - enum direction dir) -{ - unsigned int reg; - int size = ((insn >> 19) & 3) == 3 ? 8 : 4; - - if ((regs->pc | regs->npc) & 3) - return 0; - - /* Must access_ok() in all the necessary places. */ -#define WINREG_ADDR(regnum) \ - ((void __user *)(((unsigned long *)regs->u_regs[UREG_FP])+(regnum))) - - reg = (insn >> 25) & 0x1f; - if (reg >= 16) { - if (!access_ok(WINREG_ADDR(reg - 16), size)) - return -EFAULT; - } - reg = (insn >> 14) & 0x1f; - if (reg >= 16) { - if (!access_ok(WINREG_ADDR(reg - 16), size)) - return -EFAULT; - } - if (!(insn & 0x2000)) { - reg = (insn & 0x1f); - if (reg >= 16) { - if (!access_ok(WINREG_ADDR(reg - 16), size)) - return -EFAULT; - } - } -#undef WINREG_ADDR - return 0; -} - -static void user_mna_trap_fault(struct pt_regs *regs, unsigned int insn) +asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn) { send_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)safe_compute_effective_address(regs, insn), 0, current); } - -asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn) -{ - enum direction dir; - - if(!(current->thread.flags & SPARC_FLAG_UNALIGNED) || - (((insn >> 30) & 3) != 3)) - goto kill_user; - dir = decode_direction(insn); - if(!ok_for_user(regs, insn, dir)) { - goto kill_user; - } else { - int err, size = decode_access_size(insn); - unsigned long addr; - - if(floating_point_load_or_store_p(insn)) { - printk("User FPU load/store unaligned unsupported.\n"); - goto kill_user; - } - - addr = compute_effective_address(regs, insn); - perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); - switch(dir) { - case load: - err = do_int_load(fetch_reg_addr(((insn>>25)&0x1f), - regs), - size, (unsigned long *) addr, - decode_signedness(insn)); - break; - - case store: - err = do_int_store(((insn>>25)&0x1f), size, - (unsigned long *) addr, regs); - break; - - case both: - /* - * This was supported in 2.4. However, we question - * the value of SWAP instruction across word boundaries. - */ - printk("Unaligned SWAP unsupported.\n"); - err = -EFAULT; - break; - - default: - unaligned_panic("Impossible user unaligned trap."); - goto out; - } - if (err) - goto kill_user; - else - advance(regs); - goto out; - } - -kill_user: - user_mna_trap_fault(regs, insn); -out: - ; -} diff --git a/arch/sparc/lib/checksum_32.S b/arch/sparc/lib/checksum_32.S index 7488d130faf730d6e96414ce987ff4a5e8b37ca6..781e39b3c009f9b27e886f6a6e07e6d2f5545108 100644 --- a/arch/sparc/lib/checksum_32.S +++ b/arch/sparc/lib/checksum_32.S @@ -155,13 +155,6 @@ cpout: retl ! get outta here .text; \ .align 4 -#define EXT(start,end) \ - .section __ex_table,ALLOC; \ - .align 4; \ - .word start, 0, end, cc_fault; \ - .text; \ - .align 4 - /* This aligned version executes typically in 8.5 superscalar cycles, this * is the best I can do. I say 8.5 because the final add will pair with * the next ldd in the main unrolled loop. Thus the pipe is always full. @@ -169,20 +162,20 @@ cpout: retl ! get outta here * please check the fixup code below as well. */ #define CSUMCOPY_BIGCHUNK_ALIGNED(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ - ldd [src + off + 0x00], t0; \ - ldd [src + off + 0x08], t2; \ + EX(ldd [src + off + 0x00], t0); \ + EX(ldd [src + off + 0x08], t2); \ addxcc t0, sum, sum; \ - ldd [src + off + 0x10], t4; \ + EX(ldd [src + off + 0x10], t4); \ addxcc t1, sum, sum; \ - ldd [src + off + 0x18], t6; \ + EX(ldd [src + off + 0x18], t6); \ addxcc t2, sum, sum; \ - std t0, [dst + off + 0x00]; \ + EX(std t0, [dst + off + 0x00]); \ addxcc t3, sum, sum; \ - std t2, [dst + off + 0x08]; \ + EX(std t2, [dst + off + 0x08]); \ addxcc t4, sum, sum; \ - std t4, [dst + off + 0x10]; \ + EX(std t4, [dst + off + 0x10]); \ addxcc t5, sum, sum; \ - std t6, [dst + off + 0x18]; \ + EX(std t6, [dst + off + 0x18]); \ addxcc t6, sum, sum; \ addxcc t7, sum, sum; @@ -191,39 +184,39 @@ cpout: retl ! get outta here * Viking MXCC into streaming mode. Ho hum... */ #define CSUMCOPY_BIGCHUNK(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ - ldd [src + off + 0x00], t0; \ - ldd [src + off + 0x08], t2; \ - ldd [src + off + 0x10], t4; \ - ldd [src + off + 0x18], t6; \ - st t0, [dst + off + 0x00]; \ + EX(ldd [src + off + 0x00], t0); \ + EX(ldd [src + off + 0x08], t2); \ + EX(ldd [src + off + 0x10], t4); \ + EX(ldd [src + off + 0x18], t6); \ + EX(st t0, [dst + off + 0x00]); \ addxcc t0, sum, sum; \ - st t1, [dst + off + 0x04]; \ + EX(st t1, [dst + off + 0x04]); \ addxcc t1, sum, sum; \ - st t2, [dst + off + 0x08]; \ + EX(st t2, [dst + off + 0x08]); \ addxcc t2, sum, sum; \ - st t3, [dst + off + 0x0c]; \ + EX(st t3, [dst + off + 0x0c]); \ addxcc t3, sum, sum; \ - st t4, [dst + off + 0x10]; \ + EX(st t4, [dst + off + 0x10]); \ addxcc t4, sum, sum; \ - st t5, [dst + off + 0x14]; \ + EX(st t5, [dst + off + 0x14]); \ addxcc t5, sum, sum; \ - st t6, [dst + off + 0x18]; \ + EX(st t6, [dst + off + 0x18]); \ addxcc t6, sum, sum; \ - st t7, [dst + off + 0x1c]; \ + EX(st t7, [dst + off + 0x1c]); \ addxcc t7, sum, sum; /* Yuck, 6 superscalar cycles... */ #define CSUMCOPY_LASTCHUNK(src, dst, sum, off, t0, t1, t2, t3) \ - ldd [src - off - 0x08], t0; \ - ldd [src - off - 0x00], t2; \ + EX(ldd [src - off - 0x08], t0); \ + EX(ldd [src - off - 0x00], t2); \ addxcc t0, sum, sum; \ - st t0, [dst - off - 0x08]; \ + EX(st t0, [dst - off - 0x08]); \ addxcc t1, sum, sum; \ - st t1, [dst - off - 0x04]; \ + EX(st t1, [dst - off - 0x04]); \ addxcc t2, sum, sum; \ - st t2, [dst - off - 0x00]; \ + EX(st t2, [dst - off - 0x00]); \ addxcc t3, sum, sum; \ - st t3, [dst - off + 0x04]; + EX(st t3, [dst - off + 0x04]); /* Handle the end cruft code out of band for better cache patterns. */ cc_end_cruft: @@ -331,7 +324,6 @@ __csum_partial_copy_sparc_generic: CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) -10: EXT(5b, 10b) ! note for exception handling sub %g1, 128, %g1 ! detract from length addx %g0, %g7, %g7 ! add in last carry bit andcc %g1, 0xffffff80, %g0 ! more to csum? @@ -356,8 +348,7 @@ cctbl: CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x68,%g2,%g3,%g4,%g5) CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x28,%g2,%g3,%g4,%g5) CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x18,%g2,%g3,%g4,%g5) CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x08,%g2,%g3,%g4,%g5) -12: EXT(cctbl, 12b) ! note for exception table handling - addx %g0, %g7, %g7 +12: addx %g0, %g7, %g7 andcc %o3, 0xf, %g0 ! check for low bits set ccte: bne cc_end_cruft ! something left, handle it out of band andcc %o3, 8, %g0 ! begin checks for that code @@ -367,7 +358,6 @@ ccdbl: CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) -11: EXT(ccdbl, 11b) ! note for exception table handling sub %g1, 128, %g1 ! detract from length addx %g0, %g7, %g7 ! add in last carry bit andcc %g1, 0xffffff80, %g0 ! more to csum? diff --git a/arch/sparc/lib/copy_user.S b/arch/sparc/lib/copy_user.S index dc72f2b970b7b3328b0ccc1566c2d64951669abf..954572c78539aeff5a84fedd211d3dfb4465bfea 100644 --- a/arch/sparc/lib/copy_user.S +++ b/arch/sparc/lib/copy_user.S @@ -21,98 +21,134 @@ /* Work around cpp -rob */ #define ALLOC #alloc #define EXECINSTR #execinstr + +#define EX_ENTRY(l1, l2) \ + .section __ex_table,ALLOC; \ + .align 4; \ + .word l1, l2; \ + .text; + #define EX(x,y,a,b) \ 98: x,y; \ .section .fixup,ALLOC,EXECINSTR; \ .align 4; \ -99: ba fixupretl; \ - a, b, %g3; \ - .section __ex_table,ALLOC; \ - .align 4; \ - .word 98b, 99b; \ - .text; \ - .align 4 +99: retl; \ + a, b, %o0; \ + EX_ENTRY(98b, 99b) #define EX2(x,y,c,d,e,a,b) \ 98: x,y; \ .section .fixup,ALLOC,EXECINSTR; \ .align 4; \ 99: c, d, e; \ - ba fixupretl; \ - a, b, %g3; \ - .section __ex_table,ALLOC; \ - .align 4; \ - .word 98b, 99b; \ - .text; \ - .align 4 + retl; \ + a, b, %o0; \ + EX_ENTRY(98b, 99b) #define EXO2(x,y) \ 98: x, y; \ - .section __ex_table,ALLOC; \ - .align 4; \ - .word 98b, 97f; \ - .text; \ - .align 4 + EX_ENTRY(98b, 97f) -#define EXT(start,end,handler) \ - .section __ex_table,ALLOC; \ - .align 4; \ - .word start, 0, end, handler; \ - .text; \ - .align 4 +#define LD(insn, src, offset, reg, label) \ +98: insn [%src + (offset)], %reg; \ + .section .fixup,ALLOC,EXECINSTR; \ +99: ba label; \ + mov offset, %g5; \ + EX_ENTRY(98b, 99b) -/* Please do not change following macros unless you change logic used - * in .fixup at the end of this file as well - */ +#define ST(insn, dst, offset, reg, label) \ +98: insn %reg, [%dst + (offset)]; \ + .section .fixup,ALLOC,EXECINSTR; \ +99: ba label; \ + mov offset, %g5; \ + EX_ENTRY(98b, 99b) /* Both these macros have to start with exactly the same insn */ +/* left: g7 + (g1 % 128) - offset */ #define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ - ldd [%src + (offset) + 0x00], %t0; \ - ldd [%src + (offset) + 0x08], %t2; \ - ldd [%src + (offset) + 0x10], %t4; \ - ldd [%src + (offset) + 0x18], %t6; \ - st %t0, [%dst + (offset) + 0x00]; \ - st %t1, [%dst + (offset) + 0x04]; \ - st %t2, [%dst + (offset) + 0x08]; \ - st %t3, [%dst + (offset) + 0x0c]; \ - st %t4, [%dst + (offset) + 0x10]; \ - st %t5, [%dst + (offset) + 0x14]; \ - st %t6, [%dst + (offset) + 0x18]; \ - st %t7, [%dst + (offset) + 0x1c]; - + LD(ldd, src, offset + 0x00, t0, bigchunk_fault) \ + LD(ldd, src, offset + 0x08, t2, bigchunk_fault) \ + LD(ldd, src, offset + 0x10, t4, bigchunk_fault) \ + LD(ldd, src, offset + 0x18, t6, bigchunk_fault) \ + ST(st, dst, offset + 0x00, t0, bigchunk_fault) \ + ST(st, dst, offset + 0x04, t1, bigchunk_fault) \ + ST(st, dst, offset + 0x08, t2, bigchunk_fault) \ + ST(st, dst, offset + 0x0c, t3, bigchunk_fault) \ + ST(st, dst, offset + 0x10, t4, bigchunk_fault) \ + ST(st, dst, offset + 0x14, t5, bigchunk_fault) \ + ST(st, dst, offset + 0x18, t6, bigchunk_fault) \ + ST(st, dst, offset + 0x1c, t7, bigchunk_fault) + +/* left: g7 + (g1 % 128) - offset */ #define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ - ldd [%src + (offset) + 0x00], %t0; \ - ldd [%src + (offset) + 0x08], %t2; \ - ldd [%src + (offset) + 0x10], %t4; \ - ldd [%src + (offset) + 0x18], %t6; \ - std %t0, [%dst + (offset) + 0x00]; \ - std %t2, [%dst + (offset) + 0x08]; \ - std %t4, [%dst + (offset) + 0x10]; \ - std %t6, [%dst + (offset) + 0x18]; + LD(ldd, src, offset + 0x00, t0, bigchunk_fault) \ + LD(ldd, src, offset + 0x08, t2, bigchunk_fault) \ + LD(ldd, src, offset + 0x10, t4, bigchunk_fault) \ + LD(ldd, src, offset + 0x18, t6, bigchunk_fault) \ + ST(std, dst, offset + 0x00, t0, bigchunk_fault) \ + ST(std, dst, offset + 0x08, t2, bigchunk_fault) \ + ST(std, dst, offset + 0x10, t4, bigchunk_fault) \ + ST(std, dst, offset + 0x18, t6, bigchunk_fault) + .section .fixup,#alloc,#execinstr +bigchunk_fault: + sub %g7, %g5, %o0 + and %g1, 127, %g1 + retl + add %o0, %g1, %o0 + +/* left: offset + 16 + (g1 % 16) */ #define MOVE_LASTCHUNK(src, dst, offset, t0, t1, t2, t3) \ - ldd [%src - (offset) - 0x10], %t0; \ - ldd [%src - (offset) - 0x08], %t2; \ - st %t0, [%dst - (offset) - 0x10]; \ - st %t1, [%dst - (offset) - 0x0c]; \ - st %t2, [%dst - (offset) - 0x08]; \ - st %t3, [%dst - (offset) - 0x04]; + LD(ldd, src, -(offset + 0x10), t0, lastchunk_fault) \ + LD(ldd, src, -(offset + 0x08), t2, lastchunk_fault) \ + ST(st, dst, -(offset + 0x10), t0, lastchunk_fault) \ + ST(st, dst, -(offset + 0x0c), t1, lastchunk_fault) \ + ST(st, dst, -(offset + 0x08), t2, lastchunk_fault) \ + ST(st, dst, -(offset + 0x04), t3, lastchunk_fault) -#define MOVE_HALFCHUNK(src, dst, offset, t0, t1, t2, t3) \ - lduh [%src + (offset) + 0x00], %t0; \ - lduh [%src + (offset) + 0x02], %t1; \ - lduh [%src + (offset) + 0x04], %t2; \ - lduh [%src + (offset) + 0x06], %t3; \ - sth %t0, [%dst + (offset) + 0x00]; \ - sth %t1, [%dst + (offset) + 0x02]; \ - sth %t2, [%dst + (offset) + 0x04]; \ - sth %t3, [%dst + (offset) + 0x06]; + .section .fixup,#alloc,#execinstr +lastchunk_fault: + and %g1, 15, %g1 + retl + sub %g1, %g5, %o0 +/* left: o3 + (o2 % 16) - offset */ +#define MOVE_HALFCHUNK(src, dst, offset, t0, t1, t2, t3) \ + LD(lduh, src, offset + 0x00, t0, halfchunk_fault) \ + LD(lduh, src, offset + 0x02, t1, halfchunk_fault) \ + LD(lduh, src, offset + 0x04, t2, halfchunk_fault) \ + LD(lduh, src, offset + 0x06, t3, halfchunk_fault) \ + ST(sth, dst, offset + 0x00, t0, halfchunk_fault) \ + ST(sth, dst, offset + 0x02, t1, halfchunk_fault) \ + ST(sth, dst, offset + 0x04, t2, halfchunk_fault) \ + ST(sth, dst, offset + 0x06, t3, halfchunk_fault) + +/* left: o3 + (o2 % 16) + offset + 2 */ #define MOVE_SHORTCHUNK(src, dst, offset, t0, t1) \ - ldub [%src - (offset) - 0x02], %t0; \ - ldub [%src - (offset) - 0x01], %t1; \ - stb %t0, [%dst - (offset) - 0x02]; \ - stb %t1, [%dst - (offset) - 0x01]; + LD(ldub, src, -(offset + 0x02), t0, halfchunk_fault) \ + LD(ldub, src, -(offset + 0x01), t1, halfchunk_fault) \ + ST(stb, dst, -(offset + 0x02), t0, halfchunk_fault) \ + ST(stb, dst, -(offset + 0x01), t1, halfchunk_fault) + + .section .fixup,#alloc,#execinstr +halfchunk_fault: + and %o2, 15, %o2 + sub %o3, %g5, %o3 + retl + add %o2, %o3, %o0 + +/* left: offset + 2 + (o2 % 2) */ +#define MOVE_LAST_SHORTCHUNK(src, dst, offset, t0, t1) \ + LD(ldub, src, -(offset + 0x02), t0, last_shortchunk_fault) \ + LD(ldub, src, -(offset + 0x01), t1, last_shortchunk_fault) \ + ST(stb, dst, -(offset + 0x02), t0, last_shortchunk_fault) \ + ST(stb, dst, -(offset + 0x01), t1, last_shortchunk_fault) + + .section .fixup,#alloc,#execinstr +last_shortchunk_fault: + and %o2, 1, %o2 + retl + sub %o2, %g5, %o0 .text .align 4 @@ -182,8 +218,6 @@ __copy_user: /* %o0=dst %o1=src %o2=len */ MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5) MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5) MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5) -80: - EXT(5b, 80b, 50f) subcc %g7, 128, %g7 add %o1, 128, %o1 bne 5b @@ -201,7 +235,6 @@ __copy_user: /* %o0=dst %o1=src %o2=len */ jmpl %o5 + %lo(copy_user_table_end), %g0 add %o0, %g7, %o0 -copy_user_table: MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5) MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5) MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5) @@ -210,7 +243,6 @@ copy_user_table: MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5) MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5) copy_user_table_end: - EXT(copy_user_table, copy_user_table_end, 51f) be copy_user_last7 andcc %g1, 4, %g0 @@ -250,8 +282,6 @@ ldd_std: MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5) MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5) MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5) -81: - EXT(ldd_std, 81b, 52f) subcc %g7, 128, %g7 add %o1, 128, %o1 bne ldd_std @@ -290,8 +320,6 @@ cannot_optimize: 10: MOVE_HALFCHUNK(o1, o0, 0x00, g2, g3, g4, g5) MOVE_HALFCHUNK(o1, o0, 0x08, g2, g3, g4, g5) -82: - EXT(10b, 82b, 53f) subcc %o3, 0x10, %o3 add %o1, 0x10, %o1 bne 10b @@ -308,8 +336,6 @@ byte_chunk: MOVE_SHORTCHUNK(o1, o0, -0x0c, g2, g3) MOVE_SHORTCHUNK(o1, o0, -0x0e, g2, g3) MOVE_SHORTCHUNK(o1, o0, -0x10, g2, g3) -83: - EXT(byte_chunk, 83b, 54f) subcc %o3, 0x10, %o3 add %o1, 0x10, %o1 bne byte_chunk @@ -325,16 +351,14 @@ short_end: add %o1, %o3, %o1 jmpl %o5 + %lo(short_table_end), %g0 andcc %o2, 1, %g0 -84: - MOVE_SHORTCHUNK(o1, o0, 0x0c, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x0a, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x08, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x06, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x04, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x02, g2, g3) - MOVE_SHORTCHUNK(o1, o0, 0x00, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x0c, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x0a, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x08, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x06, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x04, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x02, g2, g3) + MOVE_LAST_SHORTCHUNK(o1, o0, 0x00, g2, g3) short_table_end: - EXT(84b, short_table_end, 55f) be 1f nop EX(ldub [%o1], %g2, add %g0, 1) @@ -363,123 +387,8 @@ short_aligned_end: .section .fixup,#alloc,#execinstr .align 4 97: - mov %o2, %g3 -fixupretl: retl - mov %g3, %o0 - -/* exception routine sets %g2 to (broken_insn - first_insn)>>2 */ -50: -/* This magic counts how many bytes are left when crash in MOVE_BIGCHUNK - * happens. This is derived from the amount ldd reads, st stores, etc. - * x = g2 % 12; - * g3 = g1 + g7 - ((g2 / 12) * 32 + (x < 4) ? 0 : (x - 4) * 4); - * o0 += (g2 / 12) * 32; - */ - cmp %g2, 12 - add %o0, %g7, %o0 - bcs 1f - cmp %g2, 24 - bcs 2f - cmp %g2, 36 - bcs 3f - nop - sub %g2, 12, %g2 - sub %g7, 32, %g7 -3: sub %g2, 12, %g2 - sub %g7, 32, %g7 -2: sub %g2, 12, %g2 - sub %g7, 32, %g7 -1: cmp %g2, 4 - bcs,a 60f - clr %g2 - sub %g2, 4, %g2 - sll %g2, 2, %g2 -60: and %g1, 0x7f, %g3 - sub %o0, %g7, %o0 - add %g3, %g7, %g3 - ba fixupretl - sub %g3, %g2, %g3 -51: -/* i = 41 - g2; j = i % 6; - * g3 = (g1 & 15) + (i / 6) * 16 + (j < 4) ? (j + 1) * 4 : 16; - * o0 -= (i / 6) * 16 + 16; - */ - neg %g2 - and %g1, 0xf, %g1 - add %g2, 41, %g2 - add %o0, %g1, %o0 -1: cmp %g2, 6 - bcs,a 2f - cmp %g2, 4 - add %g1, 16, %g1 - b 1b - sub %g2, 6, %g2 -2: bcc,a 2f - mov 16, %g2 - inc %g2 - sll %g2, 2, %g2 -2: add %g1, %g2, %g3 - ba fixupretl - sub %o0, %g3, %o0 -52: -/* g3 = g1 + g7 - (g2 / 8) * 32 + (g2 & 4) ? (g2 & 3) * 8 : 0; - o0 += (g2 / 8) * 32 */ - andn %g2, 7, %g4 - add %o0, %g7, %o0 - andcc %g2, 4, %g0 - and %g2, 3, %g2 - sll %g4, 2, %g4 - sll %g2, 3, %g2 - bne 60b - sub %g7, %g4, %g7 - ba 60b - clr %g2 -53: -/* g3 = o3 + (o2 & 15) - (g2 & 8) - (g2 & 4) ? (g2 & 3) * 2 : 0; - o0 += (g2 & 8) */ - and %g2, 3, %g4 - andcc %g2, 4, %g0 - and %g2, 8, %g2 - sll %g4, 1, %g4 - be 1f - add %o0, %g2, %o0 - add %g2, %g4, %g2 -1: and %o2, 0xf, %g3 - add %g3, %o3, %g3 - ba fixupretl - sub %g3, %g2, %g3 -54: -/* g3 = o3 + (o2 & 15) - (g2 / 4) * 2 - (g2 & 2) ? (g2 & 1) : 0; - o0 += (g2 / 4) * 2 */ - srl %g2, 2, %o4 - and %g2, 1, %o5 - srl %g2, 1, %g2 - add %o4, %o4, %o4 - and %o5, %g2, %o5 - and %o2, 0xf, %o2 - add %o0, %o4, %o0 - sub %o3, %o5, %o3 - sub %o2, %o4, %o2 - ba fixupretl - add %o2, %o3, %g3 -55: -/* i = 27 - g2; - g3 = (o2 & 1) + i / 4 * 2 + !(i & 3); - o0 -= i / 4 * 2 + 1 */ - neg %g2 - and %o2, 1, %o2 - add %g2, 27, %g2 - srl %g2, 2, %o5 - andcc %g2, 3, %g0 - mov 1, %g2 - add %o5, %o5, %o5 - be,a 1f - clr %g2 -1: add %g2, %o5, %g3 - sub %o0, %g3, %o0 - ba fixupretl - add %g3, %o2, %g3 + mov %o2, %o0 .globl __copy_user_end __copy_user_end: diff --git a/arch/sparc/lib/memset.S b/arch/sparc/lib/memset.S index f427f34b8b79bd6798fb90f756035d8f989d3909..eaff68213fdf58b86fb297d2ab844ad858da5dc0 100644 --- a/arch/sparc/lib/memset.S +++ b/arch/sparc/lib/memset.S @@ -19,7 +19,7 @@ 98: x,y; \ .section .fixup,ALLOC,EXECINSTR; \ .align 4; \ -99: ba 30f; \ +99: retl; \ a, b, %o0; \ .section __ex_table,ALLOC; \ .align 4; \ @@ -27,35 +27,44 @@ .text; \ .align 4 -#define EXT(start,end,handler) \ +#define STORE(source, base, offset, n) \ +98: std source, [base + offset + n]; \ + .section .fixup,ALLOC,EXECINSTR; \ + .align 4; \ +99: ba 30f; \ + sub %o3, n - offset, %o3; \ .section __ex_table,ALLOC; \ .align 4; \ - .word start, 0, end, handler; \ + .word 98b, 99b; \ .text; \ - .align 4 + .align 4; + +#define STORE_LAST(source, base, offset, n) \ + EX(std source, [base - offset - n], \ + add %o1, offset + n); /* Please don't change these macros, unless you change the logic * in the .fixup section below as well. * Store 64 bytes at (BASE + OFFSET) using value SOURCE. */ -#define ZERO_BIG_BLOCK(base, offset, source) \ - std source, [base + offset + 0x00]; \ - std source, [base + offset + 0x08]; \ - std source, [base + offset + 0x10]; \ - std source, [base + offset + 0x18]; \ - std source, [base + offset + 0x20]; \ - std source, [base + offset + 0x28]; \ - std source, [base + offset + 0x30]; \ - std source, [base + offset + 0x38]; +#define ZERO_BIG_BLOCK(base, offset, source) \ + STORE(source, base, offset, 0x00); \ + STORE(source, base, offset, 0x08); \ + STORE(source, base, offset, 0x10); \ + STORE(source, base, offset, 0x18); \ + STORE(source, base, offset, 0x20); \ + STORE(source, base, offset, 0x28); \ + STORE(source, base, offset, 0x30); \ + STORE(source, base, offset, 0x38); #define ZERO_LAST_BLOCKS(base, offset, source) \ - std source, [base - offset - 0x38]; \ - std source, [base - offset - 0x30]; \ - std source, [base - offset - 0x28]; \ - std source, [base - offset - 0x20]; \ - std source, [base - offset - 0x18]; \ - std source, [base - offset - 0x10]; \ - std source, [base - offset - 0x08]; \ - std source, [base - offset - 0x00]; + STORE_LAST(source, base, offset, 0x38); \ + STORE_LAST(source, base, offset, 0x30); \ + STORE_LAST(source, base, offset, 0x28); \ + STORE_LAST(source, base, offset, 0x20); \ + STORE_LAST(source, base, offset, 0x18); \ + STORE_LAST(source, base, offset, 0x10); \ + STORE_LAST(source, base, offset, 0x08); \ + STORE_LAST(source, base, offset, 0x00); .text .align 4 @@ -68,8 +77,6 @@ __bzero_begin: .globl memset EXPORT_SYMBOL(__bzero) EXPORT_SYMBOL(memset) - .globl __memset_start, __memset_end -__memset_start: memset: mov %o0, %g1 mov 1, %g4 @@ -122,8 +129,6 @@ __bzero: ZERO_BIG_BLOCK(%o0, 0x00, %g2) subcc %o3, 128, %o3 ZERO_BIG_BLOCK(%o0, 0x40, %g2) -11: - EXT(10b, 11b, 20f) bne 10b add %o0, 128, %o0 @@ -138,11 +143,9 @@ __bzero: jmp %o4 add %o0, %o2, %o0 -12: ZERO_LAST_BLOCKS(%o0, 0x48, %g2) ZERO_LAST_BLOCKS(%o0, 0x08, %g2) 13: - EXT(12b, 13b, 21f) be 8f andcc %o1, 4, %g0 @@ -182,37 +185,13 @@ __bzero: 5: retl clr %o0 -__memset_end: .section .fixup,#alloc,#execinstr .align 4 -20: - cmp %g2, 8 - bleu 1f - and %o1, 0x7f, %o1 - sub %g2, 9, %g2 - add %o3, 64, %o3 -1: - sll %g2, 3, %g2 - add %o3, %o1, %o0 - b 30f - sub %o0, %g2, %o0 -21: - mov 8, %o0 - and %o1, 7, %o1 - sub %o0, %g2, %o0 - sll %o0, 3, %o0 - b 30f - add %o0, %o1, %o0 30: -/* %o4 is faulting address, %o5 is %pc where fault occurred */ - save %sp, -104, %sp - mov %i5, %o0 - mov %i7, %o1 - call lookup_fault - mov %i4, %o2 - ret - restore + and %o1, 0x7f, %o1 + retl + add %o3, %o1, %o0 .globl __bzero_end __bzero_end: diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile index 68db1f859b02857e979539d0b4408a6b0d26fe64..871354aa3c002b875defade17825d7600066fee4 100644 --- a/arch/sparc/mm/Makefile +++ b/arch/sparc/mm/Makefile @@ -8,7 +8,7 @@ ccflags-y := -Werror obj-$(CONFIG_SPARC64) += ultra.o tlb.o tsb.o obj-y += fault_$(BITS).o obj-y += init_$(BITS).o -obj-$(CONFIG_SPARC32) += extable.o srmmu.o iommu.o io-unit.o +obj-$(CONFIG_SPARC32) += srmmu.o iommu.o io-unit.o obj-$(CONFIG_SPARC32) += srmmu_access.o obj-$(CONFIG_SPARC32) += hypersparc.o viking.o tsunami.o swift.o obj-$(CONFIG_SPARC32) += leon_mm.o diff --git a/arch/sparc/mm/extable.c b/arch/sparc/mm/extable.c deleted file mode 100644 index 241b4064187333f04998fa3aaa1d3352608cdabd..0000000000000000000000000000000000000000 --- a/arch/sparc/mm/extable.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/sparc/mm/extable.c - */ - -#include -#include -#include - -void sort_extable(struct exception_table_entry *start, - struct exception_table_entry *finish) -{ -} - -/* Caller knows they are in a range if ret->fixup == 0 */ -const struct exception_table_entry * -search_extable(const struct exception_table_entry *base, - const size_t num, - unsigned long value) -{ - int i; - - /* Single insn entries are encoded as: - * word 1: insn address - * word 2: fixup code address - * - * Range entries are encoded as: - * word 1: first insn address - * word 2: 0 - * word 3: last insn address + 4 bytes - * word 4: fixup code address - * - * Deleted entries are encoded as: - * word 1: unused - * word 2: -1 - * - * See asm/uaccess.h for more details. - */ - - /* 1. Try to find an exact match. */ - for (i = 0; i < num; i++) { - if (base[i].fixup == 0) { - /* A range entry, skip both parts. */ - i++; - continue; - } - - /* A deleted entry; see trim_init_extable */ - if (base[i].fixup == -1) - continue; - - if (base[i].insn == value) - return &base[i]; - } - - /* 2. Try to find a range match. */ - for (i = 0; i < (num - 1); i++) { - if (base[i].fixup) - continue; - - if (base[i].insn <= value && base[i + 1].insn > value) - return &base[i]; - - i++; - } - - return NULL; -} - -#ifdef CONFIG_MODULES -/* We could memmove them around; easier to mark the trimmed ones. */ -void trim_init_extable(struct module *m) -{ - unsigned int i; - bool range; - - for (i = 0; i < m->num_exentries; i += range ? 2 : 1) { - range = m->extable[i].fixup == 0; - - if (within_module_init(m->extable[i].insn, m)) { - m->extable[i].fixup = -1; - if (range) - m->extable[i+1].fixup = -1; - } - if (range) - i++; - } -} -#endif /* CONFIG_MODULES */ - -/* Special extable search, which handles ranges. Returns fixup */ -unsigned long search_extables_range(unsigned long addr, unsigned long *g2) -{ - const struct exception_table_entry *entry; - - entry = search_exception_tables(addr); - if (!entry) - return 0; - - /* Inside range? Fix g2 and return correct fixup */ - if (!entry->fixup) { - *g2 = (addr - entry->insn) / 4; - return (entry + 1)->fixup; - } - - return entry->fixup; -} diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index 40ce087dfecf24709ea6e5a5e6694970cbac1340..de2031c2b2d7982ebe39af78654e463c1cbfc5cd 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -54,54 +55,6 @@ static void __noreturn unhandled_fault(unsigned long address, die_if_kernel("Oops", regs); } -asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, - unsigned long address) -{ - struct pt_regs regs; - unsigned long g2; - unsigned int insn; - int i; - - i = search_extables_range(ret_pc, &g2); - switch (i) { - case 3: - /* load & store will be handled by fixup */ - return 3; - - case 1: - /* store will be handled by fixup, load will bump out */ - /* for _to_ macros */ - insn = *((unsigned int *) pc); - if ((insn >> 21) & 1) - return 1; - break; - - case 2: - /* load will be handled by fixup, store will bump out */ - /* for _from_ macros */ - insn = *((unsigned int *) pc); - if (!((insn >> 21) & 1) || ((insn>>19)&0x3f) == 15) - return 2; - break; - - default: - break; - } - - memset(®s, 0, sizeof(regs)); - regs.pc = pc; - regs.npc = pc + 4; - __asm__ __volatile__( - "rd %%psr, %0\n\t" - "nop\n\t" - "nop\n\t" - "nop\n" : "=r" (regs.psr)); - unhandled_fault(address, current, ®s); - - /* Not reached */ - return 0; -} - static inline void show_signal_msg(struct pt_regs *regs, int sig, int code, unsigned long address, struct task_struct *tsk) @@ -162,8 +115,6 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, struct vm_area_struct *vma; struct task_struct *tsk = current; struct mm_struct *mm = tsk->mm; - unsigned int fixup; - unsigned long g2; int from_user = !(regs->psr & PSR_PS); int code; vm_fault_t fault; @@ -281,30 +232,19 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, /* Is this in ex_table? */ no_context: - g2 = regs->u_regs[UREG_G2]; if (!from_user) { - fixup = search_extables_range(regs->pc, &g2); - /* Values below 10 are reserved for other things */ - if (fixup > 10) { - extern const unsigned int __memset_start[]; - extern const unsigned int __memset_end[]; + const struct exception_table_entry *entry; + entry = search_exception_tables(regs->pc); #ifdef DEBUG_EXCEPTIONS - printk("Exception: PC<%08lx> faddr<%08lx>\n", - regs->pc, address); - printk("EX_TABLE: insn<%08lx> fixup<%08x> g2<%08lx>\n", - regs->pc, fixup, g2); + printk("Exception: PC<%08lx> faddr<%08lx>\n", + regs->pc, address); + printk("EX_TABLE: insn<%08lx> fixup<%08x>\n", + regs->pc, entry->fixup); #endif - if ((regs->pc >= (unsigned long)__memset_start && - regs->pc < (unsigned long)__memset_end)) { - regs->u_regs[UREG_I4] = address; - regs->u_regs[UREG_I5] = regs->pc; - } - regs->u_regs[UREG_G2] = g2; - regs->pc = fixup; - regs->npc = regs->pc + 4; - return; - } + regs->pc = entry->fixup; + regs->npc = regs->pc + 4; + return; } unhandled_fault(address, tsk, regs); diff --git a/arch/sparc/mm/mm_32.h b/arch/sparc/mm/mm_32.h index ce750a99eea96bb968bea7b2f4414dac752a7922..ee55f10806343aa07fa405b4452fc591c5ab22b6 100644 --- a/arch/sparc/mm/mm_32.h +++ b/arch/sparc/mm/mm_32.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* fault_32.c - visible as they are called from assembler */ -asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, - unsigned long address); asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, unsigned long address); diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c index a2433ae8a65e764028e37e9d87bc0b0a7e93cbd0..4efd39aacb9f28366f3bbafb17f59a3ec181cbed 100644 --- a/arch/x86/entry/common.c +++ b/arch/x86/entry/common.c @@ -128,7 +128,8 @@ static noinstr bool __do_fast_syscall_32(struct pt_regs *regs) regs->ax = -EFAULT; instrumentation_end(); - syscall_exit_to_user_mode(regs); + local_irq_disable(); + irqentry_exit_to_user_mode(regs); return false; } diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 541fdaf6404533bd2d2558bd0ebc426324f2c96c..0051cf5c792d1aeccb7800ba4c02b354c24f885c 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -210,6 +210,8 @@ SYM_CODE_START(entry_SYSCALL_compat) /* Switch to the kernel stack */ movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp +SYM_INNER_LABEL(entry_SYSCALL_compat_safe_stack, SYM_L_GLOBAL) + /* Construct struct pt_regs on stack */ pushq $__USER32_DS /* pt_regs->ss */ pushq %r8 /* pt_regs->sp */ diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6ddeed3cd2acb1b02de96a8d78724ecb11c2cc5d..18df1712969554ce3d58b6e65c311cfc283bfa00 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -81,7 +81,11 @@ DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx); DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases); -DEFINE_STATIC_CALL_NULL(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs); +/* + * This one is magic, it will get called even when PMU init fails (because + * there is no PMU), in which case it should simply return NULL. + */ +DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs); u64 __read_mostly hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] @@ -1944,13 +1948,6 @@ static void _x86_pmu_read(struct perf_event *event) x86_perf_event_update(event); } -static inline struct perf_guest_switch_msr * -perf_guest_get_msrs_nop(int *nr) -{ - *nr = 0; - return NULL; -} - static int __init init_hw_perf_events(void) { struct x86_pmu_quirk *quirk; @@ -2025,7 +2022,7 @@ static int __init init_hw_perf_events(void) x86_pmu.read = _x86_pmu_read; if (!x86_pmu.guest_get_msrs) - x86_pmu.guest_get_msrs = perf_guest_get_msrs_nop; + x86_pmu.guest_get_msrs = (void *)&__static_call_return0; x86_pmu_static_call_update(); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 5bac48d5c18e86251f205213412052d39c6aacec..7bbb5bb98d8cd327efdccaf7308209b7cb35de62 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3662,8 +3662,10 @@ static int intel_pmu_hw_config(struct perf_event *event) if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; if (!(event->attr.sample_type & - ~intel_pmu_large_pebs_flags(event))) + ~intel_pmu_large_pebs_flags(event))) { event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; + event->attach_state |= PERF_ATTACH_SCHED_CB; + } } if (x86_pmu.pebs_aliases) x86_pmu.pebs_aliases(event); @@ -3676,6 +3678,7 @@ static int intel_pmu_hw_config(struct perf_event *event) ret = intel_pmu_setup_lbr_filter(event); if (ret) return ret; + event->attach_state |= PERF_ATTACH_SCHED_CB; /* * BTS is set up earlier in this path, so don't account twice diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h index a0f839aa144d9eeb347247e7f79e07683b5564f8..98b4dae5e8bc8a93398682080ab180982b33280f 100644 --- a/arch/x86/include/asm/insn-eval.h +++ b/arch/x86/include/asm/insn-eval.h @@ -23,6 +23,8 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx); int insn_get_code_seg_params(struct pt_regs *regs); int insn_fetch_from_user(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE]); +int insn_fetch_from_user_inatomic(struct pt_regs *regs, + unsigned char buf[MAX_INSN_SIZE]); bool insn_decode(struct insn *insn, struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE], int buf_size); diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 877a4025d8da081316f9805eede414e8a11cd5f7..9bc091ecaaeb97fee3eca9650d8b249450f03192 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -963,7 +963,7 @@ struct kvm_arch { struct kvm_pit *vpit; atomic_t vapics_in_nmi_mode; struct mutex apic_map_lock; - struct kvm_apic_map *apic_map; + struct kvm_apic_map __rcu *apic_map; atomic_t apic_map_dirty; bool apic_access_page_done; @@ -1036,7 +1036,7 @@ struct kvm_arch { bool bus_lock_detection_enabled; - struct kvm_pmu_event_filter *pmu_event_filter; + struct kvm_pmu_event_filter __rcu *pmu_event_filter; struct task_struct *nx_lpage_recovery_thread; #ifdef CONFIG_X86_64 diff --git a/arch/x86/include/asm/proto.h b/arch/x86/include/asm/proto.h index 2c35f1c01a2df103854215bdba3bec992fe2e177..b6a9d51d1d7911894fa6b831b2f01a05f1daf57f 100644 --- a/arch/x86/include/asm/proto.h +++ b/arch/x86/include/asm/proto.h @@ -25,6 +25,7 @@ void __end_SYSENTER_singlestep_region(void); void entry_SYSENTER_compat(void); void __end_entry_SYSENTER_compat(void); void entry_SYSCALL_compat(void); +void entry_SYSCALL_compat_safe_stack(void); void entry_INT80_compat(void); #ifdef CONFIG_XEN_PV void xen_entry_INT80_compat(void); diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index d8324a23669610e379078543e3cbed3855aaae3e..409f661481e110c3471b83477a159cae4052b540 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -94,6 +94,8 @@ struct pt_regs { #include #endif +#include + struct cpuinfo_x86; struct task_struct; @@ -175,6 +177,19 @@ static inline bool any_64bit_mode(struct pt_regs *regs) #ifdef CONFIG_X86_64 #define current_user_stack_pointer() current_pt_regs()->sp #define compat_user_stack_pointer() current_pt_regs()->sp + +static inline bool ip_within_syscall_gap(struct pt_regs *regs) +{ + bool ret = (regs->ip >= (unsigned long)entry_SYSCALL_64 && + regs->ip < (unsigned long)entry_SYSCALL_64_safe_stack); + +#ifdef CONFIG_IA32_EMULATION + ret = ret || (regs->ip >= (unsigned long)entry_SYSCALL_compat && + regs->ip < (unsigned long)entry_SYSCALL_compat_safe_stack); +#endif + + return ret; +} #endif static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) diff --git a/arch/x86/include/asm/smap.h b/arch/x86/include/asm/smap.h index 8b58d6975d5d4b4fa3a77e25529caf464b23bbfe..0bc9b0895f33e5a65c9f4304ae6d92fafade2394 100644 --- a/arch/x86/include/asm/smap.h +++ b/arch/x86/include/asm/smap.h @@ -58,9 +58,8 @@ static __always_inline unsigned long smap_save(void) unsigned long flags; asm volatile ("# smap_save\n\t" - ALTERNATIVE("jmp 1f", "", X86_FEATURE_SMAP) - "pushf; pop %0; " __ASM_CLAC "\n\t" - "1:" + ALTERNATIVE("", "pushf; pop %0; " __ASM_CLAC "\n\t", + X86_FEATURE_SMAP) : "=rm" (flags) : : "memory", "cc"); return flags; @@ -69,9 +68,8 @@ static __always_inline unsigned long smap_save(void) static __always_inline void smap_restore(unsigned long flags) { asm volatile ("# smap_restore\n\t" - ALTERNATIVE("jmp 1f", "", X86_FEATURE_SMAP) - "push %0; popf\n\t" - "1:" + ALTERNATIVE("", "push %0; popf\n\t", + X86_FEATURE_SMAP) : : "g" (flags) : "memory", "cc"); } diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index aa593743acf679781bbfd98117bfc269f5c999b4..1fc0962c89c082b5b638a79efc040e4940de9991 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -268,21 +268,20 @@ static void __init kvmclock_init_mem(void) static int __init kvm_setup_vsyscall_timeinfo(void) { -#ifdef CONFIG_X86_64 - u8 flags; + kvmclock_init_mem(); - if (!per_cpu(hv_clock_per_cpu, 0) || !kvmclock_vsyscall) - return 0; +#ifdef CONFIG_X86_64 + if (per_cpu(hv_clock_per_cpu, 0) && kvmclock_vsyscall) { + u8 flags; - flags = pvclock_read_flags(&hv_clock_boot[0].pvti); - if (!(flags & PVCLOCK_TSC_STABLE_BIT)) - return 0; + flags = pvclock_read_flags(&hv_clock_boot[0].pvti); + if (!(flags & PVCLOCK_TSC_STABLE_BIT)) + return 0; - kvm_clock.vdso_clock_mode = VDSO_CLOCKMODE_PVCLOCK; + kvm_clock.vdso_clock_mode = VDSO_CLOCKMODE_PVCLOCK; + } #endif - kvmclock_init_mem(); - return 0; } early_initcall(kvm_setup_vsyscall_timeinfo); diff --git a/arch/x86/kernel/sev-es.c b/arch/x86/kernel/sev-es.c index 84c1821819afb8fb3da3b09b8d429930bd1d4da3..04a780abb512d01eb246067eff2b27f6e8501c51 100644 --- a/arch/x86/kernel/sev-es.c +++ b/arch/x86/kernel/sev-es.c @@ -121,8 +121,18 @@ static void __init setup_vc_stacks(int cpu) cea_set_pte((void *)vaddr, pa, PAGE_KERNEL); } -static __always_inline bool on_vc_stack(unsigned long sp) +static __always_inline bool on_vc_stack(struct pt_regs *regs) { + unsigned long sp = regs->sp; + + /* User-mode RSP is not trusted */ + if (user_mode(regs)) + return false; + + /* SYSCALL gap still has user-mode RSP */ + if (ip_within_syscall_gap(regs)) + return false; + return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC))); } @@ -144,7 +154,7 @@ void noinstr __sev_es_ist_enter(struct pt_regs *regs) old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]); /* Make room on the IST stack */ - if (on_vc_stack(regs->sp)) + if (on_vc_stack(regs)) new_ist = ALIGN_DOWN(regs->sp, 8) - sizeof(old_ist); else new_ist = old_ist - sizeof(old_ist); @@ -248,7 +258,7 @@ static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) int res; if (user_mode(ctxt->regs)) { - res = insn_fetch_from_user(ctxt->regs, buffer); + res = insn_fetch_from_user_inatomic(ctxt->regs, buffer); if (!res) { ctxt->fi.vector = X86_TRAP_PF; ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER; @@ -1248,13 +1258,12 @@ static __always_inline bool on_vc_fallback_stack(struct pt_regs *regs) DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) { struct sev_es_runtime_data *data = this_cpu_read(runtime_data); + irqentry_state_t irq_state; struct ghcb_state state; struct es_em_ctxt ctxt; enum es_result result; struct ghcb *ghcb; - lockdep_assert_irqs_disabled(); - /* * Handle #DB before calling into !noinstr code to avoid recursive #DB. */ @@ -1263,6 +1272,8 @@ DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) return; } + irq_state = irqentry_nmi_enter(regs); + lockdep_assert_irqs_disabled(); instrumentation_begin(); /* @@ -1325,6 +1336,7 @@ DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) out: instrumentation_end(); + irqentry_nmi_exit(regs, irq_state); return; diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 7f5aec758f0eeac2d9bcebcd80963bc9d79e7ab3..ac1874a2a70e8cc41654bc652a8922238192a8ff 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -694,8 +694,7 @@ asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *r * In the SYSCALL entry path the RSP value comes from user-space - don't * trust it and switch to the current kernel stack */ - if (regs->ip >= (unsigned long)entry_SYSCALL_64 && - regs->ip < (unsigned long)entry_SYSCALL_64_safe_stack) { + if (ip_within_syscall_gap(regs)) { sp = this_cpu_read(cpu_current_top_of_stack); goto sync; } diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c index 2a1d47f47eee2b3d1f5034d1828d1faa2ee9e4c0..a1202536fc57cc2b4af2b0bfde3f08fb6f9c034a 100644 --- a/arch/x86/kernel/unwind_orc.c +++ b/arch/x86/kernel/unwind_orc.c @@ -13,7 +13,7 @@ #define orc_warn_current(args...) \ ({ \ - if (state->task == current) \ + if (state->task == current && !state->error) \ orc_warn(args); \ }) @@ -367,8 +367,8 @@ static bool deref_stack_regs(struct unwind_state *state, unsigned long addr, if (!stack_access_ok(state, addr, sizeof(struct pt_regs))) return false; - *ip = regs->ip; - *sp = regs->sp; + *ip = READ_ONCE_NOCHECK(regs->ip); + *sp = READ_ONCE_NOCHECK(regs->sp); return true; } @@ -380,8 +380,8 @@ static bool deref_stack_iret_regs(struct unwind_state *state, unsigned long addr if (!stack_access_ok(state, addr, IRET_FRAME_SIZE)) return false; - *ip = regs->ip; - *sp = regs->sp; + *ip = READ_ONCE_NOCHECK(regs->ip); + *sp = READ_ONCE_NOCHECK(regs->sp); return true; } @@ -402,12 +402,12 @@ static bool get_reg(struct unwind_state *state, unsigned int reg_off, return false; if (state->full_regs) { - *val = ((unsigned long *)state->regs)[reg]; + *val = READ_ONCE_NOCHECK(((unsigned long *)state->regs)[reg]); return true; } if (state->prev_regs) { - *val = ((unsigned long *)state->prev_regs)[reg]; + *val = READ_ONCE_NOCHECK(((unsigned long *)state->prev_regs)[reg]); return true; } diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 45d40bfacb7cbe35b6deff4359404ccf314ace22..cc369b9ad8f11ccd5a725f0826dcab4f9ab507e7 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1642,7 +1642,16 @@ static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) } if (kvm_use_posted_timer_interrupt(apic->vcpu)) { - kvm_wait_lapic_expire(vcpu); + /* + * Ensure the guest's timer has truly expired before posting an + * interrupt. Open code the relevant checks to avoid querying + * lapic_timer_int_injected(), which will be false since the + * interrupt isn't yet injected. Waiting until after injecting + * is not an option since that won't help a posted interrupt. + */ + if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && + vcpu->arch.apic->lapic_timer.timer_advance_ns) + __kvm_wait_lapic_expire(vcpu); kvm_apic_inject_pending_timer_irqs(apic); return; } @@ -2595,6 +2604,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) apic_update_ppr(apic); hrtimer_cancel(&apic->lapic_timer.timer); + apic->lapic_timer.expired_tscdeadline = 0; apic_update_lvtt(apic); apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); update_divide_count(apic); diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c index c926c6b899a106c704a68b25997209aff05ff3b1..d78915019b082f7b5f4509fa84e2405dc5f63d5d 100644 --- a/arch/x86/kvm/mmu/tdp_mmu.c +++ b/arch/x86/kvm/mmu/tdp_mmu.c @@ -337,7 +337,18 @@ static void handle_removed_tdp_mmu_page(struct kvm *kvm, u64 *pt, cpu_relax(); } } else { + /* + * If the SPTE is not MMU-present, there is no backing + * page associated with the SPTE and so no side effects + * that need to be recorded, and exclusive ownership of + * mmu_lock ensures the SPTE can't be made present. + * Note, zapping MMIO SPTEs is also unnecessary as they + * are guarded by the memslots generation, not by being + * unreachable. + */ old_child_spte = READ_ONCE(*sptep); + if (!is_shadow_present_pte(old_child_spte)) + continue; /* * Marking the SPTE as a removed SPTE is not diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index baee91c1e936432bfedcd218e9f4532c10448a80..58a45bb139f88ab78c4a01e370693379968f0984 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -115,13 +115,6 @@ static const struct svm_direct_access_msrs { { .index = MSR_INVALID, .always = false }, }; -/* enable NPT for AMD64 and X86 with PAE */ -#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) -bool npt_enabled = true; -#else -bool npt_enabled; -#endif - /* * These 2 parameters are used to config the controls for Pause-Loop Exiting: * pause_filter_count: On processors that support Pause filtering(indicated @@ -170,9 +163,12 @@ module_param(pause_filter_count_shrink, ushort, 0444); static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX; module_param(pause_filter_count_max, ushort, 0444); -/* allow nested paging (virtualized MMU) for all guests */ -static int npt = true; -module_param(npt, int, S_IRUGO); +/* + * Use nested page tables by default. Note, NPT may get forced off by + * svm_hardware_setup() if it's unsupported by hardware or the host kernel. + */ +bool npt_enabled = true; +module_param_named(npt, npt_enabled, bool, 0444); /* allow nested virtualization in KVM/SVM */ static int nested = true; @@ -988,10 +984,15 @@ static __init int svm_hardware_setup(void) goto err; } - if (!boot_cpu_has(X86_FEATURE_NPT)) + /* + * KVM's MMU doesn't support using 2-level paging for itself, and thus + * NPT isn't supported if the host is using 2-level paging since host + * CR4 is unchanged on VMRUN. + */ + if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE)) npt_enabled = false; - if (npt_enabled && !npt) + if (!boot_cpu_has(X86_FEATURE_NPT)) npt_enabled = false; kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 50810d4714628c2f3978847e9068c6106529797a..32cf8287d4a77306bb38da05ee6250441879e6f7 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6580,8 +6580,8 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) int i, nr_msrs; struct perf_guest_switch_msr *msrs; + /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ msrs = perf_guest_get_msrs(&nr_msrs); - if (!msrs) return; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2a20ce60152ea98e9521ed928c0cae06139317ab..47e021bdcc94ab324d03057b881cad0dcfd78534 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10601,7 +10601,7 @@ void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, return (void __user *)hva; } else { if (!slot || !slot->npages) - return 0; + return NULL; old_npages = slot->npages; hva = slot->userspace_addr; diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index 4229950a5d78c328a38f185119cc85098a36ce66..bb0b3fe1e0a0251c716ec2568576d8e0ceb13900 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -1415,6 +1415,25 @@ void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs) } } +static unsigned long insn_get_effective_ip(struct pt_regs *regs) +{ + unsigned long seg_base = 0; + + /* + * If not in user-space long mode, a custom code segment could be in + * use. This is true in protected mode (if the process defined a local + * descriptor table), or virtual-8086 mode. In most of the cases + * seg_base will be zero as in USER_CS. + */ + if (!user_64bit_mode(regs)) { + seg_base = insn_get_seg_base(regs, INAT_SEG_REG_CS); + if (seg_base == -1L) + return 0; + } + + return seg_base + regs->ip; +} + /** * insn_fetch_from_user() - Copy instruction bytes from user-space memory * @regs: Structure with register values as seen when entering kernel mode @@ -1431,24 +1450,43 @@ void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs) */ int insn_fetch_from_user(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE]) { - unsigned long seg_base = 0; + unsigned long ip; int not_copied; - /* - * If not in user-space long mode, a custom code segment could be in - * use. This is true in protected mode (if the process defined a local - * descriptor table), or virtual-8086 mode. In most of the cases - * seg_base will be zero as in USER_CS. - */ - if (!user_64bit_mode(regs)) { - seg_base = insn_get_seg_base(regs, INAT_SEG_REG_CS); - if (seg_base == -1L) - return 0; - } + ip = insn_get_effective_ip(regs); + if (!ip) + return 0; + + not_copied = copy_from_user(buf, (void __user *)ip, MAX_INSN_SIZE); + return MAX_INSN_SIZE - not_copied; +} + +/** + * insn_fetch_from_user_inatomic() - Copy instruction bytes from user-space memory + * while in atomic code + * @regs: Structure with register values as seen when entering kernel mode + * @buf: Array to store the fetched instruction + * + * Gets the linear address of the instruction and copies the instruction bytes + * to the buf. This function must be used in atomic context. + * + * Returns: + * + * Number of instruction bytes copied. + * + * 0 if nothing was copied. + */ +int insn_fetch_from_user_inatomic(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE]) +{ + unsigned long ip; + int not_copied; + + ip = insn_get_effective_ip(regs); + if (!ip) + return 0; - not_copied = copy_from_user(buf, (void __user *)(seg_base + regs->ip), - MAX_INSN_SIZE); + not_copied = __copy_from_user_inatomic(buf, (void __user *)ip, MAX_INSN_SIZE); return MAX_INSN_SIZE - not_copied; } diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 79e7a0ec1da584c39f6ce8a4d243324ce00a5b6e..6926d0ca6c71797ffcbbf4e3c3e532f80c8244c3 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1349,6 +1349,7 @@ st: if (is_imm8(insn->off)) insn->imm == (BPF_XOR | BPF_FETCH)) { u8 *branch_target; bool is64 = BPF_SIZE(insn->code) == BPF_DW; + u32 real_src_reg = src_reg; /* * Can't be implemented with a single x86 insn. @@ -1357,6 +1358,9 @@ st: if (is_imm8(insn->off)) /* Will need RAX as a CMPXCHG operand so save R0 */ emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); + if (src_reg == BPF_REG_0) + real_src_reg = BPF_REG_AX; + branch_target = prog; /* Load old value */ emit_ldx(&prog, BPF_SIZE(insn->code), @@ -1366,9 +1370,9 @@ st: if (is_imm8(insn->off)) * put the result in the AUX_REG. */ emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); - maybe_emit_mod(&prog, AUX_REG, src_reg, is64); + maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], - add_2reg(0xC0, AUX_REG, src_reg)); + add_2reg(0xC0, AUX_REG, real_src_reg)); /* Attempt to swap in new value */ err = emit_atomic(&prog, BPF_CMPXCHG, dst_reg, AUX_REG, insn->off, @@ -1381,7 +1385,7 @@ st: if (is_imm8(insn->off)) */ EMIT2(X86_JNE, -(prog - branch_target) - 2); /* Return the pre-modification value */ - emit_mov_reg(&prog, is64, src_reg, BPF_REG_0); + emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); /* Restore R0 after clobbering RAX */ emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); break; diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index a3cc33091f46c1039d48eeeeda2af6ec648caea7..17d80f751fcb2477fa16799261c6db8823941fcc 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c @@ -741,7 +741,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, map_ops[i].status = GNTST_general_error; unmap[0].host_addr = map_ops[i].host_addr, unmap[0].handle = map_ops[i].handle; - map_ops[i].handle = ~0; + map_ops[i].handle = INVALID_GRANT_HANDLE; if (map_ops[i].flags & GNTMAP_device_map) unmap[0].dev_bus_addr = map_ops[i].dev_bus_addr; else @@ -751,7 +751,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, kmap_ops[i].status = GNTST_general_error; unmap[1].host_addr = kmap_ops[i].host_addr, unmap[1].handle = kmap_ops[i].handle; - kmap_ops[i].handle = ~0; + kmap_ops[i].handle = INVALID_GRANT_HANDLE; if (kmap_ops[i].flags & GNTMAP_device_map) unmap[1].dev_bus_addr = kmap_ops[i].dev_bus_addr; else @@ -776,7 +776,6 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, out: return ret; } -EXPORT_SYMBOL_GPL(set_foreign_p2m_mapping); int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops, struct gnttab_unmap_grant_ref *kunmap_ops, @@ -802,7 +801,6 @@ int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops, return ret; } -EXPORT_SYMBOL_GPL(clear_foreign_p2m_mapping); #ifdef CONFIG_XEN_DEBUG_FS #include diff --git a/block/bio.c b/block/bio.c index a1c4d2900c7a83b0107f06e2a0a6bda0e71d3add..26b7f721cda88b37c991e9e7f9caef3145223b1a 100644 --- a/block/bio.c +++ b/block/bio.c @@ -33,7 +33,7 @@ static struct biovec_slab { { .nr_vecs = 16, .name = "biovec-16" }, { .nr_vecs = 64, .name = "biovec-64" }, { .nr_vecs = 128, .name = "biovec-128" }, - { .nr_vecs = BIO_MAX_PAGES, .name = "biovec-max" }, + { .nr_vecs = BIO_MAX_VECS, .name = "biovec-max" }, }; static struct biovec_slab *biovec_slab(unsigned short nr_vecs) @@ -46,7 +46,7 @@ static struct biovec_slab *biovec_slab(unsigned short nr_vecs) return &bvec_slabs[1]; case 65 ... 128: return &bvec_slabs[2]; - case 129 ... BIO_MAX_PAGES: + case 129 ... BIO_MAX_VECS: return &bvec_slabs[3]; default: BUG(); @@ -151,9 +151,9 @@ static void bio_put_slab(struct bio_set *bs) void bvec_free(mempool_t *pool, struct bio_vec *bv, unsigned short nr_vecs) { - BIO_BUG_ON(nr_vecs > BIO_MAX_PAGES); + BIO_BUG_ON(nr_vecs > BIO_MAX_VECS); - if (nr_vecs == BIO_MAX_PAGES) + if (nr_vecs == BIO_MAX_VECS) mempool_free(bv, pool); else if (nr_vecs > BIO_INLINE_VECS) kmem_cache_free(biovec_slab(nr_vecs)->slab, bv); @@ -186,15 +186,15 @@ struct bio_vec *bvec_alloc(mempool_t *pool, unsigned short *nr_vecs, /* * Try a slab allocation first for all smaller allocations. If that * fails and __GFP_DIRECT_RECLAIM is set retry with the mempool. - * The mempool is sized to handle up to BIO_MAX_PAGES entries. + * The mempool is sized to handle up to BIO_MAX_VECS entries. */ - if (*nr_vecs < BIO_MAX_PAGES) { + if (*nr_vecs < BIO_MAX_VECS) { struct bio_vec *bvl; bvl = kmem_cache_alloc(bvs->slab, bvec_alloc_gfp(gfp_mask)); if (likely(bvl) || !(gfp_mask & __GFP_DIRECT_RECLAIM)) return bvl; - *nr_vecs = BIO_MAX_PAGES; + *nr_vecs = BIO_MAX_VECS; } return mempool_alloc(pool, gfp_mask); diff --git a/block/blk-cgroup-rwstat.c b/block/blk-cgroup-rwstat.c index 85d5790ac49b03da55c3439b9b364d8539072843..3304e841df7ce924a1a64c69b5ab9102294d6801 100644 --- a/block/blk-cgroup-rwstat.c +++ b/block/blk-cgroup-rwstat.c @@ -109,6 +109,7 @@ void blkg_rwstat_recursive_sum(struct blkcg_gq *blkg, struct blkcg_policy *pol, lockdep_assert_held(&blkg->q->queue_lock); + memset(sum, 0, sizeof(*sum)); rcu_read_lock(); blkg_for_each_descendant_pre(pos_blkg, pos_css, blkg) { struct blkg_rwstat *rwstat; @@ -122,7 +123,7 @@ void blkg_rwstat_recursive_sum(struct blkcg_gq *blkg, struct blkcg_policy *pol, rwstat = (void *)pos_blkg + off; for (i = 0; i < BLKG_RWSTAT_NR; i++) - sum->cnt[i] = blkg_rwstat_read_counter(rwstat, i); + sum->cnt[i] += blkg_rwstat_read_counter(rwstat, i); } rcu_read_unlock(); } diff --git a/block/blk-crypto-fallback.c b/block/blk-crypto-fallback.c index c176b7af56a7a57742f65757a3d9901ac9e14497..c322176a1e0995391bcfb358f427f6dc2c5f738e 100644 --- a/block/blk-crypto-fallback.c +++ b/block/blk-crypto-fallback.c @@ -219,7 +219,7 @@ static bool blk_crypto_split_bio_if_needed(struct bio **bio_ptr) bio_for_each_segment(bv, bio, iter) { num_sectors += bv.bv_len >> SECTOR_SHIFT; - if (++i == BIO_MAX_PAGES) + if (++i == BIO_MAX_VECS) break; } if (num_sectors < bio_sectors(bio)) { diff --git a/block/blk-lib.c b/block/blk-lib.c index 752f9c7220622a9b30ac7f6e23aabdf9f7a7e3e4..7b256131b20bbb221e6500ba655b1dd2e05ddc2c 100644 --- a/block/blk-lib.c +++ b/block/blk-lib.c @@ -296,7 +296,7 @@ static unsigned int __blkdev_sectors_to_bio_pages(sector_t nr_sects) { sector_t pages = DIV_ROUND_UP_SECTOR_T(nr_sects, PAGE_SIZE / 512); - return min(pages, (sector_t)BIO_MAX_PAGES); + return min(pages, (sector_t)BIO_MAX_VECS); } static int __blkdev_issue_zero_pages(struct block_device *bdev, diff --git a/block/blk-map.c b/block/blk-map.c index 369e204d14d013f66e3422444d19361d09a10863..1ffef782fcf2dd96487d398e0499c871cb497c03 100644 --- a/block/blk-map.c +++ b/block/blk-map.c @@ -249,7 +249,7 @@ static int bio_map_user_iov(struct request *rq, struct iov_iter *iter, if (!iov_iter_count(iter)) return -EINVAL; - bio = bio_kmalloc(gfp_mask, iov_iter_npages(iter, BIO_MAX_PAGES)); + bio = bio_kmalloc(gfp_mask, iov_iter_npages(iter, BIO_MAX_VECS)); if (!bio) return -ENOMEM; bio->bi_opf |= req_op(rq); diff --git a/block/blk-zoned.c b/block/blk-zoned.c index 833978c02e6083fd346784bdce244fe3b7d467c3..c0276b42d9fb7c5c1f6140b38a2864afc955d69a 100644 --- a/block/blk-zoned.c +++ b/block/blk-zoned.c @@ -240,7 +240,7 @@ int blkdev_zone_mgmt(struct block_device *bdev, enum req_opf op, */ if (op == REQ_OP_ZONE_RESET && blkdev_allow_reset_all_zones(bdev, sector, nr_sectors)) { - bio->bi_opf = REQ_OP_ZONE_RESET_ALL; + bio->bi_opf = REQ_OP_ZONE_RESET_ALL | REQ_SYNC; break; } @@ -318,6 +318,22 @@ int blkdev_report_zones_ioctl(struct block_device *bdev, fmode_t mode, return 0; } +static int blkdev_truncate_zone_range(struct block_device *bdev, fmode_t mode, + const struct blk_zone_range *zrange) +{ + loff_t start, end; + + if (zrange->sector + zrange->nr_sectors <= zrange->sector || + zrange->sector + zrange->nr_sectors > get_capacity(bdev->bd_disk)) + /* Out of range */ + return -EINVAL; + + start = zrange->sector << SECTOR_SHIFT; + end = ((zrange->sector + zrange->nr_sectors) << SECTOR_SHIFT) - 1; + + return truncate_bdev_range(bdev, mode, start, end); +} + /* * BLKRESETZONE, BLKOPENZONE, BLKCLOSEZONE and BLKFINISHZONE ioctl processing. * Called from blkdev_ioctl. @@ -329,6 +345,7 @@ int blkdev_zone_mgmt_ioctl(struct block_device *bdev, fmode_t mode, struct request_queue *q; struct blk_zone_range zrange; enum req_opf op; + int ret; if (!argp) return -EINVAL; @@ -352,6 +369,11 @@ int blkdev_zone_mgmt_ioctl(struct block_device *bdev, fmode_t mode, switch (cmd) { case BLKRESETZONE: op = REQ_OP_ZONE_RESET; + + /* Invalidate the page cache, including dirty pages. */ + ret = blkdev_truncate_zone_range(bdev, mode, &zrange); + if (ret) + return ret; break; case BLKOPENZONE: op = REQ_OP_ZONE_OPEN; @@ -366,8 +388,20 @@ int blkdev_zone_mgmt_ioctl(struct block_device *bdev, fmode_t mode, return -ENOTTY; } - return blkdev_zone_mgmt(bdev, op, zrange.sector, zrange.nr_sectors, - GFP_KERNEL); + ret = blkdev_zone_mgmt(bdev, op, zrange.sector, zrange.nr_sectors, + GFP_KERNEL); + + /* + * Invalidate the page cache again for zone reset: writes can only be + * direct for zoned devices so concurrent writes would not add any page + * to the page cache after/during reset. The page cache may be filled + * again due to concurrent reads though and dropping the pages for + * these is fine. + */ + if (!ret && cmd == BLKRESETZONE) + ret = blkdev_truncate_zone_range(bdev, mode, &zrange); + + return ret; } static inline unsigned long *blk_alloc_zone_bitmap(int node, diff --git a/block/bounce.c b/block/bounce.c index 87983a35079c22b821e7aa21bf2a1a3b5a75164b..6c441f4f1cd4aacc0b1b97dd10ee5657d08a166f 100644 --- a/block/bounce.c +++ b/block/bounce.c @@ -229,10 +229,10 @@ static struct bio *bounce_clone_bio(struct bio *bio_src) * - The point of cloning the biovec is to produce a bio with a biovec * the caller can modify: bi_idx and bi_bvec_done should be 0. * - * - The original bio could've had more than BIO_MAX_PAGES biovecs; if + * - The original bio could've had more than BIO_MAX_VECS biovecs; if * we tried to clone the whole thing bio_alloc_bioset() would fail. * But the clone should succeed as long as the number of biovecs we - * actually need to allocate is fewer than BIO_MAX_PAGES. + * actually need to allocate is fewer than BIO_MAX_VECS. * * - Lastly, bi_vcnt should not be looked at or relied upon by code * that does not own the bio - reason being drivers don't use it for @@ -299,7 +299,7 @@ static void __blk_queue_bounce(struct request_queue *q, struct bio **bio_orig, int sectors = 0; bio_for_each_segment(from, *bio_orig, iter) { - if (i++ < BIO_MAX_PAGES) + if (i++ < BIO_MAX_VECS) sectors += from.bv_len >> 9; if (page_to_pfn(from.bv_page) > q->limits.bounce_pfn) bounce = true; diff --git a/block/genhd.c b/block/genhd.c index c55e8f0fced1d830eb27c39dabf54357925e7d74..8c8f543572e64edc09147b4c6f833bc96dfdca9c 100644 --- a/block/genhd.c +++ b/block/genhd.c @@ -534,10 +534,8 @@ static void register_disk(struct device *parent, struct gendisk *disk, kobject_create_and_add("holders", &ddev->kobj); disk->slave_dir = kobject_create_and_add("slaves", &ddev->kobj); - if (disk->flags & GENHD_FL_HIDDEN) { - dev_set_uevent_suppress(ddev, 0); + if (disk->flags & GENHD_FL_HIDDEN) return; - } disk_scan_partitions(disk); diff --git a/crypto/Kconfig b/crypto/Kconfig index 15c9c28d9f5333866cd179accc1bb030741aca2d..5809cc198fa7c35dcc087447e8e7c244a41a885a 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -767,7 +767,7 @@ config CRYPTO_POLY1305_X86_64 config CRYPTO_POLY1305_MIPS tristate "Poly1305 authenticator algorithm (MIPS optimized)" - depends on CPU_MIPS32 || (CPU_MIPS64 && 64BIT) + depends on MIPS select CRYPTO_ARCH_HAVE_LIB_POLY1305 config CRYPTO_MD4 diff --git a/drivers/atm/eni.c b/drivers/atm/eni.c index 316a9947541fe005fac119697fe93c70f70f9051..b574cce98dc3686ce473b1f2cc132b4de8616ed2 100644 --- a/drivers/atm/eni.c +++ b/drivers/atm/eni.c @@ -2260,7 +2260,8 @@ static int eni_init_one(struct pci_dev *pci_dev, return rc; err_eni_release: - eni_do_release(dev); + dev->phy = NULL; + iounmap(ENI_DEV(dev)->ioaddr); err_unregister: atm_dev_deregister(dev); err_free_consistent: diff --git a/drivers/atm/idt77105.c b/drivers/atm/idt77105.c index 3c081b6171a8fc39ffd3ac2535533861ffc14d9f..bfca7b8a6f31e8c04b3dd6be960c45bbb8029021 100644 --- a/drivers/atm/idt77105.c +++ b/drivers/atm/idt77105.c @@ -262,7 +262,7 @@ static int idt77105_start(struct atm_dev *dev) { unsigned long flags; - if (!(dev->dev_data = kmalloc(sizeof(struct idt77105_priv),GFP_KERNEL))) + if (!(dev->phy_data = kmalloc(sizeof(struct idt77105_priv),GFP_KERNEL))) return -ENOMEM; PRIV(dev)->dev = dev; spin_lock_irqsave(&idt77105_priv_lock, flags); @@ -337,7 +337,7 @@ static int idt77105_stop(struct atm_dev *dev) else idt77105_all = walk->next; dev->phy = NULL; - dev->dev_data = NULL; + dev->phy_data = NULL; kfree(walk); break; } diff --git a/drivers/atm/lanai.c b/drivers/atm/lanai.c index d7277c26e423239e6e6971b7c6ba5f44a9e33d54..32d7aa141d96633dd9198cd1a6a0ded5baf3bcf5 100644 --- a/drivers/atm/lanai.c +++ b/drivers/atm/lanai.c @@ -2233,6 +2233,7 @@ static int lanai_dev_open(struct atm_dev *atmdev) conf1_write(lanai); #endif iounmap(lanai->base); + lanai->base = NULL; error_pci: pci_disable_device(lanai->pci); error: @@ -2245,6 +2246,8 @@ static int lanai_dev_open(struct atm_dev *atmdev) static void lanai_dev_close(struct atm_dev *atmdev) { struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; + if (lanai->base==NULL) + return; printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n", lanai->number); lanai_timed_poll_stop(lanai); @@ -2552,7 +2555,7 @@ static int lanai_init_one(struct pci_dev *pci, struct atm_dev *atmdev; int result; - lanai = kmalloc(sizeof(*lanai), GFP_KERNEL); + lanai = kzalloc(sizeof(*lanai), GFP_KERNEL); if (lanai == NULL) { printk(KERN_ERR DEV_LABEL ": couldn't allocate dev_data structure!\n"); diff --git a/drivers/atm/uPD98402.c b/drivers/atm/uPD98402.c index 7850758b5bb82bb736adf02c8f438076846786f2..239852d855589440f41075bd5e919627bc34fcf1 100644 --- a/drivers/atm/uPD98402.c +++ b/drivers/atm/uPD98402.c @@ -211,7 +211,7 @@ static void uPD98402_int(struct atm_dev *dev) static int uPD98402_start(struct atm_dev *dev) { DPRINTK("phy_start\n"); - if (!(dev->dev_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL))) + if (!(dev->phy_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL))) return -ENOMEM; spin_lock_init(&PRIV(dev)->lock); memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats)); diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c index 37179a8b1ceba78fc3b3dd32a42a10aeea7131b0..fa3719ef80e4d12b93655189ed4cec22075a04e0 100644 --- a/drivers/base/swnode.c +++ b/drivers/base/swnode.c @@ -938,6 +938,9 @@ int software_node_register(const struct software_node *node) if (software_node_to_swnode(node)) return -EEXIST; + if (node->parent && !parent) + return -EINVAL; + return PTR_ERR_OR_ZERO(swnode_register(node, parent, 0)); } EXPORT_SYMBOL_GPL(software_node_register); @@ -1002,25 +1005,33 @@ EXPORT_SYMBOL_GPL(fwnode_remove_software_node); /** * device_add_software_node - Assign software node to a device * @dev: The device the software node is meant for. - * @swnode: The software node. + * @node: The software node. * - * This function will register @swnode and make it the secondary firmware node - * pointer of @dev. If @dev has no primary node, then @swnode will become the primary - * node. + * This function will make @node the secondary firmware node pointer of @dev. If + * @dev has no primary node, then @node will become the primary node. The + * function will register @node automatically if it wasn't already registered. */ -int device_add_software_node(struct device *dev, const struct software_node *swnode) +int device_add_software_node(struct device *dev, const struct software_node *node) { + struct swnode *swnode; int ret; /* Only one software node per device. */ if (dev_to_swnode(dev)) return -EBUSY; - ret = software_node_register(swnode); - if (ret) - return ret; + swnode = software_node_to_swnode(node); + if (swnode) { + kobject_get(&swnode->kobj); + } else { + ret = software_node_register(node); + if (ret) + return ret; + + swnode = software_node_to_swnode(node); + } - set_secondary_fwnode(dev, software_node_fwnode(swnode)); + set_secondary_fwnode(dev, &swnode->fwnode); return 0; } diff --git a/drivers/block/drbd/drbd_int.h b/drivers/block/drbd/drbd_int.h index 7d9cc433b758ae9c29ac3cd76428f7dcc4fc6fac..5d9181382ce1909d7ebdd3c6e52e02044d42202a 100644 --- a/drivers/block/drbd/drbd_int.h +++ b/drivers/block/drbd/drbd_int.h @@ -1324,7 +1324,7 @@ struct bm_extent { * A followup commit may allow even bigger BIO sizes, * once we thought that through. */ #define DRBD_MAX_BIO_SIZE (1U << 20) -#if DRBD_MAX_BIO_SIZE > (BIO_MAX_PAGES << PAGE_SHIFT) +#if DRBD_MAX_BIO_SIZE > (BIO_MAX_VECS << PAGE_SHIFT) #error Architecture not supported: DRBD_MAX_BIO_SIZE > BIO_MAX_SIZE #endif #define DRBD_MAX_BIO_SIZE_SAFE (1U << 12) /* Works always = 4k */ diff --git a/drivers/block/rsxx/core.c b/drivers/block/rsxx/core.c index 5ac1881396afb135e74867e732be6e8943366afd..227e1be4c6f99e0f9d80615c375286d69333efd4 100644 --- a/drivers/block/rsxx/core.c +++ b/drivers/block/rsxx/core.c @@ -871,6 +871,7 @@ static int rsxx_pci_probe(struct pci_dev *dev, card->event_wq = create_singlethread_workqueue(DRIVER_NAME"_event"); if (!card->event_wq) { dev_err(CARD_TO_DEV(card), "Failed card event setup.\n"); + st = -ENOMEM; goto failed_event_handler; } diff --git a/drivers/block/umem.c b/drivers/block/umem.c index 982732dbe82e6971aeb19e221a0910409fd73735..664280f23bee19f89ff5e5e238e7cc68c0e6d0dc 100644 --- a/drivers/block/umem.c +++ b/drivers/block/umem.c @@ -877,6 +877,7 @@ static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) if (card->mm_pages[0].desc == NULL || card->mm_pages[1].desc == NULL) { dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n"); + ret = -ENOMEM; goto failed_alloc; } reset_page(&card->mm_pages[0]); @@ -888,8 +889,10 @@ static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) spin_lock_init(&card->lock); card->queue = blk_alloc_queue(NUMA_NO_NODE); - if (!card->queue) + if (!card->queue) { + ret = -ENOMEM; goto failed_alloc; + } tasklet_init(&card->tasklet, process_page, (unsigned long)card); diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index a711a2e2a7946bc466913c38585b867b62151748..cf8deecc39efbcda33968186c89861aa62f666d3 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -627,7 +627,7 @@ static ssize_t writeback_store(struct device *dev, struct bio_vec bio_vec; struct page *page; ssize_t ret = len; - int mode; + int mode, err; unsigned long blk_idx = 0; if (sysfs_streq(buf, "idle")) @@ -638,8 +638,8 @@ static ssize_t writeback_store(struct device *dev, if (strncmp(buf, PAGE_WB_SIG, sizeof(PAGE_WB_SIG) - 1)) return -EINVAL; - ret = kstrtol(buf + sizeof(PAGE_WB_SIG) - 1, 10, &index); - if (ret || index >= nr_pages) + if (kstrtol(buf + sizeof(PAGE_WB_SIG) - 1, 10, &index) || + index >= nr_pages) return -EINVAL; nr_pages = 1; @@ -663,7 +663,7 @@ static ssize_t writeback_store(struct device *dev, goto release_init_lock; } - while (nr_pages--) { + for (; nr_pages != 0; index++, nr_pages--) { struct bio_vec bvec; bvec.bv_page = page; @@ -728,12 +728,17 @@ static ssize_t writeback_store(struct device *dev, * XXX: A single page IO would be inefficient for write * but it would be not bad as starter. */ - ret = submit_bio_wait(&bio); - if (ret) { + err = submit_bio_wait(&bio); + if (err) { zram_slot_lock(zram, index); zram_clear_flag(zram, index, ZRAM_UNDER_WB); zram_clear_flag(zram, index, ZRAM_IDLE); zram_slot_unlock(zram, index); + /* + * Return last IO error unless every IO were + * not suceeded. + */ + ret = err; continue; } diff --git a/drivers/char/hw_random/pseries-rng.c b/drivers/char/hw_random/pseries-rng.c index 8038a8a9fb581a457dedcc48353b2a092e0b614e..f4949b689bd5ad5a6fe6633a4b812f1d92c8e818 100644 --- a/drivers/char/hw_random/pseries-rng.c +++ b/drivers/char/hw_random/pseries-rng.c @@ -54,10 +54,9 @@ static int pseries_rng_probe(struct vio_dev *dev, return hwrng_register(&pseries_rng); } -static int pseries_rng_remove(struct vio_dev *dev) +static void pseries_rng_remove(struct vio_dev *dev) { hwrng_unregister(&pseries_rng); - return 0; } static const struct vio_device_id pseries_rng_driver_ids[] = { diff --git a/drivers/char/tpm/tpm_ibmvtpm.c b/drivers/char/tpm/tpm_ibmvtpm.c index 994385bf37c0c044181f0ec2743779d80e09b38b..903604769de99cf2aa98e68145a3caa9f8a23e30 100644 --- a/drivers/char/tpm/tpm_ibmvtpm.c +++ b/drivers/char/tpm/tpm_ibmvtpm.c @@ -343,7 +343,7 @@ static int ibmvtpm_crq_send_init_complete(struct ibmvtpm_dev *ibmvtpm) * * Return: Always 0. */ -static int tpm_ibmvtpm_remove(struct vio_dev *vdev) +static void tpm_ibmvtpm_remove(struct vio_dev *vdev) { struct tpm_chip *chip = dev_get_drvdata(&vdev->dev); struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev); @@ -372,8 +372,6 @@ static int tpm_ibmvtpm_remove(struct vio_dev *vdev) kfree(ibmvtpm); /* For tpm_ibmvtpm_get_desired_dma */ dev_set_drvdata(&vdev->dev, NULL); - - return 0; } /** diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 3ba2f716fe9783c829e99b6bff345098ba0b477f..5e07065ec22f7420483897314247834567800ae1 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -103,6 +103,8 @@ static const struct of_device_id whitelist[] __initconst = { static const struct of_device_id blacklist[] __initconst = { { .compatible = "allwinner,sun50i-h6", }, + { .compatible = "arm,vexpress", }, + { .compatible = "calxeda,highbank", }, { .compatible = "calxeda,ecx-2000", }, diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index d3c23447b892d3e87c0fadb25351c5404aa3485b..f86859bf76f11d9f68b8d64a7b33ab75e274f3d5 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -317,9 +317,9 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) } base = ioremap(res->start, resource_size(res)); - if (IS_ERR(base)) { + if (!base) { dev_err(dev, "failed to map resource %pR\n", res); - ret = PTR_ERR(base); + ret = -ENOMEM; goto release_region; } @@ -374,7 +374,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) error: kfree(data); unmap_base: - iounmap(data->base); + iounmap(base); release_region: release_mem_region(res->start, resource_size(res)); return ret; diff --git a/drivers/crypto/nx/nx-842-pseries.c b/drivers/crypto/nx/nx-842-pseries.c index 2de5e3672e4233e0ab3673c04627146129ff5d64..cc8dd3072b8b77f0b9acb4971d80a68d1e3718fc 100644 --- a/drivers/crypto/nx/nx-842-pseries.c +++ b/drivers/crypto/nx/nx-842-pseries.c @@ -1042,7 +1042,7 @@ static int nx842_probe(struct vio_dev *viodev, return ret; } -static int nx842_remove(struct vio_dev *viodev) +static void nx842_remove(struct vio_dev *viodev) { struct nx842_devdata *old_devdata; unsigned long flags; @@ -1063,8 +1063,6 @@ static int nx842_remove(struct vio_dev *viodev) if (old_devdata) kfree(old_devdata->counters); kfree(old_devdata); - - return 0; } static const struct vio_device_id nx842_vio_driver_ids[] = { diff --git a/drivers/crypto/nx/nx.c b/drivers/crypto/nx/nx.c index 0d2dc5be7f1925f55f930edc651b2e7c8483c56a..1d0e8a1ba160507337f71ebb8d541ec7c09d76e5 100644 --- a/drivers/crypto/nx/nx.c +++ b/drivers/crypto/nx/nx.c @@ -783,7 +783,7 @@ static int nx_probe(struct vio_dev *viodev, const struct vio_device_id *id) return nx_register_algs(); } -static int nx_remove(struct vio_dev *viodev) +static void nx_remove(struct vio_dev *viodev) { dev_dbg(&viodev->dev, "entering nx_remove for UA 0x%x\n", viodev->unit_address); @@ -811,8 +811,6 @@ static int nx_remove(struct vio_dev *viodev) nx_unregister_skcipher(&nx_ecb_aes_alg, NX_FC_AES, NX_MODE_AES_ECB); } - - return 0; } diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c index 6b5db954569fc4b9c6dcdcc2bc78c157b2beb482..56bf5ad01ad54e40c297a4697a2b7f3aea1058cb 100644 --- a/drivers/dma-buf/dma-heap.c +++ b/drivers/dma-buf/dma-heap.c @@ -202,6 +202,18 @@ void *dma_heap_get_drvdata(struct dma_heap *heap) return heap->priv; } +/** + * dma_heap_get_name() - get heap name + * @heap: DMA-Heap to retrieve private data for + * + * Returns: + * The char* for the heap name. + */ +const char *dma_heap_get_name(struct dma_heap *heap) +{ + return heap->name; +} + struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) { struct dma_heap *heap, *h, *err_ret; diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/heaps/cma_heap.c index 5d64eccd21d638203ed25e72d143ffbfa8e94327..0c05b79870f967c08a4dde2a8644b91753d94741 100644 --- a/drivers/dma-buf/heaps/cma_heap.c +++ b/drivers/dma-buf/heaps/cma_heap.c @@ -339,6 +339,7 @@ static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, buffer->pagecount = pagecount; /* create the dmabuf */ + exp_info.exp_name = dma_heap_get_name(heap); exp_info.ops = &cma_heap_buf_ops; exp_info.size = buffer->len; exp_info.flags = fd_flags; diff --git a/drivers/dma-buf/heaps/system_heap.c b/drivers/dma-buf/heaps/system_heap.c index 29e49ac1725135ee6254ed9e0726e42bc885e7b3..23a7e74ef9666beb0b1a49471b4f658a849b235a 100644 --- a/drivers/dma-buf/heaps/system_heap.c +++ b/drivers/dma-buf/heaps/system_heap.c @@ -390,6 +390,7 @@ static struct dma_buf *system_heap_allocate(struct dma_heap *heap, } /* create the dmabuf */ + exp_info.exp_name = dma_heap_get_name(heap); exp_info.ops = &system_heap_buf_ops; exp_info.size = buffer->len; exp_info.flags = fd_flags; diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c index b69d63143e0d833449f5701cd114257987109e4a..7bf0a7acae5e689f8f3470ead6b67dc54ac08f2c 100644 --- a/drivers/firmware/efi/libstub/arm64-stub.c +++ b/drivers/firmware/efi/libstub/arm64-stub.c @@ -24,7 +24,7 @@ efi_status_t check_platform_features(void) return EFI_SUCCESS; tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_TGRAN_SHIFT) & 0xf; - if (tg != ID_AA64MMFR0_TGRAN_SUPPORTED) { + if (tg < ID_AA64MMFR0_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_TGRAN_SUPPORTED_MAX) { if (IS_ENABLED(CONFIG_ARM64_64K_PAGES)) efi_err("This 64 KB granular kernel is not supported by your CPU\n"); else diff --git a/drivers/firmware/efi/libstub/efi-stub.c b/drivers/firmware/efi/libstub/efi-stub.c index ec2f3985bef351b1a389284c1d202646cf699b2c..26e69788f27a42dd1fcbceeeb8bab3085b59a526 100644 --- a/drivers/firmware/efi/libstub/efi-stub.c +++ b/drivers/firmware/efi/libstub/efi-stub.c @@ -96,6 +96,18 @@ static void install_memreserve_table(void) efi_err("Failed to install memreserve config table!\n"); } +static u32 get_supported_rt_services(void) +{ + const efi_rt_properties_table_t *rt_prop_table; + u32 supported = EFI_RT_SUPPORTED_ALL; + + rt_prop_table = get_efi_config_table(EFI_RT_PROPERTIES_TABLE_GUID); + if (rt_prop_table) + supported &= rt_prop_table->runtime_services_supported; + + return supported; +} + /* * EFI entry point for the arm/arm64 EFI stubs. This is the entrypoint * that is described in the PE/COFF header. Most of the code is the same @@ -250,6 +262,10 @@ efi_status_t __efiapi efi_pe_entry(efi_handle_t handle, (prop_tbl->memory_protection_attribute & EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA); + /* force efi_novamap if SetVirtualAddressMap() is unsupported */ + efi_novamap |= !(get_supported_rt_services() & + EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP); + /* hibernation expects the runtime regions to stay in the same place */ if (!IS_ENABLED(CONFIG_HIBERNATION) && !efi_nokaslr && !flat_va_mapping) { /* diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 5ea09fd01544482aaadda083a0dae7de0f54a924..c91d0565159661967faa6a73ae0dfc9834fcfada 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -113,8 +113,29 @@ MODULE_DEVICE_TABLE(i2c, pca953x_id); #ifdef CONFIG_GPIO_PCA953X_IRQ #include -#include -#include + +static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; + +static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { + { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, + { } +}; + +static int pca953x_acpi_get_irq(struct device *dev) +{ + int ret; + + ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); + if (ret) + dev_warn(dev, "can't add GPIO ACPI mapping\n"); + + ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); + if (ret < 0) + return ret; + + dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); + return ret; +} static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { { @@ -133,59 +154,6 @@ static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { }, {} }; - -#ifdef CONFIG_ACPI -static int pca953x_acpi_get_pin(struct acpi_resource *ares, void *data) -{ - struct acpi_resource_gpio *agpio; - int *pin = data; - - if (acpi_gpio_get_irq_resource(ares, &agpio)) - *pin = agpio->pin_table[0]; - return 1; -} - -static int pca953x_acpi_find_pin(struct device *dev) -{ - struct acpi_device *adev = ACPI_COMPANION(dev); - int pin = -ENOENT, ret; - LIST_HEAD(r); - - ret = acpi_dev_get_resources(adev, &r, pca953x_acpi_get_pin, &pin); - acpi_dev_free_resource_list(&r); - if (ret < 0) - return ret; - - return pin; -} -#else -static inline int pca953x_acpi_find_pin(struct device *dev) { return -ENXIO; } -#endif - -static int pca953x_acpi_get_irq(struct device *dev) -{ - int pin, ret; - - pin = pca953x_acpi_find_pin(dev); - if (pin < 0) - return pin; - - dev_info(dev, "Applying ACPI interrupt quirk (GPIO %d)\n", pin); - - if (!gpio_is_valid(pin)) - return -EINVAL; - - ret = gpio_request(pin, "pca953x interrupt"); - if (ret) - return ret; - - ret = gpio_to_irq(pin); - - /* When pin is used as an IRQ, no need to keep it requested */ - gpio_free(pin); - - return ret; -} #endif static const struct acpi_device_id pca953x_acpi_ids[] = { diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index e37a57d0a2f07f44a2bf4426b3909f97c0ab7e8b..1aacd2a5a1fd53560469dbd3571a7929f4a4e4ca 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -174,7 +174,7 @@ static void acpi_gpiochip_request_irq(struct acpi_gpio_chip *acpi_gpio, int ret, value; ret = request_threaded_irq(event->irq, NULL, event->handler, - event->irqflags, "ACPI:Event", event); + event->irqflags | IRQF_ONESHOT, "ACPI:Event", event); if (ret) { dev_err(acpi_gpio->chip->parent, "Failed to setup interrupt handler for %d\n", @@ -677,6 +677,7 @@ static int acpi_populate_gpio_lookup(struct acpi_resource *ares, void *data) if (!lookup->desc) { const struct acpi_resource_gpio *agpio = &ares->data.gpio; bool gpioint = agpio->connection_type == ACPI_RESOURCE_GPIO_TYPE_INT; + struct gpio_desc *desc; u16 pin_index; if (lookup->info.quirks & ACPI_GPIO_QUIRK_ONLY_GPIOIO && gpioint) @@ -689,8 +690,12 @@ static int acpi_populate_gpio_lookup(struct acpi_resource *ares, void *data) if (pin_index >= agpio->pin_table_length) return 1; - lookup->desc = acpi_get_gpiod(agpio->resource_source.string_ptr, + if (lookup->info.quirks & ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER) + desc = gpio_to_desc(agpio->pin_table[pin_index]); + else + desc = acpi_get_gpiod(agpio->resource_source.string_ptr, agpio->pin_table[pin_index]); + lookup->desc = desc; lookup->info.pin_config = agpio->pin_config; lookup->info.debounce = agpio->debounce_timeout; lookup->info.gpioint = gpioint; @@ -940,8 +945,9 @@ struct gpio_desc *acpi_node_get_gpiod(struct fwnode_handle *fwnode, } /** - * acpi_dev_gpio_irq_get() - Find GpioInt and translate it to Linux IRQ number + * acpi_dev_gpio_irq_get_by() - Find GpioInt and translate it to Linux IRQ number * @adev: pointer to a ACPI device to get IRQ from + * @name: optional name of GpioInt resource * @index: index of GpioInt resource (starting from %0) * * If the device has one or more GpioInt resources, this function can be @@ -951,9 +957,12 @@ struct gpio_desc *acpi_node_get_gpiod(struct fwnode_handle *fwnode, * The function is idempotent, though each time it runs it will configure GPIO * pin direction according to the flags in GpioInt resource. * + * The function takes optional @name parameter. If the resource has a property + * name, then only those will be taken into account. + * * Return: Linux IRQ number (> %0) on success, negative errno on failure. */ -int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index) +int acpi_dev_gpio_irq_get_by(struct acpi_device *adev, const char *name, int index) { int idx, i; unsigned int irq_flags; @@ -963,7 +972,7 @@ int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index) struct acpi_gpio_info info; struct gpio_desc *desc; - desc = acpi_get_gpiod_by_index(adev, NULL, i, &info); + desc = acpi_get_gpiod_by_index(adev, name, i, &info); /* Ignore -EPROBE_DEFER, it only matters if idx matches */ if (IS_ERR(desc) && PTR_ERR(desc) != -EPROBE_DEFER) @@ -1008,7 +1017,7 @@ int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index) } return -ENOENT; } -EXPORT_SYMBOL_GPL(acpi_dev_gpio_irq_get); +EXPORT_SYMBOL_GPL(acpi_dev_gpio_irq_get_by); static acpi_status acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address, diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index adf55db080d86f1d3c07832972e2a468e53380e3..7ec0822c050553627a1414e7c5ac231d5d44a4a0 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -367,22 +367,18 @@ static int gpiochip_set_desc_names(struct gpio_chip *gc) * * Looks for device property "gpio-line-names" and if it exists assigns * GPIO line names for the chip. The memory allocated for the assigned - * names belong to the underlying software node and should not be released + * names belong to the underlying firmware node and should not be released * by the caller. */ static int devprop_gpiochip_set_names(struct gpio_chip *chip) { struct gpio_device *gdev = chip->gpiodev; - struct device *dev = chip->parent; + struct fwnode_handle *fwnode = dev_fwnode(&gdev->dev); const char **names; int ret, i; int count; - /* GPIO chip may not have a parent device whose properties we inspect. */ - if (!dev) - return 0; - - count = device_property_string_array_count(dev, "gpio-line-names"); + count = fwnode_property_string_array_count(fwnode, "gpio-line-names"); if (count < 0) return 0; @@ -396,7 +392,7 @@ static int devprop_gpiochip_set_names(struct gpio_chip *chip) if (!names) return -ENOMEM; - ret = device_property_read_string_array(dev, "gpio-line-names", + ret = fwnode_property_read_string_array(fwnode, "gpio-line-names", names, count); if (ret < 0) { dev_warn(&gdev->dev, "failed to read GPIO line names\n"); @@ -474,9 +470,13 @@ EXPORT_SYMBOL_GPL(gpiochip_line_is_valid); static void gpiodevice_release(struct device *dev) { - struct gpio_device *gdev = dev_get_drvdata(dev); + struct gpio_device *gdev = container_of(dev, struct gpio_device, dev); + unsigned long flags; + spin_lock_irqsave(&gpio_lock, flags); list_del(&gdev->list); + spin_unlock_irqrestore(&gpio_lock, flags); + ida_free(&gpio_ida, gdev->id); kfree_const(gdev->label); kfree(gdev->descs); @@ -605,7 +605,6 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, goto err_free_ida; device_initialize(&gdev->dev); - dev_set_drvdata(&gdev->dev, gdev); if (gc->parent && gc->parent->driver) gdev->owner = gc->parent->driver->owner; else if (gc->owner) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index e392a90ca6876cc3dcec88baacb3bc4099bbac6c..3c16bd1afd871839b919d283672e8f48d062a3dc 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -228,6 +228,7 @@ source "drivers/gpu/drm/arm/Kconfig" config DRM_RADEON tristate "ATI Radeon" depends on DRM && PCI && MMU + depends on AGP || !AGP select FW_LOADER select DRM_KMS_HELPER select DRM_TTM @@ -351,8 +352,6 @@ source "drivers/gpu/drm/vc4/Kconfig" source "drivers/gpu/drm/etnaviv/Kconfig" -source "drivers/gpu/drm/arc/Kconfig" - source "drivers/gpu/drm/hisilicon/Kconfig" source "drivers/gpu/drm/mediatek/Kconfig" @@ -385,6 +384,8 @@ source "drivers/gpu/drm/tidss/Kconfig" source "drivers/gpu/drm/xlnx/Kconfig" +source "drivers/gpu/drm/gud/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 926adef289db96d7c2d8c7c77f97acf81e6f799b..5279db4392dffd5198f4cc67e3021f486674d579 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -7,7 +7,7 @@ drm-y := drm_auth.o drm_cache.o \ drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_drv.o \ drm_sysfs.o drm_hashtab.o drm_mm.o \ - drm_crtc.o drm_fourcc.o drm_modes.o drm_edid.o \ + drm_crtc.o drm_fourcc.o drm_modes.o drm_edid.o drm_displayid.o \ drm_encoder_slave.o \ drm_trace_points.o drm_prime.o \ drm_rect.o drm_vma_manager.o drm_flip_work.o \ @@ -44,7 +44,8 @@ drm_kms_helper-y := drm_bridge_connector.o drm_crtc_helper.o drm_dp_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ drm_kms_helper_common.o drm_dp_dual_mode_helper.o \ drm_simple_kms_helper.o drm_modeset_helper.o \ - drm_scdc_helper.o drm_gem_framebuffer_helper.o \ + drm_scdc_helper.o drm_gem_atomic_helper.o \ + drm_gem_framebuffer_helper.o \ drm_atomic_state_helper.o drm_damage_helper.o \ drm_format_helper.o drm_self_refresh_helper.o @@ -110,7 +111,6 @@ obj-y += panel/ obj-y += bridge/ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/ obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/ -obj-$(CONFIG_DRM_ARCPGU)+= arc/ obj-y += hisilicon/ obj-$(CONFIG_DRM_ZTE) += zte/ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ @@ -125,3 +125,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ obj-$(CONFIG_DRM_MCDE) += mcde/ obj-$(CONFIG_DRM_TIDSS) += tidss/ obj-y += xlnx/ +obj-y += gud/ diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 9375e7f1242057274c70eec0f24678bdee6f0965..74a8105fd2c0309464352285d67340dc372791fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -34,15 +34,6 @@ config DRM_AMDGPU_USERPTR This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it isn't already selected to enabled full userptr support. -config DRM_AMDGPU_GART_DEBUGFS - bool "Allow GART access through debugfs" - depends on DRM_AMDGPU - depends on DEBUG_FS - default n - help - Selecting this option creates a debugfs file to inspect the mapped - pages. Uses more memory for housekeeping, enable only for debugging. - source "drivers/gpu/drm/amd/acp/Kconfig" source "drivers/gpu/drm/amd/display/Kconfig" source "drivers/gpu/drm/amd/amdkfd/Kconfig" diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 13ebb1f71e49753b3ee0579502f6c32498e04e90..741b68874e5388b9fe3a88af127487d9d7432270 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -71,7 +71,7 @@ amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \ - nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o + nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o # add DF block amdgpu-y += \ @@ -83,7 +83,8 @@ amdgpu-y += \ gmc_v7_0.o \ gmc_v8_0.o \ gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \ - gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o + gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \ + mmhub_v1_7.o # add UMC block amdgpu-y += \ @@ -106,7 +107,8 @@ amdgpu-y += \ psp_v3_1.o \ psp_v10_0.o \ psp_v11_0.o \ - psp_v12_0.o + psp_v12_0.o \ + psp_v13_0.o # add DCE block amdgpu-y += \ @@ -121,6 +123,7 @@ amdgpu-y += \ gfx_v8_0.o \ gfx_v9_0.o \ gfx_v9_4.o \ + gfx_v9_4_2.o \ gfx_v10_0.o # add async DMA block @@ -129,6 +132,7 @@ amdgpu-y += \ sdma_v2_4.o \ sdma_v3_0.o \ sdma_v4_0.o \ + sdma_v4_4.o \ sdma_v5_0.o \ sdma_v5_2.o @@ -172,7 +176,8 @@ amdgpu-y += \ amdgpu-y += \ smuio_v9_0.o \ smuio_v11_0.o \ - smuio_v11_0_6.o + smuio_v11_0_6.o \ + smuio_v13_0.o # add amdkfd interfaces amdgpu-y += amdgpu_amdkfd.o @@ -187,6 +192,7 @@ amdgpu-y += \ amdgpu_amdkfd_gfx_v8.o \ amdgpu_amdkfd_gfx_v9.o \ amdgpu_amdkfd_arcturus.o \ + amdgpu_amdkfd_aldebaran.o \ amdgpu_amdkfd_gfx_v10.o \ amdgpu_amdkfd_gfx_v10_3.o diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c b/drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c new file mode 100644 index 0000000000000000000000000000000000000000..28e6c9ab8767951396fc76f6ed6761ba16e1c27e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c @@ -0,0 +1,54 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "soc15.h" + +#include "soc15_common.h" +#include "aldebaran_ip_offset.h" + +int aldebaran_reg_base_init(struct amdgpu_device *adev) +{ + /* HW has more IP blocks, only initialized the block needed by our driver */ + uint32_t i; + for (i = 0 ; i < MAX_INSTANCE ; ++i) { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); + adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); + adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); + adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b6879d97c9c9c16fe055fb6c3cfee2f8491ab7fb..a037c223c251b7ca57b026534a30a1d4c89c2af3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -124,6 +124,16 @@ struct amdgpu_mgpu_info uint32_t num_gpu; uint32_t num_dgpu; uint32_t num_apu; + + /* delayed reset_func for XGMI configuration if necessary */ + struct delayed_work delayed_reset_work; + bool pending_reset; +}; + +struct amdgpu_watchdog_timer +{ + bool timeout_fatal_disable; + uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ }; #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 @@ -177,13 +187,17 @@ extern int amdgpu_compute_multipipe; extern int amdgpu_gpu_recovery; extern int amdgpu_emu_mode; extern uint amdgpu_smu_memory_pool_size; +extern int amdgpu_smu_pptable_id; extern uint amdgpu_dc_feature_mask; +extern uint amdgpu_freesync_vid_mode; extern uint amdgpu_dc_debug_mask; extern uint amdgpu_dm_abm_level; +extern int amdgpu_backlight; extern struct amdgpu_mgpu_info mgpu_info; extern int amdgpu_ras_enable; extern uint amdgpu_ras_mask; extern int amdgpu_bad_page_threshold; +extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; extern int amdgpu_async_gfx_ring; extern int amdgpu_mcbp; extern int amdgpu_discovery; @@ -583,6 +597,19 @@ enum amd_reset_method { AMD_RESET_METHOD_PCI, }; +struct amdgpu_video_codec_info { + u32 codec_type; + u32 max_width; + u32 max_height; + u32 max_pixels_per_frame; + u32 max_level; +}; + +struct amdgpu_video_codecs { + const u32 codec_count; + const struct amdgpu_video_codec_info *codec_array; +}; + /* * ASIC specific functions. */ @@ -627,6 +654,9 @@ struct amdgpu_asic_funcs { void (*pre_asic_init)(struct amdgpu_device *adev); /* enter/exit umd stable pstate */ int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); + /* query video codecs */ + int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs); }; /* @@ -791,12 +821,7 @@ struct amdgpu_device { bool accel_working; struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; - struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; - unsigned debugfs_count; -#if defined(CONFIG_DEBUG_FS) - struct dentry *debugfs_preempt; - struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; -#endif + struct debugfs_blob_wrapper debugfs_vbios_blob; struct amdgpu_atif *atif; struct amdgpu_atcs atcs; struct mutex srbm_mutex; @@ -852,8 +877,6 @@ struct amdgpu_device { spinlock_t audio_endpt_idx_lock; amdgpu_block_rreg_t audio_endpt_rreg; amdgpu_block_wreg_t audio_endpt_wreg; - void __iomem *rio_mem; - resource_size_t rio_mem_size; struct amdgpu_doorbell doorbell; /* clock/pll info */ @@ -896,6 +919,7 @@ struct amdgpu_device { struct amdgpu_irq_src vupdate_irq; struct amdgpu_irq_src pageflip_irq; struct amdgpu_irq_src hpd_irq; + struct amdgpu_irq_src dmub_trace_irq; /* rings */ u64 fence_context; @@ -1023,6 +1047,7 @@ struct amdgpu_device { int asic_reset_res; struct work_struct xgmi_reset_work; + struct list_head reset_list; long gfx_timeout; long sdma_timeout; @@ -1065,7 +1090,7 @@ static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) return &adev->ddev; } -static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) +static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) { return container_of(bdev, struct amdgpu_device, mman.bdev); } @@ -1087,9 +1112,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); -u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); -void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); - u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 pcie_index, u32 pcie_data, u32 reg_addr); @@ -1106,6 +1128,15 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); +int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, + struct amdgpu_job *job, + bool *need_full_reset_arg); + +int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, + struct list_head *device_list_handle, + bool *need_full_reset_arg, + bool skip_hw_reset); + int emu_soc_asic_init(struct amdgpu_device *adev); /* @@ -1171,8 +1202,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); } while (0) #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) -#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) -#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK @@ -1226,6 +1255,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) +#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); @@ -1246,6 +1276,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 array_size); bool amdgpu_device_supports_atpx(struct drm_device *dev); +int amdgpu_device_mode1_reset(struct amdgpu_device *adev); bool amdgpu_device_supports_boco(struct drm_device *dev); bool amdgpu_device_supports_baco(struct drm_device *dev); bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 36a741d63ddcf602ca408e025b7b198b43157d2a..2e9b16fb3fcd149b2063b05a9c936e3f0e5a42f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -903,7 +903,7 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev) */ bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { -#if defined(CONFIG_AMD_PMC) +#if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE) if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) { if (adev->flags & AMD_IS_APU) return true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index c5343a5eecbeb6ac11ca5dd31b766abec0080f63..1c6be53313a83b711481f2251954b531e682d257 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -44,7 +44,7 @@ int amdgpu_amdkfd_init(void) int ret; si_meminfo(&si); - amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh; + amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; amdgpu_amdkfd_total_mem_size *= si.mem_unit; ret = kgd2kfd_init(); @@ -165,7 +165,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) adev->doorbell_index.last_non_cp; } - kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources); + adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, + adev_to_drm(adev), &gpu_resources); } } @@ -638,13 +639,6 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) { struct amdgpu_device *adev = (struct amdgpu_device *)kgd; - /* Temp workaround to fix the soft hang observed in certain compute - * applications if GFXOFF is enabled. - */ - if (adev->asic_type == CHIP_SIENNA_CICHLID) { - pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); - amdgpu_gfx_off_ctrl(adev, idle); - } amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index a81d9cacf9b8fc31f324972904d1fa7ab49b0b80..14f68c02812686e46804f669a45696585fedb4f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -80,6 +80,7 @@ struct amdgpu_amdkfd_fence { struct amdgpu_kfd_dev { struct kfd_dev *dev; uint64_t vram_used; + bool init_complete; }; enum kgd_engine_type { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c new file mode 100644 index 0000000000000000000000000000000000000000..a5434b71385624816c5013fcd50d36a6897e8b34 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -0,0 +1,47 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "amdgpu.h" +#include "amdgpu_amdkfd.h" +#include "amdgpu_amdkfd_arcturus.h" +#include "amdgpu_amdkfd_gfx_v9.h" + +const struct kfd2kgd_calls aldebaran_kfd2kgd = { + .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, + .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, + .init_interrupts = kgd_gfx_v9_init_interrupts, + .hqd_load = kgd_gfx_v9_hqd_load, + .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load, + .hqd_sdma_load = kgd_arcturus_hqd_sdma_load, + .hqd_dump = kgd_gfx_v9_hqd_dump, + .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump, + .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, + .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied, + .hqd_destroy = kgd_gfx_v9_hqd_destroy, + .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy, + .address_watch_disable = kgd_gfx_v9_address_watch_disable, + .address_watch_execute = kgd_gfx_v9_address_watch_execute, + .wave_control_execute = kgd_gfx_v9_wave_control_execute, + .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, + .get_atc_vmid_pasid_mapping_info = + kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, + .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 604757a1e44051dcd19583af7d723860afa154d4..9ef9f3ddad4822904a9ddeeab017ea0053d613bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -122,7 +122,7 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, return sdma_rlc_reg_offset; } -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, +int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { struct amdgpu_device *adev = get_amdgpu_device(kgd); @@ -192,7 +192,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, return 0; } -static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, +int kgd_arcturus_hqd_sdma_dump(struct kgd_dev *kgd, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) { @@ -224,7 +224,7 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, return 0; } -static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) +bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) { struct amdgpu_device *adev = get_amdgpu_device(kgd); struct v9_sdma_mqd *m; @@ -243,7 +243,7 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, +int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, unsigned int utimeout) { struct amdgpu_device *adev = get_amdgpu_device(kgd); @@ -289,13 +289,13 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .init_interrupts = kgd_gfx_v9_init_interrupts, .hqd_load = kgd_gfx_v9_hqd_load, .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load, - .hqd_sdma_load = kgd_hqd_sdma_load, + .hqd_sdma_load = kgd_arcturus_hqd_sdma_load, .hqd_dump = kgd_gfx_v9_hqd_dump, - .hqd_sdma_dump = kgd_hqd_sdma_dump, + .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump, .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, - .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, + .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied, .hqd_destroy = kgd_gfx_v9_hqd_destroy, - .hqd_sdma_destroy = kgd_hqd_sdma_destroy, + .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy, .address_watch_disable = kgd_gfx_v9_address_watch_disable, .address_watch_execute = kgd_gfx_v9_address_watch_execute, .wave_control_execute = kgd_gfx_v9_wave_control_execute, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h new file mode 100644 index 0000000000000000000000000000000000000000..ce08131b7b5fde418712692ffdd6dc7a5184d9b3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h @@ -0,0 +1,30 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm); +int kgd_arcturus_hqd_sdma_dump(struct kgd_dev *kgd, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs); +bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); +int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, + unsigned int utimeout); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 3107b9575929184bbf624d579bdcf3589116efdc..5af46493397662dd7cab015da86d1a895894db8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -40,13 +40,13 @@ static atomic_t fence_seq = ATOMIC_INIT(0); * All the BOs in a process share an eviction fence. When process X wants * to map VRAM memory but TTM can't find enough space, TTM will attempt to * evict BOs from its LRU list. TTM checks if the BO is valuable to evict - * by calling ttm_bo_driver->eviction_valuable(). + * by calling ttm_device_funcs->eviction_valuable(). * - * ttm_bo_driver->eviction_valuable() - will return false if the BO belongs + * ttm_device_funcs->eviction_valuable() - will return false if the BO belongs * to process X. Otherwise, it will return true to indicate BO can be * evicted by TTM. * - * If ttm_bo_driver->eviction_valuable returns true, then TTM will continue + * If ttm_device_funcs->eviction_valuable returns true, then TTM will continue * the evcition process for that BO by calling ttm_bo_evict --> amdgpu_bo_move * --> amdgpu_copy_buffer(). This sets up job in GPU scheduler. * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index ac0a432a9bf79fc6878e616c1f93f7c05d542705..e93850f2f3b11c400eea93b0b5da27259681a15e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -31,6 +31,7 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" #include +#include "amdgpu_xgmi.h" /* BO flag to indicate a KFD userptr BO */ #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63) @@ -96,7 +97,7 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void) uint64_t mem; si_meminfo(&si); - mem = si.totalram - si.totalhigh; + mem = si.freeram - si.freehigh; mem *= si.mem_unit; spin_lock_init(&kfd_mem_limit.mem_limit_lock); @@ -119,6 +120,16 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void) */ #define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14) +static size_t amdgpu_amdkfd_acc_size(uint64_t size) +{ + size >>= PAGE_SHIFT; + size *= sizeof(dma_addr_t) + sizeof(void *); + + return __roundup_pow_of_two(sizeof(struct amdgpu_bo)) + + __roundup_pow_of_two(sizeof(struct ttm_tt)) + + PAGE_ALIGN(size); +} + static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, uint64_t size, u32 domain, bool sg) { @@ -127,8 +138,7 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed; int ret = 0; - acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, - sizeof(struct amdgpu_bo)); + acc_size = amdgpu_amdkfd_acc_size(size); vram_needed = 0; if (domain == AMDGPU_GEM_DOMAIN_GTT) { @@ -175,8 +185,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev, { size_t acc_size; - acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, - sizeof(struct amdgpu_bo)); + acc_size = amdgpu_amdkfd_acc_size(size); spin_lock(&kfd_mem_limit.mem_limit_lock); if (domain == AMDGPU_GEM_DOMAIN_GTT) { @@ -404,7 +413,10 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) { struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT; + bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED; uint32_t mapping_flags; + uint64_t pte_flags; + bool snoop = false; mapping_flags = AMDGPU_VM_PAGE_READABLE; if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE) @@ -425,12 +437,41 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; } break; + case CHIP_ALDEBARAN: + if (coherent && uncached) { + if (adev->gmc.xgmi.connected_to_cpu || + !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)) + snoop = true; + mapping_flags |= AMDGPU_VM_MTYPE_UC; + } else if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + if (bo_adev == adev) { + mapping_flags |= AMDGPU_VM_MTYPE_RW; + if (adev->gmc.xgmi.connected_to_cpu) + snoop = true; + } else { + mapping_flags |= AMDGPU_VM_MTYPE_NC; + if (amdgpu_xgmi_same_hive(adev, bo_adev)) + snoop = true; + } + } else { + snoop = true; + if (adev->gmc.xgmi.connected_to_cpu) + /* system memory uses NC on A+A */ + mapping_flags |= AMDGPU_VM_MTYPE_NC; + else + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + } + break; default: mapping_flags |= coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; } - return amdgpu_gem_va_map_flags(adev, mapping_flags); + pte_flags = amdgpu_gem_va_map_flags(adev, mapping_flags); + pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; + + return pte_flags; } /* add_bo_to_vm - Add a BO to a VM diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 86add0f4ea4d0a9b49506f7f202db4888cc57058..e05648a8a14544ee575edadb0151c106c56149b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1905,40 +1905,6 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) return r; } -/** - * cail_ioreg_write - write IO register - * - * @info: atom card_info pointer - * @reg: IO register offset - * @val: value to write to the pll register - * - * Provides a IO register accessor for the atom interpreter (r4xx+). - */ -static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) -{ - struct amdgpu_device *adev = drm_to_adev(info->dev); - - WREG32_IO(reg, val); -} - -/** - * cail_ioreg_read - read IO register - * - * @info: atom card_info pointer - * @reg: IO register offset - * - * Provides an IO register accessor for the atom interpreter (r4xx+). - * Returns the value of the IO register. - */ -static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) -{ - struct amdgpu_device *adev = drm_to_adev(info->dev); - uint32_t r; - - r = RREG32_IO(reg); - return r; -} - static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, struct device_attribute *attr, char *buf) @@ -1998,15 +1964,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) atom_card_info->dev = adev_to_drm(adev); atom_card_info->reg_read = cail_reg_read; atom_card_info->reg_write = cail_reg_write; - /* needed for iio ops */ - if (adev->rio_mem) { - atom_card_info->ioreg_read = cail_ioreg_read; - atom_card_info->ioreg_write = cail_ioreg_write; - } else { - DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); - atom_card_info->ioreg_read = cail_reg_read; - atom_card_info->ioreg_write = cail_reg_write; - } atom_card_info->mc_read = cail_mc_read; atom_card_info->mc_write = cail_mc_write; atom_card_info->pll_read = cail_pll_read; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 6107ac91db250731468f7e86b56ffbe63daca372..60716b35444b4535bb243d206dc5be88dacd8f68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -117,12 +117,15 @@ union igp_info { union umc_info { struct atom_umc_info_v3_1 v31; + struct atom_umc_info_v3_2 v32; + struct atom_umc_info_v3_3 v33; }; union vram_info { struct atom_vram_info_header_v2_3 v23; struct atom_vram_info_header_v2_4 v24; struct atom_vram_info_header_v2_5 v25; + struct atom_vram_info_header_v2_6 v26; }; union vram_module { @@ -164,6 +167,7 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, vram_type = AMDGPU_VRAM_TYPE_GDDR5; break; case ATOM_DGPU_VRAM_TYPE_HBM2: + case ATOM_DGPU_VRAM_TYPE_HBM2E: vram_type = AMDGPU_VRAM_TYPE_HBM; break; case ATOM_DGPU_VRAM_TYPE_GDDR6: @@ -315,6 +319,26 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, if (vram_vendor) *vram_vendor = mem_vendor; break; + case 6: + if (module_id > vram_info->v26.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v26.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v9.vram_module_size); + i++; + } + mem_type = vram_module->v9.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v9.channel_num; + mem_channel_width = vram_module->v9.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; default: return -EINVAL; } @@ -337,19 +361,39 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) union umc_info *umc_info; u8 frev, crev; bool ecc_default_enabled = false; + u8 umc_config; + u32 umc_config1; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { - /* support umc_info 3.1+ */ - if ((frev == 3 && crev >= 1) || (frev > 3)) { + if (frev == 3) { umc_info = (union umc_info *) (mode_info->atom_context->bios + data_offset); - ecc_default_enabled = - (le32_to_cpu(umc_info->v31.umc_config) & - UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + switch (crev) { + case 1: + umc_config = le32_to_cpu(umc_info->v31.umc_config); + ecc_default_enabled = + (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + break; + case 2: + umc_config = le32_to_cpu(umc_info->v32.umc_config); + ecc_default_enabled = + (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + break; + case 3: + umc_config = le32_to_cpu(umc_info->v33.umc_config); + umc_config1 = le32_to_cpu(umc_info->v33.umc_config1); + ecc_default_enabled = + ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) || + (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false; + break; + default: + /* unsupported crev */ + return false; + } } } @@ -479,7 +523,8 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) } union gfx_info { - struct atom_gfx_info_v2_4 v24; + struct atom_gfx_info_v2_4 v24; + struct atom_gfx_info_v2_7 v27; }; int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) @@ -514,6 +559,22 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); return 0; + case 7: + adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines; + adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; + adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; + adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; + adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches; + adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); + adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds; + adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth; + adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth); + adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer; + adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size); + adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd); + adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu; + adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size); + return 0; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index cfb1a9a044772c828e80b8b80916330033ed61a2..27b19503773b93a4cc7a2019d9eff80150212ea5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -97,6 +97,10 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) if (amdgpu_device_need_post(adev)) return false; + /* FB BAR not enabled */ + if (pci_resource_len(adev->pdev, 0) == 0) + return false; + adev->bios = NULL; vram_base = pci_resource_start(adev->pdev, 0); bios = ioremap_wc(vram_base, size); @@ -316,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) adev->bios = kmalloc(size, GFP_KERNEL); if (!adev->bios) { - DRM_ERROR("Unable to allocate bios\n"); + dev_err(adev->dev, "Unable to allocate bios\n"); return false; } @@ -364,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) return false; tbl_size = hdr->length; if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { - DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); + dev_info(adev->dev, "ACPI VFCT table present but broken (too short #1),skipping\n"); return false; } @@ -377,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) offset += sizeof(VFCT_IMAGE_HEADER); if (offset > tbl_size) { - DRM_ERROR("ACPI VFCT image header truncated\n"); + dev_info(adev->dev, "ACPI VFCT image header truncated,skipping\n"); return false; } offset += vhdr->ImageLength; if (offset > tbl_size) { - DRM_ERROR("ACPI VFCT image truncated\n"); + dev_info(adev->dev, "ACPI VFCT image truncated,skipping\n"); return false; } @@ -406,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) } } - DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); + dev_info(adev->dev, "ACPI VFCT table present but broken (too short #2),skipping\n"); return false; } #else @@ -453,7 +457,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev) goto success; } - DRM_ERROR("Unable to locate a BIOS ROM\n"); + dev_err(adev->dev, "Unable to locate a BIOS ROM\n"); return false; success: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 3e240b952e7912a36365bdf7d2191e981b08598d..b5c7669980458480f2ff167fd55521eb18a56852 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -117,7 +117,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs if (cs->in.num_chunks == 0) return 0; - chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); + chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); if (!chunk_array) return -ENOMEM; @@ -144,7 +144,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs } p->nchunks = cs->in.num_chunks; - p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), + p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), GFP_KERNEL); if (!p->chunks) { ret = -ENOMEM; @@ -238,7 +238,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs if (p->uf_entry.tv.bo) p->job->uf_addr = uf_offset; - kfree(chunk_array); + kvfree(chunk_array); /* Use this opportunity to fill in task info for the vm */ amdgpu_vm_set_task_info(vm); @@ -250,11 +250,11 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs free_partial_kdata: for (; i >= 0; i--) kvfree(p->chunks[i].kdata); - kfree(p->chunks); + kvfree(p->chunks); p->chunks = NULL; p->nchunks = 0; free_chunk: - kfree(chunk_array); + kvfree(chunk_array); return ret; } @@ -559,7 +559,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, sizeof(struct page *), GFP_KERNEL | __GFP_ZERO); if (!e->user_pages) { - DRM_ERROR("calloc failure\n"); + DRM_ERROR("kvmalloc_array failure\n"); return -ENOMEM; } @@ -706,7 +706,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, for (i = 0; i < parser->nchunks; i++) kvfree(parser->chunks[i].kdata); - kfree(parser->chunks); + kvfree(parser->chunks); if (parser->job) amdgpu_job_free(parser->job); if (parser->uf_entry.tv.bo) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 43059ead733bdc60a86557e5d1b838971794da54..bcaf271b39bf52e3792decd63fe0bdc745f1b562 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "amdgpu.h" #include "amdgpu_pm.h" @@ -38,45 +37,6 @@ #include "amdgpu_securedisplay.h" #include "amdgpu_fw_attestation.h" -/** - * amdgpu_debugfs_add_files - Add simple debugfs entries - * - * @adev: Device to attach debugfs entries to - * @files: Array of function callbacks that respond to reads - * @nfiles: Number of callbacks to register - * - */ -int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - const struct drm_info_list *files, - unsigned nfiles) -{ - unsigned i; - - for (i = 0; i < adev->debugfs_count; i++) { - if (adev->debugfs[i].files == files) { - /* Already registered */ - return 0; - } - } - - i = adev->debugfs_count + 1; - if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { - DRM_ERROR("Reached maximum number of debugfs components.\n"); - DRM_ERROR("Report so we increase " - "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); - return -EINVAL; - } - adev->debugfs[adev->debugfs_count].files = files; - adev->debugfs[adev->debugfs_count].num_files = nfiles; - adev->debugfs_count = i; -#if defined(CONFIG_DEBUG_FS) - drm_debugfs_create_files(files, nfiles, - adev_to_drm(adev)->primary->debugfs_root, - adev_to_drm(adev)->primary); -#endif - return 0; -} - int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) @@ -1228,22 +1188,20 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) adev, debugfs_regs[i]); if (!i && !IS_ERR_OR_NULL(ent)) i_size_write(ent->d_inode, adev->rmmio_size); - adev->debugfs_regs[i] = ent; } return 0; } -static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) +static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct drm_device *dev = adev_to_drm(adev); int r = 0, i; r = pm_runtime_get_sync(dev->dev); if (r < 0) { - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(dev->dev); return r; } @@ -1285,30 +1243,19 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) return 0; } -static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) +static int amdgpu_debugfs_evict_vram(void *data, u64 *val) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - - seq_write(m, adev->bios, adev->bios_size); - return 0; -} - -static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct drm_device *dev = adev_to_drm(adev); int r; r = pm_runtime_get_sync(dev->dev); if (r < 0) { - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(dev->dev); return r; } - seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); + *val = amdgpu_bo_evict_vram(adev); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -1316,11 +1263,11 @@ static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) return 0; } -static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data) + +static int amdgpu_debugfs_evict_gtt(void *data, u64 *val) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct drm_device *dev = adev_to_drm(adev); struct ttm_resource_manager *man; int r; @@ -1331,8 +1278,7 @@ static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data) } man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); - r = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - seq_printf(m, "(%d)\n", r); + *val = ttm_resource_manager_evict_all(&adev->mman.bdev, man); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -1340,10 +1286,11 @@ static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data) return 0; } -static int amdgpu_debugfs_vm_info(struct seq_file *m, void *data) + +static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct drm_device *dev = adev_to_drm(adev); struct drm_file *file; int r; @@ -1369,13 +1316,12 @@ static int amdgpu_debugfs_vm_info(struct seq_file *m, void *data) return r; } -static const struct drm_info_list amdgpu_debugfs_list[] = { - {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, - {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, - {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram}, - {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt}, - {"amdgpu_vm_info", &amdgpu_debugfs_vm_info}, -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); +DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, + NULL, "%lld\n"); +DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, + NULL, "%lld\n"); static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -1586,71 +1532,50 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return 0; } -DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL, +DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL, +DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); int amdgpu_debugfs_init(struct amdgpu_device *adev) { + struct dentry *root = adev_to_drm(adev)->primary->debugfs_root; + struct dentry *ent; int r, i; - adev->debugfs_preempt = - debugfs_create_file("amdgpu_preempt_ib", 0600, - adev_to_drm(adev)->primary->debugfs_root, adev, - &fops_ib_preempt); - if (!(adev->debugfs_preempt)) { + + + ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev, + &fops_ib_preempt); + if (!ent) { DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n"); return -EIO; } - adev->smu.debugfs_sclk = - debugfs_create_file("amdgpu_force_sclk", 0200, - adev_to_drm(adev)->primary->debugfs_root, adev, - &fops_sclk_set); - if (!(adev->smu.debugfs_sclk)) { + ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev, + &fops_sclk_set); + if (!ent) { DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); return -EIO; } /* Register debugfs entries for amdgpu_ttm */ - r = amdgpu_ttm_debugfs_init(adev); - if (r) { - DRM_ERROR("Failed to init debugfs\n"); - return r; - } - - r = amdgpu_debugfs_pm_init(adev); - if (r) { - DRM_ERROR("Failed to register debugfs file for dpm!\n"); - return r; - } - - if (amdgpu_debugfs_sa_init(adev)) { - dev_err(adev->dev, "failed to register debugfs file for SA\n"); - } - - if (amdgpu_debugfs_fence_init(adev)) - dev_err(adev->dev, "fence debugfs file creation failed\n"); - - r = amdgpu_debugfs_gem_init(adev); - if (r) - DRM_ERROR("registering gem debugfs failed (%d).\n", r); + amdgpu_ttm_debugfs_init(adev); + amdgpu_debugfs_pm_init(adev); + amdgpu_debugfs_sa_init(adev); + amdgpu_debugfs_fence_init(adev); + amdgpu_debugfs_gem_init(adev); r = amdgpu_debugfs_regs_init(adev); if (r) DRM_ERROR("registering register debugfs failed (%d).\n", r); - r = amdgpu_debugfs_firmware_init(adev); - if (r) - DRM_ERROR("registering firmware debugfs failed (%d).\n", r); + amdgpu_debugfs_firmware_init(adev); #if defined(CONFIG_DRM_AMD_DC) - if (amdgpu_device_has_dc_support(adev)) { - if (dtn_debugfs_init(adev)) - DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); - } + if (amdgpu_device_has_dc_support(adev)) + dtn_debugfs_init(adev); #endif for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { @@ -1665,17 +1590,26 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) } amdgpu_ras_debugfs_create_all(adev); - amdgpu_debugfs_autodump_init(adev); - amdgpu_rap_debugfs_init(adev); - amdgpu_securedisplay_debugfs_init(adev); - amdgpu_fw_attestation_debugfs_init(adev); - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, - ARRAY_SIZE(amdgpu_debugfs_list)); + debugfs_create_file("amdgpu_evict_vram", 0444, root, adev, + &amdgpu_evict_vram_fops); + debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev, + &amdgpu_evict_gtt_fops); + debugfs_create_file("amdgpu_test_ib", 0444, root, adev, + &amdgpu_debugfs_test_ib_fops); + debugfs_create_file("amdgpu_vm_info", 0444, root, adev, + &amdgpu_debugfs_vm_info_fops); + + adev->debugfs_vbios_blob.data = adev->bios; + adev->debugfs_vbios_blob.size = adev->bios_size; + debugfs_create_blob("amdgpu_vbios", 0444, root, + &adev->debugfs_vbios_blob); + + return 0; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 2803884d338d53c1218b969fdb61c13658885660..141a8474e24f24d75b340b236ecdee7ef5b178f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -26,11 +26,6 @@ /* * Debugfs */ -struct amdgpu_debugfs { - const struct drm_info_list *files; - unsigned num_files; -}; - struct amdgpu_autodump { struct completion dumping; struct wait_queue_head gpu_hang; @@ -39,10 +34,7 @@ struct amdgpu_autodump { int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); -int amdgpu_debugfs_add_files(struct amdgpu_device *adev, - const struct drm_info_list *files, - unsigned nfiles); -int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); -int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); -int amdgpu_debugfs_gem_init(struct amdgpu_device *adev); +void amdgpu_debugfs_fence_init(struct amdgpu_device *adev); +void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); +void amdgpu_debugfs_gem_init(struct amdgpu_device *adev); int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6447cd6ca5a8eb54841e2c9999c33a1437b02408..0f82c5d212372354a2de059509f478e67c7c3fd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -110,6 +110,7 @@ const char *amdgpu_asic_name[] = { "RAVEN", "ARCTURUS", "RENOIR", + "ALDEBARAN", "NAVI10", "NAVI14", "NAVI12", @@ -464,49 +465,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, } } -/** - * amdgpu_io_rreg - read an IO register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * - * Returns the 32 bit value from the offset specified. - */ -u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) -{ - if (adev->in_pci_err_recovery) - return 0; - - if ((reg * 4) < adev->rio_mem_size) - return ioread32(adev->rio_mem + (reg * 4)); - else { - iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); - return ioread32(adev->rio_mem + (mmMM_DATA * 4)); - } -} - -/** - * amdgpu_io_wreg - write to an IO register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @v: 32 bit value to write to the register - * - * Writes the value specified to the offset specified. - */ -void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) -{ - if (adev->in_pci_err_recovery) - return; - - if ((reg * 4) < adev->rio_mem_size) - iowrite32(v, adev->rio_mem + (reg * 4)); - else { - iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); - iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); - } -} - /** * amdgpu_mm_rdoorbell - read a doorbell dword * @@ -1223,6 +1181,10 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) } } + /* Don't post if we need to reset whole hive on init */ + if (adev->gmc.xgmi.pending_reset) + return false; + if (adev->has_hw_reset) { adev->has_hw_reset = false; return true; @@ -1810,6 +1772,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) case CHIP_CARRIZO: case CHIP_STONEY: case CHIP_VEGA20: + case CHIP_ALDEBARAN: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: @@ -2010,6 +1973,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: if (adev->flags & AMD_IS_APU) adev->family = AMDGPU_FAMILY_RV; else @@ -2045,6 +2009,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) adev->pm.pp_feature = amdgpu_pp_feature_mask; if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) adev->pm.pp_feature &= ~PP_GFXOFF_MASK; + if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) + adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; for (i = 0; i < adev->num_ip_blocks; i++) { if ((amdgpu_ip_block_mask & (1 << i)) == 0) { @@ -2149,6 +2115,9 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) continue; + if (!adev->ip_blocks[i].status.sw) + continue; + /* no need to do the fw loading again if already done*/ if (adev->ip_blocks[i].status.hw == true) break; @@ -2289,7 +2258,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (adev->gmc.xgmi.num_physical_nodes > 1) amdgpu_xgmi_add_device(adev); - amdgpu_amdkfd_device_init(adev); + + /* Don't init kfd if whole hive need to be reset during init */ + if (!adev->gmc.xgmi.pending_reset) + amdgpu_amdkfd_device_init(adev); amdgpu_fru_get_product_info(adev); @@ -2498,6 +2470,11 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) if (r) DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); + /* For XGMI + passthrough configuration on arcturus, enable light SBR */ + if (adev->asic_type == CHIP_ARCTURUS && + amdgpu_passthrough(adev) && + adev->gmc.xgmi.num_physical_nodes > 1) + smu_set_light_sbr(&adev->smu, true); if (adev->gmc.xgmi.num_physical_nodes > 1) { mutex_lock(&mgpu_info.mutex); @@ -2734,6 +2711,16 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = false; continue; } + + /* skip unnecessary suspend if we do not initialize them yet */ + if (adev->gmc.xgmi.pending_reset && + !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { + adev->ip_blocks[i].status.hw = false; + continue; + } /* XXX handle errors */ r = adev->ip_blocks[i].version->funcs->suspend(adev); /* XXX handle errors */ @@ -2753,7 +2740,6 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) } } } - adev->ip_blocks[i].status.hw = false; } return 0; @@ -2774,8 +2760,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) { int r; - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { + amdgpu_virt_fini_data_exchange(adev); amdgpu_virt_request_full_gpu(adev, false); + } r = amdgpu_device_ip_suspend_phase1(adev); if (r) @@ -3257,7 +3245,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* mutex initialization are all done here so we * can recall function without having locking issues */ - atomic_set(&adev->irq.ih.lock, 0); mutex_init(&adev->firmware.mutex); mutex_init(&adev->pm.mutex); mutex_init(&adev->gfx.gpu_clock_mutex); @@ -3290,6 +3277,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->shadow_list); mutex_init(&adev->shadow_list_lock); + INIT_LIST_HEAD(&adev->reset_list); + INIT_DELAYED_WORK(&adev->delayed_init_work, amdgpu_device_delayed_init_work_handler); INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, @@ -3328,17 +3317,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); - /* io port mapping */ - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { - adev->rio_mem_size = pci_resource_len(adev->pdev, i); - adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); - break; - } - } - if (adev->rio_mem == NULL) - DRM_INFO("PCI I/O BAR is not found.\n"); - /* enable PCIE atomic ops */ r = pci_enable_atomic_ops_to_root(adev->pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32 | @@ -3405,10 +3383,28 @@ int amdgpu_device_init(struct amdgpu_device *adev, * E.g., driver was not cleanly unloaded previously, etc. */ if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { - r = amdgpu_asic_reset(adev); - if (r) { - dev_err(adev->dev, "asic reset on init failed\n"); - goto failed; + if (adev->gmc.xgmi.num_physical_nodes) { + dev_info(adev->dev, "Pending hive reset.\n"); + adev->gmc.xgmi.pending_reset = true; + /* Only need to init necessary block for SMU to handle the reset */ + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { + DRM_DEBUG("IP %s disabled for hw_init.\n", + adev->ip_blocks[i].version->funcs->name); + adev->ip_blocks[i].status.hw = true; + } + } + } else { + r = amdgpu_asic_reset(adev); + if (r) { + dev_err(adev->dev, "asic reset on init failed\n"); + goto failed; + } } } @@ -3474,11 +3470,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; adev->virt.ops = NULL; r = -EAGAIN; - goto failed; + goto release_ras_con; } dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); - goto failed; + goto release_ras_con; } dev_info(adev->dev, @@ -3539,19 +3535,19 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* enable clockgating, etc. after ib tests, etc. since some blocks require * explicit gating rather than handling it automatically. */ - r = amdgpu_device_ip_late_init(adev); - if (r) { - dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); - amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); - goto failed; + if (!adev->gmc.xgmi.pending_reset) { + r = amdgpu_device_ip_late_init(adev); + if (r) { + dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); + amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); + goto release_ras_con; + } + /* must succeed. */ + amdgpu_ras_resume(adev); + queue_delayed_work(system_wq, &adev->delayed_init_work, + msecs_to_jiffies(AMDGPU_RESUME_MS)); } - /* must succeed. */ - amdgpu_ras_resume(adev); - - queue_delayed_work(system_wq, &adev->delayed_init_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); - if (amdgpu_sriov_vf(adev)) flush_delayed_work(&adev->delayed_init_work); @@ -3568,8 +3564,15 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (amdgpu_device_cache_pci_state(adev->pdev)) pci_restore_state(pdev); + if (adev->gmc.xgmi.pending_reset) + queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, + msecs_to_jiffies(AMDGPU_RESUME_MS)); + return 0; +release_ras_con: + amdgpu_release_ras_context(adev); + failed: amdgpu_vf_error_trans_all(adev); if (atpx) @@ -3594,6 +3597,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev) { dev_info(adev->dev, "amdgpu: finishing device.\n"); flush_delayed_work(&adev->delayed_init_work); + ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); adev->shutdown = true; kfree(adev->pci_state); @@ -3640,9 +3644,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev) vga_switcheroo_fini_domain_pm_ops(adev->dev); if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, NULL, NULL, NULL); - if (adev->rio_mem) - pci_iounmap(adev->pdev, adev->rio_mem); - adev->rio_mem = NULL; iounmap(adev->rmmio); adev->rmmio = NULL; amdgpu_device_doorbell_fini(adev); @@ -4237,15 +4238,56 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) return false; } +int amdgpu_device_mode1_reset(struct amdgpu_device *adev) +{ + u32 i; + int ret = 0; + + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + dev_info(adev->dev, "GPU mode1 reset\n"); + + /* disable BM */ + pci_clear_master(adev->pdev); + + amdgpu_device_cache_pci_state(adev->pdev); + + if (amdgpu_dpm_is_mode1_reset_supported(adev)) { + dev_info(adev->dev, "GPU smu mode1 reset\n"); + ret = amdgpu_dpm_mode1_reset(adev); + } else { + dev_info(adev->dev, "GPU psp mode1 reset\n"); + ret = psp_gpu_reset(adev); + } + + if (ret) + dev_err(adev->dev, "GPU mode1 reset failed\n"); + + amdgpu_device_load_pci_state(adev->pdev); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + u32 memsize = adev->nbio.funcs->get_memsize(adev); -static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, - struct amdgpu_job *job, - bool *need_full_reset_arg) + if (memsize != 0xffffffff) + break; + udelay(1); + } + + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + return ret; +} + +int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, + struct amdgpu_job *job, + bool *need_full_reset_arg) { int i, r = 0; bool need_full_reset = *need_full_reset_arg; - amdgpu_debugfs_wait_dump(adev); + /* no need to dump if device is not in good state during probe period */ + if (!adev->gmc.xgmi.pending_reset) + amdgpu_debugfs_wait_dump(adev); if (amdgpu_sriov_vf(adev)) { /* stop the data exchange thread */ @@ -4291,23 +4333,24 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, return r; } -static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, - struct list_head *device_list_handle, - bool *need_full_reset_arg, - bool skip_hw_reset) +int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, + struct list_head *device_list_handle, + bool *need_full_reset_arg, + bool skip_hw_reset) { struct amdgpu_device *tmp_adev = NULL; bool need_full_reset = *need_full_reset_arg, vram_lost = false; int r = 0; /* - * ASIC reset has to be done on all HGMI hive nodes ASAP + * ASIC reset has to be done on all XGMI hive nodes ASAP * to allow proper links negotiation in FW (within 1 sec) */ if (!skip_hw_reset && need_full_reset) { - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { /* For XGMI run all resets in parallel to speed up the process */ if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { + tmp_adev->gmc.xgmi.pending_reset = false; if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) r = -EALREADY; } else @@ -4322,8 +4365,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, /* For XGMI wait for all resets to complete before proceed */ if (!r) { - list_for_each_entry(tmp_adev, device_list_handle, - gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { flush_work(&tmp_adev->xgmi_reset_work); r = tmp_adev->asic_reset_res; @@ -4335,7 +4377,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, } if (!r && amdgpu_ras_intr_triggered()) { - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { if (tmp_adev->mmhub.funcs && tmp_adev->mmhub.funcs->reset_ras_error_count) tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev); @@ -4344,13 +4386,13 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, amdgpu_ras_intr_cleared(); } - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { if (need_full_reset) { /* post card */ - if (amdgpu_device_asic_init(tmp_adev)) + r = amdgpu_device_asic_init(tmp_adev); + if (r) { dev_warn(tmp_adev->dev, "asic atom init failed!"); - - if (!r) { + } else { dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); r = amdgpu_device_ip_resume_phase1(tmp_adev); if (r) @@ -4383,6 +4425,9 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, */ amdgpu_register_gpu_instance(tmp_adev); + if (!hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) + amdgpu_xgmi_add_device(tmp_adev); + r = amdgpu_device_ip_late_init(tmp_adev); if (r) goto out; @@ -4399,7 +4444,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, * bad_page_threshold value to fix this once * probing driver again. */ - if (!amdgpu_ras_check_err_threshold(tmp_adev)) { + if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { /* must succeed. */ amdgpu_ras_resume(tmp_adev); } else { @@ -4449,7 +4494,6 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, down_write(&adev->reset_sem); } - atomic_inc(&adev->gpu_reset_counter); switch (amdgpu_asic_reset_method(adev)) { case AMD_RESET_METHOD_MODE1: adev->mp1_state = PP_MP1_STATE_SHUTDOWN; @@ -4656,16 +4700,18 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ INIT_LIST_HEAD(&device_list); if (adev->gmc.xgmi.num_physical_nodes > 1) { - if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list)) - list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list); - device_list_handle = &hive->device_list; + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) + list_add_tail(&tmp_adev->reset_list, &device_list); + if (!list_is_first(&adev->reset_list, &device_list)) + list_rotate_to_front(&adev->reset_list, &device_list); + device_list_handle = &device_list; } else { - list_add_tail(&adev->gmc.xgmi.head, &device_list); + list_add_tail(&adev->reset_list, &device_list); device_list_handle = &device_list; } /* block all schedulers and reset given job's ring */ - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { /* * Try to put the audio codec into suspend state * before gpu reset started. @@ -4710,6 +4756,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, if (need_emergency_restart) amdgpu_job_stop_all_jobs_on_sched(&ring->sched); } + atomic_inc(&tmp_adev->gpu_reset_counter); } if (need_emergency_restart) @@ -4729,7 +4776,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, } retry: /* Rest of adevs pre asic reset from XGMI hive. */ - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { r = amdgpu_device_pre_asic_reset(tmp_adev, (tmp_adev == adev) ? job : NULL, &need_full_reset); @@ -4756,7 +4803,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, skip_hw_reset: /* Post ASIC reset for all devs .*/ - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = tmp_adev->rings[i]; @@ -4787,10 +4834,17 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, } skip_sched_resume: - list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { - /*unlock kfd: SRIOV would do it separately */ + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { + /* unlock kfd: SRIOV would do it separately */ if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) amdgpu_amdkfd_post_reset(tmp_adev); + + /* kfd_post_reset will do nothing if kfd device is not initialized, + * need to bring up kfd here if it's not be initialized before + */ + if (!adev->kfd.init_complete) + amdgpu_amdkfd_device_init(adev); + if (audio_suspended) amdgpu_device_resume_display_audio(tmp_adev); amdgpu_device_unlock_adev(tmp_adev); @@ -5052,6 +5106,7 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta drm_sched_stop(&ring->sched, NULL); } + atomic_inc(&adev->gpu_reset_counter); return PCI_ERS_RESULT_NEED_RESET; case pci_channel_io_perm_failure: /* Permanent error, prepare for device removal */ @@ -5100,7 +5155,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) DRM_INFO("PCI error: slot reset callback!!\n"); INIT_LIST_HEAD(&device_list); - list_add_tail(&adev->gmc.xgmi.head, &device_list); + list_add_tail(&adev->reset_list, &device_list); /* wait for asic to come out of reset */ msleep(500); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 48cb33e5b3826caac252debfc011dc6b2c91c322..b05301e1815c8c2f22381eb57642022045235514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -870,17 +870,62 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return r; } +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + + rfb->base.obj[0] = obj; + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) + goto err; + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + return 0; +err: + drm_err(dev, "Failed to init gem fb: %d\n", ret); + rfb->base.obj[0] = NULL; + return ret; +} + +int amdgpu_display_gem_fb_verify_and_init( + struct drm_device *dev, struct amdgpu_framebuffer *rfb, + struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + + rfb->base.obj[0] = obj; + + /* Verify that bo size can fit the fb size. */ + ret = drm_gem_fb_init_with_funcs(dev, &rfb->base, file_priv, mode_cmd, + &amdgpu_fb_funcs); + if (ret) + goto err; + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + return 0; +err: + drm_err(dev, "Failed to verify and init gem fb: %d\n", ret); + rfb->base.obj[0] = NULL; + return ret; +} + int amdgpu_display_framebuffer_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { int ret, i; - rfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); - ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); - if (ret) - goto fail; /* * This needs to happen before modifier conversion as that might change @@ -891,13 +936,13 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", i, mode_cmd->handles[0], mode_cmd->handles[i]); ret = -EINVAL; - goto fail; + return ret; } } ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); if (ret) - goto fail; + return ret; if (dev->mode_config.allow_fb_modifiers && !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { @@ -905,20 +950,17 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, if (ret) { drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", rfb->tiling_flags); - goto fail; + return ret; } } for (i = 1; i < rfb->base.format->num_planes; ++i) { + drm_gem_object_get(rfb->base.obj[0]); + drm_gem_object_put(rfb->base.obj[i]); rfb->base.obj[i] = rfb->base.obj[0]; - drm_gem_object_get(rfb->base.obj[i]); } return 0; - -fail: - rfb->base.obj[0] = NULL; - return ret; } struct drm_framebuffer * @@ -953,13 +995,15 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, return ERR_PTR(-ENOMEM); } - ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); + ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, + mode_cmd, obj); if (ret) { kfree(amdgpu_fb); drm_gem_object_put(obj); return ERR_PTR(ret); } + drm_gem_object_put(obj); return &amdgpu_fb->base; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 47e0b48dc26fd72f0a5e4869a3b0ba677e6db2da..e0c4f7c7f1b95a2e1054d64fdd96390d355e615e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -321,17 +321,12 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, struct sg_table *sgt, enum dma_data_direction dir) { - struct dma_buf *dma_buf = attach->dmabuf; - struct drm_gem_object *obj = dma_buf->priv; - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - if (sgt->sgl->page_link) { dma_unmap_sgtable(attach->dev, sgt, dir, 0); sg_free_table(sgt); kfree(sgt); } else { - amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt); + amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt); } } @@ -434,22 +429,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf) { struct dma_resv *resv = dma_buf->resv; struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_bo *bo; - struct amdgpu_bo_param bp; struct drm_gem_object *gobj; + struct amdgpu_bo *bo; + uint64_t flags = 0; int ret; - memset(&bp, 0, sizeof(bp)); - bp.size = dma_buf->size; - bp.byte_align = PAGE_SIZE; - bp.domain = AMDGPU_GEM_DOMAIN_CPU; - bp.flags = 0; - bp.type = ttm_bo_type_sg; - bp.resv = resv; dma_resv_lock(resv, NULL); + + if (dma_buf->ops == &amdgpu_dmabuf_ops) { + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv); + + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC; + } + ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_CPU, - 0, ttm_bo_type_sg, resv, &gobj); + AMDGPU_GEM_DOMAIN_CPU, flags, + ttm_bo_type_sg, resv, &gobj); if (ret) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4575192d9b087a0e0336ea3618a6a22b0c557a37..33991b4a5627e37842bbd63e29395acb81587b7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -45,6 +45,7 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_ras.h" +#include "amdgpu_xgmi.h" /* * KMS wrapper. @@ -90,9 +91,10 @@ * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC * - 3.39.0 - DMABUF implicit sync does a full pipeline sync * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ + * - 3.41.0 - Add video codec query */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 40 +#define KMS_DRIVER_MINOR 41 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit; @@ -145,6 +147,7 @@ int amdgpu_compute_multipipe = -1; int amdgpu_gpu_recovery = -1; /* auto */ int amdgpu_emu_mode; uint amdgpu_smu_memory_pool_size; +int amdgpu_smu_pptable_id = -1; /* * FBC (bit 0) disabled by default * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default @@ -162,16 +165,26 @@ int amdgpu_discovery = -1; int amdgpu_mes; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; -int amdgpu_tmz; +int amdgpu_tmz = -1; /* auto */ +uint amdgpu_freesync_vid_mode; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; +static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); + struct amdgpu_mgpu_info mgpu_info = { .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), + .delayed_reset_work = __DELAYED_WORK_INITIALIZER( + mgpu_info.delayed_reset_work, + amdgpu_drv_delayed_reset_work_handler, 0), }; int amdgpu_ras_enable = -1; uint amdgpu_ras_mask = 0xffffffff; int amdgpu_bad_page_threshold = -1; +struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { + .timeout_fatal_disable = false, + .period = 0x23, /* default to max. timeout = 1 << 0x23 cycles */ +}; /** * DOC: vramlimit (int) @@ -527,6 +540,20 @@ module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); +/** + * DOC: timeout_fatal_disable (bool) + * Disable Watchdog timeout fatal error event + */ +MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); +module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); + +/** + * DOC: timeout_period (uint) + * Modify the watchdog timeout max_cycles as (1 << period) + */ +MODULE_PARM_DESC(timeout_period, "watchdog timeout period (1 to 0x23(default), timeout maxCycles = (1 << period)"); +module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); + /** * DOC: si_support (int) * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, @@ -748,6 +775,13 @@ bool no_system_mem_limit; module_param(no_system_mem_limit, bool, 0644); MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); +/** + * DOC: no_queue_eviction_on_vm_fault (int) + * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). + */ +int amdgpu_no_queue_eviction_on_vm_fault = 0; +MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); +module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); #endif /** @@ -781,6 +815,10 @@ uint amdgpu_dm_abm_level; MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); +int amdgpu_backlight = -1; +MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); +module_param_named(backlight, amdgpu_backlight, bint, 0444); + /** * DOC: tmz (int) * Trusted Memory Zone (TMZ) is a method to protect data being written @@ -788,9 +826,20 @@ module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); * * The default value: 0 (off). TODO: change to auto till it is completed. */ -MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); +MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); module_param_named(tmz, amdgpu_tmz, int, 0444); +/** + * DOC: freesync_video (uint) + * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience + * when setting a freesync supported mode for which full modeset is not needed. + * The default value: 0 (off). + */ +MODULE_PARM_DESC( + freesync_video, + "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); +module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); + /** * DOC: reset_method (int) * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) @@ -811,6 +860,15 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); +/** + * DOC: smu_pptable_id (int) + * Used to override pptable id. id = 0 use VBIOS pptable. + * id > 0 use the soft pptable with specicfied id. + */ +MODULE_PARM_DESC(smu_pptable_id, + "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); +module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); + static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_SI {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, @@ -1120,6 +1178,11 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, + /* Aldebaran */ + {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, + {0, 0, 0} }; @@ -1276,6 +1339,69 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) adev->mp1_state = PP_MP1_STATE_NONE; } +/** + * amdgpu_drv_delayed_reset_work_handler - work handler for reset + * + * @work: work_struct. + */ +static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) +{ + struct list_head device_list; + struct amdgpu_device *adev; + int i, r; + bool need_full_reset = true; + + mutex_lock(&mgpu_info.mutex); + if (mgpu_info.pending_reset == true) { + mutex_unlock(&mgpu_info.mutex); + return; + } + mgpu_info.pending_reset = true; + mutex_unlock(&mgpu_info.mutex); + + for (i = 0; i < mgpu_info.num_dgpu; i++) { + adev = mgpu_info.gpu_ins[i].adev; + r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset); + if (r) { + dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", + r, adev_to_drm(adev)->unique); + } + if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) + r = -EALREADY; + } + for (i = 0; i < mgpu_info.num_dgpu; i++) { + adev = mgpu_info.gpu_ins[i].adev; + flush_work(&adev->xgmi_reset_work); + adev->gmc.xgmi.pending_reset = false; + } + + /* reset function will rebuild the xgmi hive info , clear it now */ + for (i = 0; i < mgpu_info.num_dgpu; i++) + amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); + + INIT_LIST_HEAD(&device_list); + + for (i = 0; i < mgpu_info.num_dgpu; i++) + list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); + + /* unregister the GPU first, reset function will add them back */ + list_for_each_entry(adev, &device_list, reset_list) + amdgpu_unregister_gpu_instance(adev); + + r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true); + if (r) { + DRM_ERROR("reinit gpus failure"); + return; + } + for (i = 0; i < mgpu_info.num_dgpu; i++) { + adev = mgpu_info.gpu_ins[i].adev; + if (!adev->kfd.init_complete) + amdgpu_amdkfd_device_init(adev); + amdgpu_ttm_set_buffer_funcs_status(adev, true); + } + return; +} + static int amdgpu_pmops_suspend(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 51cd49c6f38fd06f58369e3265cafa5367573a3f..4c5c19820d37fb68bd9e944841c88cc04c27de9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -146,7 +146,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, size = mode_cmd->pitches[0] * height; aligned_size = ALIGN(size, PAGE_SIZE); ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, - ttm_bo_type_kernel, NULL, &gobj); + ttm_bo_type_device, NULL, &gobj); if (ret) { pr_err("failed to allocate framebuffer (%d)\n", aligned_size); return -ENOMEM; @@ -232,8 +232,8 @@ static int amdgpufb_create(struct drm_fb_helper *helper, goto out; } - ret = amdgpu_display_framebuffer_init(adev_to_drm(adev), &rfbdev->rfb, - &mode_cmd, gobj); + ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, + &mode_cmd, gobj); if (ret) { DRM_ERROR("failed to initialize framebuffer %d\n", ret); goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d56f4023ebb3142c256def1da84c75b1d0054cde..1a4809d9e85022681771065da141736069a12c7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -36,8 +36,6 @@ #include #include -#include - #include "amdgpu.h" #include "amdgpu_trace.h" @@ -487,7 +485,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, num_hw_submission, amdgpu_job_hang_limit, - timeout, ring->name); + timeout, NULL, ring->name); if (r) { DRM_ERROR("Failed to create scheduler on ring %s.\n", ring->name); @@ -533,6 +531,8 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) if (!ring || !ring->fence_drv.initialized) continue; + if (!ring->no_scheduler) + drm_sched_fini(&ring->sched); r = amdgpu_fence_wait_empty(ring); if (r) { /* no need to trigger GPU reset as we are unloading */ @@ -541,8 +541,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) if (ring->fence_drv.irq_src) amdgpu_irq_put(adev, ring->fence_drv.irq_src, ring->fence_drv.irq_type); - if (!ring->no_scheduler) - drm_sched_fini(&ring->sched); + del_timer_sync(&ring->fence_drv.fallback_timer); for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) dma_fence_put(ring->fence_drv.fences[j]); @@ -697,11 +696,9 @@ static const struct dma_fence_ops amdgpu_fence_ops = { * Fence debugfs */ #if defined(CONFIG_DEBUG_FS) -static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) +static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; int i; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { @@ -746,11 +743,10 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) * * Manually trigger a gpu reset at the next fence wait. */ -static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) +static int gpu_recover_get(void *data, u64 *val) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct drm_device *dev = adev_to_drm(adev); int r; r = pm_runtime_get_sync(dev->dev); @@ -759,8 +755,7 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) return 0; } - seq_printf(m, "gpu recover\n"); - amdgpu_device_gpu_recover(adev, NULL); + *val = amdgpu_device_gpu_recover(adev, NULL); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -768,26 +763,24 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_debugfs_fence_list[] = { - {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, - {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); +DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, + "%lld\n"); -static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { - {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, -}; #endif -int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) +void amdgpu_debugfs_fence_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - if (amdgpu_sriov_vf(adev)) - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, - ARRAY_SIZE(amdgpu_debugfs_fence_list_sriov)); - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, - ARRAY_SIZE(amdgpu_debugfs_fence_list)); -#else - return 0; + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file("amdgpu_fence_info", 0444, root, adev, + &amdgpu_debugfs_fence_info_fops); + + if (!amdgpu_sriov_vf(adev)) + debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev, + &amdgpu_debugfs_gpu_recover_fops); #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 0db933026722f9b17eaf50187aeb8dfbf6aa4a19..5807cad833d370fb8838c6d07e34cf400e4ef34b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -71,7 +71,7 @@ */ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) { - struct page *dummy_page = ttm_bo_glob.dummy_read_page; + struct page *dummy_page = ttm_glob.dummy_read_page; if (adev->dummy_page_addr) return 0; @@ -202,6 +202,7 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) return; } amdgpu_bo_unref(&adev->gart.bo); + adev->gart.ptr = NULL; } /* @@ -236,9 +237,6 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, t = offset / AMDGPU_GPU_PAGE_SIZE; p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; for (i = 0; i < pages; i++, p++) { -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - adev->gart.pages[p] = NULL; -#endif page_base = adev->dummy_page_addr; if (!adev->gart.ptr) continue; @@ -312,9 +310,6 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, struct page **pagelist, dma_addr_t *dma_addr, uint64_t flags) { -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - unsigned t,p; -#endif int r, i; if (!adev->gart.ready) { @@ -322,13 +317,6 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, return -EINVAL; } -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - t = offset / AMDGPU_GPU_PAGE_SIZE; - p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (i = 0; i < pages; i++, p++) - adev->gart.pages[p] = pagelist ? pagelist[i] : NULL; -#endif - if (!adev->gart.ptr) return 0; @@ -373,14 +361,6 @@ int amdgpu_gart_init(struct amdgpu_device *adev) DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - /* Allocate pages table */ - adev->gart.pages = vzalloc(array_size(sizeof(void *), - adev->gart.num_cpu_pages)); - if (adev->gart.pages == NULL) - return -ENOMEM; -#endif - return 0; } @@ -393,9 +373,5 @@ int amdgpu_gart_init(struct amdgpu_device *adev) */ void amdgpu_gart_fini(struct amdgpu_device *adev) { -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - vfree(adev->gart.pages); - adev->gart.pages = NULL; -#endif amdgpu_gart_dummy_page_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index afa2e2877d87cf7065d7000a4a5ed451ca673e43..a25fe97b0196da4b6754e3a7bfbc62c4cab906e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -46,9 +46,6 @@ struct amdgpu_gart { unsigned num_gpu_pages; unsigned num_cpu_pages; unsigned table_size; -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - struct page **pages; -#endif bool ready; /* Asic default pte flags */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index b443907afceadfebab03bec153292bff145d5a0a..fb7171e5507cb957e794210f9caef897f65bfae0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -32,7 +32,6 @@ #include #include -#include #include #include "amdgpu.h" @@ -855,10 +854,10 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, } #if defined(CONFIG_DEBUG_FS) -static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) +static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct drm_device *dev = adev_to_drm(adev); struct drm_file *file; int r; @@ -896,16 +895,17 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_debugfs_gem_list[] = { - {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); + #endif -int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) +void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, - ARRAY_SIZE(amdgpu_debugfs_gem_list)); + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file("amdgpu_gem_info", 0444, root, adev, + &amdgpu_debugfs_gem_info_fops); #endif - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 8e0a6c62322ec9d62d569d717982580abd58901f..689addb1520d26bbac50f74ab560c848b9670174 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -601,6 +601,7 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) struct ras_ih_if ih_info = { .cb = amdgpu_gfx_process_ras_data_cb, }; + struct ras_query_if info = { 0 }; if (!adev->gfx.ras_if) { adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); @@ -612,13 +613,19 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) strcpy(adev->gfx.ras_if->name, "gfx"); } fs_info.head = ih_info.head = *adev->gfx.ras_if; - r = amdgpu_ras_late_init(adev, adev->gfx.ras_if, &fs_info, &ih_info); if (r) goto free; if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) { + if (adev->gmc.xgmi.connected_to_cpu) { + info.head = *adev->gfx.ras_if; + amdgpu_ras_query_error_status(adev, &info); + } else { + amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX); + } + r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); if (r) goto late_fini; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 72dbcd2bc6a630e5ff69d6a335e99fad1f95e5bf..38af93f501e1e030c16defe2244847d265fb5680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -30,6 +30,7 @@ #include "clearstate_defs.h" #include "amdgpu_ring.h" #include "amdgpu_rlc.h" +#include "soc15.h" /* GFX current status */ #define AMDGPU_GFX_NORMAL_MODE 0x00000000L @@ -224,7 +225,9 @@ struct amdgpu_gfx_funcs { void (*reset_ras_error_count) (struct amdgpu_device *adev); void (*init_spm_golden)(struct amdgpu_device *adev); void (*query_ras_error_status) (struct amdgpu_device *adev); + void (*reset_ras_error_status) (struct amdgpu_device *adev); void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); + void (*enable_watchdog_timer)(struct amdgpu_device *adev); }; struct sq_work { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index fe1a39ffda724f5490791da76dff6c90e8646d57..6f7995293a1efca92903b3db3ef5904acaaa967e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -31,6 +31,57 @@ #include "amdgpu_ras.h" #include "amdgpu_xgmi.h" +/** + * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 + * + * @adev: amdgpu_device pointer + * + * Allocate video memory for pdb0 and map it for CPU access + * Returns 0 for success, error for failure. + */ +int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) +{ + int r; + struct amdgpu_bo_param bp; + u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; + uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; + + memset(&bp, 0, sizeof(bp)); + bp.size = PAGE_ALIGN((npdes + 1) * 8); + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + bp.type = ttm_bo_type_kernel; + bp.resv = NULL; + r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); + if (r) + return r; + + r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); + if (unlikely(r != 0)) + goto bo_reserve_failure; + + r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); + if (r) + goto bo_pin_failure; + r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); + if (r) + goto bo_kmap_failure; + + amdgpu_bo_unreserve(adev->gmc.pdb0_bo); + return 0; + +bo_kmap_failure: + amdgpu_bo_unpin(adev->gmc.pdb0_bo); +bo_pin_failure: + amdgpu_bo_unreserve(adev->gmc.pdb0_bo); +bo_reserve_failure: + amdgpu_bo_unref(&adev->gmc.pdb0_bo); + return r; +} + /** * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO * @@ -158,6 +209,39 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, mc->vram_end, mc->real_vram_size >> 20); } +/** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture + * + * @adev: amdgpu device structure holding all necessary information + * @mc: memory controller structure holding memory information + * + * This function is only used if use GART for FB translation. In such + * case, we use sysvm aperture (vmid0 page tables) for both vram + * and gart (aka system memory) access. + * + * GPUVM (and our organization of vmid0 page tables) require sysvm + * aperture to be placed at a location aligned with 8 times of native + * page size. For example, if vm_context0_cntl.page_table_block_size + * is 12, then native page size is 8G (2M*2^12), sysvm should start + * with a 64G aligned address. For simplicity, we just put sysvm at + * address 0. So vram start at address 0 and gart is right after vram. + */ +void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) +{ + u64 hive_vram_start = 0; + u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; + mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; + mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; + mc->gart_start = hive_vram_end + 1; + mc->gart_end = mc->gart_start + mc->gart_size - 1; + mc->fb_start = hive_vram_start; + mc->fb_end = hive_vram_end; + dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", + mc->mc_vram_size >> 20, mc->vram_start, + mc->vram_end, mc->real_vram_size >> 20); + dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", + mc->gart_size >> 20, mc->gart_start, mc->gart_end); +} + /** * amdgpu_gmc_gart_location - try to find GART location * @@ -165,7 +249,6 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, * @mc: memory controller structure holding memory information * * Function will place try to place GART before or after VRAM. - * * If GART size is bigger than space left then we ajust GART size. * Thus function will never fails. */ @@ -176,8 +259,6 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); - mc->gart_size += adev->pm.smu_prv_buffer_size; - /* VCE doesn't like it when BOs cross a 4GB segment, so align * the GART base on a 4GB boundary as well. */ @@ -384,6 +465,16 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_RAVEN: + if (amdgpu_tmz == 0) { + adev->gmc.tmz_enabled = false; + dev_info(adev->dev, + "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); + } else { + adev->gmc.tmz_enabled = true; + dev_info(adev->dev, + "Trusted Memory Zone (TMZ) feature enabled\n"); + } + break; case CHIP_RENOIR: case CHIP_NAVI10: case CHIP_NAVI14: @@ -423,6 +514,7 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: case CHIP_VEGA20: + case CHIP_ALDEBARAN: /* * noretry = 0 will cause kfd page fault tests fail * for some ASICs, so set default to 1 for these ASICs. @@ -518,3 +610,55 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) adev->mman.stolen_extended_size = 0; } } + +/** + * amdgpu_gmc_init_pdb0 - initialize PDB0 + * + * @adev: amdgpu_device pointer + * + * This function is only used when GART page table is used + * for FB address translatioin. In such a case, we construct + * a 2-level system VM page table: PDB0->PTB, to cover both + * VRAM of the hive and system memory. + * + * PDB0 is static, initialized once on driver initialization. + * The first n entries of PDB0 are used as PTE by setting + * P bit to 1, pointing to VRAM. The n+1'th entry points + * to a big PTB covering system memory. + * + */ +void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) +{ + int i; + uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? + /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M + */ + u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + u64 pde0_page_size = (1ULL<gmc.vmid0_page_table_block_size)<<21; + u64 vram_addr = adev->vm_manager.vram_base_offset - + adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; + u64 vram_end = vram_addr + vram_size; + u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) + + adev->vm_manager.vram_base_offset - adev->gmc.vram_start; + + flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; + flags |= AMDGPU_PTE_WRITEABLE; + flags |= AMDGPU_PTE_SNOOPED; + flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); + flags |= AMDGPU_PDE_PTE; + + /* The first n PDE0 entries are used as PTE, + * pointing to vram + */ + for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) + amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); + + /* The n+1'th PDE0 entry points to a huge + * PTB who has more than 512 entries each + * pointing to a 4K system page + */ + flags = AMDGPU_PTE_VALID; + flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; + /* Requires gart_ptb_gpu_pa to be 4K aligned */ + amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index aa0c83776ce0c977d49db8bcd84f3b1ec0cdc800..7e248a4e2fa3c1c999284916df9a2043f4a6b090 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -149,6 +149,8 @@ struct amdgpu_xgmi { struct list_head head; bool supported; struct ras_common_if *ras_if; + bool connected_to_cpu; + bool pending_reset; }; struct amdgpu_gmc { @@ -189,10 +191,13 @@ struct amdgpu_gmc { u64 gart_end; /* Frame buffer aperture of this GPU device. Different from * fb_start (see below), this only covers the local GPU device. - * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios) - * and calculate vram_start of this local device by adding an - * offset inside the XGMI hive. - * Under VMID0, logical address == MC address + * If driver uses FB aperture to access FB, driver get fb_start from + * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start + * of this local device by adding an offset inside the XGMI hive. + * If driver uses GART table for VMID0 FB access, driver finds a hole in + * VMID0's virtual address space to place the SYSVM aperture inside + * which the first part is vram and the second part is gart (covering + * system ram). */ u64 vram_start; u64 vram_end; @@ -204,6 +209,15 @@ struct amdgpu_gmc { */ u64 fb_start; u64 fb_end; + /* In the case of use GART table for vmid0 FB access, [fb_start, fb_end] + * will be squeezed to GART aperture. But we have a PSP FW issue to fix + * for now. To temporarily workaround the PSP FW issue, added below two + * variables to remember the original fb_start/end to re-enable FB + * aperture to workaround the PSP FW issue. Will delete it after we + * get a proper PSP FW fix. + */ + u64 fb_start_original; + u64 fb_end_original; unsigned vram_width; u64 real_vram_size; int vram_mtrr; @@ -240,6 +254,12 @@ struct amdgpu_gmc { struct amdgpu_xgmi xgmi; struct amdgpu_irq_src ecc_irq; int noretry; + + uint32_t vmid0_page_table_block_size; + uint32_t vmid0_page_table_depth; + struct amdgpu_bo *pdb0_bo; + /* CPU kmapped address of pdb0*/ + void *ptr_pdb0; }; #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) @@ -281,6 +301,7 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) return addr; } +int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, uint64_t *addr, uint64_t *flags); int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, @@ -288,6 +309,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, uint64_t flags); uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); +void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, u64 base); void amdgpu_gmc_gart_location(struct amdgpu_device *adev, @@ -309,4 +331,5 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); +void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 7645223ea0ef2173a96f8750aea0a57aaac90bd8..148a3b481b12970826d346bc083d358275aad292 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -30,7 +30,6 @@ #include #include -#include #include "amdgpu.h" #include "atom.h" @@ -453,11 +452,9 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev) */ #if defined(CONFIG_DEBUG_FS) -static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) +static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; seq_printf(m, "--------------------- DELAYED --------------------- \n"); amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], @@ -471,18 +468,18 @@ static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_debugfs_sa_list[] = { - {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info); #endif -int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) +void amdgpu_debugfs_sa_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, - ARRAY_SIZE(amdgpu_debugfs_sa_list)); -#else - return 0; + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file("amdgpu_sa_info", 0444, root, adev, + &amdgpu_debugfs_sa_info_fops); + #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index dc852af4f3b76f6a33bfa0784addd7f80f7c443d..faaa6aa2faaf2aba9c32bdd4497c985cbfbc4571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -99,6 +99,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; ih->rptr_cpu = &adev->wb.wb[rptr_offs]; } + + init_waitqueue_head(&ih->wait_process); return 0; } @@ -160,6 +162,52 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, } } +/* Waiter helper that checks current rptr matches or passes checkpoint wptr */ +static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev, + struct amdgpu_ih_ring *ih, + uint32_t checkpoint_wptr, + uint32_t *prev_rptr) +{ + uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask); + + /* rptr has wrapped. */ + if (cur_rptr < *prev_rptr) + cur_rptr += ih->ptr_mask + 1; + *prev_rptr = cur_rptr; + + return cur_rptr >= checkpoint_wptr; +} + +/** + * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint + * + * @adev: amdgpu_device pointer + * @ih: ih ring to process + * + * Used to ensure ring has processed IVs up to the checkpoint write pointer. + */ +int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, + struct amdgpu_ih_ring *ih) +{ + uint32_t checkpoint_wptr, rptr; + + if (!ih->enabled || adev->shutdown) + return -ENODEV; + + checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); + /* Order wptr with rptr. */ + rmb(); + rptr = READ_ONCE(ih->rptr); + + /* wptr has wrapped. */ + if (rptr > checkpoint_wptr) + checkpoint_wptr += ih->ptr_mask + 1; + + return wait_event_interruptible(ih->wait_process, + amdgpu_ih_has_checkpoint_processed(adev, ih, + checkpoint_wptr, &rptr)); +} + /** * amdgpu_ih_process - interrupt handler * @@ -180,10 +228,6 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) wptr = amdgpu_ih_get_wptr(adev, ih); restart_ih: - /* is somebody else already processing irqs? */ - if (atomic_xchg(&ih->lock, 1)) - return IRQ_NONE; - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); /* Order reading of wptr vs. reading of IH ring data */ @@ -195,7 +239,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) } amdgpu_ih_set_rptr(adev, ih); - atomic_set(&ih->lock, 0); + wake_up_all(&ih->wait_process); /* make sure wptr hasn't changed while processing */ wptr = amdgpu_ih_get_wptr(adev, ih); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 6ed4a85fc7c31e7916472257dc243a6d2c09afc3..0649b59830a59b0203889aeef7ac1d02e0fbd615 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -64,8 +64,10 @@ struct amdgpu_ih_ring { bool enabled; unsigned rptr; - atomic_t lock; struct amdgpu_ih_regs ih_regs; + + /* For waiting on IH processing at checkpoint. */ + wait_queue_head_t wait_process; }; /* provided by the ih block */ @@ -87,6 +89,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, unsigned int num_dw); +int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, + struct amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index afbbec82a289c8300cd823b0e41ed1dc221fb166..af026109421a35667a1ee15af5eca43212d4ea38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -65,6 +65,41 @@ #define AMDGPU_WAIT_IDLE_TIMEOUT 200 +const char *soc15_ih_clientid_name[] = { + "IH", + "SDMA2 or ACP", + "ATHUB", + "BIF", + "SDMA3 or DCE", + "SDMA4 or ISP", + "VMC1 or PCIE0", + "RLC", + "SDMA0", + "SDMA1", + "SE0SH", + "SE1SH", + "SE2SH", + "SE3SH", + "VCN1 or UVD1", + "THM", + "VCN or UVD", + "SDMA5 or VCE0", + "VMC", + "SDMA6 or XDMA", + "GRBM_CP", + "ATS", + "ROM_SMUIO", + "DF", + "SDMA7 or VCE1", + "PWR", + "reserved", + "UTCL2", + "EA", + "UTCL2LOG", + "MP0", + "MP1" +}; + /** * amdgpu_hotplug_work_func - work handler for display hotplug event * @@ -535,7 +570,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; - if (!src) + if (!src || !src->funcs || !src->funcs->set) continue; for (k = 0; k < src->num_types; k++) amdgpu_irq_update(adev, src, k); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index ff48101bab551373f7ef54682af1cac4ad728491..759b34799221e9e418a1814500600093bb3ab331 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -28,7 +28,7 @@ #include "amdgpu.h" #include "amdgpu_trace.h" -static void amdgpu_job_timedout(struct drm_sched_job *s_job) +static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) { struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); struct amdgpu_job *job = to_amdgpu_job(s_job); @@ -41,7 +41,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job) amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { DRM_ERROR("ring %s timeout, but soft recovered\n", s_job->sched->name); - return; + return DRM_GPU_SCHED_STAT_NOMINAL; } amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); @@ -53,10 +53,12 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job) if (amdgpu_device_should_recover_gpu(ring->adev)) { amdgpu_device_gpu_recover(ring->adev, job); + return DRM_GPU_SCHED_STAT_NOMINAL; } else { drm_sched_suspend_timeout(&ring->sched); if (amdgpu_sriov_vf(adev)) adev->virt.tdr_debug = true; + return DRM_GPU_SCHED_STAT_NOMINAL; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 64beb33996042647143539bace349d026fbf90dc..ada807de978b3fbe060c0ec604c3408bf370bca5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -27,7 +27,6 @@ */ #include "amdgpu.h" -#include #include #include "amdgpu_uvd.h" #include "amdgpu_vce.h" @@ -287,22 +286,30 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, break; case AMDGPU_INFO_FW_TA: switch (query_fw->index) { - case 0: + case TA_FW_TYPE_PSP_XGMI: fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_xgmi_ucode_version; break; - case 1: + case TA_FW_TYPE_PSP_RAS: fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_ras_ucode_version; break; - case 2: + case TA_FW_TYPE_PSP_HDCP: fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_hdcp_ucode_version; break; - case 3: + case TA_FW_TYPE_PSP_DTM: fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_dtm_ucode_version; break; + case TA_FW_TYPE_PSP_RAP: + fw_info->ver = adev->psp.ta_fw_version; + fw_info->feature = adev->psp.ta_rap_ucode_version; + break; + case TA_FW_TYPE_PSP_SECUREDISPLAY: + fw_info->ver = adev->psp.ta_fw_version; + fw_info->feature = adev->psp.ta_securedisplay_ucode_version; + break; default: return -EINVAL; } @@ -981,6 +988,63 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) min_t(u64, size, sizeof(ras_mask))) ? -EFAULT : 0; } + case AMDGPU_INFO_VIDEO_CAPS: { + const struct amdgpu_video_codecs *codecs; + struct drm_amdgpu_info_video_caps *caps; + int r; + + switch (info->video_cap.type) { + case AMDGPU_INFO_VIDEO_CAPS_DECODE: + r = amdgpu_asic_query_video_codecs(adev, false, &codecs); + if (r) + return -EINVAL; + break; + case AMDGPU_INFO_VIDEO_CAPS_ENCODE: + r = amdgpu_asic_query_video_codecs(adev, true, &codecs); + if (r) + return -EINVAL; + break; + default: + DRM_DEBUG_KMS("Invalid request %d\n", + info->video_cap.type); + return -EINVAL; + } + + caps = kzalloc(sizeof(*caps), GFP_KERNEL); + if (!caps) + return -ENOMEM; + + for (i = 0; i < codecs->codec_count; i++) { + int idx = codecs->codec_array[i].codec_type; + + switch (idx) { + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: + case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: + caps->codec_info[idx].valid = 1; + caps->codec_info[idx].max_width = + codecs->codec_array[i].max_width; + caps->codec_info[idx].max_height = + codecs->codec_array[i].max_height; + caps->codec_info[idx].max_pixels_per_frame = + codecs->codec_array[i].max_pixels_per_frame; + caps->codec_info[idx].max_level = + codecs->codec_array[i].max_level; + break; + default: + break; + } + } + r = copy_to_user(out, caps, + min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; + kfree(caps); + return r; + } default: DRM_DEBUG_KMS("Invalid request %d\n", info->query); return -EINVAL; @@ -1262,16 +1326,25 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) */ #if defined(CONFIG_DEBUG_FS) -static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) +static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_amdgpu_info_firmware fw_info; struct drm_amdgpu_query_fw query_fw; struct atom_context *ctx = adev->mode_info.atom_context; int ret, i; + static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { +#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type + TA_FW_NAME(XGMI), + TA_FW_NAME(RAS), + TA_FW_NAME(HDCP), + TA_FW_NAME(DTM), + TA_FW_NAME(RAP), + TA_FW_NAME(SECUREDISPLAY), +#undef TA_FW_NAME + }; + /* VCE */ query_fw.fw_type = AMDGPU_INFO_FW_VCE; ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); @@ -1389,31 +1462,14 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) fw_info.feature, fw_info.ver); query_fw.fw_type = AMDGPU_INFO_FW_TA; - for (i = 0; i < 4; i++) { + for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { query_fw.index = i; ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); if (ret) continue; - switch (query_fw.index) { - case 0: - seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", - "RAS", fw_info.feature, fw_info.ver); - break; - case 1: - seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", - "XGMI", fw_info.feature, fw_info.ver); - break; - case 2: - seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", - "HDCP", fw_info.feature, fw_info.ver); - break; - case 3: - seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", - "DTM", fw_info.feature, fw_info.ver); - break; - default: - return -EINVAL; - } + + seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", + ta_fw_name[i], fw_info.feature, fw_info.ver); } /* SMC */ @@ -1472,17 +1528,18 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) return 0; } -static const struct drm_info_list amdgpu_firmware_info_list[] = { - {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); + #endif -int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) +void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, - ARRAY_SIZE(amdgpu_firmware_info_list)); -#else - return 0; + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file("amdgpu_firmware_info", 0444, root, + adev, &amdgpu_debugfs_firmware_info_fops); + #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 319cb19e1b99f07d6a86feb6f45d9778087114ab..cb0b581bbce7bc23e8577497e1c991a9f4bb32f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -602,6 +602,14 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); +int amdgpu_display_gem_fb_verify_and_init( + struct drm_device *dev, struct amdgpu_framebuffer *rfb, + struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); int amdgpu_display_framebuffer_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, const struct drm_mode_fb_cmd2 *mode_cmd, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 4b29b820544281cc3f1ab3c717866e6c0ea66b00..ac1bb5089260483c37b4488f6799a84c8d61c99e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -523,7 +523,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, }; struct amdgpu_bo *bo; unsigned long page_align, size = bp->size; - size_t acc_size; int r; /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ @@ -546,9 +545,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, *bo_ptr = NULL; - acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, - sizeof(struct amdgpu_bo)); - bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); if (bo == NULL) return -ENOMEM; @@ -577,8 +573,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, bo->tbo.priority = 1; r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, - &bo->placement, page_align, &ctx, acc_size, - NULL, bp->resv, &amdgpu_bo_destroy); + &bo->placement, page_align, &ctx, NULL, + bp->resv, &amdgpu_bo_destroy); if (unlikely(r != 0)) return r; @@ -1065,13 +1061,17 @@ static const char *amdgpu_vram_names[] = { */ int amdgpu_bo_init(struct amdgpu_device *adev) { - /* reserve PAT memory space to WC for VRAM */ - arch_io_reserve_memtype_wc(adev->gmc.aper_base, - adev->gmc.aper_size); + /* On A+A platform, VRAM can be mapped as WB */ + if (!adev->gmc.xgmi.connected_to_cpu) { + /* reserve PAT memory space to WC for VRAM */ + arch_io_reserve_memtype_wc(adev->gmc.aper_base, + adev->gmc.aper_size); + + /* Add an MTRR for the VRAM */ + adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, + adev->gmc.aper_size); + } - /* Add an MTRR for the VRAM */ - adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, - adev->gmc.aper_size); DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", adev->gmc.mc_vram_size >> 20, (unsigned long long)adev->gmc.aper_size >> 20); @@ -1089,8 +1089,10 @@ int amdgpu_bo_init(struct amdgpu_device *adev) void amdgpu_bo_fini(struct amdgpu_device *adev) { amdgpu_ttm_fini(adev); - arch_phys_wc_del(adev->gmc.vram_mtrr); - arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); + if (!adev->gmc.xgmi.connected_to_cpu) { + arch_phys_wc_del(adev->gmc.vram_mtrr); + arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); + } } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 9ac37569823ff4c7bc9ef22093c4189b6d969bcb..54ceb065e5463d72901cebb6bbc1b49785e0c9e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -100,7 +100,6 @@ struct amdgpu_bo { struct amdgpu_bo *parent; struct amdgpu_bo *shadow; - struct amdgpu_mn *mn; #ifdef CONFIG_MMU_NOTIFIER @@ -329,7 +328,7 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, struct seq_file *m); u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m); #endif -int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); +void amdgpu_debugfs_sa_init(struct amdgpu_device *adev); bool amdgpu_bo_support_uswc(u64 bo_flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 839917eb7bc3c56995f2a5d9a2b80841f461dbb2..bae304b0d67a17a00ccec21965b603f75475d3ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -34,6 +34,7 @@ #include "psp_v10_0.h" #include "psp_v11_0.h" #include "psp_v12_0.h" +#include "psp_v13_0.h" #include "amdgpu_ras.h" #include "amdgpu_securedisplay.h" @@ -56,7 +57,7 @@ static int psp_load_smu_fw(struct psp_context *psp); * - Load XGMI/RAS/HDCP/DTM TA if any * * This new sequence is required for - * - Arcturus + * - Arcturus and onwards * - Navi12 and onwards */ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) @@ -71,7 +72,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp if (adev->flags & AMD_IS_APU) return; - if ((adev->asic_type == CHIP_ARCTURUS) || + if ((adev->asic_type >= CHIP_ARCTURUS) || (adev->asic_type >= CHIP_NAVI12)) psp->pmfw_centralized_cstate_management = true; } @@ -109,6 +110,9 @@ static int psp_early_init(void *handle) case CHIP_RENOIR: psp_v12_0_set_psp_funcs(psp); break; + case CHIP_ALDEBARAN: + psp_v13_0_set_psp_funcs(psp); + break; default: return -EINVAL; } @@ -383,7 +387,7 @@ static int psp_tmr_init(struct psp_context *psp) * Note: this memory need be reserved till the driver * uninitializes. */ - tmr_size = PSP_TMR_SIZE; + tmr_size = PSP_TMR_SIZE(psp->adev); /* For ASICs support RLC autoload, psp will parse the toc * and calculate the total size of TMR needed */ @@ -399,10 +403,20 @@ static int psp_tmr_init(struct psp_context *psp) } pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; - ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), AMDGPU_GEM_DOMAIN_VRAM, &psp->tmr_bo, &psp->tmr_mc_addr, pptr); + /* workaround the tmr_mc_addr: + * PSP requires an address in FB aperture. Right now driver produce + * tmr_mc_addr in the GART aperture. Convert it back to FB aperture + * for PSP. Will revert it after we get a fix from PSP FW. + */ + if (psp->adev->asic_type == CHIP_ALDEBARAN) { + psp->tmr_mc_addr -= psp->adev->gmc.fb_start; + psp->tmr_mc_addr += psp->adev->gmc.fb_start_original; + } + return ret; } @@ -542,6 +556,28 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp, return ret; } +static int psp_rl_load(struct amdgpu_device *adev) +{ + struct psp_context *psp = &adev->psp; + struct psp_gfx_cmd_resp *cmd = psp->cmd; + + if (psp->rl_bin_size == 0) + return 0; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); + + memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); + + cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); + cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; + cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; + + return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); +} + static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, uint64_t asd_mc, uint32_t size) { @@ -755,8 +791,9 @@ static int psp_xgmi_unload(struct psp_context *psp) struct psp_gfx_cmd_resp *cmd; struct amdgpu_device *adev = psp->adev; - /* XGMI TA unload currently is not supported on Arcturus */ - if (adev->asic_type == CHIP_ARCTURUS) + /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ + if (adev->asic_type == CHIP_ARCTURUS || + (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) return 0; /* @@ -1561,6 +1598,7 @@ static int psp_rap_unload(struct psp_context *psp) static int psp_rap_initialize(struct psp_context *psp) { int ret; + enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; /* * TODO: bypass the initialize in sriov for now @@ -1584,8 +1622,8 @@ static int psp_rap_initialize(struct psp_context *psp) if (ret) return ret; - ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE); - if (ret != TA_RAP_STATUS__SUCCESS) { + ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); + if (ret || status != TA_RAP_STATUS__SUCCESS) { psp_rap_unload(psp); amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, @@ -1594,8 +1632,10 @@ static int psp_rap_initialize(struct psp_context *psp) psp->rap_context.rap_initialized = false; - dev_warn(psp->adev->dev, "RAP TA initialize fail.\n"); - return -EINVAL; + dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", + ret, status); + + return ret; } return 0; @@ -1620,13 +1660,13 @@ static int psp_rap_terminate(struct psp_context *psp) return ret; } -int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) +int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) { struct ta_rap_shared_memory *rap_cmd; - int ret; + int ret = 0; if (!psp->rap_context.rap_initialized) - return -EINVAL; + return 0; if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) @@ -1642,14 +1682,16 @@ int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) rap_cmd->validation_method_id = METHOD_A; ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); - if (ret) { - mutex_unlock(&psp->rap_context.mutex); - return ret; - } + if (ret) + goto out_unlock; + if (status) + *status = rap_cmd->rap_status; + +out_unlock: mutex_unlock(&psp->rap_context.mutex); - return rap_cmd->rap_status; + return ret; } // RAP end @@ -2276,6 +2318,12 @@ static int psp_load_fw(struct amdgpu_device *adev) return ret; } + ret = psp_rl_load(adev); + if (ret) { + DRM_ERROR("PSP load RL failed!\n"); + return ret; + } + if (psp->adev->psp.ta_fw) { ret = psp_ras_initialize(psp); if (ret) @@ -2751,6 +2799,9 @@ int psp_init_sos_microcode(struct psp_context *psp, adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); + adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); + adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + + le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); } break; default: @@ -3052,3 +3103,11 @@ const struct amdgpu_ip_block_version psp_v12_0_ip_block = .rev = 0, .funcs = &psp_ip_funcs, }; + +const struct amdgpu_ip_block_version psp_v13_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_PSP, + .major = 13, + .minor = 0, + .rev = 0, + .funcs = &psp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index cb50ba445f8c86e46c720259f5457ffc5f32e272..64f1433908355aed26cea81b3a8905236aba6789 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -37,7 +37,7 @@ #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 #define PSP_1_MEG 0x100000 -#define PSP_TMR_SIZE 0x400000 +#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 #define PSP_RAP_SHARED_MEM_SIZE 0x4000 @@ -248,11 +248,13 @@ struct psp_context uint32_t toc_bin_size; uint32_t kdb_bin_size; uint32_t spl_bin_size; + uint32_t rl_bin_size; uint8_t *sys_start_addr; uint8_t *sos_start_addr; uint8_t *toc_start_addr; uint8_t *kdb_start_addr; uint8_t *spl_start_addr; + uint8_t *rl_start_addr; /* tmr buffer */ struct amdgpu_bo *tmr_bo; @@ -365,11 +367,13 @@ struct amdgpu_psp_funcs { extern const struct amd_ip_funcs psp_ip_funcs; extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; -extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, - uint32_t field_val, uint32_t mask, bool check_changed); - extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; +extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; +extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; + +extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, + uint32_t field_val, uint32_t mask, bool check_changed); int psp_gpu_reset(struct amdgpu_device *adev); int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, @@ -395,12 +399,11 @@ int psp_ras_trigger_error(struct psp_context *psp, int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); -int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id); +int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); int psp_rlc_autoload_start(struct psp_context *psp); -extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, uint32_t value); int psp_ring_cmd_submit(struct psp_context *psp, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c index 8da5356c36f174eddc8e2ef79f00466711c7abc5..51909bf8798ccf303f566bdf153de985fc43bc55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c @@ -48,6 +48,7 @@ static ssize_t amdgpu_rap_debugfs_write(struct file *f, const char __user *buf, struct ta_rap_cmd_output_data *rap_cmd_output; struct drm_device *dev = adev_to_drm(adev); uint32_t op; + enum ta_rap_status status; int ret; if (*pos || size != 2) @@ -70,9 +71,8 @@ static ssize_t amdgpu_rap_debugfs_write(struct file *f, const char __user *buf, switch (op) { case 2: - ret = psp_rap_invoke(&adev->psp, op); - - if (ret == TA_RAP_STATUS__SUCCESS) { + ret = psp_rap_invoke(&adev->psp, op, &status); + if (!ret && status == TA_RAP_STATUS__SUCCESS) { dev_info(adev->dev, "RAP L0 validate test success.\n"); } else { rap_shared_mem = (struct ta_rap_shared_memory *) @@ -97,6 +97,7 @@ static ssize_t amdgpu_rap_debugfs_write(struct file *f, const char __user *buf, default: dev_info(adev->dev, "Unsupported op id: %d, ", op); dev_info(adev->dev, "Only support op 2(L0 validate test).\n"); + break; } amdgpu_gfx_off_ctrl(adev, true); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 1fb2a91ad30ad797e06d4ae1b26b91b289f30bd5..0e16683876aa482128ebd6f9333872debb06789a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -109,7 +109,7 @@ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, ssize_t s; char val[128]; - if (amdgpu_ras_error_query(obj->adev, &info)) + if (amdgpu_ras_query_error_status(obj->adev, &info)) return -EINVAL; s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", @@ -434,7 +434,7 @@ static ssize_t amdgpu_ras_sysfs_read(struct device *dev, return snprintf(buf, PAGE_SIZE, "Query currently inaccessible\n"); - if (amdgpu_ras_error_query(obj->adev, &info)) + if (amdgpu_ras_query_error_status(obj->adev, &info)) return -EINVAL; return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", @@ -463,7 +463,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!con) + if (!adev->ras_features || !con) return NULL; if (head->block >= AMDGPU_RAS_BLOCK_COUNT) @@ -490,7 +490,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, struct ras_manager *obj; int i; - if (!con) + if (!adev->ras_features || !con) return NULL; if (head) { @@ -590,7 +590,11 @@ static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, con->features |= BIT(head->block); } else { if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { - con->features &= ~BIT(head->block); + /* skip clean gfx ras context feature for VEGA20 Gaming. + * will clean later + */ + if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX))) + con->features &= ~BIT(head->block); put_obj(obj); } } @@ -693,6 +697,10 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, if (ret) return ret; + /* gfx block ras dsiable cmd must send to ras-ta */ + if (head->block == AMDGPU_RAS_BLOCK__GFX) + con->features |= BIT(head->block); + ret = amdgpu_ras_feature_enable(adev, head, 0); } } else @@ -757,8 +765,8 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, /* feature ctl end */ /* query/inject/cure begin */ -int amdgpu_ras_error_query(struct amdgpu_device *adev, - struct ras_query_if *info) +int amdgpu_ras_query_error_status(struct amdgpu_device *adev, + struct ras_query_if *info) { struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); struct ras_err_data err_data = {0, 0, 0, NULL}; @@ -787,10 +795,16 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev, case AMDGPU_RAS_BLOCK__GFX: if (adev->gfx.funcs->query_ras_error_count) adev->gfx.funcs->query_ras_error_count(adev, &err_data); + + if (adev->gfx.funcs->query_ras_error_status) + adev->gfx.funcs->query_ras_error_status(adev); break; case AMDGPU_RAS_BLOCK__MMHUB: if (adev->mmhub.funcs->query_ras_error_count) adev->mmhub.funcs->query_ras_error_count(adev, &err_data); + + if (adev->mmhub.funcs->query_ras_error_status) + adev->mmhub.funcs->query_ras_error_status(adev); break; case AMDGPU_RAS_BLOCK__PCIE_BIF: if (adev->nbio.funcs->query_ras_error_count) @@ -826,6 +840,35 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev, return 0; } +int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, + enum amdgpu_ras_block block) +{ + if (!amdgpu_ras_is_supported(adev, block)) + return -EINVAL; + + switch (block) { + case AMDGPU_RAS_BLOCK__GFX: + if (adev->gfx.funcs->reset_ras_error_count) + adev->gfx.funcs->reset_ras_error_count(adev); + + if (adev->gfx.funcs->reset_ras_error_status) + adev->gfx.funcs->reset_ras_error_status(adev); + break; + case AMDGPU_RAS_BLOCK__MMHUB: + if (adev->mmhub.funcs->reset_ras_error_count) + adev->mmhub.funcs->reset_ras_error_count(adev); + break; + case AMDGPU_RAS_BLOCK__SDMA: + if (adev->sdma.funcs->reset_ras_error_count) + adev->sdma.funcs->reset_ras_error_count(adev); + break; + default: + break; + } + + return 0; +} + /* Trigger XGMI/WAFL error */ static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, struct ta_ras_trigger_error_input *block_info) @@ -913,7 +956,7 @@ unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, struct ras_manager *obj; struct ras_err_data data = {0, 0}; - if (!con) + if (!adev->ras_features || !con) return 0; list_for_each_entry(obj, &con->head, node) { @@ -921,7 +964,7 @@ unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, .head = obj->head, }; - if (amdgpu_ras_error_query(adev, &info)) + if (amdgpu_ras_query_error_status(adev, &info)) return 0; data.ce_count += info.ce_count; @@ -1137,16 +1180,17 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) * */ /* debugfs begin */ -static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) +static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct dentry *dir; struct drm_minor *minor = adev_to_drm(adev)->primary; - con->dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); - debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, - adev, &amdgpu_ras_debugfs_ctrl_ops); - debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, - adev, &amdgpu_ras_debugfs_eeprom_ops); + dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); + debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, + &amdgpu_ras_debugfs_ctrl_ops); + debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, + &amdgpu_ras_debugfs_eeprom_ops); /* * After one uncorrectable error happens, usually GPU recovery will @@ -1156,24 +1200,24 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine * will never be called. */ - debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, - &con->reboot); + debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); /* * User could set this not to clean up hardware's error count register * of RAS IPs during ras recovery. */ - debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, - con->dir, &con->disable_ras_err_cnt_harvest); + debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, + &con->disable_ras_err_cnt_harvest); + return dir; } static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, - struct ras_fs_if *head) + struct ras_fs_if *head, + struct dentry *dir) { - struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); - if (!obj || obj->ent) + if (!obj || !dir) return; get_obj(obj); @@ -1182,14 +1226,14 @@ static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, head->debugfs_name, sizeof(obj->fs_data.debugfs_name)); - obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, - S_IWUGO | S_IRUGO, con->dir, obj, - &amdgpu_ras_debugfs_ops); + debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, + obj, &amdgpu_ras_debugfs_ops); } void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct dentry *dir; struct ras_manager *obj; struct ras_fs_if fs_info; @@ -1200,7 +1244,7 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) return; - amdgpu_ras_debugfs_create_ctrl_node(adev); + dir = amdgpu_ras_debugfs_create_ctrl_node(adev); list_for_each_entry(obj, &con->head, node) { if (amdgpu_ras_is_supported(adev, obj->head.block) && @@ -1208,34 +1252,11 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) sprintf(fs_info.debugfs_name, "%s_err_inject", ras_block_str(obj->head.block)); fs_info.head = obj->head; - amdgpu_ras_debugfs_create(adev, &fs_info); + amdgpu_ras_debugfs_create(adev, &fs_info, dir); } } } -static void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, - struct ras_common_if *head) -{ - struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); - - if (!obj || !obj->ent) - return; - - obj->ent = NULL; - put_obj(obj); -} - -static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) -{ - struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - struct ras_manager *obj, *tmp; - - list_for_each_entry_safe(obj, tmp, &con->head, node) { - amdgpu_ras_debugfs_remove(adev, &obj->head); - } - - con->dir = NULL; -} /* debugfs end */ /* ras fs */ @@ -1282,8 +1303,17 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) { - if (IS_ENABLED(CONFIG_DEBUG_FS)) - amdgpu_ras_debugfs_remove_all(adev); + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct ras_manager *con_obj, *ip_obj, *tmp; + + if (IS_ENABLED(CONFIG_DEBUG_FS)) { + list_for_each_entry_safe(con_obj, tmp, &con->head, node) { + ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); + if (ip_obj) + put_obj(ip_obj); + } + } + amdgpu_ras_sysfs_remove_all(adev); return 0; } @@ -1447,7 +1477,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!con) + if (!adev->ras_features || !con) return; list_for_each_entry(obj, &con->head, node) { @@ -1464,7 +1494,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) continue; - amdgpu_ras_error_query(adev, &info); + amdgpu_ras_query_error_status(adev, &info); } } @@ -1495,7 +1525,7 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!con) + if (!adev->ras_features || !con) return; list_for_each_entry(obj, &con->head, node) { @@ -1809,7 +1839,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) bool exc_err_limit = false; int ret; - if (con) + if (adev->ras_features && con) data = &con->eh_data; else return 0; @@ -1828,6 +1858,12 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); + /* Todo: During test the SMU might fail to read the eeprom through I2C + * when the GPU is pending on XGMI reset during probe time + * (Mostly after second bus reset), skip it now + */ + if (adev->gmc.xgmi.pending_reset) + return 0; ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); /* * This calling fails when exc_err_limit is true or @@ -1928,11 +1964,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev, return; if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { - dev_info(adev->dev, "HBM ECC is active.\n"); + dev_info(adev->dev, "MEM ECC is active.\n"); *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | 1 << AMDGPU_RAS_BLOCK__DF); } else - dev_info(adev->dev, "HBM ECC is not presented.\n"); + dev_info(adev->dev, "MEM ECC is not presented.\n"); if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { dev_info(adev->dev, "SRAM ECC is active.\n"); @@ -1970,6 +2006,15 @@ int amdgpu_ras_init(struct amdgpu_device *adev) amdgpu_ras_check_supported(adev, &con->hw_supported, &con->supported); if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) { + /* set gfx block ras context feature for VEGA20 Gaming + * send ras disable cmd to ras ta during ras late init. + */ + if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) { + con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); + + return 0; + } + r = 0; goto release_con; } @@ -2083,8 +2128,12 @@ void amdgpu_ras_resume(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj, *tmp; - if (!con) + if (!adev->ras_features || !con) { + /* clean ras context for VEGA20 Gaming after send ras disable cmd */ + amdgpu_release_ras_context(adev); + return; + } if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { /* Set up all other IPs which are not implemented. There is a @@ -2125,7 +2174,7 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!con) + if (!adev->ras_features || !con) return; amdgpu_ras_disable_all_features(adev, 0); @@ -2139,7 +2188,7 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!con) + if (!adev->ras_features || !con) return 0; /* Need disable ras on all IPs here before ip [hw/sw]fini */ @@ -2152,7 +2201,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!con) + if (!adev->ras_features || !con) return 0; amdgpu_ras_fs_fini(adev); @@ -2196,18 +2245,16 @@ bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) return false; } -bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev) +void amdgpu_release_ras_context(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - bool exc_err_limit = false; - if (con && (amdgpu_bad_page_threshold != 0)) - amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control, - &exc_err_limit); + if (!con) + return; - /* - * We are only interested in variable exc_err_limit, - * as it says if GPU is in bad state or not. - */ - return exc_err_limit; + if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { + con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); + amdgpu_ras_set_context(adev, NULL); + kfree(con); + } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 762f5e46c007cf184ee39cae3cfa4fa114798942..60df268a0c66d25f4e6a159e5186d0e639b81821 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -318,8 +318,6 @@ struct amdgpu_ras { uint32_t supported; uint32_t features; struct list_head head; - /* debugfs */ - struct dentry *dir; /* sysfs */ struct device_attribute features_attr; struct bin_attribute badpages_attr; @@ -395,8 +393,6 @@ struct ras_manager { struct list_head node; /* the device */ struct amdgpu_device *adev; - /* debugfs */ - struct dentry *ent; /* sysfs */ struct device_attribute sysfs_attr; int attr_inuse; @@ -495,8 +491,6 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev); unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, bool is_ce); -bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev); - /* error handling functions */ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, struct eeprom_table_record *bps, int pages); @@ -594,9 +588,12 @@ int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); -int amdgpu_ras_error_query(struct amdgpu_device *adev, +int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info); +int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, + enum amdgpu_ras_block block); + int amdgpu_ras_error_inject(struct amdgpu_device *adev, struct ras_inject_if *info); @@ -629,4 +626,6 @@ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); + +void amdgpu_release_ras_context(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 19d9aa76cfbfbca0db3a66f29197ba4fbaae5ced..a05dbbbd9803b80ba909905052a633046f1b6522 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -434,47 +434,28 @@ static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) return curr_address; } -int amdgpu_ras_eeprom_check_err_threshold( - struct amdgpu_ras_eeprom_control *control, - bool *exceed_err_limit) +bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) { - struct amdgpu_device *adev = to_amdgpu_device(control); - unsigned char buff[EEPROM_ADDRESS_SIZE + - EEPROM_TABLE_HEADER_SIZE] = { 0 }; - struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; - struct i2c_msg msg = { - .addr = control->i2c_address, - .flags = I2C_M_RD, - .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, - .buf = buff, - }; - int ret; - - *exceed_err_limit = false; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); if (!__is_ras_eeprom_supported(adev)) - return 0; - - /* read EEPROM table header */ - mutex_lock(&control->tbl_mutex); - ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1); - if (ret < 1) { - dev_err(adev->dev, "Failed to read EEPROM table header.\n"); - goto err; - } + return false; - __decode_table_header_from_buff(hdr, &buff[2]); + /* skip check eeprom table for VEGA20 Gaming */ + if (!con) + return false; + else + if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) + return false; - if (hdr->header == EEPROM_TABLE_HDR_BAD) { + if (con->eeprom_control.tbl_hdr.header == EEPROM_TABLE_HDR_BAD) { dev_warn(adev->dev, "This GPU is in BAD status."); dev_warn(adev->dev, "Please retire it or setting one bigger " "threshold value when reloading driver.\n"); - *exceed_err_limit = true; + return true; } -err: - mutex_unlock(&control->tbl_mutex); - return 0; + return false; } int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index c7a5e5c7c61ebb0656000a2eb51f4aa9793b8d75..17872117097455a308b6348391eb68e662afc02c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -80,9 +80,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, bool *exceed_err_limit); int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control); -int amdgpu_ras_eeprom_check_err_threshold( - struct amdgpu_ras_eeprom_control *control, - bool *exceed_err_limit); +bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev); int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, struct eeprom_table_record *records, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h new file mode 100644 index 0000000000000000000000000000000000000000..b49a61d07d605e307a84812fa1c37d4755dcce9e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ + +#ifndef __AMDGPU_RES_CURSOR_H__ +#define __AMDGPU_RES_CURSOR_H__ + +#include +#include + +/* state back for walking over vram_mgr and gtt_mgr allocations */ +struct amdgpu_res_cursor { + uint64_t start; + uint64_t size; + uint64_t remaining; + struct drm_mm_node *node; +}; + +/** + * amdgpu_res_first - initialize a amdgpu_res_cursor + * + * @res: TTM resource object to walk + * @start: Start of the range + * @size: Size of the range + * @cur: cursor object to initialize + * + * Start walking over the range of allocations between @start and @size. + */ +static inline void amdgpu_res_first(struct ttm_resource *res, + uint64_t start, uint64_t size, + struct amdgpu_res_cursor *cur) +{ + struct drm_mm_node *node; + + if (!res || !res->mm_node) { + cur->start = start; + cur->size = size; + cur->remaining = size; + cur->node = NULL; + return; + } + + BUG_ON(start + size > res->num_pages << PAGE_SHIFT); + + node = res->mm_node; + while (start > node->size << PAGE_SHIFT) + start -= node++->size << PAGE_SHIFT; + + cur->start = (node->start << PAGE_SHIFT) + start; + cur->size = min((node->size << PAGE_SHIFT) - start, size); + cur->remaining = size; + cur->node = node; +} + +/** + * amdgpu_res_next - advance the cursor + * + * @cur: the cursor to advance + * @size: number of bytes to move forward + * + * Move the cursor @size bytes forwrad, walking to the next node if necessary. + */ +static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size) +{ + struct drm_mm_node *node = cur->node; + + BUG_ON(size > cur->remaining); + + cur->remaining -= size; + if (!cur->remaining) + return; + + cur->size -= size; + if (cur->size) { + cur->start += size; + return; + } + + cur->node = ++node; + cur->start = node->start << PAGE_SHIFT; + cur->size = min(node->size << PAGE_SHIFT, cur->remaining); +} + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index e5b8fb8e75c5250427761a0466e66f65ea138aa6..f8fb755e3aa64e42f1bff0830b61ed279abd58cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -64,6 +64,11 @@ struct amdgpu_sdma { struct amdgpu_irq_src trap_irq; struct amdgpu_irq_src illegal_inst_irq; struct amdgpu_irq_src ecc_irq; + struct amdgpu_irq_src vm_hole_irq; + struct amdgpu_irq_src doorbell_invalid_irq; + struct amdgpu_irq_src pool_timeout_irq; + struct amdgpu_irq_src srbm_write_irq; + int num_instances; uint32_t srbm_soft_reset; bool has_page_queue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c index 834440ab9ff74740820f11d35a04074947b1273a..9cf856c94f944ef1865774b2e8b3f39edca5d3f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c @@ -69,6 +69,9 @@ void psp_securedisplay_parse_resp_status(struct psp_context *psp, case TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR: dev_err(psp->adev->dev, "Secure display: Failed to Read CRC"); break; + case TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR: + dev_err(psp->adev->dev, "Secure display: Failed to initialize I2C."); + break; default: dev_err(psp->adev->dev, "Secure display: Failed to parse status: %d\n", status); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h index 03009157aec8d2898172d845c45c850e7e919679..b860ec913ac5c1e5cb0781f9fb869c9ed321d5d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h @@ -28,6 +28,8 @@ struct amdgpu_smuio_funcs { u32 (*get_rom_data_offset)(struct amdgpu_device *adev); void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable); void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags); + u32 (*get_die_id)(struct amdgpu_device *adev); + bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev); }; struct amdgpu_smuio { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 9fd2157b133accc9e71894fcdc9515c764270948..1c6131489a851ae8d4447d4ffa70b5093de73bc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -47,7 +47,6 @@ #include #include -#include #include #include "amdgpu.h" @@ -57,14 +56,15 @@ #include "amdgpu_sdma.h" #include "amdgpu_ras.h" #include "amdgpu_atomfirmware.h" +#include "amdgpu_res_cursor.h" #include "bif/bif_4_1_d.h" #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 -static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, +static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); -static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, +static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm); static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, @@ -178,55 +178,12 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) filp->private_data); } -/** - * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. - * - * @bo: The bo to assign the memory to. - * @mm_node: Memory manager node for drm allocator. - * @mem: The region where the bo resides. - * - */ -static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, - struct drm_mm_node *mm_node, - struct ttm_resource *mem) -{ - uint64_t addr = 0; - - if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { - addr = mm_node->start << PAGE_SHIFT; - addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), - mem->mem_type); - } - return addr; -} - -/** - * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to - * @offset. It also modifies the offset to be within the drm_mm_node returned - * - * @mem: The region where the bo resides. - * @offset: The offset that drm_mm_node is used for finding. - * - */ -static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, - uint64_t *offset) -{ - struct drm_mm_node *mm_node = mem->mm_node; - - while (*offset >= (mm_node->size << PAGE_SHIFT)) { - *offset -= (mm_node->size << PAGE_SHIFT); - ++mm_node; - } - return mm_node; -} - /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @bo: buffer object to map * @mem: memory object to map - * @mm_node: drm_mm node object to map + * @mm_cur: range to map * @num_pages: number of pages to map - * @offset: offset into @mm_node where to start * @window: which GART window to use * @ring: DMA ring to use for the copy * @tmz: if we should setup a TMZ enabled mapping @@ -237,10 +194,10 @@ static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, */ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, struct ttm_resource *mem, - struct drm_mm_node *mm_node, - unsigned num_pages, uint64_t offset, - unsigned window, struct amdgpu_ring *ring, - bool tmz, uint64_t *addr) + struct amdgpu_res_cursor *mm_cur, + unsigned num_pages, unsigned window, + struct amdgpu_ring *ring, bool tmz, + uint64_t *addr) { struct amdgpu_device *adev = ring->adev; struct amdgpu_job *job; @@ -257,14 +214,15 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, /* Map only what can't be accessed directly */ if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { - *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; + *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + + mm_cur->start; return 0; } *addr = adev->gmc.gart_start; *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GPU_PAGE_SIZE; - *addr += offset & ~PAGE_MASK; + *addr += mm_cur->start & ~PAGE_MASK; num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes = num_pages * 8; @@ -292,17 +250,17 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, cpu_addr = &job->ibs[0].ptr[num_dw]; if (mem->mem_type == TTM_PL_TT) { - dma_addr_t *dma_address; + dma_addr_t *dma_addr; - dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT]; - r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, + dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; + r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); if (r) goto error_free; } else { dma_addr_t dma_address; - dma_address = (mm_node->start << PAGE_SHIFT) + offset; + dma_address = mm_cur->start; dma_address += adev->vm_manager.vram_base_offset; for (i = 0; i < num_pages; ++i) { @@ -354,9 +312,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GPU_PAGE_SIZE); - uint64_t src_node_size, dst_node_size, src_offset, dst_offset; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - struct drm_mm_node *src_mm, *dst_mm; + struct amdgpu_res_cursor src_mm, dst_mm; struct dma_fence *fence = NULL; int r = 0; @@ -365,29 +322,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, return -EINVAL; } - src_offset = src->offset; - if (src->mem->mm_node) { - src_mm = amdgpu_find_mm_node(src->mem, &src_offset); - src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; - } else { - src_mm = NULL; - src_node_size = ULLONG_MAX; - } - - dst_offset = dst->offset; - if (dst->mem->mm_node) { - dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); - dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; - } else { - dst_mm = NULL; - dst_node_size = ULLONG_MAX; - } + amdgpu_res_first(src->mem, src->offset, size, &src_mm); + amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); mutex_lock(&adev->mman.gtt_window_lock); - - while (size) { - uint32_t src_page_offset = src_offset & ~PAGE_MASK; - uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; + while (src_mm.remaining) { + uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; + uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; struct dma_fence *next; uint32_t cur_size; uint64_t from, to; @@ -396,19 +337,19 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, * begins at an offset, then adjust the size accordingly */ cur_size = max(src_page_offset, dst_page_offset); - cur_size = min(min3(src_node_size, dst_node_size, size), + cur_size = min(min3(src_mm.size, dst_mm.size, size), (uint64_t)(GTT_MAX_BYTES - cur_size)); /* Map src to window 0 and dst to window 1. */ - r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, + r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, PFN_UP(cur_size + src_page_offset), - src_offset, 0, ring, tmz, &from); + 0, ring, tmz, &from); if (r) goto error; - r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, + r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, PFN_UP(cur_size + dst_page_offset), - dst_offset, 1, ring, tmz, &to); + 1, ring, tmz, &to); if (r) goto error; @@ -420,27 +361,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, dma_fence_put(fence); fence = next; - size -= cur_size; - if (!size) - break; - - src_node_size -= cur_size; - if (!src_node_size) { - ++src_mm; - src_node_size = src_mm->size << PAGE_SHIFT; - src_offset = 0; - } else { - src_offset += cur_size; - } - - dst_node_size -= cur_size; - if (!dst_node_size) { - ++dst_mm; - dst_node_size = dst_mm->size << PAGE_SHIFT; - dst_offset = 0; - } else { - dst_offset += cur_size; - } + amdgpu_res_next(&src_mm, cur_size); + amdgpu_res_next(&dst_mm, cur_size); } error: mutex_unlock(&adev->mman.gtt_window_lock); @@ -519,7 +441,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, static bool amdgpu_mem_visible(struct amdgpu_device *adev, struct ttm_resource *mem) { - struct drm_mm_node *nodes = mem->mm_node; + uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; + struct amdgpu_res_cursor cursor; if (mem->mem_type == TTM_PL_SYSTEM || mem->mem_type == TTM_PL_TT) @@ -527,12 +450,13 @@ static bool amdgpu_mem_visible(struct amdgpu_device *adev, if (mem->mem_type != TTM_PL_VRAM) return false; + amdgpu_res_first(mem, 0, mem_size, &cursor); + /* ttm_resource_ioremap only supports contiguous memory */ - if (nodes->size != mem->num_pages) + if (cursor.size != mem_size) return false; - return ((nodes->start + nodes->size) << PAGE_SHIFT) - <= adev->gmc.visible_vram_size; + return cursor.start + cursor.size <= adev->gmc.visible_vram_size; } /* @@ -646,7 +570,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, * * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() */ -static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) +static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem) { struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); struct drm_mm_node *mm_node = mem->mm_node; @@ -674,7 +598,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso mem->bus.offset += adev->gmc.aper_base; mem->bus.is_iomem = true; - mem->bus.caching = ttm_write_combined; + if (adev->gmc.xgmi.connected_to_cpu) + mem->bus.caching = ttm_cached; + else + mem->bus.caching = ttm_write_combined; break; default: return -EINVAL; @@ -686,12 +613,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, unsigned long page_offset) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); - uint64_t offset = (page_offset << PAGE_SHIFT); - struct drm_mm_node *mm; + struct amdgpu_res_cursor cursor; - mm = amdgpu_find_mm_node(&bo->mem, &offset); - offset += adev->gmc.aper_base; - return mm->start + (offset >> PAGE_SHIFT); + amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor); + return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; } /** @@ -893,7 +818,7 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) * * Called by amdgpu_ttm_backend_bind() **/ -static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, +static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm) { struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); @@ -931,7 +856,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, /* * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages */ -static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, +static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm) { struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); @@ -1015,7 +940,7 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). * This handles binding GTT memory to the device address space. */ -static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, +static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem) { @@ -1155,7 +1080,7 @@ int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and * ttm_tt_destroy(). */ -static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, +static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm) { struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); @@ -1180,7 +1105,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, gtt->bound = false; } -static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev, +static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm) { struct amdgpu_ttm_tt *gtt = (void *)ttm; @@ -1234,7 +1159,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, * Map the pages of a ttm_tt object to an address space visible * to the underlying device. */ -static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev, +static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) { @@ -1278,7 +1203,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev, * Unmaps pages of a ttm_tt object from the device address space and * unpopulates the page array backing it. */ -static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, +static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm) { struct amdgpu_ttm_tt *gtt = (void *)ttm; @@ -1430,6 +1355,10 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) flags |= AMDGPU_PTE_SNOOPED; } + if (mem && mem->mem_type == TTM_PL_VRAM && + mem->bus.caching == ttm_cached) + flags |= AMDGPU_PTE_SNOOPED; + return flags; } @@ -1469,7 +1398,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, const struct ttm_place *place) { unsigned long num_pages = bo->mem.num_pages; - struct drm_mm_node *node = bo->mem.mm_node; + struct amdgpu_res_cursor cursor; struct dma_resv_list *flist; struct dma_fence *f; int i; @@ -1501,13 +1430,15 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, case TTM_PL_VRAM: /* Check each drm MM node individually */ - while (num_pages) { - if (place->fpfn < (node->start + node->size) && - !(place->lpfn && place->lpfn <= node->start)) + amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT, + &cursor); + while (cursor.remaining) { + if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) + && !(place->lpfn && + place->lpfn <= PFN_DOWN(cursor.start))) return true; - num_pages -= node->size; - ++node; + amdgpu_res_next(&cursor, cursor.size); } return false; @@ -1531,41 +1462,36 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * access for debugging purposes. */ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, - unsigned long offset, - void *buf, int len, int write) + unsigned long offset, void *buf, int len, + int write) { struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); - struct drm_mm_node *nodes; + struct amdgpu_res_cursor cursor; + unsigned long flags; uint32_t value = 0; int ret = 0; - uint64_t pos; - unsigned long flags; if (bo->mem.mem_type != TTM_PL_VRAM) return -EIO; - pos = offset; - nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); - pos += (nodes->start << PAGE_SHIFT); - - while (len && pos < adev->gmc.mc_vram_size) { - uint64_t aligned_pos = pos & ~(uint64_t)3; - uint64_t bytes = 4 - (pos & 3); - uint32_t shift = (pos & 3) * 8; + amdgpu_res_first(&bo->mem, offset, len, &cursor); + while (cursor.remaining) { + uint64_t aligned_pos = cursor.start & ~(uint64_t)3; + uint64_t bytes = 4 - (cursor.start & 3); + uint32_t shift = (cursor.start & 3) * 8; uint32_t mask = 0xffffffff << shift; - if (len < bytes) { - mask &= 0xffffffff >> (bytes - len) * 8; - bytes = len; + if (cursor.size < bytes) { + mask &= 0xffffffff >> (bytes - cursor.size) * 8; + bytes = cursor.size; } if (mask != 0xffffffff) { spin_lock_irqsave(&adev->mmio_idx_lock, flags); WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); - if (!write || mask != 0xffffffff) - value = RREG32_NO_KIQ(mmMM_DATA); + value = RREG32_NO_KIQ(mmMM_DATA); if (write) { value &= ~mask; value |= (*(uint32_t *)buf << shift) & mask; @@ -1577,21 +1503,15 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, memcpy(buf, &value, bytes); } } else { - bytes = (nodes->start + nodes->size) << PAGE_SHIFT; - bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); - - amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, - bytes, write); + bytes = cursor.size & 0x3ull; + amdgpu_device_vram_access(adev, cursor.start, + (uint32_t *)buf, bytes, + write); } ret += bytes; buf = (uint8_t *)buf + bytes; - pos += bytes; - len -= bytes; - if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { - ++nodes; - pos = (nodes->start << PAGE_SHIFT); - } + amdgpu_res_next(&cursor, bytes); } return ret; @@ -1603,7 +1523,7 @@ amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) amdgpu_bo_move_notify(bo, false, NULL); } -static struct ttm_bo_driver amdgpu_bo_driver = { +static struct ttm_device_funcs amdgpu_bo_driver = { .ttm_tt_create = &amdgpu_ttm_tt_create, .ttm_tt_populate = &amdgpu_ttm_tt_populate, .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, @@ -1696,7 +1616,7 @@ static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; - + DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", ctx->train_data_size, ctx->p2c_train_data_offset, @@ -1785,7 +1705,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) mutex_init(&adev->mman.gtt_window_lock); /* No others user of address space so set it to 0 */ - r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, + r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, adev_to_drm(adev)->anon_inode->i_mapping, adev_to_drm(adev)->vma_offset_manager, adev->need_swiotlb, @@ -1812,8 +1732,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) /* Change the size here instead of the init above so only lpfn is affected */ amdgpu_ttm_set_buffer_funcs_status(adev, false); #ifdef CONFIG_64BIT - adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, - adev->gmc.visible_vram_size); +#ifdef CONFIG_X86 + if (adev->gmc.xgmi.connected_to_cpu) + adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, + adev->gmc.visible_vram_size); + + else +#endif + adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, + adev->gmc.visible_vram_size); #endif /* @@ -1926,7 +1853,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); - ttm_bo_device_release(&adev->mman.bdev); + ttm_device_fini(&adev->mman.bdev); adev->mman.initialized = false; DRM_INFO("amdgpu: ttm finalized\n"); } @@ -2002,7 +1929,7 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) return ret; } -static struct vm_operations_struct amdgpu_ttm_vm_ops = { +static const struct vm_operations_struct amdgpu_ttm_vm_ops = { .fault = amdgpu_ttm_fault, .open = ttm_bo_vm_open, .close = ttm_bo_vm_close, @@ -2053,7 +1980,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, return r; if (vm_needs_flush) { - job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); + job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? + adev->gmc.pdb0_bo : adev->gart.bo); job->vm_needs_flush = true; } if (resv) { @@ -2104,9 +2032,9 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - struct drm_mm_node *mm_node; - unsigned long num_pages; + struct amdgpu_res_cursor cursor; unsigned int num_loops, num_dw; + uint64_t num_bytes; struct amdgpu_job *job; int r; @@ -2122,15 +2050,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, return r; } - num_pages = bo->tbo.mem.num_pages; - mm_node = bo->tbo.mem.mm_node; + num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT; num_loops = 0; - while (num_pages) { - uint64_t byte_count = mm_node->size << PAGE_SHIFT; - num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); - num_pages -= mm_node->size; - ++mm_node; + amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); + while (cursor.remaining) { + num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); + amdgpu_res_next(&cursor, cursor.size); } num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; @@ -2152,27 +2078,16 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, } } - num_pages = bo->tbo.mem.num_pages; - mm_node = bo->tbo.mem.mm_node; - - while (num_pages) { - uint64_t byte_count = mm_node->size << PAGE_SHIFT; - uint64_t dst_addr; - - dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); - while (byte_count) { - uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, - max_bytes); + amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); + while (cursor.remaining) { + uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); + uint64_t dst_addr = cursor.start; - amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, - dst_addr, cur_size_in_bytes); + dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); + amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, + cur_size); - dst_addr += cur_size_in_bytes; - byte_count -= cur_size_in_bytes; - } - - num_pages -= mm_node->size; - ++mm_node; + amdgpu_res_next(&cursor, cur_size); } amdgpu_ring_pad_ib(ring, &job->ibs[0]); @@ -2191,36 +2106,74 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, #if defined(CONFIG_DEBUG_FS) -static int amdgpu_mm_dump_table(struct seq_file *m, void *data) +static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - unsigned ttm_pl = (uintptr_t)node->info_ent->data; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + TTM_PL_VRAM); struct drm_printer p = drm_seq_file_printer(m); man->func->debug(man, &p); return 0; } -static int amdgpu_ttm_pool_debugfs(struct seq_file *m, void *data) +static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; return ttm_pool_debugfs(&adev->mman.bdev.pool, m); } -static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { - {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, - {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, - {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, - {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, - {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, - {"ttm_page_pool", amdgpu_ttm_pool_debugfs, 0, NULL}, -}; +static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + TTM_PL_TT); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_GDS); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_GWS); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_OA); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); /* * amdgpu_ttm_vram_read - Linear read access to VRAM @@ -2308,58 +2261,6 @@ static const struct file_operations amdgpu_ttm_vram_fops = { .llseek = default_llseek, }; -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - -/* - * amdgpu_ttm_gtt_read - Linear read access to GTT memory - */ -static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, - size_t size, loff_t *pos) -{ - struct amdgpu_device *adev = file_inode(f)->i_private; - ssize_t result = 0; - int r; - - while (size) { - loff_t p = *pos / PAGE_SIZE; - unsigned off = *pos & ~PAGE_MASK; - size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); - struct page *page; - void *ptr; - - if (p >= adev->gart.num_cpu_pages) - return result; - - page = adev->gart.pages[p]; - if (page) { - ptr = kmap(page); - ptr += off; - - r = copy_to_user(buf, ptr, cur_size); - kunmap(adev->gart.pages[p]); - } else - r = clear_user(buf, cur_size); - - if (r) - return -EFAULT; - - result += cur_size; - buf += cur_size; - *pos += cur_size; - size -= cur_size; - } - - return result; -} - -static const struct file_operations amdgpu_ttm_gtt_fops = { - .owner = THIS_MODULE, - .read = amdgpu_ttm_gtt_read, - .llseek = default_llseek -}; - -#endif - /* * amdgpu_iomem_read - Virtual read access to GPU mapped memory * @@ -2474,46 +2375,29 @@ static const struct file_operations amdgpu_ttm_iomem_fops = { .llseek = default_llseek }; -static const struct { - char *name; - const struct file_operations *fops; - int domain; -} ttm_debugfs_entries[] = { - { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, -#endif - { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, -}; - #endif -int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) +void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - unsigned count; - struct drm_minor *minor = adev_to_drm(adev)->primary; - struct dentry *ent, *root = minor->debugfs_root; - - for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { - ent = debugfs_create_file( - ttm_debugfs_entries[count].name, - S_IFREG | S_IRUGO, root, - adev, - ttm_debugfs_entries[count].fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); - if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) - i_size_write(ent->d_inode, adev->gmc.mc_vram_size); - else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) - i_size_write(ent->d_inode, adev->gmc.gart_size); - adev->mman.debugfs_entries[count] = ent; - } - - count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); - return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); -#else - return 0; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file_size("amdgpu_vram", 0444, root, adev, + &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); + debugfs_create_file("amdgpu_iomem", 0444, root, adev, + &amdgpu_ttm_iomem_fops); + debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, + &amdgpu_mm_vram_table_fops); + debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, + &amdgpu_mm_tt_table_fops); + debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, + &amdgpu_mm_gds_table_fops); + debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, + &amdgpu_mm_gws_table_fops); + debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, + &amdgpu_mm_oa_table_fops); + debugfs_create_file("ttm_page_pool", 0444, root, adev, + &amdgpu_ttm_page_pool_fops); #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index d2987536d7cd9556fa70f39a88576101608a17b5..dec0db8b0b13c14e6bfaf7eed23afdc5b4093923 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -60,14 +60,10 @@ struct amdgpu_gtt_mgr { }; struct amdgpu_mman { - struct ttm_bo_device bdev; + struct ttm_device bdev; bool initialized; void __iomem *aper_base_kaddr; -#if defined(CONFIG_DEBUG_FS) - struct dentry *debugfs_entries[8]; -#endif - /* buffer handling */ const struct amdgpu_buffer_funcs *buffer_funcs; struct amdgpu_ring *buffer_funcs_ring; @@ -119,8 +115,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, struct device *dev, enum dma_data_direction dir, struct sg_table **sgt); -void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev, - struct device *dev, +void amdgpu_vram_mgr_free_sgt(struct device *dev, enum dma_data_direction dir, struct sg_table *sgt); uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man); @@ -186,6 +181,6 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, struct ttm_resource *mem); -int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); +void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 1beb08af347f9d8fc6011334bf72ae070e692ed0..9733224117e36866fc07f28021d1ef1189d1532c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -402,6 +402,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_ALDEBARAN: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 46449e70348bea565a144fdb0d152b2bd6b8dda5..2c42874f77847ac1eecacc5e7aa18f3c2154b308 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -105,6 +105,9 @@ struct psp_firmware_header_v1_3 { uint32_t spl_header_version; uint32_t spl_offset_bytes; uint32_t spl_size_bytes; + uint32_t rl_header_version; + uint32_t rl_offset_bytes; + uint32_t rl_size_bytes; }; /* version_major=1, version_minor=0 */ @@ -136,6 +139,7 @@ enum ta_fw_type { TA_FW_TYPE_PSP_DTM, TA_FW_TYPE_PSP_RAP, TA_FW_TYPE_PSP_SECUREDISPLAY, + TA_FW_TYPE_MAX_INDEX, }; struct ta_fw_bin_desc { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 99b82f3c26177c7d5fecc7ee93ed875d3f9f0be6..201645963ba519a6c0d96a41fb4fd64cff0089cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -47,6 +47,7 @@ #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" +#define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); MODULE_FIRMWARE(FIRMWARE_PICASSO); @@ -54,6 +55,7 @@ MODULE_FIRMWARE(FIRMWARE_RAVEN2); MODULE_FIRMWARE(FIRMWARE_ARCTURUS); MODULE_FIRMWARE(FIRMWARE_RENOIR); MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); +MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); MODULE_FIRMWARE(FIRMWARE_NAVI10); MODULE_FIRMWARE(FIRMWARE_NAVI14); MODULE_FIRMWARE(FIRMWARE_NAVI12); @@ -100,6 +102,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) else fw_name = FIRMWARE_GREEN_SARDINE; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) + adev->vcn.indirect_sram = true; + break; + case CHIP_ALDEBARAN: + fw_name = FIRMWARE_ALDEBARAN; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 13aa417f6be7f03b9aa4e55278745e3d3b955dde..1843bf8de0cfba4127d9bed63cac7ca35e8dc1db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -155,6 +155,7 @@ } \ } while (0) +#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6) #define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8) #define AMDGPU_VCN_SW_RING_FLAG (1 << 9) @@ -243,6 +244,12 @@ struct amdgpu_vcn { int inst_idx, struct dpg_pause_state *new_state); }; +struct amdgpu_fw_shared_rb_ptrs_struct { + /* to WA DPG R/W ptr issues.*/ + uint32_t rptr; + uint32_t wptr; +}; + struct amdgpu_fw_shared_multi_queue { uint8_t decode_queue_mode; uint8_t encode_generalpurpose_queue_mode; @@ -258,10 +265,12 @@ struct amdgpu_fw_shared_sw_ring { struct amdgpu_fw_shared { uint32_t present_flag_0; - uint8_t pad[53]; + uint8_t pad[44]; + struct amdgpu_fw_shared_rb_ptrs_struct rb; + uint8_t pad1[1]; struct amdgpu_fw_shared_multi_queue multi_queue; struct amdgpu_fw_shared_sw_ring sw_ring; -} __attribute__((__packed__)); +}; struct amdgpu_vcn_decode_buffer { uint32_t valid_buf_flag; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 5da04d45b63795a0305178719dcdbe2025a95cef..d9ffff8eb41d2f1a1ef8c9909a697910a375bf30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -640,6 +640,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); break; default: /* other chip doesn't support SRIOV */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ad91c0c3c42357cd3499df51286a77e86c861cf0..f314e1e269cdff8fa81b993f3a25136769813abf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -92,13 +92,13 @@ struct amdgpu_prt_cb { static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) { mutex_lock(&vm->eviction_lock); - vm->saved_flags = memalloc_nofs_save(); + vm->saved_flags = memalloc_noreclaim_save(); } static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) { if (mutex_trylock(&vm->eviction_lock)) { - vm->saved_flags = memalloc_nofs_save(); + vm->saved_flags = memalloc_noreclaim_save(); return 1; } return 0; @@ -106,7 +106,7 @@ static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) { - memalloc_nofs_restore(vm->saved_flags); + memalloc_noreclaim_restore(vm->saved_flags); mutex_unlock(&vm->eviction_lock); } @@ -638,15 +638,15 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, struct amdgpu_vm_bo_base *bo_base; if (vm->bulk_moveable) { - spin_lock(&ttm_bo_glob.lru_lock); + spin_lock(&adev->mman.bdev.lru_lock); ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); - spin_unlock(&ttm_bo_glob.lru_lock); + spin_unlock(&adev->mman.bdev.lru_lock); return; } memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); - spin_lock(&ttm_bo_glob.lru_lock); + spin_lock(&adev->mman.bdev.lru_lock); list_for_each_entry(bo_base, &vm->idle, vm_status) { struct amdgpu_bo *bo = bo_base->bo; @@ -660,7 +660,7 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, &bo->shadow->tbo.mem, &vm->lru_bulk_move); } - spin_unlock(&ttm_bo_glob.lru_lock); + spin_unlock(&adev->mman.bdev.lru_lock); vm->bulk_moveable = true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index c89b66bb70e2e7c03de3723c304121907029e8d3..b2fc475ce6f705e5d044fed6f2e5916ef77992cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -639,15 +639,13 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, /** * amdgpu_vram_mgr_free_sgt - allocate and fill a sg table * - * @adev: amdgpu device pointer * @dev: device pointer * @dir: data direction of resource to unmap * @sgt: sg table to free * * Free a previously allocate sg table. */ -void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev, - struct device *dev, +void amdgpu_vram_mgr_free_sgt(struct device *dev, enum dma_data_direction dir, struct sg_table *sgt) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 659b385b27b5a04ca02b9e2a1f7b450ab1a41168..33f748e5bbfc2c3a3b363bd1869f59b5fa2a4a95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -468,15 +468,22 @@ int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_dev } +/* + * NOTE psp_xgmi_node_info.num_hops layout is as follows: + * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) + * num_hops[5:3] = reserved + * num_hops[2:0] = number of hops + */ int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) { struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; + uint8_t num_hops_mask = 0x7; int i; for (i = 0 ; i < top->num_nodes; ++i) if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) - return top->nodes[i].num_hops; + return top->nodes[i].num_hops & num_hops_mask; return -EINVAL; } @@ -492,7 +499,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) if (!adev->gmc.xgmi.supported) return 0; - if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { + if (!adev->gmc.xgmi.pending_reset && + amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { ret = psp_xgmi_initialize(&adev->psp); if (ret) { dev_err(adev->dev, @@ -538,7 +546,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) task_barrier_add_task(&hive->tb); - if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { + if (!adev->gmc.xgmi.pending_reset && + amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { /* update node list for other device in the hive */ if (tmp_adev != adev) { @@ -567,7 +576,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) } } - if (!ret) + if (!ret && !adev->gmc.xgmi.pending_reset) ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); exit_unlock: diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c index 7b1b18350bf92aa7b9baf4330747f8ff072c5413..2ac4988ea0ffbd4e9504a58704241e856fa31d28 100644 --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c @@ -74,10 +74,8 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: - athub_v2_1_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); - athub_v2_1_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); + athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 515890f4f5a0e9c2b3d2ee9879646c8ef1d50c89..3dcb8b32f48bf9965fe02fc6e0978c9cbbc76bbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -114,11 +114,11 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, base++; break; case ATOM_IIO_READ: - temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); + temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); base += 3; break; case ATOM_IIO_WRITE: - ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); + ctx->card->reg_write(ctx->card, CU16(base + 1), temp); base += 3; break; case ATOM_IIO_CLEAR: diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index 4205bbe5d8d7076090f409a9f683b70d9866e446..d279759cab47b5e0eac39b54203ebbee2d4c6204 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -116,8 +116,6 @@ struct card_info { struct drm_device *dev; void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ - void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ - uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */ void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 4d6832cc7fb066511a21d4cd37ad7225cd268beb..c0fcc41ee574a53713d929acced1140df80a2804 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -26,6 +26,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -70,6 +72,80 @@ #include "amdgpu_amdkfd.h" #include "dce_virtual.h" +static const struct amdgpu_video_codec_info cik_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs cik_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(cik_video_codecs_encode_array), + .codec_array = cik_video_codecs_encode_array, +}; + +static const struct amdgpu_video_codec_info cik_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 41, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 4, + }, +}; + +static const struct amdgpu_video_codecs cik_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(cik_video_codecs_decode_array), + .codec_array = cik_video_codecs_decode_array, +}; + +static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (adev->asic_type) { + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: + if (encode) + *codecs = &cik_video_codecs_encode; + else + *codecs = &cik_video_codecs_decode; + return 0; + default: + return -EINVAL; + } +} + /* * Indirect registers accessor */ @@ -1933,6 +2009,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .get_pcie_replay_count = &cik_get_pcie_replay_count, .supports_baco = &cik_asic_supports_baco, .pre_asic_init = &cik_pre_asic_init, + .query_video_codecs = &cik_query_video_codecs, }; static int cik_common_early_init(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 7944781e1086bee1b9e381007d598fa4400f75ef..ea825b4f8ee807d538d6e8395da6bdc8805f02f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1862,7 +1862,6 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; - struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -1981,8 +1980,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, #endif break; default: - DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(target_fb->format->format, &format_name)); + DRM_ERROR("Unsupported screen format %p4cc\n", + &target_fb->format->format); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 1b6ff04700118dd30d3bdf64f7ca2df697f21221..a360a6dec1988c5909449ab11f95cc5ae0c341b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1904,7 +1904,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; - struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -2023,8 +2022,8 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, #endif break; default: - DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(target_fb->format->format, &format_name)); + DRM_ERROR("Unsupported screen format %p4cc\n", + &target_fb->format->format); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 83a88385b7620d1c56762980ce96e84bbca3f4c8..ef124ac853b60f3b03da2dbe9b7b2ade7ee522ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1820,7 +1820,6 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, u32 viewport_w, viewport_h; int r; bool bypass_lut = false; - struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -1929,8 +1928,8 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, #endif break; default: - DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(target_fb->format->format, &format_name)); + DRM_ERROR("Unsupported screen format %p4cc\n", + &target_fb->format->format); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 224b30214427f8df2ff0920718d891381d958a1c..c986501838285fd354789d0753a016799f0b6b23 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1791,7 +1791,6 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, u32 viewport_w, viewport_h; int r; bool bypass_lut = false; - struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -1902,8 +1901,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, #endif break; default: - DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(target_fb->format->format, &format_name)); + DRM_ERROR("Unsupported screen format %p4cc\n", + &target_fb->format->format); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c index 6b4b30a8dce5ead531d534840d81328c990a8c62..44109a6b8f4427060f9be5c5010f11df1083dce4 100644 --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c @@ -568,6 +568,8 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, if (ret) return ret; + df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val, + hi_base_addr, hi_val); if (is_remove) { df_v3_6_reset_perfmon_cntr(adev, config, counter_idx); diff --git a/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c old mode 100755 new mode 100644 diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 84d2eaa381013781ec62d71a2fa63c48a5a63830..4d45844a1d92b1f023e42859a46ffb5cf40126a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6718,7 +6718,8 @@ static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev, return 0; } -static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data) +static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data, + bool from_wq) { u32 enc, se_id, sh_id, cu_id; char type[20]; @@ -6756,7 +6757,7 @@ static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data) * or from BH in which case we can access SQ_EDC_INFO * instance */ - if (in_task()) { + if (from_wq) { mutex_lock(&adev->grbm_idx_mutex); gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id); @@ -6794,7 +6795,7 @@ static void gfx_v8_0_sq_irq_work_func(struct work_struct *work) struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); struct sq_work *sq_work = container_of(work, struct sq_work, work); - gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data); + gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true); } static int gfx_v8_0_sq_irq(struct amdgpu_device *adev, @@ -6809,7 +6810,7 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev, * just print whatever info is possible directly from the ISR. */ if (work_pending(&adev->gfx.sq_work.work)) { - gfx_v8_0_parse_sq_irq(adev, ih_data); + gfx_v8_0_parse_sq_irq(adev, ih_data, false); } else { adev->gfx.sq_work.ih_data = ih_data; schedule_work(&adev->gfx.sq_work.work); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 65db88bb6cbcd6a3d77c64524cbeddba933e7662..1393ccae74180149559c4736515884fb365f3600 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -49,6 +49,7 @@ #include "gfx_v9_4.h" #include "gfx_v9_0.h" +#include "gfx_v9_4_2.h" #include "asic_reg/pwr/pwr_10_0_offset.h" #include "asic_reg/pwr/pwr_10_0_sh_mask.h" @@ -107,14 +108,12 @@ MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin"); MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); MODULE_FIRMWARE("amdgpu/renoir_me.bin"); MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); -MODULE_FIRMWARE("amdgpu/renoir_mec2.bin"); MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); @@ -124,6 +123,10 @@ MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); + #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 @@ -981,11 +984,16 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_gc_9_1_rn, ARRAY_SIZE(golden_settings_gc_9_1_rn)); return; /* for renoir, don't need common goldensetting */ + case CHIP_ALDEBARAN: + gfx_v9_4_2_init_golden_registers(adev, + adev->smuio.funcs->get_die_id(adev)); + break; default: break; } - if (adev->asic_type != CHIP_ARCTURUS) + if ((adev->asic_type != CHIP_ARCTURUS) && + (adev->asic_type != CHIP_ALDEBARAN)) soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); } @@ -1517,6 +1525,16 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, return err; } +static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_ALDEBARAN || + adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_RENOIR) + return false; + + return true; +} + static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, const char *chip_name) { @@ -1538,21 +1556,23 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - cp_hdr = (const struct gfx_firmware_header_v1_0 *) - adev->gfx.mec2_fw->data; - adev->gfx.mec2_fw_version = - le32_to_cpu(cp_hdr->header.ucode_version); - adev->gfx.mec2_feature_version = - le32_to_cpu(cp_hdr->ucode_feature_version); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; + if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (!err) { + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw_version = + le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.mec2_feature_version = + le32_to_cpu(cp_hdr->ucode_feature_version); + } else { + err = 0; + adev->gfx.mec2_fw = NULL; + } } if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { @@ -1581,8 +1601,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, /* TODO: Determine if MEC2 JT FW loading can be removed for all GFX V9 asic and above */ - if (adev->asic_type != CHIP_ARCTURUS && - adev->asic_type != CHIP_RENOIR) { + if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; info->fw = adev->gfx.mec2_fw; @@ -1642,6 +1661,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) else chip_name = "green_sardine"; break; + case CHIP_ALDEBARAN: + chip_name = "aldebaran"; + break; default: BUG(); } @@ -1882,7 +1904,10 @@ static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) { - return 5; + if (gfx_v9_0_load_mec2_fw_bin_support(adev)) + return 5; + else + return 4; } static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) @@ -2088,6 +2113,21 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { .query_ras_error_status = &gfx_v9_4_query_ras_error_status, }; +static const struct amdgpu_gfx_funcs gfx_v9_4_2_gfx_funcs = { + .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, + .select_se_sh = &gfx_v9_0_select_se_sh, + .read_wave_data = &gfx_v9_0_read_wave_data, + .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, + .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, + .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, + .ras_error_inject = &gfx_v9_4_2_ras_error_inject, + .query_ras_error_count = &gfx_v9_4_2_query_ras_error_count, + .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count, + .query_ras_error_status = &gfx_v9_4_2_query_ras_error_status, + .reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status, + .enable_watchdog_timer = &gfx_v9_4_2_enable_watchdog_timer, +}; + static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) { u32 gb_addr_config; @@ -2159,6 +2199,21 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) gb_addr_config &= ~0xf3e777ff; gb_addr_config |= 0x22010042; break; + case CHIP_ALDEBARAN: + adev->gfx.funcs = &gfx_v9_4_2_gfx_funcs; + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); + gb_addr_config &= ~0xf3e777ff; + gb_addr_config |= 0x22014042; + /* check vbios table if gpu info is not available */ + err = amdgpu_atomfirmware_get_gfx_info(adev); + if (err) + return err; + break; default: BUG(); break; @@ -2249,6 +2304,7 @@ static int gfx_v9_0_sw_init(void *handle) case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: adev->gfx.mec.num_mec = 2; break; default: @@ -2634,17 +2690,15 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, { u32 tmp; - /* don't toggle interrupts that are only applicable - * to me0 pipe0 on AISCs that have me0 removed */ - if (!adev->gfx.num_gfx_rings) - return; + /* These interrupts should be enabled to drive DS clock */ tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); + if(adev->gfx.num_gfx_rings) + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } @@ -3696,11 +3750,18 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; + struct v9_mqd *tmp_mqd; gfx_v9_0_kiq_setting(ring); - if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ - /* reset MQD to a clean status */ + /* GPU could be in bad state during probe, driver trigger the reset + * after load the SMU, in this case , the mqd is not be initialized. + * driver need to re-init the mqd. + * check mqd->cp_hqd_pq_control since this value should not be 0 + */ + tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; + if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ + /* for GPU_RESET case , reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); @@ -3736,8 +3797,15 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; + struct v9_mqd *tmp_mqd; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control + * is not be initialized before + */ + tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; + + if (!tmp_mqd->cp_hqd_pq_control || + (!amdgpu_in_reset(adev) && !adev->in_suspend)) { memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -3913,6 +3981,9 @@ static int gfx_v9_0_hw_init(void *handle) if (r) return r; + if (adev->asic_type == CHIP_ALDEBARAN) + gfx_v9_4_2_set_power_brake_sequence(adev); + return r; } @@ -4101,7 +4172,7 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) * * also don't wait anymore for IRQ context * */ - if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) + if (r < 1 && (amdgpu_in_reset(adev))) goto failed_kiq_read; might_sleep(); @@ -4486,7 +4557,8 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) if (!ring->sched.ready) return 0; - if (adev->asic_type == CHIP_ARCTURUS) { + if (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) { vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); vgpr_init_regs_ptr = vgpr_init_regs_arcturus; @@ -4636,7 +4708,8 @@ static int gfx_v9_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->asic_type == CHIP_ARCTURUS) + if (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) adev->gfx.num_gfx_rings = 0; else adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; @@ -4662,7 +4735,8 @@ static int gfx_v9_0_ecc_late_init(void *handle) * to GDS in suspend/resume sequence on several cards. So just * limit this operation in cold boot sequence. */ - if (!adev->in_suspend) { + if ((!adev->in_suspend) && + (adev->gds.gds_size)) { r = gfx_v9_0_do_edc_gds_workarounds(adev); if (r) return r; @@ -4673,14 +4747,13 @@ static int gfx_v9_0_ecc_late_init(void *handle) if (r) return r; - if (adev->gfx.funcs && - adev->gfx.funcs->reset_ras_error_count) - adev->gfx.funcs->reset_ras_error_count(adev); - r = amdgpu_gfx_ras_late_init(adev); if (r) return r; + if (adev->gfx.funcs->enable_watchdog_timer) + adev->gfx.funcs->enable_watchdog_timer(adev); + return 0; } @@ -4858,7 +4931,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; - if (adev->asic_type == CHIP_ARCTURUS) + if (!adev->gfx.num_gfx_rings) return; amdgpu_gfx_rlc_enter_safe_mode(adev); @@ -5105,6 +5178,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle, case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: gfx_v9_0_update_gfx_clock_gating(adev, state == AMD_CG_STATE_GATE); break; @@ -6924,6 +6998,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; break; default: @@ -6944,6 +7019,12 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) case CHIP_ARCTURUS: adev->gds.gds_size = 0x1000; break; + case CHIP_ALDEBARAN: + /* aldebaran removed all the GDS internal memory, + * only support GWS opcode in kernel, like barrier + * semaphore.etc */ + adev->gds.gds_size = 0; + break; default: adev->gds.gds_size = 0x10000; break; @@ -6966,6 +7047,10 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) case CHIP_ARCTURUS: adev->gds.gds_compute_max_wave_id = 0xfff; break; + case CHIP_ALDEBARAN: + /* deprecated for Aldebaran, no usage at all */ + adev->gds.gds_compute_max_wave_id = 0; + break; default: /* this really depends on the chip */ adev->gds.gds_compute_max_wave_id = 0x7ff; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c new file mode 100644 index 0000000000000000000000000000000000000000..2e94998c98120904b1646b35f82dd44a6b84b429 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -0,0 +1,1286 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "soc15.h" + +#include "gc/gc_9_4_2_offset.h" +#include "gc/gc_9_4_2_sh_mask.h" +#include "gfx_v9_0.h" + +#include "gfx_v9_4_2.h" +#include "amdgpu_ras.h" +#include "amdgpu_gfx.h" + +enum gfx_v9_4_2_utc_type { + VML2_MEM, + VML2_WALKER_MEM, + UTCL2_MEM, + ATC_L2_CACHE_2M, + ATC_L2_CACHE_32K, + ATC_L2_CACHE_4K +}; + +struct gfx_v9_4_2_utc_block { + enum gfx_v9_4_2_utc_type type; + uint32_t num_banks; + uint32_t num_ways; + uint32_t num_mem_blocks; + struct soc15_reg idx_reg; + struct soc15_reg data_reg; + uint32_t sec_count_mask; + uint32_t sec_count_shift; + uint32_t ded_count_mask; + uint32_t ded_count_shift; + uint32_t clear; +}; + +static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351), +}; + +static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49), +}; + +static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xfffffeef, 0x10b0000), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0xffffffff, 0x30800400), + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20), +}; + +static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev); +static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev); + +void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, + uint32_t die_id) +{ + soc15_program_register_sequence(adev, + golden_settings_gc_9_4_2_alde, + ARRAY_SIZE(golden_settings_gc_9_4_2_alde)); + + /* apply golden settings per die */ + switch (die_id) { + case 0: + soc15_program_register_sequence(adev, + golden_settings_gc_9_4_2_alde_die_0, + ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0)); + break; + case 1: + soc15_program_register_sequence(adev, + golden_settings_gc_9_4_2_alde_die_1, + ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1)); + break; + default: + dev_warn(adev->dev, + "invalid die id %d, ignore channel fabricid remap settings\n", + die_id); + break; + } + + return; +} + +void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, + uint32_t first_vmid, + uint32_t last_vmid) +{ + uint32_t data; + int i; + + mutex_lock(&adev->srbm_mutex); + + for (i = first_vmid; i < last_vmid; i++) { + data = 0; + soc15_grbm_select(adev, 0, 0, 0, i); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, + 0); + WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data); + } + + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) +{ + u32 tmp; + + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + + tmp = 0; + tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1); + WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp); + + tmp = 0; + tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1); + WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); + + WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); + tmp = 0; + tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1); + WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp); + + WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); + tmp = 0; + tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12); + WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp); +} + +static const struct soc15_reg_entry gfx_v9_4_2_edc_counter_regs[] = { + /* CPF */ + { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), 0, 1, 1 }, + /* CPC */ + { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 0, 1, 1 }, + /* GDS */ + { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 0, 1, 1 }, + /* RLC */ + { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), 0, 1, 1 }, + { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), 0, 1, 1 }, + /* SPI */ + { SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), 0, 8, 1 }, + /* SQC */ + { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), 0, 8, 7 }, + { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), 0, 8, 7 }, + { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), 0, 8, 7 }, + { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), 0, 8, 7 }, + /* SQ */ + { SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), 0, 8, 14 }, + /* TCP */ + { SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), 0, 8, 14 }, + /* TCI */ + { SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), 0, 1, 69 }, + /* TCC */ + { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), 0, 1, 16 }, + { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), 0, 1, 16 }, + /* TCA */ + { SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), 0, 1, 2 }, + /* TCX */ + { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), 0, 1, 2 }, + { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), 0, 1, 2 }, + /* TD */ + { SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), 0, 8, 14 }, + /* TA */ + { SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), 0, 8, 14 }, + /* GCEA */ + { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), 0, 1, 16 }, + { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), 0, 1, 16 }, + { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 1, 16 }, +}; + +static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 instance) +{ + u32 data; + + if (instance == 0xffffffff) + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, + INSTANCE_BROADCAST_WRITES, 1); + else + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, + instance); + + if (se_num == 0xffffffff) + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, + 1); + else + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + + if (sh_num == 0xffffffff) + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, + 1); + else + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + + WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data); +} + +static const struct soc15_ras_field_entry gfx_v9_4_2_ras_fields[] = { + /* CPF */ + { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), + SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2), + SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) }, + { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), + SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1), + SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) }, + { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), + SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), + SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) }, + + /* CPC */ + { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), + SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), + SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) }, + { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), + SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), + SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) }, + { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), + SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1), + SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) }, + { "CPC_DC_CSINVOC_RAM_ME1", + SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), + SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1), + SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) }, + { "CPC_DC_RESTORE_RAM_ME1", + SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), + SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1), + SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) }, + { "CPC_DC_CSINVOC_RAM1_ME1", + SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), + SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1), + SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) }, + { "CPC_DC_RESTORE_RAM1_ME1", + SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), + SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1), + SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) }, + + /* GDS */ + { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), + SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC), + SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) }, + { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), + SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) }, + { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) }, + { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) }, + { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) }, + { "GDS_ME1_PIPE0_PIPE_MEM", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) }, + { "GDS_ME1_PIPE1_PIPE_MEM", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) }, + { "GDS_ME1_PIPE2_PIPE_MEM", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) }, + { "GDS_ME1_PIPE3_PIPE_MEM", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), + SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) }, + { "GDS_ME0_GFXHP3D_PIX_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_PIX_DED) }, + { "GDS_ME0_GFXHP3D_VTX_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_VTX_DED) }, + { "GDS_ME0_CS_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_CS_DED) }, + { "GDS_ME0_GFXHP3D_GS_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_GS_DED) }, + { "GDS_ME1_PIPE0_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE0_DED) }, + { "GDS_ME1_PIPE1_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE1_DED) }, + { "GDS_ME1_PIPE2_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE2_DED) }, + { "GDS_ME1_PIPE3_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE3_DED) }, + { "GDS_ME2_PIPE0_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE0_DED) }, + { "GDS_ME2_PIPE1_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE1_DED) }, + { "GDS_ME2_PIPE2_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE2_DED) }, + { "GDS_ME2_PIPE3_DED", + SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, + SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE3_DED) }, + + /* RLC */ + { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) }, + { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) }, + { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) }, + { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) }, + { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) }, + { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) }, + { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) }, + { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) }, + { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT), + SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) }, + + /* SPI */ + { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) }, + { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) }, + { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) }, + { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT), + SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) }, + + /* SQC - regSQC_EDC_CNT */ + { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) }, + { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) }, + { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) }, + { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) }, + { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) }, + { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) }, + { "SQC_DATA_CU3_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_DED_COUNT) }, + { "SQC_DATA_CU3_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_DED_COUNT) }, + + /* SQC - regSQC_EDC_CNT2 */ + { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) }, + { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) }, + { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) }, + { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) }, + { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) }, + { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT) }, + + /* SQC - regSQC_EDC_CNT3 */ + { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), + SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) }, + { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), + SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) }, + { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) }, + { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) }, + { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT) }, + + /* SQC - regSQC_EDC_PARITY_CNT3 */ + { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) }, + { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_DED_COUNT) }, + { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) }, + { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_DED_COUNT) }, + { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) }, + { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_DED_COUNT) }, + { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) }, + { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_DED_COUNT) }, + + /* SQ */ + { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) }, + { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) }, + { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) }, + { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) }, + { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) }, + { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) }, + { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), + SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) }, + + /* TCP */ + { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) }, + { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) }, + { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) }, + { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) }, + { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_DED_COUNT) }, + { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) }, + { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), + SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) }, + + /* TCI */ + { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), + SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT), + SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) }, + + /* TCC */ + { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) }, + { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) }, + { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) }, + { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) }, + { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) }, + { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) }, + { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) }, + { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) }, + { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) }, + { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) }, + { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) }, + { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) }, + { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) }, + { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) }, + { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), + SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT), + SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) }, + + /* TCA */ + { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), + SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) }, + { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), + SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) }, + + /* TCX */ + { "TCX_GROUP0", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_SEC_COUNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_DED_COUNT) }, + { "TCX_GROUP1", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_SEC_COUNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_DED_COUNT) }, + { "TCX_GROUP2", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_SEC_COUNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_DED_COUNT) }, + { "TCX_GROUP3", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_SEC_COUNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_DED_COUNT) }, + { "TCX_GROUP4", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_SEC_COUNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_DED_COUNT) }, + { "TCX_GROUP5", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP5_SED_COUNT), 0, 0 }, + { "TCX_GROUP6", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP6_SED_COUNT), 0, 0 }, + { "TCX_GROUP7", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP7_SED_COUNT), 0, 0 }, + { "TCX_GROUP8", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP8_SED_COUNT), 0, 0 }, + { "TCX_GROUP9", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP9_SED_COUNT), 0, 0 }, + { "TCX_GROUP10", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), + SOC15_REG_FIELD(TCX_EDC_CNT, GROUP10_SED_COUNT), 0, 0 }, + { "TCX_GROUP11", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), + SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP11_SED_COUNT), 0, 0 }, + { "TCX_GROUP12", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), + SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP12_SED_COUNT), 0, 0 }, + { "TCX_GROUP13", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), + SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP13_SED_COUNT), 0, 0 }, + { "TCX_GROUP14", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), + SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP14_SED_COUNT), 0, 0 }, + + /* TD */ + { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), + SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), + SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) }, + { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), + SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), + SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) }, + { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), + SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT), + SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) }, + + /* TA */ + { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) }, + { "TA_FS_AFIFO_LO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_DED_COUNT) }, + { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) }, + { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) }, + { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) }, + { "TA_FS_AFIFO_HI", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_SEC_COUNT), + SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_DED_COUNT) }, + + /* EA - regGCEA_EDC_CNT */ + { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) }, + { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) }, + { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) }, + { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) }, + { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) }, + { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_DED_COUNT) }, + { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 }, + { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 }, + { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 }, + { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), + SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 }, + + /* EA - regGCEA_EDC_CNT2 */ + { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) }, + { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) }, + { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) }, + { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 }, + { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 }, + { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) }, + { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) }, + { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) }, + { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) }, + + /* EA - regGCEA_EDC_CNT3 */ + { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) }, + { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) }, + { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) }, + { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) }, + { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) }, + { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, + SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) }, + { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) }, + { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) }, + { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) }, + { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) }, + { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_SEC_COUNT), + SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) }, +}; + +static const char * const vml2_walker_mems[] = { + "UTC_VML2_CACHE_PDE0_MEM0", + "UTC_VML2_CACHE_PDE0_MEM1", + "UTC_VML2_CACHE_PDE1_MEM0", + "UTC_VML2_CACHE_PDE1_MEM1", + "UTC_VML2_CACHE_PDE2_MEM0", + "UTC_VML2_CACHE_PDE2_MEM1", + "UTC_VML2_RDIF_ARADDRS", + "UTC_VML2_RDIF_LOG_FIFO", + "UTC_VML2_QUEUE_REQ", + "UTC_VML2_QUEUE_RET", +}; + +static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = { + { VML2_MEM, 8, 2, 2, + { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_CNTL) }, + SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, SEC_COUNT), + SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, DED_COUNT), + REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, + { VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1, + { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_CNTL) }, + SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, SEC_COUNT), + SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, DED_COUNT), + REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, + { UTCL2_MEM, 18, 1, 2, + { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_CNTL) }, + SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, SEC_COUNT), + SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, DED_COUNT), + REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, + { ATC_L2_CACHE_2M, 8, 2, 1, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_CNTL) }, + SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, SEC_COUNT), + SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, DED_COUNT), + REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) }, + { ATC_L2_CACHE_32K, 8, 2, 2, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_CNTL) }, + SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, SEC_COUNT), + SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, DED_COUNT), + REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) }, + { ATC_L2_CACHE_4K, 8, 2, 8, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_INDEX) }, + { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) }, + SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, SEC_COUNT), + SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, DED_COUNT), + REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) }, +}; + +static const struct soc15_reg_entry gfx_v9_4_2_rdrsp_status_regs = + { SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 }; + +static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev, + const struct soc15_reg_entry *reg, + uint32_t se_id, uint32_t inst_id, + uint32_t value, uint32_t *sec_count, + uint32_t *ded_count) +{ + uint32_t i; + uint32_t sec_cnt, ded_cnt; + + for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) { + if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset || + gfx_v9_4_2_ras_fields[i].seg != reg->seg || + gfx_v9_4_2_ras_fields[i].inst != reg->inst) + continue; + + sec_cnt = SOC15_RAS_REG_FIELD_VAL( + value, gfx_v9_4_2_ras_fields[i], sec); + if (sec_cnt) { + dev_info(adev->dev, + "GFX SubBlock %s, Instance[%d][%d], SEC %d\n", + gfx_v9_4_2_ras_fields[i].name, se_id, inst_id, + sec_cnt); + *sec_count += sec_cnt; + } + + ded_cnt = SOC15_RAS_REG_FIELD_VAL( + value, gfx_v9_4_2_ras_fields[i], ded); + if (ded_cnt) { + dev_info(adev->dev, + "GFX SubBlock %s, Instance[%d][%d], DED %d\n", + gfx_v9_4_2_ras_fields[i].name, se_id, inst_id, + ded_cnt); + *ded_count += ded_cnt; + } + } + + return 0; +} + +static int gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev, + uint32_t *sec_count, uint32_t *ded_count) +{ + uint32_t i, j, k, data; + uint32_t sec_cnt = 0, ded_cnt = 0; + + if (sec_count && ded_count) { + *sec_count = 0; + *ded_count = 0; + } + + mutex_lock(&adev->grbm_idx_mutex); + + for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) { + for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) { + for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance; + k++) { + gfx_v9_4_2_select_se_sh(adev, j, 0, k); + + /* if sec/ded_count is null, just clear counter */ + if (!sec_count || !ded_count) { + WREG32(SOC15_REG_ENTRY_OFFSET( + gfx_v9_4_2_edc_counter_regs[i]), 0); + continue; + } + + data = RREG32(SOC15_REG_ENTRY_OFFSET( + gfx_v9_4_2_edc_counter_regs[i])); + + if (!data) + continue; + + gfx_v9_4_2_get_reg_error_count(adev, + &gfx_v9_4_2_edc_counter_regs[i], + j, k, data, &sec_cnt, &ded_cnt); + + /* clear counter after read */ + WREG32(SOC15_REG_ENTRY_OFFSET( + gfx_v9_4_2_edc_counter_regs[i]), 0); + } + } + } + + if (sec_count && ded_count) { + *sec_count += sec_cnt; + *ded_count += ded_cnt; + } + + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + +static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev, + struct gfx_v9_4_2_utc_block *blk, + uint32_t instance, uint32_t sec_cnt, + uint32_t ded_cnt) +{ + uint32_t bank, way, mem; + static const char *vml2_way_str[] = { "BIGK", "4K" }; + static const char *utcl2_rounter_str[] = { "VMC", "APT" }; + + mem = instance % blk->num_mem_blocks; + way = (instance / blk->num_mem_blocks) % blk->num_ways; + bank = instance / (blk->num_mem_blocks * blk->num_ways); + + switch (blk->type) { + case VML2_MEM: + dev_info( + adev->dev, + "GFX SubBlock UTC_VML2_BANK_CACHE_%d_%s_MEM%d, SED %d, DED %d\n", + bank, vml2_way_str[way], mem, sec_cnt, ded_cnt); + break; + case VML2_WALKER_MEM: + dev_info(adev->dev, "GFX SubBlock %s, SED %d, DED %d\n", + vml2_walker_mems[bank], sec_cnt, ded_cnt); + break; + case UTCL2_MEM: + dev_info( + adev->dev, + "GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n", + bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt); + break; + case ATC_L2_CACHE_2M: + dev_info( + adev->dev, + "GFX SubBlock UTC_ATCL2_CACHE_2M_BANK%d_WAY%d_MEM, SED %d, DED %d\n", + bank, way, sec_cnt, ded_cnt); + break; + case ATC_L2_CACHE_32K: + dev_info( + adev->dev, + "GFX SubBlock UTC_ATCL2_CACHE_32K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n", + bank, way, mem, sec_cnt, ded_cnt); + break; + case ATC_L2_CACHE_4K: + dev_info( + adev->dev, + "GFX SubBlock UTC_ATCL2_CACHE_4K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n", + bank, way, mem, sec_cnt, ded_cnt); + break; + } +} + +static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev, + uint32_t *sec_count, + uint32_t *ded_count) +{ + uint32_t i, j, data; + uint32_t sec_cnt, ded_cnt; + uint32_t num_instances; + struct gfx_v9_4_2_utc_block *blk; + + if (sec_count && ded_count) { + *sec_count = 0; + *ded_count = 0; + } + + for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) { + blk = &gfx_v9_4_2_utc_blocks[i]; + num_instances = + blk->num_banks * blk->num_ways * blk->num_mem_blocks; + for (j = 0; j < num_instances; j++) { + WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j); + + /* if sec/ded_count is NULL, just clear counter */ + if (!sec_count || !ded_count) { + WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), + blk->clear); + continue; + } + + data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg)); + if (!data) + continue; + + sec_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, sec); + *sec_count += sec_cnt; + ded_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, ded); + *ded_count += ded_cnt; + + /* clear counter after read */ + WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), + blk->clear); + + /* print the edc count */ + gfx_v9_4_2_log_utc_edc_count(adev, blk, j, sec_cnt, + ded_cnt); + } + } + + return 0; +} + +int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) +{ + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + uint32_t sec_count = 0, ded_count = 0; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return -EINVAL; + + err_data->ue_count = 0; + err_data->ce_count = 0; + + gfx_v9_4_2_query_sram_edc_count(adev, &sec_count, &ded_count); + err_data->ce_count += sec_count; + err_data->ue_count += ded_count; + + gfx_v9_4_2_query_utc_edc_count(adev, &sec_count, &ded_count); + err_data->ce_count += sec_count; + err_data->ue_count += ded_count; + + return 0; +} + +static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev) +{ + WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3); + WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3); + WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3); +} + +static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev) +{ + uint32_t i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) { + for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance; + j++) { + gfx_v9_4_2_select_se_sh(adev, i, 0, j); + WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10); + } + } + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) +{ + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return; + + gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL); + gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL); +} + +int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if) +{ + struct ras_inject_if *info = (struct ras_inject_if *)inject_if; + int ret; + struct ta_ras_trigger_error_input block_info = { 0 }; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return -EINVAL; + + block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); + block_info.sub_block_index = info->head.sub_block_index; + block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); + block_info.address = info->address; + block_info.value = info->value; + + mutex_lock(&adev->grbm_idx_mutex); + ret = psp_ras_trigger_error(&adev->psp, &block_info); + mutex_unlock(&adev->grbm_idx_mutex); + + return ret; +} + +static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) +{ + uint32_t i, j; + uint32_t reg_value; + + mutex_lock(&adev->grbm_idx_mutex); + + for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) { + for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance; + j++) { + gfx_v9_4_2_select_se_sh(adev, i, 0, j); + reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( + gfx_v9_4_2_rdrsp_status_regs)); + if (reg_value) + dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n", + j, reg_value); + /* clear after read */ + WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10); + } + } + + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev) +{ + uint32_t data; + + data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS); + if (!data) { + dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); + WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3); + } + + data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS); + if (!data) { + dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); + WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3); + } + + data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS); + if (!data) { + dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); + WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3); + } +} + +void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) +{ + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return; + + gfx_v9_4_2_query_ea_err_status(adev); + gfx_v9_4_2_query_utc_err_status(adev); + gfx_v9_4_2_query_sq_timeout_status(adev); +} + +void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) +{ + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return; + + gfx_v9_4_2_reset_utc_err_status(adev); + gfx_v9_4_2_reset_ea_err_status(adev); + gfx_v9_4_2_reset_sq_timeout_status(adev); +} + +void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) +{ + uint32_t i; + uint32_t data; + + data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, + amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : + 0); + + if (amdgpu_watchdog_timer.timeout_fatal_disable && + (amdgpu_watchdog_timer.period < 1 || + amdgpu_watchdog_timer.period > 0x23)) { + dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); + amdgpu_watchdog_timer.period = 0x23; + } + data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, + amdgpu_watchdog_timer.period); + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + gfx_v9_4_2_select_se_sh(adev, i, 0xffffffff, 0xffffffff); + WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data); + } + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) +{ + WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32_SOC15(GC, 0, regSQ_IND_DATA); +} + +static void gfx_v9_4_2_log_cu_timeout_status(struct amdgpu_device *adev, + uint32_t status) +{ + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; + uint32_t i, simd, wave; + uint32_t wave_status; + uint32_t wave_pc_lo, wave_pc_hi; + uint32_t wave_exec_lo, wave_exec_hi; + uint32_t wave_inst_dw0, wave_inst_dw1; + uint32_t wave_ib_sts; + + for (i = 0; i < 32; i++) { + if (!((i << 1) & status)) + continue; + + simd = i / cu_info->max_waves_per_simd; + wave = i % cu_info->max_waves_per_simd; + + wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + wave_exec_lo = + wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + wave_exec_hi = + wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + wave_inst_dw0 = + wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + wave_inst_dw1 = + wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + + dev_info( + adev->dev, + "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", + simd, wave, wave_status, + ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), + ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), + ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), + wave_ib_sts); + } +} + +static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev) +{ + uint32_t se_idx, sh_idx, cu_idx; + uint32_t status; + + mutex_lock(&adev->grbm_idx_mutex); + for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; + se_idx++) { + for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; + sh_idx++) { + for (cu_idx = 0; + cu_idx < adev->gfx.config.max_cu_per_sh; + cu_idx++) { + gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx, + cu_idx); + status = RREG32_SOC15(GC, 0, + regSQ_TIMEOUT_STATUS); + if (status != 0) { + dev_info( + adev->dev, + "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", + se_idx, sh_idx, cu_idx); + gfx_v9_4_2_log_cu_timeout_status( + adev, status); + } + /* clear old status */ + WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0); + } + } + } + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev) +{ + uint32_t se_idx, sh_idx, cu_idx; + + mutex_lock(&adev->grbm_idx_mutex); + for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; + se_idx++) { + for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; + sh_idx++) { + for (cu_idx = 0; + cu_idx < adev->gfx.config.max_cu_per_sh; + cu_idx++) { + gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx, + cu_idx); + WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0); + } + } + } + gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h new file mode 100644 index 0000000000000000000000000000000000000000..c143d178ef9803c98ec41b9d08f4e64d8a640443 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h @@ -0,0 +1,40 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFX_V9_4_2_H__ +#define __GFX_V9_4_2_H__ + +void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, + uint32_t first_vmid, uint32_t last_vmid); +void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, + uint32_t die_id); +void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev); + +void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev); +int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if); +void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev); +int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status); +void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev); +void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev); +#endif /* __GFX_V9_4_2_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 6ddd53ba8b777b3c3a272ff01a71c3063743cfe2..d189507dcef0c43eb8b19080592bc9ab4287d7e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -53,19 +53,39 @@ static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) { - uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + uint64_t pt_base; - gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); + if (adev->gmc.pdb0_bo) + pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); + else + pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, - (u32)(adev->gmc.gart_start >> 12)); - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, - (u32)(adev->gmc.gart_start >> 44)); + gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, - (u32)(adev->gmc.gart_end >> 12)); - WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, - (u32)(adev->gmc.gart_end >> 44)); + /* If use GART for FB translation, vmid0 page table covers both + * vram and system memory (gart) + */ + if (adev->gmc.pdb0_bo) { + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.fb_start >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.fb_start >> 44)); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } else { + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } } static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) @@ -116,6 +136,27 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); } + + /* In the case squeezing vram into GART aperture, we don't use + * FB aperture and AGP aperture. Disable them. + */ + if (adev->gmc.pdb0_bo) { + if (adev->asic_type == CHIP_ALDEBARAN) { + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18); + } else { + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); + } + } } static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) @@ -173,8 +214,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + if (adev->gmc.xgmi.connected_to_cpu) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); } @@ -184,7 +230,10 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, + adev->gmc.vmid0_page_table_depth); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, + adev->gmc.vmid0_page_table_block_size); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c index c0ab71df0d90475ead34768ea4b2db0e9a64c7ed..8fca72ebd11cd7d30a5072d0b1e113f210ef7bf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c @@ -28,13 +28,42 @@ #include "soc15_common.h" +#define mmMC_VM_XGMI_LFB_CNTL_ALDE 0x0978 +#define mmMC_VM_XGMI_LFB_CNTL_ALDE_BASE_IDX 0 +#define mmMC_VM_XGMI_LFB_SIZE_ALDE 0x0979 +#define mmMC_VM_XGMI_LFB_SIZE_ALDE_BASE_IDX 0 +//MC_VM_XGMI_LFB_CNTL +#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION__SHIFT 0x0 +#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION__SHIFT 0x4 +#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION_MASK 0x0000000FL +#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION_MASK 0x000000F0L +//MC_VM_XGMI_LFB_SIZE +#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE__SHIFT 0x0 +#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE_MASK 0x0001FFFFL + int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev) { - u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); - u32 max_region = + u32 max_num_physical_nodes; + u32 max_physical_node_id; + u32 xgmi_lfb_cntl; + u32 max_region; + u64 seg_size; + + if (adev->asic_type == CHIP_ALDEBARAN) { + xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); + seg_size = REG_GET_FIELD( + RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), + MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; + } else { + xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); + seg_size = REG_GET_FIELD( + RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), + MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; + } + + max_region = REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); - u32 max_num_physical_nodes = 0; - u32 max_physical_node_id = 0; + switch (adev->asic_type) { case CHIP_VEGA20: @@ -45,23 +74,30 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev) max_num_physical_nodes = 8; max_physical_node_id = 7; break; + case CHIP_ALDEBARAN: + /* just using duplicates for Aldebaran support, revisit later */ + max_num_physical_nodes = 8; + max_physical_node_id = 7; + break; default: return -EINVAL; } /* PF_MAX_REGION=0 means xgmi is disabled */ - if (max_region) { + if (max_region || adev->gmc.xgmi.connected_to_cpu) { adev->gmc.xgmi.num_physical_nodes = max_region + 1; + if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) return -EINVAL; adev->gmc.xgmi.physical_node_id = - REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); + REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, + PF_LFB_REGION); + if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) return -EINVAL; - adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( - RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), - MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; + + adev->gmc.xgmi.node_segment_size = seg_size; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 3b7c6c31fce1f17590a11b4b03b0e59db224e37c..33e54eed2eec40513669654a43e659ce4a032db9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -113,7 +113,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, /* Delegate it to a different ring if the hardware hasn't * already done it. */ - if (in_interrupt()) { + if (entry->ih == &adev->irq.ih) { amdgpu_irq_delegate(adev, entry, 8); return 1; } @@ -152,8 +152,9 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, entry->src_id, entry->ring_id, entry->vmid, entry->pasid, task_info.process_name, task_info.tgid, task_info.task_name, task_info.pid); - dev_err(adev->dev, " in page starting at address 0x%012llx from client %d\n", - addr, entry->client_id); + dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", + addr, entry->client_id, + soc15_ih_clientid_name[entry->client_id]); if (!amdgpu_sriov_vf(adev)) hub->vmhub_funcs->print_l2_protection_fault_status(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index f5b69484c45abf226d81feef1eb26eaab397722f..405d6ad09022ca8a63fbcba78a418481fcdb1c4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -346,6 +346,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; } + adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v6_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index dee2b34effb619811907271bb166bc1ac7896c91..210ada2289ec9cf931991f4f37b448474306ca9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -414,6 +414,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; } + adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v7_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 2d832fc231191bcd39032f6fe27f29cc5f63ac68..c1bd190841f8588680c38a0cc45a2f15b42b62e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -599,6 +599,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; } + adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v8_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 3686e777c76cb232cfbfbafc66680bb1a073db34..468acc06b681fe819f4a8a2e1a137ad2cd4ececb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -50,6 +50,7 @@ #include "athub_v1_0.h" #include "gfxhub_v1_1.h" #include "mmhub_v9_4.h" +#include "mmhub_v1_7.h" #include "umc_v6_1.h" #include "umc_v6_0.h" @@ -279,6 +280,47 @@ static const char *mmhub_client_ids_arcturus[][2] = { [384][1] = "OSS", }; +static const char *mmhub_client_ids_aldebaran[][2] = { + [2][0] = "MP1", + [3][0] = "MP0", + [32+1][0] = "DBGU_IO0", + [32+2][0] = "DBGU_IO2", + [32+4][0] = "MPIO", + [96+11][0] = "JPEG0", + [96+12][0] = "VCN0", + [96+13][0] = "VCNU0", + [128+11][0] = "JPEG1", + [128+12][0] = "VCN1", + [128+13][0] = "VCNU1", + [160+1][0] = "XDP", + [160+14][0] = "HDP", + [256+0][0] = "SDMA0", + [256+1][0] = "SDMA1", + [256+2][0] = "SDMA2", + [256+3][0] = "SDMA3", + [256+4][0] = "SDMA4", + [384+0][0] = "OSS", + [2][1] = "MP1", + [3][1] = "MP0", + [32+1][1] = "DBGU_IO0", + [32+2][1] = "DBGU_IO2", + [32+4][1] = "MPIO", + [96+11][1] = "JPEG0", + [96+12][1] = "VCN0", + [96+13][1] = "VCNU0", + [128+11][1] = "JPEG1", + [128+12][1] = "VCN1", + [128+13][1] = "VCNU1", + [160+1][1] = "XDP", + [160+14][1] = "HDP", + [256+0][1] = "SDMA0", + [256+1][1] = "SDMA1", + [256+2][1] = "SDMA2", + [256+3][1] = "SDMA3", + [256+4][1] = "SDMA4", + [384+0][1] = "OSS", +}; + static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), @@ -484,7 +526,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, /* Delegate it to a different ring if the hardware hasn't * already done it. */ - if (in_interrupt()) { + if (entry->ih == &adev->irq.ih) { amdgpu_irq_delegate(adev, entry, 8); return 1; } @@ -520,8 +562,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, entry->src_id, entry->ring_id, entry->vmid, entry->pasid, task_info.process_name, task_info.tgid, task_info.task_name, task_info.pid); - dev_err(adev->dev, " in page starting at address 0x%012llx from client %d\n", - addr, entry->client_id); + dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", + addr, entry->client_id, + soc15_ih_clientid_name[entry->client_id]); if (amdgpu_sriov_vf(adev)) return 0; @@ -568,6 +611,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, case CHIP_RENOIR: mmhub_cid = mmhub_client_ids_renoir[cid][rw]; break; + case CHIP_ALDEBARAN: + mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; + break; default: mmhub_cid = NULL; break; @@ -642,6 +688,9 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, uint32_t vmhub) { + if (adev->asic_type == CHIP_ALDEBARAN) + return false; + return ((vmhub == AMDGPU_MMHUB_0 || vmhub == AMDGPU_MMHUB_1) && (!amdgpu_sriov_vf(adev)) && @@ -1033,10 +1082,14 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, *flags &= ~AMDGPU_PTE_VALID; } - if (adev->asic_type == CHIP_ARCTURUS && + if ((adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) && !(*flags & AMDGPU_PTE_SYSTEM) && mapping->bo_va->is_xgmi) *flags |= AMDGPU_PTE_SNOOPED; + + if (adev->asic_type == CHIP_ALDEBARAN) + *flags |= mapping->flags & AMDGPU_PTE_SNOOPED; } static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) @@ -1123,6 +1176,9 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) case CHIP_ARCTURUS: adev->mmhub.funcs = &mmhub_v9_4_funcs; break; + case CHIP_ALDEBARAN: + adev->mmhub.funcs = &mmhub_v1_7_funcs; + break; default: adev->mmhub.funcs = &mmhub_v1_0_funcs; break; @@ -1144,6 +1200,16 @@ static int gmc_v9_0_early_init(void *handle) gmc_v9_0_set_mmhub_funcs(adev); gmc_v9_0_set_gfxhub_funcs(adev); + if (adev->asic_type == CHIP_VEGA20 || + adev->asic_type == CHIP_ARCTURUS) + adev->gmc.xgmi.supported = true; + + if (adev->asic_type == CHIP_ALDEBARAN) { + adev->gmc.xgmi.supported = true; + adev->gmc.xgmi.connected_to_cpu = + adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); + } + adev->gmc.shared_aperture_start = 0x2000000000000000ULL; adev->gmc.shared_aperture_end = adev->gmc.shared_aperture_start + (4ULL << 30) - 1; @@ -1194,9 +1260,13 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; - amdgpu_gmc_vram_location(adev, mc, base); - amdgpu_gmc_gart_location(adev, mc); - amdgpu_gmc_agp_location(adev, mc); + if (adev->gmc.xgmi.connected_to_cpu) { + amdgpu_gmc_sysvm_location(adev, mc); + } else { + amdgpu_gmc_vram_location(adev, mc, base); + amdgpu_gmc_gart_location(adev, mc); + amdgpu_gmc_agp_location(adev, mc); + } /* base offset of vram pages */ adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); @@ -1223,7 +1293,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; adev->gmc.real_vram_size = adev->gmc.mc_vram_size; - if (!(adev->flags & AMD_IS_APU)) { + if (!(adev->flags & AMD_IS_APU) && + !adev->gmc.xgmi.connected_to_cpu) { r = amdgpu_device_resize_fb_bar(adev); if (r) return r; @@ -1232,10 +1303,28 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); #ifdef CONFIG_X86_64 - if (adev->flags & AMD_IS_APU) { - adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); + /* + * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi + * interface can use VRAM through here as it appears system reserved + * memory in host address space. + * + * For APUs, VRAM is just the stolen system memory and can be accessed + * directly. + * + * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. + */ + + /* check whether both host-gpu and gpu-gpu xgmi links exist */ + if ((adev->flags & AMD_IS_APU) || + (adev->gmc.xgmi.supported && + adev->gmc.xgmi.connected_to_cpu)) { + adev->gmc.aper_base = + adev->gfxhub.funcs->get_mc_fb_offset(adev) + + adev->gmc.xgmi.physical_node_id * + adev->gmc.xgmi.node_segment_size; adev->gmc.aper_size = adev->gmc.real_vram_size; } + #endif /* In case the PCI BAR is larger than the actual amount of vram */ adev->gmc.visible_vram_size = adev->gmc.aper_size; @@ -1249,6 +1338,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) case CHIP_VEGA12: /* all engines support GPUVM */ case CHIP_VEGA20: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: default: adev->gmc.gart_size = 512ULL << 20; break; @@ -1261,6 +1351,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; } + adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; + gmc_v9_0_vram_gtt_location(adev, &adev->gmc); return 0; @@ -1274,6 +1366,15 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) WARN(1, "VEGA10 PCIE GART already initialized\n"); return 0; } + + if (adev->gmc.xgmi.connected_to_cpu) { + adev->gmc.vmid0_page_table_depth = 1; + adev->gmc.vmid0_page_table_block_size = 12; + } else { + adev->gmc.vmid0_page_table_depth = 0; + adev->gmc.vmid0_page_table_block_size = 0; + } + /* Initialize common gart structure */ r = amdgpu_gart_init(adev); if (r) @@ -1281,7 +1382,16 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) adev->gart.table_size = adev->gart.num_gpu_pages * 8; adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | AMDGPU_PTE_EXECUTABLE; - return amdgpu_gart_table_vram_alloc(adev); + + r = amdgpu_gart_table_vram_alloc(adev); + if (r) + return r; + + if (adev->gmc.xgmi.connected_to_cpu) { + r = amdgpu_gmc_pdb0_alloc(adev); + } + + return r; } /** @@ -1352,6 +1462,7 @@ static int gmc_v9_0_sw_init(void *handle) case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_RENOIR: + case CHIP_ALDEBARAN: adev->num_vmhubs = 2; @@ -1448,7 +1559,8 @@ static int gmc_v9_0_sw_init(void *handle) * for video processing. */ adev->vm_manager.first_kfd_vmid = - adev->asic_type == CHIP_ARCTURUS ? 3 : 8; + (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8; amdgpu_vm_manager_init(adev); @@ -1465,6 +1577,7 @@ static int gmc_v9_0_sw_fini(void *handle) amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); amdgpu_gart_table_vram_free(adev); + amdgpu_bo_unref(&adev->gmc.pdb0_bo); amdgpu_bo_fini(adev); amdgpu_gart_fini(adev); @@ -1525,10 +1638,14 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) { int r; + if (adev->gmc.xgmi.connected_to_cpu) + amdgpu_gmc_init_pdb0(adev); + if (adev->gart.bo == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } + r = amdgpu_gart_table_vram_pin(adev); if (r) return r; @@ -1541,9 +1658,14 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", - (unsigned)(adev->gmc.gart_size >> 20), - (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); + DRM_INFO("PCIE GART of %uM enabled.\n", + (unsigned)(adev->gmc.gart_size >> 20)); + if (adev->gmc.pdb0_bo) + DRM_INFO("PDB0 located at 0x%016llX\n", + (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); + DRM_INFO("PTB located at 0x%016llX\n", + (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); + adev->gart.ready = true; return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index e46621fed5b953952e3ccddbae27fd55aac67fff..edbd35d293ebfe83d766de96f2343ddd7d6fc62e 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -49,6 +49,9 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { + if (adev->asic_type == CHIP_ALDEBARAN) + return; + if (!ring || !ring->funcs->emit_wreg) WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); else diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index c6724a0e0c436cf4870691122bcdab97f2f3f3e2..072774ae16bd48c4fe571b1dd3b6c42ea9016277 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -565,6 +565,26 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { .set_powergating_state = jpeg_v2_5_set_powergating_state, }; +static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { + .name = "jpeg_v2_6", + .early_init = jpeg_v2_5_early_init, + .late_init = NULL, + .sw_init = jpeg_v2_5_sw_init, + .sw_fini = jpeg_v2_5_sw_fini, + .hw_init = jpeg_v2_5_hw_init, + .hw_fini = jpeg_v2_5_hw_fini, + .suspend = jpeg_v2_5_suspend, + .resume = jpeg_v2_5_resume, + .is_idle = jpeg_v2_5_is_idle, + .wait_for_idle = jpeg_v2_5_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = jpeg_v2_5_set_clockgating_state, + .set_powergating_state = jpeg_v2_5_set_powergating_state, +}; + static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, @@ -595,6 +615,36 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, }; +static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_JPEG, + .align_mask = 0xf, + .vmhub = AMDGPU_MMHUB_0, + .get_rptr = jpeg_v2_5_dec_ring_get_rptr, + .get_wptr = jpeg_v2_5_dec_ring_get_wptr, + .set_wptr = jpeg_v2_5_dec_ring_set_wptr, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + + 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ + 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ + 8 + 16, + .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ + .emit_ib = jpeg_v2_0_dec_ring_emit_ib, + .emit_fence = jpeg_v2_0_dec_ring_emit_fence, + .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, + .test_ring = amdgpu_jpeg_dec_ring_test_ring, + .test_ib = amdgpu_jpeg_dec_ring_test_ib, + .insert_nop = jpeg_v2_0_dec_ring_nop, + .insert_start = jpeg_v2_0_dec_ring_insert_start, + .insert_end = jpeg_v2_0_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_jpeg_ring_begin_use, + .end_use = amdgpu_jpeg_ring_end_use, + .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, + .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, +}; + static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) { int i; @@ -602,8 +652,10 @@ static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { if (adev->jpeg.harvest_config & (1 << i)) continue; - - adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; + if (adev->asic_type == CHIP_ARCTURUS) + adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; + else /* CHIP_ALDEBARAN */ + adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs; adev->jpeg.inst[i].ring_dec.me = i; DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); } @@ -635,3 +687,12 @@ const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = .rev = 0, .funcs = &jpeg_v2_5_ip_funcs, }; + +const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_JPEG, + .major = 2, + .minor = 6, + .rev = 0, + .funcs = &jpeg_v2_6_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h index 2b4087c026204a7e877ff61fb6c2ec6376143191..3b0aa29b98796f8320cbef7ce1b7e54a086611c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h @@ -25,5 +25,6 @@ #define __JPEG_V2_5_H__ extern const struct amdgpu_ip_block_version jpeg_v2_5_ip_block; +extern const struct amdgpu_ip_block_version jpeg_v2_6_ip_block; #endif /* __JPEG_V2_5_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c new file mode 100644 index 0000000000000000000000000000000000000000..ae7d8a1738a3628c22ab6d50e948252bdc1f0a18 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c @@ -0,0 +1,1329 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_ras.h" +#include "mmhub_v1_7.h" + +#include "mmhub/mmhub_1_7_offset.h" +#include "mmhub/mmhub_1_7_sh_mask.h" +#include "vega10_enum.h" + +#include "soc15_common.h" +#include "soc15.h" + +#define regVM_L2_CNTL3_DEFAULT 0x80100007 +#define regVM_L2_CNTL4_DEFAULT 0x000000c1 + +static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev) +{ + u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE); + u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP); + + base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; + base <<= 24; + + top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; + top <<= 24; + + adev->gmc.fb_start = base; + adev->gmc.fb_end = top; + adev->gmc.fb_start_original = base; + adev->gmc.fb_end_original = top; + + return base; +} + +static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, + uint64_t page_table_base) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); + + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); +} + +static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t pt_base; + + if (adev->gmc.pdb0_bo) + pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); + else + pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + + mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base); + + /* If use GART for FB translation, vmid0 page table covers both + * vram and system memory (gart) + */ + if (adev->gmc.pdb0_bo) { + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.fb_start >> 12)); + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.fb_start >> 44)); + + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + + } else { + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } +} + +static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t value; + uint32_t tmp; + + /* Program the AGP BAR */ + WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0); + WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, + min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); + + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); + + /* In the case squeezing vram into GART aperture, we don't use + * FB aperture and AGP aperture. Disable them. + */ + if (adev->gmc.pdb0_bo) { + WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF); + WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24); + WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24); + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18); + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18); + } + if (amdgpu_sriov_vf(adev)) + return; + + /* Set default page address. */ + value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page_addr >> 12)); + WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page_addr >> 44)); + + tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); +} + +static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; + + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); + + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); + + WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); +} + +static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; + + if (amdgpu_sriov_vf(adev)) + return; + + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); + /* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); + + tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp); + + tmp = regVM_L2_CNTL3_DEFAULT; + if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp); + + tmp = regVM_L2_CNTL4_DEFAULT; + if (adev->gmc.xgmi.connected_to_cpu) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp); +} + +static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev) +{ + uint32_t tmp; + + tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, + adev->gmc.vmid0_page_table_depth); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, + adev->gmc.vmid0_page_table_block_size); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp); +} + +static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev) +{ + if (amdgpu_sriov_vf(adev)) + return; + + WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0XFFFFFFFF); + WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x0000000F); + + WREG32_SOC15(MMHUB, 0, + regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(MMHUB, 0, + regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); + + WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, + 0); + WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, + 0); +} + +static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + unsigned num_level, block_size; + uint32_t tmp; + int i; + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; + if (adev->gmc.translate_further) + num_level -= 1; + else + block_size -= 9; + + for (i = 0; i <= 14; i++) { + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, + num_level); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, + 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, + block_size); + /* Send no-retry XNACK on fault to suppress VM fault storm. */ + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !adev->gmc.noretry); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, + i * hub->ctx_distance, tmp); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, + i * hub->ctx_addr_distance, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, + i * hub->ctx_addr_distance, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } +} + +static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + unsigned i; + + for (i = 0; i < 18; ++i) { + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + i * hub->eng_addr_distance, 0xffffffff); + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + i * hub->eng_addr_distance, 0x1f); + } +} + +static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev) +{ + if (amdgpu_sriov_vf(adev)) { + /* + * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are + * VF copy registers so vbios post doesn't program them, for + * SRIOV driver need to program them + */ + WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, + adev->gmc.vram_start >> 24); + WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, + adev->gmc.vram_end >> 24); + } + + /* GART Enable. */ + mmhub_v1_7_init_gart_aperture_regs(adev); + mmhub_v1_7_init_system_aperture_regs(adev); + mmhub_v1_7_init_tlb_regs(adev); + mmhub_v1_7_init_cache_regs(adev); + + mmhub_v1_7_enable_system_domain(adev); + mmhub_v1_7_disable_identity_aperture(adev); + mmhub_v1_7_setup_vmid_config(adev); + mmhub_v1_7_program_invalidation(adev); + + return 0; +} + +static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + u32 tmp; + u32 i; + + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL, + i * hub->ctx_distance, 0); + + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 0); + WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); + + if (!amdgpu_sriov_vf(adev)) { + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); + WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0); + } +} + +/** + * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value) +{ + u32 tmp; + + if (amdgpu_sriov_vf(adev)) + return; + + tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + VM_L2_PROTECTION_FAULT_CNTL, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + if (!value) { + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_NO_RETRY_FAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_RETRY_FAULT, 1); + } + + WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp); +} + +static void mmhub_v1_7_init(struct amdgpu_device *adev) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, 0, + regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(MMHUB, 0, + regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL); + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); + + hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL; + hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - + regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; + hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ; + hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - + regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + +} + +static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data, def1, data1, def2 = 0, data2 = 0; + + def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); + + def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); + def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); + + if (enable) { + data |= ATC_L2_MISC_CG__ENABLE_MASK; + + data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + + data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + } else { + data &= ~ATC_L2_MISC_CG__ENABLE_MASK; + + data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + + data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + } + + if (def != data) + WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); + + if (def1 != data1) + WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1); + + if (def2 != data2) + WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); +} + +static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); + + if (enable) + data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + else + data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + + if (def != data) + WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); +} + +static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev, + enum amd_clockgating_state state) +{ + if (amdgpu_sriov_vf(adev)) + return 0; + + /* Change state only if MCCG support is enabled through driver */ + if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) + mmhub_v1_7_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE); + + /* Change state only if LS support is enabled through driver */ + if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) + mmhub_v1_7_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE); + + return 0; +} + +static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags) +{ + int data, data1; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); + + data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); + + /* AMD_CG_SUPPORT_MC_MGCG */ + if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && + !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) + *flags |= AMD_CG_SUPPORT_MC_MGCG; + + /* AMD_CG_SUPPORT_MC_LS */ + if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_MC_LS; +} + +static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = { + /* MMHUB Range 0 */ + { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, + + /* MMHUB Range 1 */ + { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, + + /* MMHAB Range 2*/ + { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, + + /* MMHUB Rang 3 */ + { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, + + /* MMHUB Range 4 */ + { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, + + /* MMHUAB Range 5 */ + { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), + }, + { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), + }, + { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), + }, + { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT), + }, + { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT), + }, + { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT), + }, + { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), + }, + { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), + }, + { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), + }, + { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), + 0, 0, + }, + { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT), + }, + { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT), + }, + { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT), + }, + { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT), + SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT), + }, + { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), + }, + { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), + }, + { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT), + }, + { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), + }, + { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), + }, + { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), + 0, 0, + SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), + }, +}; + +static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = { + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 }, +}; + +static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev, + const struct soc15_reg_entry *reg, + uint32_t value, + uint32_t *sec_count, + uint32_t *ded_count) +{ + uint32_t i; + uint32_t sec_cnt, ded_cnt; + + for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) { + if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset) + continue; + + sec_cnt = (value & + mmhub_v1_7_ras_fields[i].sec_count_mask) >> + mmhub_v1_7_ras_fields[i].sec_count_shift; + if (sec_cnt) { + dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n", + mmhub_v1_7_ras_fields[i].name, + sec_cnt); + *sec_count += sec_cnt; + } + + ded_cnt = (value & + mmhub_v1_7_ras_fields[i].ded_count_mask) >> + mmhub_v1_7_ras_fields[i].ded_count_shift; + if (ded_cnt) { + dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n", + mmhub_v1_7_ras_fields[i].name, + ded_cnt); + *ded_count += ded_cnt; + } + } + + return 0; +} + +static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) +{ + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + uint32_t sec_count = 0, ded_count = 0; + uint32_t i; + uint32_t reg_value; + + err_data->ue_count = 0; + err_data->ce_count = 0; + + for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) { + reg_value = + RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); + if (reg_value) + mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i], + reg_value, &sec_count, &ded_count); + } + + err_data->ce_count += sec_count; + err_data->ue_count += ded_count; +} + +static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev) +{ + uint32_t i; + + /* write 0 to reset the edc counters */ + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) { + for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) + WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); + } +} + +static const struct soc15_reg_entry mmhub_v1_7_err_status_regs[] = { + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 }, + { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 }, +}; + +static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev) +{ + int i; + uint32_t reg_value; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) + return; + + for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_err_status_regs); i++) { + reg_value = + RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_err_status_regs[i])); + if (reg_value) + dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n", + i, reg_value); + } +} + +const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = { + .ras_late_init = amdgpu_mmhub_ras_late_init, + .query_ras_error_count = mmhub_v1_7_query_ras_error_count, + .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count, + .get_fb_location = mmhub_v1_7_get_fb_location, + .init = mmhub_v1_7_init, + .gart_enable = mmhub_v1_7_gart_enable, + .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default, + .gart_disable = mmhub_v1_7_gart_disable, + .set_clockgating = mmhub_v1_7_set_clockgating, + .get_clockgating = mmhub_v1_7_get_clockgating, + .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs, + .query_ras_error_status = mmhub_v1_7_query_ras_error_status, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.h new file mode 100644 index 0000000000000000000000000000000000000000..bf2fbeb172d164f82f2854a8339a6e4280483e3c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.h @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __MMHUB_V1_7_H__ +#define __MMHUB_V1_7_H__ + +extern const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index 4bc1d1434065f097db3523f6a47767e120206cc2..c477f8972d5dfe2ea36e06945db1bde6d77a3460 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -52,6 +52,20 @@ #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L + +#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 +#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 +//BIF_MMSCH1_DOORBELL_ALDE_RANGE +#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 +#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 +#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL +#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L + +#define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 +#define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 + static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status); @@ -65,7 +79,12 @@ static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) { - u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); + u32 tmp; + + if (adev->asic_type == CHIP_ALDEBARAN) + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); + else + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; @@ -92,10 +111,10 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan { u32 reg, doorbell_range; - if (instance < 2) + if (instance < 2) { reg = instance + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); - else + } else { /* * These registers address of SDMA2~7 is not consecutive * from SDMA0~1. Need plus 4 dwords offset. @@ -103,9 +122,19 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 ++ * BIF_SDMA4_DOORBELL_RANGE: ++ * ARCTURUS: 0x3be0 ++ * ALDEBARAN: 0x3be4 */ - reg = instance + 0x4 + - SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); + if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) + reg = instance + 0x4 + 0x1 + + SOC15_REG_OFFSET(NBIO, 0, + mmBIF_SDMA0_DOORBELL_RANGE); + else + reg = instance + 0x4 + + SOC15_REG_OFFSET(NBIO, 0, + mmBIF_SDMA0_DOORBELL_RANGE); + } doorbell_range = RREG32(reg); @@ -124,9 +153,12 @@ static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do u32 reg; u32 doorbell_range; - if (instance) - reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); - else + if (instance) { + if (adev->asic_type == CHIP_ALDEBARAN) + reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); + else + reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); + } else reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); doorbell_range = RREG32(reg); diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index c625c5d8ed89052b002e8fb0b79f42d063c20d27..5846eac292c3f515ac748ec8be4c74f40a6397e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -25,6 +25,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -65,6 +67,184 @@ static const struct amd_ip_funcs nv_common_ip_funcs; +/* Navi */ +static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs nv_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), + .codec_array = nv_video_codecs_encode_array, +}; + +/* Navi1x */ +static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs nv_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), + .codec_array = nv_video_codecs_decode_array, +}; + +/* Sienna Cichlid */ +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs sc_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), + .codec_array = sc_video_codecs_decode_array, +}; + +static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (adev->asic_type) { + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: + case CHIP_VANGOGH: + if (encode) + *codecs = &nv_video_codecs_encode; + else + *codecs = &sc_video_codecs_decode; + return 0; + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_NAVI12: + if (encode) + *codecs = &nv_video_codecs_encode; + else + *codecs = &nv_video_codecs_decode; + return 0; + default: + return -EINVAL; + } +} + /* * Indirect registers accessor */ @@ -304,44 +484,6 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } -static int nv_asic_mode1_reset(struct amdgpu_device *adev) -{ - u32 i; - int ret = 0; - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - /* disable BM */ - pci_clear_master(adev->pdev); - - amdgpu_device_cache_pci_state(adev->pdev); - - if (amdgpu_dpm_is_mode1_reset_supported(adev)) { - dev_info(adev->dev, "GPU smu mode1 reset\n"); - ret = amdgpu_dpm_mode1_reset(adev); - } else { - dev_info(adev->dev, "GPU psp mode1 reset\n"); - ret = psp_gpu_reset(adev); - } - - if (ret) - dev_err(adev->dev, "GPU mode1 reset failed\n"); - amdgpu_device_load_pci_state(adev->pdev); - - /* wait for asic to come out of reset */ - for (i = 0; i < adev->usec_timeout; i++) { - u32 memsize = adev->nbio.funcs->get_memsize(adev); - - if (memsize != 0xffffffff) - break; - udelay(1); - } - - amdgpu_atombios_scratch_regs_engine_hung(adev, false); - - return ret; -} - static int nv_asic_mode2_reset(struct amdgpu_device *adev) { u32 i; @@ -444,7 +586,7 @@ static int nv_asic_reset(struct amdgpu_device *adev) break; default: dev_info(adev->dev, "MODE1 reset\n"); - ret = nv_asic_mode1_reset(adev); + ret = amdgpu_device_mode1_reset(adev); break; } @@ -847,6 +989,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = .supports_baco = &nv_asic_supports_baco, .pre_asic_init = &nv_pre_asic_init, .update_umd_stable_pstate = &nv_update_umd_stable_pstate, + .query_video_codecs = &nv_query_video_codecs, }; static int nv_common_early_init(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 3ba7bdfde65d81f8f0c91c88b93f1ce15d33cd47..a41b054fe0ba16b9f10faea3300b966c26d46e35 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -235,6 +235,7 @@ enum psp_gfx_fw_type { GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */ + GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */ GFX_FW_TYPE_MAX }; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c new file mode 100644 index 0000000000000000000000000000000000000000..fcdce46445d60160d2d7ac9483353df5f41581f6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -0,0 +1,378 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v13_0.h" + +#include "mp/mp_13_0_2_offset.h" +#include "mp/mp_13_0_2_sh_mask.h" + +MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); + +static int psp_v13_0_init_microcode(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + const char *chip_name; + int err = 0; + + switch (adev->asic_type) { + case CHIP_ALDEBARAN: + chip_name = "aldebaran"; + break; + default: + BUG(); + } + + err = psp_init_sos_microcode(psp, chip_name); + if (err) + return err; + + err = psp_init_ta_microcode(&adev->psp, chip_name); + + return err; +} + +static bool psp_v13_0_is_sos_alive(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + uint32_t sol_reg; + + sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); + + return sol_reg != 0x0; +} + +static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + + int ret; + int retry_loop; + + for (retry_loop = 0; retry_loop < 10; retry_loop++) { + /* Wait for bootloader to signify that is + ready having bit 31 of C2PMSG_35 set to 1 */ + ret = psp_wait_for(psp, + SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), + 0x80000000, + 0x80000000, + false); + + if (ret == 0) + return 0; + } + + return ret; +} + +static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) +{ + int ret; + uint32_t psp_gfxdrv_command_reg = 0; + struct amdgpu_device *adev = psp->adev; + + /* Check tOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + if (psp_v13_0_is_sos_alive(psp)) + return 0; + + ret = psp_v13_0_wait_for_bootloader(psp); + if (ret) + return ret; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + + /* Copy PSP KDB binary to memory */ + memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); + + /* Provide the PSP KDB to bootloader */ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, + (uint32_t)(psp->fw_pri_mc_addr >> 20)); + psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, + psp_gfxdrv_command_reg); + + ret = psp_v13_0_wait_for_bootloader(psp); + + return ret; +} + +static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) +{ + int ret; + uint32_t psp_gfxdrv_command_reg = 0; + struct amdgpu_device *adev = psp->adev; + + /* Check sOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + if (psp_v13_0_is_sos_alive(psp)) + return 0; + + ret = psp_v13_0_wait_for_bootloader(psp); + if (ret) + return ret; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + + /* Copy PSP System Driver binary to memory */ + memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); + + /* Provide the sys driver to bootloader */ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, + (uint32_t)(psp->fw_pri_mc_addr >> 20)); + psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, + psp_gfxdrv_command_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + ret = psp_v13_0_wait_for_bootloader(psp); + + return ret; +} + +static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) +{ + int ret; + unsigned int psp_gfxdrv_command_reg = 0; + struct amdgpu_device *adev = psp->adev; + + /* Check sOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + if (psp_v13_0_is_sos_alive(psp)) + return 0; + + ret = psp_v13_0_wait_for_bootloader(psp); + if (ret) + return ret; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + + /* Copy Secure OS binary to PSP memory */ + memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); + + /* Provide the PSP secure OS to bootloader */ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, + (uint32_t)(psp->fw_pri_mc_addr >> 20)); + psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, + psp_gfxdrv_command_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), + RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), + 0, true); + + return ret; +} + +static int psp_v13_0_ring_init(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring; + struct amdgpu_device *adev = psp->adev; + + ring = &psp->km_ring; + + ring->ring_type = ring_type; + + /* allocate 4k Page of Local Frame Buffer memory for ring */ + ring->ring_size = 0x1000; + ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + if (ret) { + ring->ring_size = 0; + return ret; + } + + return 0; +} + +static int psp_v13_0_ring_stop(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), + 0x80000000, 0x80000000, false); + } else { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, + GFX_CTRL_CMD_ID_DESTROY_RINGS); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), + 0x80000000, 0x80000000, false); + } + + return ret; +} + +static int psp_v13_0_ring_create(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + unsigned int psp_ring_reg = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + ret = psp_v13_0_ring_stop(psp, ring_type); + if (ret) { + DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_102 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); + /* Write high address of the ring to C2PMSG_103 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); + + /* Write the ring initialization command to C2PMSG_101 */ + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_INIT_GPCOM_RING); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_101 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), + 0x80000000, 0x8000FFFF, false); + + } else { + /* Wait for sOS ready for ring creation */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), + 0x80000000, 0x80000000, false); + if (ret) { + DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_69 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); + /* Write high address of the ring to C2PMSG_70 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); + /* Write size of ring to C2PMSG_71 */ + psp_ring_reg = ring->ring_size; + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); + /* Write the ring initialization command to C2PMSG_64 */ + psp_ring_reg = ring_type; + psp_ring_reg = psp_ring_reg << 16; + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_64 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), + 0x80000000, 0x8000FFFF, false); + } + + return ret; +} + +static int psp_v13_0_ring_destroy(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + ret = psp_v13_0_ring_stop(psp, ring_type); + if (ret) + DRM_ERROR("Fail to stop psp ring\n"); + + amdgpu_bo_free_kernel(&adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + + return ret; +} + +static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) +{ + uint32_t data; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) + data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); + else + data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); + + return data; +} + +static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_CONSUME_CMD); + } else + WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); +} + +static const struct psp_funcs psp_v13_0_funcs = { + .init_microcode = psp_v13_0_init_microcode, + .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, + .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, + .bootloader_load_sos = psp_v13_0_bootloader_load_sos, + .ring_init = psp_v13_0_ring_init, + .ring_create = psp_v13_0_ring_create, + .ring_stop = psp_v13_0_ring_stop, + .ring_destroy = psp_v13_0_ring_destroy, + .ring_get_wptr = psp_v13_0_ring_get_wptr, + .ring_set_wptr = psp_v13_0_ring_set_wptr, +}; + +void psp_v13_0_set_psp_funcs(struct psp_context *psp) +{ + psp->funcs = &psp_v13_0_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.h new file mode 100644 index 0000000000000000000000000000000000000000..b2414a729ca17890765a5d4fb0a307dc980f24da --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __PSP_V13_0_H__ +#define __PSP_V13_0_H__ + +#include "amdgpu_psp.h" + +void psp_v13_0_set_psp_funcs(struct psp_context *psp); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index c8c22c1d1e65546613a433a8f0853d0da6c6c455..98b7db516438931656236f29db54fa893804e2e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -56,6 +56,7 @@ #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" #include "amdgpu_ras.h" +#include "sdma_v4_4.h" MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); @@ -69,6 +70,7 @@ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L @@ -259,6 +261,24 @@ static const struct soc15_reg_golden golden_settings_sdma_arct[] = SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) }; +static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), + SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), + SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), + SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), + SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), @@ -482,6 +502,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_sdma_arct, ARRAY_SIZE(golden_settings_sdma_arct)); break; + case CHIP_ALDEBARAN: + soc15_program_register_sequence(adev, + golden_settings_sdma_aldebaran, + ARRAY_SIZE(golden_settings_sdma_aldebaran)); + break; case CHIP_RAVEN: soc15_program_register_sequence(adev, golden_settings_sdma_4_1, @@ -564,7 +589,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) /* arcturus shares the same FW memory across all SDMA isntances */ - if (adev->asic_type == CHIP_ARCTURUS) + if (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) break; } @@ -621,6 +647,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) else chip_name = "green_sardine"; break; + case CHIP_ALDEBARAN: + chip_name = "aldebaran"; + break; default: BUG(); } @@ -636,8 +665,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) goto out; for (i = 1; i < adev->sdma.num_instances; i++) { - if (adev->asic_type == CHIP_ARCTURUS) { - /* Acturus will leverage the same FW memory + if (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) { + /* Acturus & Aldebaran will leverage the same FW memory for every SDMA instance */ memcpy((void *)&adev->sdma.instance[i], (void *)&adev->sdma.instance[0], @@ -1825,6 +1855,8 @@ static int sdma_v4_0_early_init(void *handle) adev->sdma.num_instances = 1; else if (adev->asic_type == CHIP_ARCTURUS) adev->sdma.num_instances = 8; + else if (adev->asic_type == CHIP_ALDEBARAN) + adev->sdma.num_instances = 5; else adev->sdma.num_instances = 2; @@ -1895,6 +1927,33 @@ static int sdma_v4_0_sw_init(void *handle) return r; } + /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ + for (i = 0; i < adev->sdma.num_instances; i++) { + r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), + SDMA0_4_0__SRCID__SDMA_VM_HOLE, + &adev->sdma.vm_hole_irq); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), + SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, + &adev->sdma.doorbell_invalid_irq); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), + SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, + &adev->sdma.pool_timeout_irq); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), + SDMA0_4_0__SRCID__SDMA_SRBMWRITE, + &adev->sdma.srbm_write_irq); + if (r) + return r; + } + for (i = 0; i < adev->sdma.num_instances; i++) { ring = &adev->sdma.instance[i].ring; ring->ring_obj = NULL; @@ -2149,6 +2208,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, return 0; } +static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + int instance; + struct amdgpu_task_info task_info; + u64 addr; + + instance = sdma_v4_0_irq_id_to_seq(entry->client_id); + if (instance < 0 || instance >= adev->sdma.num_instances) { + dev_err(adev->dev, "sdma instance invalid %d\n", instance); + return -EINVAL; + } + + addr = (u64)entry->src_data[0] << 12; + addr |= ((u64)entry->src_data[1] & 0xf) << 44; + + memset(&task_info, 0, sizeof(struct amdgpu_task_info)); + amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); + + dev_info(adev->dev, + "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " + "pasid:%u, for process %s pid %d thread %s pid %d\n", + instance, addr, entry->src_id, entry->ring_id, entry->vmid, + entry->pasid, task_info.process_name, task_info.tgid, + task_info.task_name, task_info.pid); + return 0; +} + +static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + dev_err(adev->dev, "MC or SEM address in VM hole\n"); + sdma_v4_0_print_iv_entry(adev, entry); + return 0; +} + +static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); + sdma_v4_0_print_iv_entry(adev, entry); + return 0; +} + +static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + dev_err(adev->dev, + "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); + sdma_v4_0_print_iv_entry(adev, entry); + return 0; +} + +static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + dev_err(adev->dev, + "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); + sdma_v4_0_print_iv_entry(adev, entry); + return 0; +} + static void sdma_v4_0_update_medium_grain_clock_gating( struct amdgpu_device *adev, bool enable) @@ -2222,21 +2347,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle, if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->asic_type) { - case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_RAVEN: - case CHIP_ARCTURUS: - case CHIP_RENOIR: - sdma_v4_0_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE); - sdma_v4_0_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE); - break; - default: - break; - } + sdma_v4_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE); + sdma_v4_0_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE); return 0; } @@ -2249,7 +2363,7 @@ static int sdma_v4_0_set_powergating_state(void *handle, case CHIP_RAVEN: case CHIP_RENOIR: sdma_v4_1_update_power_gating(adev, - state == AMD_PG_STATE_GATE ? true : false); + state == AMD_PG_STATE_GATE); break; default: break; @@ -2465,7 +2579,21 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { .process = amdgpu_sdma_process_ecc_irq, }; +static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { + .process = sdma_v4_0_process_vm_hole_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { + .process = sdma_v4_0_process_doorbell_invalid_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { + .process = sdma_v4_0_process_pool_timeout_irq, +}; +static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { + .process = sdma_v4_0_process_srbm_write_irq, +}; static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) { @@ -2474,9 +2602,17 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; break; + case 5: + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; + adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; + break; case 8: adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; + adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST; break; case 2: default: @@ -2487,6 +2623,10 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; + adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; + adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; + adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; + adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; } /** @@ -2655,6 +2795,9 @@ static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) case CHIP_ARCTURUS: adev->sdma.funcs = &sdma_v4_0_ras_funcs; break; + case CHIP_ALDEBARAN: + adev->sdma.funcs = &sdma_v4_4_ras_funcs; + break; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c new file mode 100644 index 0000000000000000000000000000000000000000..6fcb95c89999313dc7b90a0b54f3281370eed137 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c @@ -0,0 +1,232 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "sdma/sdma_4_4_0_offset.h" +#include "sdma/sdma_4_4_0_sh_mask.h" +#include "soc15.h" +#include "amdgpu_ras.h" + +#define SDMA1_REG_OFFSET 0x600 +#define SDMA2_REG_OFFSET 0x1cda0 +#define SDMA3_REG_OFFSET 0x1d1a0 +#define SDMA4_REG_OFFSET 0x1d5a0 + +/* helper function that allow only use sdma0 register offset + * to calculate register offset for all the sdma instances */ +static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev, + uint32_t instance, + uint32_t offset) +{ + uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; + + switch (instance) { + case 0: + return (sdma_base + offset); + case 1: + return (sdma_base + SDMA1_REG_OFFSET + offset); + case 2: + return (sdma_base + SDMA2_REG_OFFSET + offset); + case 3: + return (sdma_base + SDMA3_REG_OFFSET + offset); + case 4: + return (sdma_base + SDMA4_REG_OFFSET + offset); + default: + break; + } + return 0; +} + +static const struct soc15_ras_field_entry sdma_v4_4_ras_fields[] = { + { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), + 0, 0, + }, + { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), + 0, 0, + }, + { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UCODE_BUF_SED), + 0, 0, + }, + { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_RB_CMD_BUF_SED), + 0, 0, + }, + { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_IB_CMD_BUF_SED), + 0, 0, + }, + { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UTCL1_RD_FIFO_SED), + 0, 0, + }, + { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_UTCL1_RDBST_FIFO_SED), + 0, 0, + }, + { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_DATA_LUT_FIFO_SED), + 0, 0, + }, + { "SDMA_SPLIT_DATA_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_SPLIT_DATA_BUF_SED), + 0, 0, + }, + { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_MC_WR_ADDR_FIFO_SED), + 0, 0, + }, + { "SDMA_MC_RDRET_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2), + SOC15_REG_FIELD(SDMA0_EDC_COUNTER2, SDMA_MC_WR_ADDR_FIFO_SED), + 0, 0, + }, +}; + +static void sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev, + uint32_t value, + uint32_t instance, + uint32_t *sec_count) +{ + uint32_t i; + uint32_t sec_cnt; + + /* double bits error (multiple bits) error detection is not supported */ + for (i = 0; i < ARRAY_SIZE(sdma_v4_4_ras_fields); i++) { + /* the SDMA_EDC_COUNTER register in each sdma instance + * shares the same sed shift_mask + * */ + sec_cnt = (value & + sdma_v4_4_ras_fields[i].sec_count_mask) >> + sdma_v4_4_ras_fields[i].sec_count_shift; + if (sec_cnt) { + dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n", + sdma_v4_4_ras_fields[i].name, + instance, sec_cnt); + *sec_count += sec_cnt; + } + } +} + +static int sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev, + uint32_t instance, + void *ras_error_status) +{ + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + uint32_t sec_count = 0; + uint32_t reg_value = 0; + uint32_t reg_offset = 0; + + reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER); + reg_value = RREG32(reg_offset); + /* double bit error is not supported */ + if (reg_value) + sdma_v4_4_get_ras_error_count(adev, reg_value, instance, &sec_count); + /* err_data->ce_count should be initialized to 0 + * before calling into this function */ + err_data->ce_count += sec_count; + /* double bit error is not supported + * set ue count to 0 */ + err_data->ue_count = 0; + + return 0; +}; + +static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev) +{ + int i; + uint32_t reg_offset; + + /* write 0 to EDC_COUNTER reg to clear sdma edc counters */ + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { + for (i = 0; i < adev->sdma.num_instances; i++) { + reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER); + WREG32(reg_offset, 0); + reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2); + WREG32(reg_offset, 0); + } + } +} + +const struct amdgpu_sdma_ras_funcs sdma_v4_4_ras_funcs = { + .ras_late_init = amdgpu_sdma_ras_late_init, + .ras_fini = amdgpu_sdma_ras_fini, + .query_ras_error_count = sdma_v4_4_query_ras_error_count, + .reset_ras_error_count = sdma_v4_4_reset_ras_error_count, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.h new file mode 100644 index 0000000000000000000000000000000000000000..74a6e5b5e949ae997203768474989475a78e53c3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SDMA_V4_4_H__ +#define __SDMA_V4_4_H__ + +extern const struct amdgpu_sdma_ras_funcs sdma_v4_4_ras_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 690a5090475a57d93e57eca61f181899dd9a1966..b39e7db0e299ef3954cd0fa9aacf2e3d65558729 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1595,9 +1595,9 @@ static int sdma_v5_2_set_clockgating_state(void *handle, case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: sdma_v5_2_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); sdma_v5_2_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 6b5cf7882a12d03aa133ec30a5c1b0177162c6e1..7cbc2bb03bc63596d07cab21e5d4ba3f522abb7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -26,6 +26,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -905,6 +907,114 @@ static const u32 hainan_mgcg_cgcg_init[] = 0x3630, 0xfffffff0, 0x00000100, }; +/* XXX: update when we support VCE */ +#if 0 +/* tahiti, pitcarin, verde */ +static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs tahiti_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array), + .codec_array = tahiti_video_codecs_encode_array, +}; +#else +static const struct amdgpu_video_codecs tahiti_video_codecs_encode = +{ + .codec_count = 0, + .codec_array = NULL, +}; +#endif +/* oland and hainan don't support encode */ +static const struct amdgpu_video_codecs hainan_video_codecs_encode = +{ + .codec_count = 0, + .codec_array = NULL, +}; + +/* tahiti, pitcarin, verde, oland */ +static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 41, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 2048, + .max_height = 1152, + .max_pixels_per_frame = 2048 * 1152, + .max_level = 4, + }, +}; + +static const struct amdgpu_video_codecs tahiti_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array), + .codec_array = tahiti_video_codecs_decode_array, +}; + +/* hainan doesn't support decode */ +static const struct amdgpu_video_codecs hainan_video_codecs_decode = +{ + .codec_count = 0, + .codec_array = NULL, +}; + +static int si_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (adev->asic_type) { + case CHIP_VERDE: + case CHIP_TAHITI: + case CHIP_PITCAIRN: + if (encode) + *codecs = &tahiti_video_codecs_encode; + else + *codecs = &tahiti_video_codecs_decode; + return 0; + case CHIP_OLAND: + if (encode) + *codecs = &hainan_video_codecs_encode; + else + *codecs = &tahiti_video_codecs_decode; + return 0; + case CHIP_HAINAN: + if (encode) + *codecs = &hainan_video_codecs_encode; + else + *codecs = &hainan_video_codecs_decode; + return 0; + default: + return -EINVAL; + } +} + static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) { unsigned long flags; @@ -1903,6 +2013,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs = .get_pcie_replay_count = &si_get_pcie_replay_count, .supports_baco = &si_asic_supports_baco, .pre_asic_init = &si_pre_asic_init, + .query_video_codecs = &si_query_video_codecs, }; static uint32_t si_get_rev_id(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c new file mode 100644 index 0000000000000000000000000000000000000000..079b094c48ad7fdd0a173c30a80b1d0b65f2234f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c @@ -0,0 +1,121 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "smuio_v13_0.h" +#include "smuio/smuio_13_0_2_offset.h" +#include "smuio/smuio_13_0_2_sh_mask.h" + +#define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK 0x00000001L + +static u32 smuio_v13_0_get_rom_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX); +} + +static u32 smuio_v13_0_get_rom_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA); +} + +static void smuio_v13_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable) +{ + u32 def, data; + + /* enable/disable ROM CG is not supported on APU */ + if (adev->flags & AMD_IS_APU) + return; + + def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) + data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); + else + data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; + + if (def != data) + WREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0, data); +} + +static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) +{ + u32 data; + + /* CGTT_ROM_CLK_CTRL0 is not available for APU */ + if (adev->flags & AMD_IS_APU) + return; + + data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) + *flags |= AMD_CG_SUPPORT_ROM_MGCG; +} + +/** + * smuio_v13_0_get_die_id - query die id from FCH. + * + * @adev: amdgpu device pointer + * + * Returns die id + */ +static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev) +{ + u32 data, die_id; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); + + return die_id; +} + +/** + * smuio_v13_0_supports_host_gpu_xgmi - detect xgmi interface between cpu and gpu/s. + * + * @adev: amdgpu device pointer + * + * Returns true on success or false otherwise. + */ +static bool smuio_v13_0_is_host_gpu_xgmi_supported(struct amdgpu_device *adev) +{ + u32 data; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); + /* data[4:0] + * bit 0 == 0 host-gpu interface is PCIE + * bit 0 == 1 host-gpu interface is Alternate Protocal + * for AMD, this is XGMI + */ + data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK; + + return data ? true : false; +} + +const struct amdgpu_smuio_funcs smuio_v13_0_funcs = { + .get_rom_index_offset = smuio_v13_0_get_rom_index_offset, + .get_rom_data_offset = smuio_v13_0_get_rom_data_offset, + .get_die_id = smuio_v13_0_get_die_id, + .is_host_gpu_xgmi_supported = smuio_v13_0_is_host_gpu_xgmi_supported, + .update_rom_clock_gating = smuio_v13_0_update_rom_clock_gating, + .get_clock_gating_state = smuio_v13_0_get_clock_gating_state, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.h b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.h new file mode 100644 index 0000000000000000000000000000000000000000..a3bfe3e4fb46827276c4549f9276c36f7649fbe0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMUIO_V13_0_H__ +#define __SMUIO_V13_0_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_smuio_funcs smuio_v13_0_funcs; + +#endif /* __SMUIO_V13_0_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 1221aa6b40a9f53d8b7c18d88727ad9815cebfd8..3808402cd964ec2a3a1bdd090c54cbb29a29dea3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -25,6 +25,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -71,6 +73,7 @@ #include "jpeg_v2_5.h" #include "smuio_v9_0.h" #include "smuio_v11_0.h" +#include "smuio_v13_0.h" #include "dce_virtual.h" #include "mxgpu_ai.h" #include "amdgpu_smu.h" @@ -83,6 +86,234 @@ #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 +/* Vega, Raven, Arcturus */ +static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs vega_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), + .codec_array = vega_video_codecs_encode_array, +}; + +/* Vega */ +static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs vega_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), + .codec_array = vega_video_codecs_decode_array, +}; + +/* Raven */ +static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs rv_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), + .codec_array = rv_video_codecs_decode_array, +}; + +/* Renoir, Arcturus */ +static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs rn_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), + .codec_array = rn_video_codecs_decode_array, +}; + +static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (adev->asic_type) { + case CHIP_VEGA20: + case CHIP_VEGA10: + case CHIP_VEGA12: + if (encode) + *codecs = &vega_video_codecs_encode; + else + *codecs = &vega_video_codecs_decode; + return 0; + case CHIP_RAVEN: + if (encode) + *codecs = &vega_video_codecs_encode; + else + *codecs = &rv_video_codecs_decode; + return 0; + case CHIP_ARCTURUS: + case CHIP_RENOIR: + if (encode) + *codecs = &vega_video_codecs_encode; + else + *codecs = &rn_video_codecs_decode; + return 0; + default: + return -EINVAL; + } +} + /* * Indirect registers accessor */ @@ -419,40 +650,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, } -static int soc15_asic_mode1_reset(struct amdgpu_device *adev) -{ - u32 i; - int ret = 0; - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - dev_info(adev->dev, "GPU mode1 reset\n"); - - /* disable BM */ - pci_clear_master(adev->pdev); - - amdgpu_device_cache_pci_state(adev->pdev); - - ret = psp_gpu_reset(adev); - if (ret) - dev_err(adev->dev, "GPU mode1 reset failed\n"); - - amdgpu_device_load_pci_state(adev->pdev); - - /* wait for asic to come out of reset */ - for (i = 0; i < adev->usec_timeout; i++) { - u32 memsize = adev->nbio.funcs->get_memsize(adev); - - if (memsize != 0xffffffff) - break; - udelay(1); - } - - amdgpu_atombios_scratch_regs_engine_hung(adev, false); - - return ret; -} - static int soc15_asic_baco_reset(struct amdgpu_device *adev) { struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); @@ -477,13 +674,21 @@ static enum amd_reset_method soc15_asic_reset_method(struct amdgpu_device *adev) { bool baco_reset = false; + bool connected_to_cpu = false; struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) + connected_to_cpu = true; + if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || amdgpu_reset_method == AMD_RESET_METHOD_BACO || - amdgpu_reset_method == AMD_RESET_METHOD_PCI) - return amdgpu_reset_method; + amdgpu_reset_method == AMD_RESET_METHOD_PCI) { + /* If connected to cpu, driver only support mode2 */ + if (connected_to_cpu) + return AMD_RESET_METHOD_MODE2; + return amdgpu_reset_method; + } if (amdgpu_reset_method != -1) dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", @@ -509,6 +714,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev) if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) baco_reset = false; break; + case CHIP_ALDEBARAN: + /* + * 1.connected to cpu: driver issue mode2 reset + * 2.discret gpu: driver issue mode1 reset + */ + if (connected_to_cpu) + return AMD_RESET_METHOD_MODE2; + break; default: break; } @@ -538,7 +751,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev) return amdgpu_dpm_mode2_reset(adev); default: dev_info(adev->dev, "MODE1 reset\n"); - return soc15_asic_mode1_reset(adev); + return amdgpu_device_mode1_reset(adev); } } @@ -661,6 +874,9 @@ static void soc15_reg_base_init(struct amdgpu_device *adev) case CHIP_ARCTURUS: arct_reg_base_init(adev); break; + case CHIP_ALDEBARAN: + aldebaran_reg_base_init(adev); + break; default: DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); break; @@ -683,14 +899,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) if (!amdgpu_sriov_vf(adev)) soc15_reg_base_init(adev); - if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) - adev->gmc.xgmi.supported = true; - if (adev->flags & AMD_IS_APU) { adev->nbio.funcs = &nbio_v7_0_funcs; adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; } else if (adev->asic_type == CHIP_VEGA20 || - adev->asic_type == CHIP_ARCTURUS) { + adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) { adev->nbio.funcs = &nbio_v7_4_funcs; adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; } else { @@ -699,7 +913,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) } adev->hdp.funcs = &hdp_v4_0_funcs; - if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) + if (adev->asic_type == CHIP_VEGA20 || + adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) adev->df.funcs = &df_v3_6_funcs; else adev->df.funcs = &df_v1_7_funcs; @@ -707,6 +923,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) adev->smuio.funcs = &smuio_v11_0_funcs; + else if (adev->asic_type == CHIP_ALDEBARAN) + adev->smuio.funcs = &smuio_v13_0_funcs; else adev->smuio.funcs = &smuio_v9_0_funcs; @@ -826,6 +1044,27 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); break; + case CHIP_ALDEBARAN: + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); + + if (amdgpu_sriov_vf(adev)) { + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); + } else { + amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + } + + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); + + amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); + amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); + amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); + break; default: return -EINVAL; } @@ -994,6 +1233,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = .get_pcie_replay_count = &soc15_get_pcie_replay_count, .supports_baco = &soc15_supports_baco, .pre_asic_init = &soc15_pre_asic_init, + .query_video_codecs = &soc15_query_video_codecs, }; static const struct amdgpu_asic_funcs vega20_asic_funcs = @@ -1015,6 +1255,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs = .get_pcie_replay_count = &soc15_get_pcie_replay_count, .supports_baco = &soc15_supports_baco, .pre_asic_init = &soc15_pre_asic_init, + .query_video_codecs = &soc15_query_video_codecs, }; static int soc15_common_early_init(void *handle) @@ -1244,6 +1485,21 @@ static int soc15_common_early_init(void *handle) AMD_PG_SUPPORT_JPEG | AMD_PG_SUPPORT_VCN_DPG; break; + case CHIP_ALDEBARAN: + adev->asic_funcs = &vega20_asic_funcs; + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_IH_CG; + /*AMD_CG_SUPPORT_VCN_MGCG |AMD_CG_SUPPORT_JPEG_MGCG;*/ + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; + adev->external_rev_id = adev->rev_id + 0x3c; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -1477,6 +1733,7 @@ static int soc15_common_set_clockgating_state(void *handle, state == AMD_CG_STATE_GATE); break; case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: adev->hdp.funcs->update_clock_gating(adev, state == AMD_CG_STATE_GATE); break; @@ -1498,15 +1755,18 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags) adev->hdp.funcs->get_clock_gating_state(adev, flags); - /* AMD_CG_SUPPORT_DRM_MGCG */ - data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); - if (!(data & 0x01000000)) - *flags |= AMD_CG_SUPPORT_DRM_MGCG; + if (adev->asic_type != CHIP_ALDEBARAN) { - /* AMD_CG_SUPPORT_DRM_LS */ - data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); - if (data & 0x1) - *flags |= AMD_CG_SUPPORT_DRM_LS; + /* AMD_CG_SUPPORT_DRM_MGCG */ + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); + if (!(data & 0x01000000)) + *flags |= AMD_CG_SUPPORT_DRM_MGCG; + + /* AMD_CG_SUPPORT_DRM_LS */ + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); + if (data & 0x1) + *flags |= AMD_CG_SUPPORT_DRM_LS; + } /* AMD_CG_SUPPORT_ROM_MGCG */ adev->smuio.funcs->get_clock_gating_state(adev, flags); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index 8f38f047265bc6ef7bac9b78b3cfb7980c08eb3f..034cfdfc4dbe74b81ab96b225264760a5ab1fb25 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -49,6 +49,13 @@ struct soc15_reg_rlcg { u32 reg; }; +struct soc15_reg { + uint32_t hwip; + uint32_t inst; + uint32_t seg; + uint32_t reg_offset; +}; + struct soc15_reg_entry { uint32_t hwip; uint32_t inst; @@ -88,6 +95,10 @@ struct soc15_ras_field_entry { #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT +#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift) + +#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift) + void soc15_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); void soc15_set_virt_ops(struct amdgpu_device *adev); @@ -100,6 +111,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, int vega10_reg_base_init(struct amdgpu_device *adev); int vega20_reg_base_init(struct amdgpu_device *adev); int arct_reg_base_init(struct amdgpu_device *adev); +int aldebaran_reg_base_init(struct amdgpu_device *adev); void vega10_doorbell_index_init(struct amdgpu_device *adev); void vega20_doorbell_index_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index a5c00ab8b021a1c2bcad99d2108e9b8cfc23df07..8cdf5d1685cbbb789287fd17d37cacd0cd1120b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -100,6 +100,30 @@ } \ } while (0) +#define WREG32_RLC_EX(prefix, reg, value) \ + do { \ + if (amdgpu_sriov_fullaccess(adev)) { \ + uint32_t i = 0; \ + uint32_t retries = 50000; \ + uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \ + uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \ + uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \ + WREG32(r0, value); \ + WREG32(r1, (reg | 0x80000000)); \ + WREG32(spare_int, 0x1); \ + for (i = 0; i < retries; i++) { \ + u32 tmp = RREG32(r1); \ + if (!(tmp & 0x80000000)) \ + break; \ + udelay(10); \ + } \ + if (i >= retries) \ + pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ + } else { \ + WREG32(reg, value); \ + } \ + } while (0) + #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ do { \ uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ @@ -118,12 +142,36 @@ } \ } while (0) +#define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ + do { \ + uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ + if (amdgpu_sriov_fullaccess(adev)) { \ + uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \ + uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \ + uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \ + uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \ + if (target_reg == grbm_cntl) \ + WREG32(r2, value); \ + else if (target_reg == grbm_idx) \ + WREG32(r3, value); \ + WREG32(target_reg, value); \ + } else { \ + WREG32(target_reg, value); \ + } \ + } while (0) + #define WREG32_SOC15_RLC(ip, inst, reg, value) \ do { \ uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ WREG32_RLC(target_reg, value); \ } while (0) +#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ + do { \ + uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ + WREG32_RLC_EX(prefix, target_reg, value); \ + } while (0) + #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ diff --git a/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h b/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h index 5039375bb1d42b8dc27d261d93652df85ca86287..cf8ff064dc72e901e211b4aa76210d716ad6e5a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h +++ b/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h @@ -50,6 +50,7 @@ enum ta_securedisplay_status { TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR = 0x04, /* Fail to Write to I2C */ TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR = 0x05, /*Fail Read DIO Scratch Register*/ TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR = 0x06, /* Fail to Read CRC*/ + TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR = 0x07, /* Failed to initialize I2C */ TA_SECUREDISPLAY_STATUS__MAX = 0x7FFFFFFF,/* Maximum Value for status*/ }; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index b6e0f4ba6272c1d3c891cd87605dd8d4075b4646..87ec883f7e0674aca6b6b8825857075e064ea25e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1545,6 +1545,36 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, }; +static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_DEC, + .align_mask = 0xf, + .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v2_5_dec_ring_get_rptr, + .get_wptr = vcn_v2_5_dec_ring_get_wptr, + .set_wptr = vcn_v2_5_dec_ring_set_wptr, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + + 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ + 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ + 6, + .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ + .emit_ib = vcn_v2_0_dec_ring_emit_ib, + .emit_fence = vcn_v2_0_dec_ring_emit_fence, + .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, + .test_ring = vcn_v2_0_dec_ring_test_ring, + .test_ib = amdgpu_vcn_dec_ring_test_ib, + .insert_nop = vcn_v2_0_dec_ring_insert_nop, + .insert_start = vcn_v2_0_dec_ring_insert_start, + .insert_end = vcn_v2_0_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, + .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, + .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, +}; + /** * vcn_v2_5_enc_ring_get_rptr - get enc read pointer * @@ -1644,6 +1674,36 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, }; +static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_ENC, + .align_mask = 0x3f, + .nop = VCN_ENC_CMD_NO_OP, + .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v2_5_enc_ring_get_rptr, + .get_wptr = vcn_v2_5_enc_ring_get_wptr, + .set_wptr = vcn_v2_5_enc_ring_set_wptr, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + + 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ + 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ + 1, /* vcn_v2_0_enc_ring_insert_end */ + .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ + .emit_ib = vcn_v2_0_enc_ring_emit_ib, + .emit_fence = vcn_v2_0_enc_ring_emit_fence, + .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, + .test_ring = amdgpu_vcn_enc_ring_test_ring, + .test_ib = amdgpu_vcn_enc_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = vcn_v2_0_enc_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, + .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, + .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, +}; + static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) { int i; @@ -1651,7 +1711,10 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { if (adev->vcn.harvest_config & (1 << i)) continue; - adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; + if (adev->asic_type == CHIP_ARCTURUS) + adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; + else /* CHIP_ALDEBARAN */ + adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs; adev->vcn.inst[i].ring_dec.me = i; DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); } @@ -1665,7 +1728,10 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) if (adev->vcn.harvest_config & (1 << j)) continue; for (i = 0; i < adev->vcn.num_enc_rings; ++i) { - adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; + if (adev->asic_type == CHIP_ARCTURUS) + adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; + else /* CHIP_ALDEBARAN */ + adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs; adev->vcn.inst[j].ring_enc[i].me = j; } DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); @@ -1830,6 +1896,26 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .set_powergating_state = vcn_v2_5_set_powergating_state, }; +static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { + .name = "vcn_v2_6", + .early_init = vcn_v2_5_early_init, + .late_init = NULL, + .sw_init = vcn_v2_5_sw_init, + .sw_fini = vcn_v2_5_sw_fini, + .hw_init = vcn_v2_5_hw_init, + .hw_fini = vcn_v2_5_hw_fini, + .suspend = vcn_v2_5_suspend, + .resume = vcn_v2_5_resume, + .is_idle = vcn_v2_5_is_idle, + .wait_for_idle = vcn_v2_5_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = vcn_v2_5_set_clockgating_state, + .set_powergating_state = vcn_v2_5_set_powergating_state, +}; + const struct amdgpu_ip_block_version vcn_v2_5_ip_block = { .type = AMD_IP_BLOCK_TYPE_VCN, @@ -1838,3 +1924,12 @@ const struct amdgpu_ip_block_version vcn_v2_5_ip_block = .rev = 0, .funcs = &vcn_v2_5_ip_funcs, }; + +const struct amdgpu_ip_block_version vcn_v2_6_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCN, + .major = 2, + .minor = 6, + .rev = 0, + .funcs = &vcn_v2_6_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h index 8d9c0800b8e0a12af4e7b7ec97ced0658b514489..e72f799ed0fd4ee9f2b7069b7a5ea289cccc0f35 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h @@ -25,5 +25,6 @@ #define __VCN_V2_5_H__ extern const struct amdgpu_ip_block_version vcn_v2_5_ip_block; +extern const struct amdgpu_ip_block_version vcn_v2_6_ip_block; #endif /* __VCN_V2_5_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index def583916294d6b7369ca9fc0de2d64d096e7561..b61d1ba1aa9db00053781d545a8a291292847097 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -238,7 +238,8 @@ static int vcn_v3_0_sw_init(void *handle) fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | - cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); + cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | + cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); } @@ -1074,7 +1075,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); + /* Reset FW shared memory RBC WPTR/RPTR */ + fw_shared->rb.rptr = 0; + fw_shared->rb.wptr = lower_32_bits(ring->wptr); + + /*resetting done, fw can check RB ring */ fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + /* Unstall DPG */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); @@ -1239,9 +1246,11 @@ static int vcn_v3_0_start(struct amdgpu_device *adev) /* Initialize the ring buffer's read and write pointers */ WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); + WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); + fw_shared->rb.wptr = lower_32_bits(ring->wptr); fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); @@ -1662,6 +1671,10 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + /* restore wptr/rptr with pointers saved in FW shared memory*/ + WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); + WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); + /* Unstall DPG */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); @@ -1721,6 +1734,15 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; + volatile struct amdgpu_fw_shared *fw_shared; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { + /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ + fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; + fw_shared->rb.wptr = lower_32_bits(ring->wptr); + WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, + lower_32_bits(ring->wptr)); + } if (ring->use_doorbell) { adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 88626d83e07bebd5eeec19fba53e4b3d0dfdb6ec..ca8efa5c6978d5e6aa15dc7dd5578518f99c2b32 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -220,10 +220,8 @@ static int vega10_ih_enable_ring(struct amdgpu_device *adev, tmp = vega10_ih_rb_cntl(ih, tmp); if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); - if (ih == &adev->irq.ih1) { - tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); + if (ih == &adev->irq.ih1) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); - } if (amdgpu_sriov_vf(adev)) { if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); @@ -265,7 +263,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) u32 ih_chicken; int ret; int i; - u32 tmp; /* disable irqs */ ret = vega10_ih_toggle_interrupts(adev, false); @@ -291,15 +288,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) } } - tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); - tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, - CLIENT18_IS_STORM_CLIENT, 1); - WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); - - tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); - tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); - WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); - pci_set_master(adev->pdev); /* enable interrupts */ @@ -345,11 +333,17 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, u32 wptr, tmp; struct amdgpu_ih_regs *ih_regs; - wptr = le32_to_cpu(*ih->wptr_cpu); - ih_regs = &ih->ih_regs; + if (ih == &adev->irq.ih) { + /* Only ring0 supports writeback. On other rings fall back + * to register-based code with overflow checking below. + */ + wptr = le32_to_cpu(*ih->wptr_cpu); - if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) - goto out; + if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) + goto out; + } + + ih_regs = &ih->ih_regs; /* Double check that the overflow wasn't already cleared. */ wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); @@ -440,15 +434,11 @@ static int vega10_ih_self_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t wptr = cpu_to_le32(entry->src_data[0]); - switch (entry->ring_id) { case 1: - *adev->irq.ih1.wptr_cpu = wptr; schedule_work(&adev->irq.ih1_work); break; case 2: - *adev->irq.ih2.wptr_cpu = wptr; schedule_work(&adev->irq.ih2_work); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 5a3c867d58811437f0a06ceaa398d2e552ca12fd..6c3cb3513b98c4813c74874324f8ac28b595e0d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -35,6 +35,9 @@ #define MAX_REARM_RETRY 10 +#define mmIH_CHICKEN_ALDEBARAN 0x18d +#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 + static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); /** @@ -104,6 +107,8 @@ static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, tmp = RREG32(ih_regs->ih_rb_cntl); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); + /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); @@ -220,10 +225,8 @@ static int vega20_ih_enable_ring(struct amdgpu_device *adev, tmp = vega20_ih_rb_cntl(ih, tmp); if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); - if (ih == &adev->irq.ih1) { - tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); + if (ih == &adev->irq.ih1) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); - } if (amdgpu_sriov_vf(adev)) { if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); @@ -297,7 +300,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev) u32 ih_chicken; int ret; int i; - u32 tmp; /* disable irqs */ ret = vega20_ih_toggle_interrupts(adev, false); @@ -316,6 +318,18 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev) WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); } + /* psp firmware won't program IH_CHICKEN for aldebaran + * driver needs to program it properly according to + * MC_SPACE type in IH_RB_CNTL */ + if (adev->asic_type == CHIP_ALDEBARAN) { + ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); + if (adev->irq.ih.use_bus_addr) { + ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, + MC_SPACE_GPA_ENABLE, 1); + } + WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); + } + for (i = 0; i < ARRAY_SIZE(ih); i++) { if (ih[i]->ring_size) { if (i == 1) @@ -326,15 +340,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev) } } - tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); - tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, - CLIENT18_IS_STORM_CLIENT, 1); - WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); - - tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); - tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); - WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); - pci_set_master(adev->pdev); /* enable interrupts */ @@ -380,11 +385,17 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, u32 wptr, tmp; struct amdgpu_ih_regs *ih_regs; - wptr = le32_to_cpu(*ih->wptr_cpu); - ih_regs = &ih->ih_regs; + if (ih == &adev->irq.ih) { + /* Only ring0 supports writeback. On other rings fall back + * to register-based code with overflow checking below. + */ + wptr = le32_to_cpu(*ih->wptr_cpu); - if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) - goto out; + if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) + goto out; + } + + ih_regs = &ih->ih_regs; /* Double check that the overflow wasn't already cleared. */ wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); @@ -476,15 +487,11 @@ static int vega20_ih_self_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t wptr = cpu_to_le32(entry->src_data[0]); - switch (entry->ring_id) { case 1: - *adev->irq.ih1.wptr_cpu = wptr; schedule_work(&adev->irq.ih1_work); break; case 2: - *adev->irq.ih2.wptr_cpu = wptr; schedule_work(&adev->irq.ih2_work); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index eafb76aebd004e3b1717d2499a271d5377152001..ea338de5818aa7b1c7b0fa546f7bbdfc92355efc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -24,6 +24,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -79,6 +81,193 @@ #include "mxgpu_vi.h" #include "amdgpu_dm.h" +/* Topaz */ +static const struct amdgpu_video_codecs topaz_video_codecs_encode = +{ + .codec_count = 0, + .codec_array = NULL, +}; + +/* Tonga, CZ, ST, Fiji */ +static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs tonga_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array), + .codec_array = tonga_video_codecs_encode_array, +}; + +/* Polaris */ +static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs polaris_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array), + .codec_array = polaris_video_codecs_encode_array, +}; + +/* Topaz */ +static const struct amdgpu_video_codecs topaz_video_codecs_decode = +{ + .codec_count = 0, + .codec_array = NULL, +}; + +/* Tonga */ +static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, +}; + +static const struct amdgpu_video_codecs tonga_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array), + .codec_array = tonga_video_codecs_decode_array, +}; + +/* CZ, ST, Fiji, Polaris */ +static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, +}; + +static const struct amdgpu_video_codecs cz_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array), + .codec_array = cz_video_codecs_decode_array, +}; + +static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + if (encode) + *codecs = &topaz_video_codecs_encode; + else + *codecs = &topaz_video_codecs_decode; + return 0; + case CHIP_TONGA: + if (encode) + *codecs = &tonga_video_codecs_encode; + else + *codecs = &tonga_video_codecs_decode; + return 0; + case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + case CHIP_VEGAM: + if (encode) + *codecs = &polaris_video_codecs_encode; + else + *codecs = &cz_video_codecs_decode; + return 0; + case CHIP_FIJI: + case CHIP_CARRIZO: + case CHIP_STONEY: + if (encode) + *codecs = &tonga_video_codecs_encode; + else + *codecs = &cz_video_codecs_decode; + return 0; + default: + return -EINVAL; + } +} + /* * Indirect registers accessor */ @@ -1085,6 +1274,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .get_pcie_replay_count = &vi_get_pcie_replay_count, .supports_baco = &vi_asic_supports_baco, .pre_asic_init = &vi_pre_asic_init, + .query_video_codecs = &vi_query_video_codecs, }; #define CZ_REV_BRISTOL(rev) \ diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c index fe14e473f026f2f01d0a4bfe67940af48b942aad..f6233019f042036db620d1187114be7fa3890e07 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c @@ -80,8 +80,9 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev, ihre->source_id == CIK_INTSRC_SDMA_TRAP || ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG || ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE || - ihre->source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT || - ihre->source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT; + ((ihre->source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT || + ihre->source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT) && + !amdgpu_no_queue_eviction_on_vm_fault); } static void cik_event_interrupt_wq(struct kfd_dev *dev, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index affbca7c0050ea4992e9763d70b10412b058f067..475f89700c74f502d1ad35411326c1e378e33565 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -1575,6 +1575,498 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbf810000, 0x00000000, }; +static const uint32_t cwsr_trap_aldebaran_hex[] = { + 0xbf820001, 0xbf8202ce, + 0xb8f8f802, 0x89788678, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf840003, + 0x866eff78, 0x00002000, + 0xbf840016, 0xb8fbf803, + 0x866eff7b, 0x00000400, + 0xbf85003b, 0x866eff7b, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000100, + 0xbf84000c, 0x866eff78, + 0x00002000, 0xbf840005, + 0xbf8e0010, 0xb8eef803, + 0x866eff6e, 0x00000400, + 0xbf84fffb, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xb8eef807, + 0x866fff6e, 0x001f8000, + 0x8e6f8b6f, 0x8977ff77, + 0xfc000000, 0x87776f77, + 0x896eff6e, 0x001f8000, + 0xb96ef807, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xc0071bbd, 0x00000000, + 0xbf8cc07f, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0xb8fbf803, + 0x867bff7b, 0x000001ff, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8fa2407, 0x8e7a9b7a, + 0x876d7a6d, 0xb8fa03c7, + 0x8e7a9a7a, 0x876d7a6d, + 0xb8faf807, 0x867aff7a, + 0x00007fff, 0xb97af807, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x867aff7f, + 0x08000000, 0x8f7a837a, + 0x87777a77, 0x867aff7f, + 0x70000000, 0x8f7a817a, + 0x87777a77, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bba, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bfa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850051, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf820101, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x08000000, + 0x8f6e836e, 0x87776e77, + 0x866eff7f, 0x70000000, + 0x8f6e816e, 0x87776e77, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, + 0xbefe00c1, 0xbeff00c1, + 0xbef600ff, 0x01000000, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, + 0x00000078, 0x80788478, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, + 0x00000078, 0x80788478, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, + 0x00000078, 0x80788478, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, + 0x00000078, 0x80788478, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, + 0x00000078, 0x80788478, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x866fff6d, 0xf8000000, + 0x8f6f9b6f, 0x8e6f906f, + 0xbeee0080, 0x876e6f6e, + 0x866fff6d, 0x04000000, + 0x8f6f9a6f, 0x8e6f8f6f, + 0x876e6f6e, 0x866fff7a, + 0x00800000, 0x8f6f976f, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0x95806f6c, 0xbf810000, +}; + static const uint32_t cwsr_trap_gfx10_hex[] = { 0xbf820001, 0xbf8201cf, 0xb0804004, 0xb978f802, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm index b195b7cd8a17b02193821139140fb5079c34641f..ac8edef09ca5bd2bd116dfe23d128f5f41671fe5 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm @@ -563,6 +563,7 @@ L_RESTORE: buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 + s_waitcnt vmcnt(0) /* restore SGPRs */ ////////////////////////////// diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 75f29d13c90f5c8f6c221a6816695884ccab3b85..eed78a04e7c77b4714e652cd71a6cbc7ce5ea9a2 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -21,9 +21,24 @@ */ /* To compile this assembly code: - * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex + * + * gfx9: + * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3 + * sp3 gfx9.sp3 -hex gfx9.hex + * + * arcturus: + * cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3 + * sp3 arcturus.sp3 -hex arcturus.hex + * + * aldebaran: + * cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3 + * sp3 aldebaran.sp3 -hex aldebaran.hex */ +#define CHIP_VEGAM 18 +#define CHIP_ARCTURUS 23 +#define CHIP_ALDEBARAN 25 + var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised @@ -44,10 +59,17 @@ var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 -var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 -var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits +var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 + +#if ASIC_FAMILY >= CHIP_ALDEBARAN +var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 6 +var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT = 12 +var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE = 6 +#else +var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 +#endif var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask @@ -134,7 +156,7 @@ var s_restore_spi_init_lo = exec_lo var s_restore_spi_init_hi = exec_hi var s_restore_mem_offset = ttmp12 -var s_restore_accvgpr_offset = ttmp13 +var s_restore_tmp2 = ttmp13 var s_restore_alloc_size = ttmp3 var s_restore_tmp = ttmp2 var s_restore_mem_offset_save = s_restore_tmp //no conflict @@ -466,12 +488,7 @@ if SAVE_AFTER_XNACK_ERROR L_SAVE_FIRST_VGPRS_WITH_TCP: end - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 - - + write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) /* save LDS */ ////////////////////////////// @@ -565,11 +582,8 @@ L_SAVE_LDS_DONE: s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on s_mov_b32 exec_hi, 0xFFFFFFFF - s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size - s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 - s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible - s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + get_num_arch_vgprs(s_save_alloc_size) + s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes // VGPR store using dw burst @@ -602,10 +616,7 @@ end v_mov_b32 v2, v2 //v0 = v[0+m0] v_mov_b32 v3, v3 //v0 = v[0+m0] - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 + write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) s_add_u32 m0, m0, 4 //next vgpr index s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes @@ -615,8 +626,17 @@ end L_SAVE_VGPR_END: -if ASIC_TARGET_ARCTURUS +#if ASIC_FAMILY >= CHIP_ARCTURUS // Save ACC VGPRs + +#if ASIC_FAMILY >= CHIP_ALDEBARAN + // ACC VGPR count may differ from ARCH VGPR count. + get_num_acc_vgprs(s_save_alloc_size, s_save_tmp) + s_and_b32 s_save_alloc_size, s_save_alloc_size, s_save_alloc_size + s_cbranch_scc0 L_SAVE_ACCVGPR_END + s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later +#endif + s_mov_b32 m0, 0x0 //VGPR initial index value =0 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 @@ -644,10 +664,7 @@ L_SAVE_ACCVGPR_LOOP: v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] end - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 + write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) s_add_u32 m0, m0, 4 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 @@ -656,7 +673,7 @@ L_SAVE_ACCVGPR_LOOP: s_set_gpr_idx_off L_SAVE_ACCVGPR_END: -end +#endif s_branch L_END_PGM @@ -724,53 +741,23 @@ L_RESTORE: /* restore VGPRs */ ////////////////////////////// L_RESTORE_VGPR: - // VGPR SR memory offset : 0 - s_mov_b32 s_restore_mem_offset, 0x0 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead s_mov_b32 exec_hi, 0xFFFFFFFF + s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size - s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 - s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) - s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) - -if ASIC_TARGET_ARCTURUS - s_mov_b32 s_restore_accvgpr_offset, s_restore_buf_rsrc2 //ACC VGPRs at end of VGPRs -end - - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3. + get_num_arch_vgprs(s_restore_alloc_size) + s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later - // VGPR load using dw burst + // ARCH VGPRs at offset: 0 + s_mov_b32 s_restore_mem_offset, 0x0 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 -if ASIC_TARGET_ARCTURUS - s_mov_b32 s_restore_accvgpr_offset_save, s_restore_accvgpr_offset - s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 -end s_mov_b32 m0, 4 //VGPR initial index value = 1 - s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 - s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later + s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 L_RESTORE_VGPR_LOOP: - -if ASIC_TARGET_ARCTURUS - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*3 - s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 - s_waitcnt vmcnt(0) - - for var vgpr = 0; vgpr < 4; ++ vgpr - v_accvgpr_write acc[vgpr], v[vgpr] - end -end - - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 - s_waitcnt vmcnt(0) //ensure data ready + read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) v_mov_b32 v0, v0 //v[0+m0] = v0 v_mov_b32 v1, v1 v_mov_b32 v2, v2 @@ -779,24 +766,38 @@ end s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? - s_set_gpr_idx_off - /* VGPR restore on v0 */ -if ASIC_TARGET_ARCTURUS - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*3 - s_waitcnt vmcnt(0) - for var vgpr = 0; vgpr < 4; ++ vgpr - v_accvgpr_write acc[vgpr], v[vgpr] - end -end +#if ASIC_FAMILY >= CHIP_ALDEBARAN + // ACC VGPR count may differ from ARCH VGPR count. + get_num_acc_vgprs(s_restore_alloc_size, s_restore_tmp2) + s_and_b32 s_restore_alloc_size, s_restore_alloc_size, s_restore_alloc_size + s_cbranch_scc0 L_RESTORE_ACCVGPR_END + s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later +#endif - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 +#if ASIC_FAMILY >= CHIP_ARCTURUS + // ACC VGPRs at offset: size(ARCH VGPRs) + s_mov_b32 m0, 0 + s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 + + L_RESTORE_ACCVGPR_LOOP: + read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) + + for var vgpr = 0; vgpr < 4; ++ vgpr + v_accvgpr_write acc[vgpr], v[vgpr] + end + + s_add_u32 m0, m0, 4 //next vgpr index + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes + s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 + s_cbranch_scc1 L_RESTORE_ACCVGPR_LOOP //VGPR restore (except v0) is complete? + L_RESTORE_ACCVGPR_END: +#endif + + s_set_gpr_idx_off + + // Restore VGPRs 0-3 last, no longer needed. + read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset_save) /* restore SGPRs */ ////////////////////////////// @@ -974,6 +975,21 @@ function check_if_tcp_store_ok L_TCP_STORE_CHECK_DONE: end +function write_4vgprs_to_mem(s_rsrc, s_mem_offset) + buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 + buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 + buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 + buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 +end + +function read_4vgprs_from_mem(s_rsrc, s_mem_offset) + buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 + buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 + buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 + buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 + s_waitcnt vmcnt(0) +end + function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset) s_mov_b32 s4, 0 @@ -1008,9 +1024,9 @@ function get_vgpr_size_bytes(s_vgpr_size_byte) s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible -if ASIC_TARGET_ARCTURUS +#if ASIC_FAMILY >= CHIP_ARCTURUS s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs -end +#endif end function get_sgpr_size_bytes(s_sgpr_size_byte) @@ -1023,6 +1039,32 @@ function get_hwreg_size_bytes return 128 //HWREG size 128 bytes end +function get_num_arch_vgprs(s_num_arch_vgprs) +#if ASIC_FAMILY >= CHIP_ALDEBARAN + // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count. + s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE) +#else + s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) +#endif + + // Number of VGPRs = (vgpr_size + 1) * 4 + s_add_u32 s_num_arch_vgprs, s_num_arch_vgprs, 1 + s_lshl_b32 s_num_arch_vgprs, s_num_arch_vgprs, 2 +end + +#if ASIC_FAMILY >= CHIP_ALDEBARAN +function get_num_acc_vgprs(s_num_acc_vgprs, s_tmp) + // VGPR count = (GPR_ALLOC.VGPR_SIZE + 1) * 8 + s_getreg_b32 s_num_acc_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) + s_add_u32 s_num_acc_vgprs, s_num_acc_vgprs, 1 + s_lshl_b32 s_num_acc_vgprs, s_num_acc_vgprs, 3 + + // ACC VGPR count = VGPR count - ARCH VGPR count. + get_num_arch_vgprs(s_tmp) + s_sub_u32 s_num_acc_vgprs, s_num_acc_vgprs, s_tmp +end +#endif + function ack_sqc_store_workaround if ACK_SQC_STORE s_waitcnt lgkmcnt(0) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8cc51cec988a4eeb44b002e62c90e2932884111a..6802c616e10e40162c994f612e8959a9d3fea08a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -556,11 +556,7 @@ static int kfd_ioctl_set_trap_handler(struct file *filep, goto out; } - if (dev->dqm->ops.set_trap_handler(dev->dqm, - &pdd->qpd, - args->tba_addr, - args->tma_addr)) - err = -EINVAL; + kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); out: mutex_unlock(&p->mutex); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index a5640a6138cf2cb019cb00d12a08d4f6faee2ad6..c60e82697385d3d65870b67720fe7139510b919b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -26,6 +26,7 @@ #include "kfd_priv.h" #include "kfd_topology.h" #include "kfd_iommu.h" +#include "amdgpu.h" #include "amdgpu_amdkfd.h" /* GPU Processor ID base for dGPUs for which VCRAT needs to be created. @@ -665,6 +666,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: pcache_info = vega10_cache_info; num_of_cache_types = ARRAY_SIZE(vega10_cache_info); break; @@ -1112,6 +1114,8 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size, struct crat_subtype_iolink *sub_type_hdr, uint32_t proximity_domain) { + struct amdgpu_device *adev = (struct amdgpu_device *)kdev->kgd; + *avail_size -= sizeof(struct crat_subtype_iolink); if (*avail_size < 0) return -ENOMEM; @@ -1128,7 +1132,18 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size, /* Fill in IOLINK subtype. * TODO: Fill-in other fields of iolink subtype */ - sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS; + if (adev->gmc.xgmi.connected_to_cpu) { + /* + * with host gpu xgmi link, host can access gpu memory whether + * or not pcie bar type is large, so always create bidirectional + * io link. + */ + sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL; + sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI; + } else { + sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS; + } + sub_type_hdr->proximity_domain_from = proximity_domain; #ifdef CONFIG_NUMA if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 72c893fff61ae270240759faa4c7fcb528850330..f860cd7059612af25df5b772a9a93ff0e38859f3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -46,6 +46,7 @@ extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; extern const struct kfd2kgd_calls arcturus_kfd2kgd; +extern const struct kfd2kgd_calls aldebaran_kfd2kgd; extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; @@ -71,6 +72,7 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { [CHIP_VEGA20] = &gfx_v9_kfd2kgd, [CHIP_RENOIR] = &gfx_v9_kfd2kgd, [CHIP_ARCTURUS] = &arcturus_kfd2kgd, + [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd, [CHIP_NAVI10] = &gfx_v10_kfd2kgd, [CHIP_NAVI12] = &gfx_v10_kfd2kgd, [CHIP_NAVI14] = &gfx_v10_kfd2kgd, @@ -392,6 +394,24 @@ static const struct kfd_device_info arcturus_device_info = { .num_sdma_queues_per_engine = 8, }; +static const struct kfd_device_info aldebaran_device_info = { + .asic_family = CHIP_ALDEBARAN, + .asic_name = "aldebaran", + .max_pasid_bits = 16, + .max_no_of_hqd = 24, + .doorbell_size = 8, + .ih_ring_entry_size = 8 * sizeof(uint32_t), + .event_interrupt_class = &event_interrupt_class_v9, + .num_of_watch_points = 4, + .mqd_size_aligned = MQD_SIZE_ALIGNED, + .supports_cwsr = true, + .needs_iommu_device = false, + .needs_pci_atomics = false, + .num_sdma_engines = 2, + .num_xgmi_sdma_engines = 3, + .num_sdma_queues_per_engine = 8, +}; + static const struct kfd_device_info renoir_device_info = { .asic_family = CHIP_RENOIR, .asic_name = "renoir", @@ -556,6 +576,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = { [CHIP_VEGA20] = {&vega20_device_info, NULL}, [CHIP_RENOIR] = {&renoir_device_info, NULL}, [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, + [CHIP_ALDEBARAN] = {&aldebaran_device_info, NULL}, [CHIP_NAVI10] = {&navi10_device_info, NULL}, [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, [CHIP_NAVI14] = {&navi14_device_info, NULL}, @@ -640,6 +661,10 @@ static void kfd_cwsr_init(struct kfd_dev *kfd) BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); kfd->cwsr_isa = cwsr_trap_arcturus_hex; kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); + } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { + BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); + kfd->cwsr_isa = cwsr_trap_aldebaran_hex; + kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); } else if (kfd->device_info->asic_family < CHIP_NAVI10) { BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); kfd->cwsr_isa = cwsr_trap_gfx9_hex; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e686ce2bf3b3cd032ff7cb90df15924d66295523..965f9f230045c7603b72d988a7a2870265f8f4df 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1128,6 +1128,9 @@ static int set_sched_resources(struct device_queue_manager *dqm) static int initialize_cpsch(struct device_queue_manager *dqm) { + uint64_t num_sdma_queues; + uint64_t num_xgmi_sdma_queues; + pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); mutex_init(&dqm->lock_hidden); @@ -1136,8 +1139,18 @@ static int initialize_cpsch(struct device_queue_manager *dqm) dqm->active_cp_queue_count = 0; dqm->gws_queue_count = 0; dqm->active_runlist = false; - dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); - dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); + + num_sdma_queues = get_num_sdma_queues(dqm); + if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap)) + dqm->sdma_bitmap = ULLONG_MAX; + else + dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1); + + num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm); + if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap)) + dqm->xgmi_sdma_bitmap = ULLONG_MAX; + else + dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1); INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); @@ -1393,6 +1406,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, uint32_t filter_param) { int retval = 0; + struct mqd_manager *mqd_mgr; if (!dqm->sched_running) return 0; @@ -1424,6 +1438,22 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, return retval; } + /* In the current MEC firmware implementation, if compute queue + * doesn't response to the preemption request in time, HIQ will + * abandon the unmap request without returning any timeout error + * to driver. Instead, MEC firmware will log the doorbell of the + * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. + * To make sure the queue unmap was successful, driver need to + * check those fields + */ + mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; + if (mqd_mgr->read_doorbell_id(dqm->packets.priv_queue->queue->mqd)) { + pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n"); + while (halt_if_hws_hang) + schedule(); + return -ETIME; + } + pm_release_ib(&dqm->packets); dqm->active_runlist = false; @@ -1596,26 +1626,6 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, return retval; } -static int set_trap_handler(struct device_queue_manager *dqm, - struct qcm_process_device *qpd, - uint64_t tba_addr, - uint64_t tma_addr) -{ - uint64_t *tma; - - if (dqm->dev->cwsr_enabled) { - /* Jump from CWSR trap handler to user trap */ - tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); - tma[0] = tba_addr; - tma[1] = tma_addr; - } else { - qpd->tba_addr = tba_addr; - qpd->tma_addr = tma_addr; - } - - return 0; -} - static int process_termination_nocpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { @@ -1859,7 +1869,6 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; dqm->ops.set_cache_memory_policy = set_cache_memory_policy; - dqm->ops.set_trap_handler = set_trap_handler; dqm->ops.process_termination = process_termination_cpsch; dqm->ops.evict_process_queues = evict_process_queues_cpsch; dqm->ops.restore_process_queues = restore_process_queues_cpsch; @@ -1878,7 +1887,6 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.initialize = initialize_nocpsch; dqm->ops.uninitialize = uninitialize; dqm->ops.set_cache_memory_policy = set_cache_memory_policy; - dqm->ops.set_trap_handler = set_trap_handler; dqm->ops.process_termination = process_termination_nocpsch; dqm->ops.evict_process_queues = evict_process_queues_nocpsch; dqm->ops.restore_process_queues = @@ -1918,6 +1926,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) case CHIP_RAVEN: case CHIP_RENOIR: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: device_queue_manager_init_v9(&dqm->asic_ops); break; case CHIP_NAVI10: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 7351dd195274e9b15d18be51e0f85378f63b2c3e..dd0d8834b4324399f4d18d779dcb94b44946d522 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -121,11 +121,6 @@ struct device_queue_manager_ops { void __user *alternate_aperture_base, uint64_t alternate_aperture_size); - int (*set_trap_handler)(struct device_queue_manager *dqm, - struct qcm_process_device *qpd, - uint64_t tba_addr, - uint64_t tma_addr); - int (*process_termination)(struct device_queue_manager *dqm, struct qcm_process_device *qpd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index 98a5e1d719c87ee289c7cf73ea95e3789d62cf6a..a2c9063076cc2e91759dd159f5917b14575a252c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -412,6 +412,7 @@ int kfd_init_apertures(struct kfd_process *process) case CHIP_RAVEN: case CHIP_RENOIR: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: case CHIP_NAVI10: case CHIP_NAVI12: case CHIP_NAVI14: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index 74a460be077bf8c138e9748d10ff7022f44c7564..1c20458f39626f608eff9aad9c8877b856cb307a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -98,9 +98,10 @@ static bool event_interrupt_isr_v9(struct kfd_dev *dev, source_id == SOC15_INTSRC_SDMA_TRAP || source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || source_id == SOC15_INTSRC_CP_BAD_OPCODE || - client_id == SOC15_IH_CLIENTID_VMC || + ((client_id == SOC15_IH_CLIENTID_VMC || client_id == SOC15_IH_CLIENTID_VMC1 || - client_id == SOC15_IH_CLIENTID_UTCL2; + client_id == SOC15_IH_CLIENTID_UTCL2) && + !amdgpu_no_queue_eviction_on_vm_fault); } static void event_interrupt_wq_v9(struct kfd_dev *dev, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c index 66bbca61e3ef5ed5b7c18b1ac4ab8277bff0fc90..9318936aa80549d9b8c489cc6755a1ad51edacb5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c @@ -20,6 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include + +#if IS_REACHABLE(CONFIG_AMD_IOMMU_V2) + #include #include #include @@ -355,3 +359,5 @@ int kfd_iommu_add_perf_counters(struct kfd_topology_device *kdev) return 0; } + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.h b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.h index dd23d9fdf6a82113fb16af9e2ae9963b03252cc5..afd420b01a0c24c3e5c9bf528416f6d44f52a4c3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.h @@ -23,7 +23,9 @@ #ifndef __KFD_IOMMU_H__ #define __KFD_IOMMU_H__ -#if defined(CONFIG_AMD_IOMMU_V2_MODULE) || defined(CONFIG_AMD_IOMMU_V2) +#include + +#if IS_REACHABLE(CONFIG_AMD_IOMMU_V2) #define KFD_SUPPORT_IOMMU_V2 @@ -46,6 +48,9 @@ static inline int kfd_iommu_check_device(struct kfd_dev *kfd) } static inline int kfd_iommu_device_init(struct kfd_dev *kfd) { +#if IS_MODULE(CONFIG_AMD_IOMMU_V2) + WARN_ONCE(1, "iommu_v2 module is not usable by built-in KFD"); +#endif return 0; } @@ -73,6 +78,6 @@ static inline int kfd_iommu_add_perf_counters(struct kfd_topology_device *kdev) return 0; } -#endif /* defined(CONFIG_AMD_IOMMU_V2) */ +#endif /* IS_REACHABLE(CONFIG_AMD_IOMMU_V2) */ #endif /* __KFD_IOMMU_H__ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index fbdb16418847ce9480655c7461e18d556931de5e..b5e2ea7550d41f1c30466068ab888986b15d4b91 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -101,6 +101,7 @@ struct mqd_manager { #if defined(CONFIG_DEBUG_FS) int (*debugfs_show_mqd)(struct seq_file *m, void *data); #endif + uint32_t (*read_doorbell_id)(void *mqd); struct mutex mqd_mutex; struct kfd_dev *dev; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 19f0fe547c57582e42282cce14f5c3d154d1f888..064914e1e8d627b79b0d489ad4d82a16191bd861 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -226,6 +226,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, __update_mqd(mm, mqd, q, 1); } +static uint32_t read_doorbell_id(void *mqd) +{ + struct cik_mqd *m = (struct cik_mqd *)mqd; + + return m->queue_doorbell_id0; +} + static void update_mqd_hawaii(struct mqd_manager *mm, void *mqd, struct queue_properties *q) { @@ -398,6 +405,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif + mqd->read_doorbell_id = read_doorbell_id; break; case KFD_MQD_TYPE_DIQ: mqd->allocate_mqd = allocate_mqd; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 18e08d82d97846a627e17a145f78edccdaf72626..c7fb59ca597fb052cd26563599de94bfe101873b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -224,6 +224,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, q->is_active = QUEUE_IS_ACTIVE(*q); } +static uint32_t read_doorbell_id(void *mqd) +{ + struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; + + return m->queue_doorbell_id0; +} + static int destroy_mqd(struct mqd_manager *mm, void *mqd, enum kfd_preempt_type type, unsigned int timeout, uint32_t pipe_id, @@ -425,6 +432,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif + mqd->read_doorbell_id = read_doorbell_id; pr_debug("%s@%i\n", __func__, __LINE__); break; case KFD_MQD_TYPE_DIQ: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 3b6f5963180d5250ac6b50daeeb360ea3ed90f3b..7f4e102ff4bd348065cd3f3183cfb8a32a670bd5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -276,6 +276,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } +static uint32_t read_doorbell_id(void *mqd) +{ + struct v9_mqd *m = (struct v9_mqd *)mqd; + + return m->queue_doorbell_id0; +} + static int destroy_mqd(struct mqd_manager *mm, void *mqd, enum kfd_preempt_type type, unsigned int timeout, uint32_t pipe_id, @@ -477,6 +484,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif + mqd->read_doorbell_id = read_doorbell_id; break; case KFD_MQD_TYPE_DIQ: mqd->allocate_mqd = allocate_mqd; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 31799e5f3b3c5e6f34afbe812fb24f17871b5bac..33dbd22d290f338aa50bcad1413fe155870e8925 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -243,6 +243,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, __update_mqd(mm, mqd, q, MTYPE_CC, 1); } +static uint32_t read_doorbell_id(void *mqd) +{ + struct vi_mqd *m = (struct vi_mqd *)mqd; + + return m->queue_doorbell_id0; +} + static void update_mqd_tonga(struct mqd_manager *mm, void *mqd, struct queue_properties *q) { @@ -446,6 +453,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif + mqd->read_doorbell_id = read_doorbell_id; break; case KFD_MQD_TYPE_DIQ: mqd->allocate_mqd = allocate_mqd; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 5d541e0cc8ca277754db8fa522eeab0c74dc6962..d903f694acbaddc6aaccdb7e33468702cfb0b610 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -242,6 +242,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) case CHIP_RAVEN: case CHIP_RENOIR: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: case CHIP_NAVI10: case CHIP_NAVI12: case CHIP_NAVI14: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 09599efa41fc918095549e0d5dc44202e00aa24c..d8c8b5ff449aaf6853d67ba001f8e4cb43a5481e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -169,6 +169,11 @@ extern bool hws_gws_support; /* Queue preemption timeout in ms */ extern int queue_preemption_timeout_ms; +/* + * Don't evict process queues on vm fault + */ +extern int amdgpu_no_queue_eviction_on_vm_fault; + /* Enable eviction debug messages */ extern bool debug_evictions; @@ -944,6 +949,10 @@ bool interrupt_is_wanted(struct kfd_dev *dev, /* amdkfd Apertures */ int kfd_init_apertures(struct kfd_process *process); +void kfd_process_set_trap_handler(struct qcm_process_device *qpd, + uint64_t tba_addr, + uint64_t tma_addr); + /* Queue Context Management */ int init_queue(struct queue **q, const struct queue_properties *properties); void uninit_queue(struct queue *q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 65803e153a223d1536522042503c45dd5251ee8b..f5237997fa186e3cada629c675b166539e61a885 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -775,10 +775,8 @@ struct kfd_process *kfd_create_process(struct file *filep) goto out; ret = kfd_process_init_cwsr_apu(process, filep); - if (ret) { - process = ERR_PTR(ret); - goto out; - } + if (ret) + goto out_destroy; if (!procfs.kobj) goto out; @@ -826,6 +824,14 @@ struct kfd_process *kfd_create_process(struct file *filep) mutex_unlock(&kfd_processes_mutex); return process; + +out_destroy: + hash_del_rcu(&process->kfd_processes); + mutex_unlock(&kfd_processes_mutex); + synchronize_srcu(&kfd_processes_srcu); + /* kfd_process_free_notifier will trigger the cleanup */ + mmu_notifier_put(&process->mmu_notifier); + return ERR_PTR(ret); } struct kfd_process *kfd_get_process(const struct task_struct *thread) @@ -1011,6 +1017,16 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } +static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) +{ + int idx = srcu_read_lock(&kfd_processes_srcu); + struct kfd_process *p = find_process_by_mm(mm); + + srcu_read_unlock(&kfd_processes_srcu, idx); + + return p ? &p->mmu_notifier : ERR_PTR(-ESRCH); +} + static void kfd_process_free_notifier(struct mmu_notifier *mn) { kfd_unref_process(container_of(mn, struct kfd_process, mmu_notifier)); @@ -1075,6 +1091,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, + .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, }; @@ -1145,6 +1162,25 @@ static int kfd_process_device_init_cwsr_dgpu(struct kfd_process_device *pdd) return 0; } +void kfd_process_set_trap_handler(struct qcm_process_device *qpd, + uint64_t tba_addr, + uint64_t tma_addr) +{ + if (qpd->cwsr_kaddr) { + /* KFD trap handler is bound, record as second-level TBA/TMA + * in first-level TMA. First-level trap will jump to second. + */ + uint64_t *tma = + (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + tma[0] = tba_addr; + tma[1] = tma_addr; + } else { + /* No trap handler bound, bind as first-level TBA/TMA. */ + qpd->tba_addr = tba_addr; + qpd->tma_addr = tma_addr; + } +} + /* * On return the kfd_process is fully operational and will be freed when the * mm is released @@ -1152,6 +1188,7 @@ static int kfd_process_device_init_cwsr_dgpu(struct kfd_process_device *pdd) static struct kfd_process *create_process(const struct task_struct *thread) { struct kfd_process *process; + struct mmu_notifier *mn; int err = -ENOMEM; process = kzalloc(sizeof(*process), GFP_KERNEL); @@ -1182,19 +1219,28 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (err != 0) goto err_init_apertures; - /* Must be last, have to use release destruction after this */ - process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; - err = mmu_notifier_register(&process->mmu_notifier, process->mm); - if (err) + /* alloc_notifier needs to find the process in the hash table */ + hash_add_rcu(kfd_processes_table, &process->kfd_processes, + (uintptr_t)process->mm); + + /* MMU notifier registration must be the last call that can fail + * because after this point we cannot unwind the process creation. + * After this point, mmu_notifier_put will trigger the cleanup by + * dropping the last process reference in the free_notifier. + */ + mn = mmu_notifier_get(&kfd_process_mmu_notifier_ops, process->mm); + if (IS_ERR(mn)) { + err = PTR_ERR(mn); goto err_register_notifier; + } + BUG_ON(mn != &process->mmu_notifier); get_task_struct(process->lead_thread); - hash_add_rcu(kfd_processes_table, &process->kfd_processes, - (uintptr_t)process->mm); return process; err_register_notifier: + hash_del_rcu(&process->kfd_processes); kfd_process_free_outstanding_kfd_bos(process); kfd_process_destroy_pdds(process); err_init_apertures: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 0be72789ccbc066a49f1b0589b21024628a73930..cdef608db4f42d615e419cc4e52c28bf2457d656 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1370,6 +1370,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) case CHIP_RAVEN: case CHIP_RENOIR: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: case CHIP_NAVI10: case CHIP_NAVI12: case CHIP_NAVI14: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 416fd910e12e1b055d579d366f3e7f31f500d1dd..b8b68087bd7a3085120b98f98bad335312eb6a9f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -47,13 +47,14 @@ #define HSA_CAP_DOORBELL_TYPE_2_0 0x2 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000 -#define HSA_CAP_SRAM_EDCSUPPORTED 0x00080000 +#define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED 0x00080000 /* Old buggy user mode depends on this being 0 */ #define HSA_CAP_MEM_EDCSUPPORTED 0x00100000 #define HSA_CAP_RASEVENTNOTIFY 0x00200000 #define HSA_CAP_ASIC_REVISION_MASK 0x03c00000 #define HSA_CAP_ASIC_REVISION_SHIFT 22 +#define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000 -#define HSA_CAP_RESERVED 0xfc078000 +#define HSA_CAP_RESERVED 0xf80f8000 struct kfd_node_properties { uint64_t hive_id; diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index e509a175ed1758b2cc5dc0b8ddb8a92f164dbae8..7dffc04a557ea12fd01f3f5454ab51edcf3738b6 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -38,4 +38,18 @@ config DEBUG_KERNEL_DC help Choose this option if you want to hit kdgb_break in assert. +config DRM_AMD_SECURE_DISPLAY + bool "Enable secure display support" + default n + depends on DEBUG_FS + depends on DRM_AMD_DC_DCN + help + Choose this option if you want to + support secure display + + This option enables the calculation + of crc of specific region via debugfs. + Cooperate with specific DMCU FW. + + endmenu diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3e1fd1e7d09f1d4e3c017d5607bef69c19948a58..00edf78975b1b775954377c0b6d2282235e04b6b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -34,6 +34,7 @@ #include "dc/inc/hw/dmcu.h" #include "dc/inc/hw/abm.h" #include "dc/dc_dmub_srv.h" +#include "dc/dc_edid_parser.h" #include "amdgpu_dm_trace.h" #include "vid.h" @@ -75,7 +76,6 @@ #include #include #include -#include #if defined(CONFIG_DRM_AMD_DC_DCN) #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" @@ -212,6 +212,9 @@ static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); static const struct drm_format_info * amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +static bool +is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, + struct drm_crtc_state *new_crtc_state); /* * dm_vblank_get_counter * @@ -335,6 +338,17 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; } +static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, + struct dm_crtc_state *new_state) +{ + if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) + return true; + else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state)) + return true; + else + return false; +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@ -566,6 +580,31 @@ static void dm_crtc_high_irq(void *interrupt_params) spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); } +#if defined(CONFIG_DRM_AMD_DC_DCN) +/** + * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for + * DCN generation ASICs + * @interrupt params - interrupt parameters + * + * Used to set crc window/read out crc value at vertical line 0 position + */ +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) +{ + struct common_irq_params *irq_params = interrupt_params; + struct amdgpu_device *adev = irq_params->adev; + struct amdgpu_crtc *acrtc; + + acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); + + if (!acrtc) + return; + + amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); +} +#endif +#endif + static int dm_set_clockgating_state(void *handle, enum amd_clockgating_state state) { @@ -951,9 +990,7 @@ static void event_mall_stutter(struct work_struct *work) else dm->active_vblank_irq_count--; - - dc_allow_idle_optimizations( - dm->dc, dm->active_vblank_irq_count == 0 ? true : false); + dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); DRM_DEBUG_DRIVER("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); @@ -1060,6 +1097,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.power_down_display_on_boot = true; + INIT_LIST_HEAD(&adev->dm.da_list); /* Display Core create. */ adev->dm.dc = dc_create(&init_data); @@ -1138,6 +1176,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) dc_init_callbacks(adev->dm.dc, &init_params); } +#endif +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); #endif if (amdgpu_dm_initialize_drm_device(adev)) { DRM_ERROR( @@ -1182,6 +1223,13 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) amdgpu_dm_destroy_drm_device(&adev->dm); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + if (adev->dm.crc_rd_wrk) { + flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); + kfree(adev->dm.crc_rd_wrk); + adev->dm.crc_rd_wrk = NULL; + } +#endif #ifdef CONFIG_DRM_AMD_DC_HDCP if (adev->dm.hdcp_workqueue) { hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); @@ -1191,6 +1239,15 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) if (adev->dm.dc) dc_deinit_callbacks(adev->dm.dc); #endif + +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (adev->dm.vblank_workqueue) { + adev->dm.vblank_workqueue->dm = NULL; + kfree(adev->dm.vblank_workqueue); + adev->dm.vblank_workqueue = NULL; + } +#endif + if (adev->dm.dc->ctx->dmub_srv) { dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); adev->dm.dc->ctx->dmub_srv = NULL; @@ -1847,6 +1904,9 @@ static int dm_suspend(void *handle) return ret; } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + amdgpu_dm_crtc_secure_display_suspend(adev); +#endif WARN_ON(adev->dm.cached_state); adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); @@ -2171,6 +2231,10 @@ static int dm_resume(void *handle) dm->cached_state = NULL; +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + amdgpu_dm_crtc_secure_display_resume(adev); +#endif + amdgpu_dm_irq_resume_late(adev); amdgpu_dm_smu_write_watermarks_table(adev); @@ -2267,6 +2331,11 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->ext_caps->bits.hdr_aux_backlight_control == 1) caps->aux_support = true; + if (amdgpu_backlight == 0) + caps->aux_support = false; + else if (amdgpu_backlight == 1) + caps->aux_support = true; + /* From the specification (CTA-861-G), for calculating the maximum * luminance we need to use: * Luminance = 50*2**(CV/32) @@ -2902,6 +2971,16 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) struct dc_interrupt_params int_params = {0}; int r; int i; +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + static const unsigned int vrtl_int_srcid[] = { + DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, + DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, + DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, + DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, + DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, + DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL + }; +#endif int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; @@ -2942,6 +3021,37 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) adev, &int_params, dm_crtc_high_irq, c_irq_params); } + /* Use otg vertical line interrupt */ +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, + vrtl_int_srcid[i], &adev->vline0_irq); + + if (r) { + DRM_ERROR("Failed to add vline0 irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); + + if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { + DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); + break; + } + + c_irq_params = &adev->dm.vline0_params[int_params.irq_source + - DC_IRQ_SOURCE_DC1_VLINE0]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_dcn_vertical_interrupt0_high_irq, c_irq_params); + } +#endif + /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx * to trigger at end of each vblank, regardless of state of the lock, @@ -3185,19 +3295,6 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) #endif } -static int set_backlight_via_aux(struct dc_link *link, uint32_t brightness) -{ - bool rc; - - if (!link) - return 1; - - rc = dc_link_set_backlight_level_nits(link, true, brightness, - AUX_BL_DEFAULT_TRANSITION_TIME_MS); - - return rc ? 0 : 1; -} - static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, unsigned *min, unsigned *max) { @@ -3260,9 +3357,10 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) brightness = convert_brightness_from_user(&caps, bd->props.brightness); // Change brightness based on AUX property if (caps.aux_support) - return set_backlight_via_aux(link, brightness); - - rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0); + rc = dc_link_set_backlight_level_nits(link, true, brightness, + AUX_BL_DEFAULT_TRANSITION_TIME_MS); + else + rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0); return rc ? 0 : 1; } @@ -3270,11 +3368,27 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) { struct amdgpu_display_manager *dm = bl_get_data(bd); - int ret = dc_link_get_backlight_level(dm->backlight_link); + struct amdgpu_dm_backlight_caps caps; + + amdgpu_dm_update_backlight_caps(dm); + caps = dm->backlight_caps; - if (ret == DC_ERROR_UNEXPECTED) - return bd->props.brightness; - return convert_brightness_to_user(&dm->backlight_caps, ret); + if (caps.aux_support) { + struct dc_link *link = (struct dc_link *)dm->backlight_link; + u32 avg, peak; + bool rc; + + rc = dc_link_get_backlight_level_nits(link, &avg, &peak); + if (!rc) + return bd->props.brightness; + return convert_brightness_to_user(&caps, avg); + } else { + int ret = dc_link_get_backlight_level(dm->backlight_link); + + if (ret == DC_ERROR_UNEXPECTED) + return bd->props.brightness; + return convert_brightness_to_user(&caps, ret); + } } static const struct backlight_ops amdgpu_dm_backlight_ops = { @@ -4574,7 +4688,6 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, const struct drm_framebuffer *fb = plane_state->fb; const struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane_state->fb); - struct drm_format_name_buf format_name; int ret; memset(plane_info, 0, sizeof(*plane_info)); @@ -4622,8 +4735,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, break; default: DRM_ERROR( - "Unsupported screen format %s\n", - drm_get_format_name(fb->format->format, &format_name)); + "Unsupported screen format %p4cc\n", + &fb->format->format); return -EINVAL; } @@ -4716,6 +4829,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, dc_plane_state->global_alpha_value = plane_info.global_alpha_value; dc_plane_state->dcc = plane_info.dcc; dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 + dc_plane_state->flip_int_enabled = true; /* * Always set input transfer function, since plane state is refreshed @@ -4992,19 +5106,16 @@ static void fill_stream_properties_from_drm_display_mode( timing_out->hdmi_vic = hv_frame.vic; } - timing_out->h_addressable = mode_in->crtc_hdisplay; - timing_out->h_total = mode_in->crtc_htotal; - timing_out->h_sync_width = - mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; - timing_out->h_front_porch = - mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; - timing_out->v_total = mode_in->crtc_vtotal; - timing_out->v_addressable = mode_in->crtc_vdisplay; - timing_out->v_front_porch = - mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; - timing_out->v_sync_width = - mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; - timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; + timing_out->h_addressable = mode_in->hdisplay; + timing_out->h_total = mode_in->htotal; + timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; + timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; + timing_out->v_total = mode_in->vtotal; + timing_out->v_addressable = mode_in->vdisplay; + timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; + timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; + timing_out->pix_clk_100hz = mode_in->clock * 10; + timing_out->aspect_ratio = get_aspect_ratio(mode_in); stream->output_color_space = get_output_color_space(timing_out); @@ -5171,6 +5282,86 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) set_master_stream(context->streams, context->stream_count); } +static struct drm_display_mode * +get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, + bool use_probed_modes) +{ + struct drm_display_mode *m, *m_pref = NULL; + u16 current_refresh, highest_refresh; + struct list_head *list_head = use_probed_modes ? + &aconnector->base.probed_modes : + &aconnector->base.modes; + + if (aconnector->freesync_vid_base.clock != 0) + return &aconnector->freesync_vid_base; + + /* Find the preferred mode */ + list_for_each_entry (m, list_head, head) { + if (m->type & DRM_MODE_TYPE_PREFERRED) { + m_pref = m; + break; + } + } + + if (!m_pref) { + /* Probably an EDID with no preferred mode. Fallback to first entry */ + m_pref = list_first_entry_or_null( + &aconnector->base.modes, struct drm_display_mode, head); + if (!m_pref) { + DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); + return NULL; + } + } + + highest_refresh = drm_mode_vrefresh(m_pref); + + /* + * Find the mode with highest refresh rate with same resolution. + * For some monitors, preferred mode is not the mode with highest + * supported refresh rate. + */ + list_for_each_entry (m, list_head, head) { + current_refresh = drm_mode_vrefresh(m); + + if (m->hdisplay == m_pref->hdisplay && + m->vdisplay == m_pref->vdisplay && + highest_refresh < current_refresh) { + highest_refresh = current_refresh; + m_pref = m; + } + } + + aconnector->freesync_vid_base = *m_pref; + return m_pref; +} + +static bool is_freesync_video_mode(struct drm_display_mode *mode, + struct amdgpu_dm_connector *aconnector) +{ + struct drm_display_mode *high_mode; + int timing_diff; + + high_mode = get_highest_refresh_rate_mode(aconnector, false); + if (!high_mode || !mode) + return false; + + timing_diff = high_mode->vtotal - mode->vtotal; + + if (high_mode->clock == 0 || high_mode->clock != mode->clock || + high_mode->hdisplay != mode->hdisplay || + high_mode->vdisplay != mode->vdisplay || + high_mode->hsync_start != mode->hsync_start || + high_mode->hsync_end != mode->hsync_end || + high_mode->htotal != mode->htotal || + high_mode->hskew != mode->hskew || + high_mode->vscan != mode->vscan || + high_mode->vsync_start - mode->vsync_start != timing_diff || + high_mode->vsync_end - mode->vsync_end != timing_diff) + return false; + else + return true; +} + static struct dc_stream_state * create_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, @@ -5184,8 +5375,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, dm_state ? &dm_state->base : NULL; struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; + struct drm_display_mode saved_mode; + struct drm_display_mode *freesync_mode = NULL; bool native_mode_found = false; - bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; + bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false; int mode_refresh; int preferred_refresh = 0; #if defined(CONFIG_DRM_AMD_DC_DCN) @@ -5193,6 +5386,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, uint32_t link_bandwidth_kbps; #endif struct dc_sink *sink = NULL; + + memset(&saved_mode, 0, sizeof(saved_mode)); + if (aconnector == NULL) { DRM_ERROR("aconnector is NULL!\n"); return stream; @@ -5245,25 +5441,38 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, */ DRM_DEBUG_DRIVER("No preferred mode found\n"); } else { - decide_crtc_timing_for_drm_display_mode( + recalculate_timing |= amdgpu_freesync_vid_mode && + is_freesync_video_mode(&mode, aconnector); + if (recalculate_timing) { + freesync_mode = get_highest_refresh_rate_mode(aconnector, false); + saved_mode = mode; + mode = *freesync_mode; + } else { + decide_crtc_timing_for_drm_display_mode( &mode, preferred_mode, dm_state ? (dm_state->scaling != RMX_OFF) : false); + } + preferred_refresh = drm_mode_vrefresh(preferred_mode); } - if (!dm_state) + if (recalculate_timing) + drm_mode_set_crtcinfo(&saved_mode, 0); + else drm_mode_set_crtcinfo(&mode, 0); - /* + /* * If scaling is enabled and refresh rate didn't change * we copy the vic and polarities of the old timings */ - if (!scale || mode_refresh != preferred_refresh) - fill_stream_properties_from_drm_display_mode(stream, - &mode, &aconnector->base, con_state, NULL, requested_bpc); + if (!recalculate_timing || mode_refresh != preferred_refresh) + fill_stream_properties_from_drm_display_mode( + stream, &mode, &aconnector->base, con_state, NULL, + requested_bpc); else - fill_stream_properties_from_drm_display_mode(stream, - &mode, &aconnector->base, con_state, old_stream, requested_bpc); + fill_stream_properties_from_drm_display_mode( + stream, &mode, &aconnector->base, con_state, old_stream, + requested_bpc); stream->timing.flags.DSC = 0; @@ -5400,15 +5609,22 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->abm_level = cur->abm_level; state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; - state->crc_src = cur->crc_src; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; - /* TODO Duplicate dc_stream after objects are stream object is flattened */ return &state->base; } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) +{ + crtc_debugfs_init(crtc); + + return 0; +} +#endif + static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) { enum dc_irq_source irq_source; @@ -5494,6 +5710,9 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .enable_vblank = dm_enable_vblank, .disable_vblank = dm_disable_vblank, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + .late_register = amdgpu_dm_crtc_late_register, +#endif }; static enum drm_connector_status @@ -6479,13 +6698,17 @@ static int dm_plane_helper_check_state(struct drm_plane_state *state, else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; - /* If completely outside of screen, viewport_width and/or viewport_height will be negative, - * which is still OK to satisfy the condition below, thereby also covering these cases - * (when plane is completely outside of screen). - * x2 for width is because of pipe-split. - */ - if (viewport_width < MIN_VIEWPORT_SIZE*2 || viewport_height < MIN_VIEWPORT_SIZE) + if (viewport_width < 0 || viewport_height < 0) { + DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); + return -EINVAL; + } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ + DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); return -EINVAL; + } else if (viewport_height < MIN_VIEWPORT_SIZE) { + DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); + return -EINVAL; + } + } /* Get min/max allowed scaling factors from plane caps. */ @@ -6505,8 +6728,10 @@ static int dm_plane_helper_check_state(struct drm_plane_state *state, } static int dm_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); struct amdgpu_device *adev = drm_to_adev(plane->dev); struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state; @@ -6514,23 +6739,24 @@ static int dm_plane_atomic_check(struct drm_plane *plane, struct drm_crtc_state *new_crtc_state; int ret; - trace_amdgpu_dm_plane_atomic_check(state); + trace_amdgpu_dm_plane_atomic_check(new_plane_state); - dm_plane_state = to_dm_plane_state(state); + dm_plane_state = to_dm_plane_state(new_plane_state); if (!dm_plane_state->dc_state) return 0; new_crtc_state = - drm_atomic_get_new_crtc_state(state->state, state->crtc); + drm_atomic_get_new_crtc_state(state, + new_plane_state->crtc); if (!new_crtc_state) return -EINVAL; - ret = dm_plane_helper_check_state(state, new_crtc_state); + ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); if (ret) return ret; - ret = fill_dc_scaling_info(state, &scaling_info); + ret = fill_dc_scaling_info(new_plane_state, &scaling_info); if (ret) return ret; @@ -6541,7 +6767,7 @@ static int dm_plane_atomic_check(struct drm_plane *plane, } static int dm_plane_atomic_async_check(struct drm_plane *plane, - struct drm_plane_state *new_plane_state) + struct drm_atomic_state *state) { /* Only support async updates on cursor planes. */ if (plane->type != DRM_PLANE_TYPE_CURSOR) @@ -6551,10 +6777,12 @@ static int dm_plane_atomic_async_check(struct drm_plane *plane, } static void dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_plane_state *new_state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); struct drm_plane_state *old_state = - drm_atomic_get_old_plane_state(new_state->state, plane); + drm_atomic_get_old_plane_state(state, plane); trace_amdgpu_dm_atomic_update_cursor(new_state); @@ -6961,11 +7189,118 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, */ drm_mode_sort(&connector->probed_modes); amdgpu_dm_get_native_mode(connector); + + /* Freesync capabilities are reset by calling + * drm_add_edid_modes() and need to be + * restored here. + */ + amdgpu_dm_update_freesync_caps(connector, edid); } else { amdgpu_dm_connector->num_modes = 0; } } +static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, + struct drm_display_mode *mode) +{ + struct drm_display_mode *m; + + list_for_each_entry (m, &aconnector->base.probed_modes, head) { + if (drm_mode_equal(m, mode)) + return true; + } + + return false; +} + +static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) +{ + const struct drm_display_mode *m; + struct drm_display_mode *new_mode; + uint i; + uint32_t new_modes_count = 0; + + /* Standard FPS values + * + * 23.976 - TV/NTSC + * 24 - Cinema + * 25 - TV/PAL + * 29.97 - TV/NTSC + * 30 - TV/NTSC + * 48 - Cinema HFR + * 50 - TV/PAL + * 60 - Commonly used + * 48,72,96 - Multiples of 24 + */ + const uint32_t common_rates[] = { 23976, 24000, 25000, 29970, 30000, + 48000, 50000, 60000, 72000, 96000 }; + + /* + * Find mode with highest refresh rate with the same resolution + * as the preferred mode. Some monitors report a preferred mode + * with lower resolution than the highest refresh rate supported. + */ + + m = get_highest_refresh_rate_mode(aconnector, true); + if (!m) + return 0; + + for (i = 0; i < ARRAY_SIZE(common_rates); i++) { + uint64_t target_vtotal, target_vtotal_diff; + uint64_t num, den; + + if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) + continue; + + if (common_rates[i] < aconnector->min_vfreq * 1000 || + common_rates[i] > aconnector->max_vfreq * 1000) + continue; + + num = (unsigned long long)m->clock * 1000 * 1000; + den = common_rates[i] * (unsigned long long)m->htotal; + target_vtotal = div_u64(num, den); + target_vtotal_diff = target_vtotal - m->vtotal; + + /* Check for illegal modes */ + if (m->vsync_start + target_vtotal_diff < m->vdisplay || + m->vsync_end + target_vtotal_diff < m->vsync_start || + m->vtotal + target_vtotal_diff < m->vsync_end) + continue; + + new_mode = drm_mode_duplicate(aconnector->base.dev, m); + if (!new_mode) + goto out; + + new_mode->vtotal += (u16)target_vtotal_diff; + new_mode->vsync_start += (u16)target_vtotal_diff; + new_mode->vsync_end += (u16)target_vtotal_diff; + new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; + new_mode->type |= DRM_MODE_TYPE_DRIVER; + + if (!is_duplicate_mode(aconnector, new_mode)) { + drm_mode_probed_add(&aconnector->base, new_mode); + new_modes_count += 1; + } else + drm_mode_destroy(aconnector->base.dev, new_mode); + } + out: + return new_modes_count; +} + +static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, + struct edid *edid) +{ + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); + + if (!(amdgpu_freesync_vid_mode && edid)) + return; + + if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) + amdgpu_dm_connector->num_modes += + add_fs_modes(amdgpu_dm_connector); +} + static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) { struct amdgpu_dm_connector *amdgpu_dm_connector = @@ -6981,6 +7316,7 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) } else { amdgpu_dm_connector_ddc_get_modes(connector, edid); amdgpu_dm_connector_add_common_modes(encoder, connector); + amdgpu_dm_connector_add_freesync_modes(connector, edid); } amdgpu_dm_fbc_init(connector); @@ -7285,8 +7621,19 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, adev, &adev->pageflip_irq, irq_type); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + amdgpu_irq_get( + adev, + &adev->vline0_irq, + irq_type); +#endif } else { - +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + amdgpu_irq_put( + adev, + &adev->vline0_irq, + irq_type); +#endif amdgpu_irq_put( adev, &adev->pageflip_irq, @@ -7410,10 +7757,6 @@ static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, int x, y; int xorigin = 0, yorigin = 0; - position->enable = false; - position->x = 0; - position->y = 0; - if (!crtc || !plane->state->fb) return 0; @@ -7460,7 +7803,7 @@ static void handle_cursor_update(struct drm_plane *plane, struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); uint64_t address = afb ? afb->address : 0; - struct dc_cursor_position position; + struct dc_cursor_position position = {0}; struct dc_cursor_attributes attributes; int ret; @@ -7545,6 +7888,7 @@ static void update_freesync_state_on_stream( struct amdgpu_device *adev = dm->adev; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); unsigned long flags; + bool pack_sdp_v1_3 = false; if (!new_stream) return; @@ -7586,7 +7930,8 @@ static void update_freesync_state_on_stream( &vrr_params, PACKET_TYPE_VRR, TRANSFER_FUNC_UNKNOWN, - &vrr_infopacket); + &vrr_infopacket, + pack_sdp_v1_3); new_crtc_state->freesync_timing_changed |= (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, @@ -7640,9 +7985,22 @@ static void update_stream_irq_parameters( if (new_crtc_state->vrr_supported && config.min_refresh_in_uhz && config.max_refresh_in_uhz) { - config.state = new_crtc_state->base.vrr_enabled ? - VRR_STATE_ACTIVE_VARIABLE : - VRR_STATE_INACTIVE; + /* + * if freesync compatible mode was set, config.state will be set + * in atomic check + */ + if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && + (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || + new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { + vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; + vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; + vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; + vrr_params.state = VRR_STATE_ACTIVE_FIXED; + } else { + config.state = new_crtc_state->base.vrr_enabled ? + VRR_STATE_ACTIVE_VARIABLE : + VRR_STATE_INACTIVE; + } } else { config.state = VRR_STATE_UNSUPPORTED; } @@ -7963,8 +8321,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * re-adjust the min/max bounds now that DC doesn't handle this * as part of commit. */ - if (amdgpu_dm_vrr_active(dm_old_crtc_state) != - amdgpu_dm_vrr_active(acrtc_state)) { + if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { spin_lock_irqsave(&pcrtc->dev->event_lock, flags); dc_stream_adjust_vmin_vmax( dm->dc, acrtc_state->stream, @@ -8249,6 +8606,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* i.e. reset mode */ if (dm_old_crtc_state->stream) remove_stream(adev, acrtc, dm_old_crtc_state->stream); + mode_set_reset_required = true; } } /* for_each_crtc_in_state() */ @@ -8307,8 +8665,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, new_con_state->hdcp_content_type, - new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true - : false); + new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED); } #endif @@ -8418,7 +8775,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) */ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - +#ifdef CONFIG_DEBUG_FS + bool configure_crc = false; + enum amdgpu_dm_pipe_crc_source cur_crc_src; +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (new_crtc_state->active && @@ -8434,12 +8794,21 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * settings for the stream. */ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + + if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { + configure_crc = true; +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + if (amdgpu_dm_crc_window_is_activated(crtc)) + configure_crc = false; +#endif + } - if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) { + if (configure_crc) amdgpu_dm_crtc_configure_crc_source( - crtc, dm_new_crtc_state, - dm_new_crtc_state->crc_src); - } + crtc, dm_new_crtc_state, cur_crc_src); #endif } } @@ -8648,6 +9017,7 @@ static void get_freesync_config_for_crtc( to_amdgpu_dm_connector(new_con_state->base.connector); struct drm_display_mode *mode = &new_crtc_state->base.mode; int vrefresh = drm_mode_vrefresh(mode); + bool fs_vid_mode = false; new_crtc_state->vrr_supported = new_con_state->freesync_capable && vrefresh >= aconnector->min_vfreq && @@ -8655,17 +9025,24 @@ static void get_freesync_config_for_crtc( if (new_crtc_state->vrr_supported) { new_crtc_state->stream->ignore_msa_timing_param = true; - config.state = new_crtc_state->base.vrr_enabled ? - VRR_STATE_ACTIVE_VARIABLE : - VRR_STATE_INACTIVE; - config.min_refresh_in_uhz = - aconnector->min_vfreq * 1000000; - config.max_refresh_in_uhz = - aconnector->max_vfreq * 1000000; + fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; + + config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; + config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; config.vsif_supported = true; config.btr = true; - } + if (fs_vid_mode) { + config.state = VRR_STATE_ACTIVE_FIXED; + config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; + goto out; + } else if (new_crtc_state->base.vrr_enabled) { + config.state = VRR_STATE_ACTIVE_VARIABLE; + } else { + config.state = VRR_STATE_INACTIVE; + } + } +out: new_crtc_state->freesync_config = config; } @@ -8678,6 +9055,50 @@ static void reset_freesync_config_for_crtc( sizeof(new_crtc_state->vrr_infopacket)); } +static bool +is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, + struct drm_crtc_state *new_crtc_state) +{ + struct drm_display_mode old_mode, new_mode; + + if (!old_crtc_state || !new_crtc_state) + return false; + + old_mode = old_crtc_state->mode; + new_mode = new_crtc_state->mode; + + if (old_mode.clock == new_mode.clock && + old_mode.hdisplay == new_mode.hdisplay && + old_mode.vdisplay == new_mode.vdisplay && + old_mode.htotal == new_mode.htotal && + old_mode.vtotal != new_mode.vtotal && + old_mode.hsync_start == new_mode.hsync_start && + old_mode.vsync_start != new_mode.vsync_start && + old_mode.hsync_end == new_mode.hsync_end && + old_mode.vsync_end != new_mode.vsync_end && + old_mode.hskew == new_mode.hskew && + old_mode.vscan == new_mode.vscan && + (old_mode.vsync_end - old_mode.vsync_start) == + (new_mode.vsync_end - new_mode.vsync_start)) + return true; + + return false; +} + +static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { + uint64_t num, den, res; + struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; + + dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; + + num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; + den = (unsigned long long)new_crtc_state->mode.htotal * + (unsigned long long)new_crtc_state->mode.vtotal; + + res = div_u64(num, den); + dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; +} + static int dm_update_crtc_state(struct amdgpu_display_manager *dm, struct drm_atomic_state *state, struct drm_crtc *crtc, @@ -8768,6 +9189,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, * TODO: Refactor this function to allow this check to work * in all conditions. */ + if (amdgpu_freesync_vid_mode && + dm_new_crtc_state->stream && + is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) + goto skip_modeset; + if (dm_new_crtc_state->stream && dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { @@ -8799,6 +9225,24 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, if (!dm_old_crtc_state->stream) goto skip_modeset; + if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && + is_timing_unchanged_for_freesync(new_crtc_state, + old_crtc_state)) { + new_crtc_state->mode_changed = false; + DRM_DEBUG_DRIVER( + "Mode change not required for front porch change, " + "setting mode_changed to %d", + new_crtc_state->mode_changed); + + set_freesync_fixed_config(dm_new_crtc_state); + + goto skip_modeset; + } else if (amdgpu_freesync_vid_mode && aconnector && + is_freesync_video_mode(&new_crtc_state->mode, + aconnector)) { + set_freesync_fixed_config(dm_new_crtc_state); + } + ret = dm_atomic_get_state(state, &dm_state); if (ret) goto fail; @@ -9376,7 +9820,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } #if defined(CONFIG_DRM_AMD_DC_DCN) - if (adev->asic_type >= CHIP_NAVI10) { + if (dc_resource_is_dsc_encoding_supported(dc)) { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { ret = add_affected_mst_dsc_crtcs(state, crtc); @@ -9682,11 +10126,85 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc, return capable; } + +static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, + uint8_t *edid_ext, int len, + struct amdgpu_hdmi_vsdb_info *vsdb_info) +{ + int i; + struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); + struct dc *dc = adev->dm.dc; + + /* send extension block to DMCU for parsing */ + for (i = 0; i < len; i += 8) { + bool res; + int offset; + + /* send 8 bytes a time */ + if (!dc_edid_parser_send_cea(dc, i, len, &edid_ext[i], 8)) + return false; + + if (i+8 == len) { + /* EDID block sent completed, expect result */ + int version, min_rate, max_rate; + + res = dc_edid_parser_recv_amd_vsdb(dc, &version, &min_rate, &max_rate); + if (res) { + /* amd vsdb found */ + vsdb_info->freesync_supported = 1; + vsdb_info->amd_vsdb_version = version; + vsdb_info->min_refresh_rate_hz = min_rate; + vsdb_info->max_refresh_rate_hz = max_rate; + return true; + } + /* not amd vsdb */ + return false; + } + + /* check for ack*/ + res = dc_edid_parser_recv_cea_ack(dc, &offset); + if (!res) + return false; + } + + return false; +} + +static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, + struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) +{ + uint8_t *edid_ext = NULL; + int i; + bool valid_vsdb_found = false; + + /*----- drm_find_cea_extension() -----*/ + /* No EDID or EDID extensions */ + if (edid == NULL || edid->extensions == 0) + return -ENODEV; + + /* Find CEA extension */ + for (i = 0; i < edid->extensions; i++) { + edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); + if (edid_ext[0] == CEA_EXT) + break; + } + + if (i == edid->extensions) + return -ENODEV; + + /*----- cea_db_offsets() -----*/ + if (edid_ext[0] != CEA_EXT) + return -ENODEV; + + valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); + + return valid_vsdb_found ? i : -ENODEV; +} + void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct edid *edid) { - int i; - bool edid_check_required; + int i = 0; struct detailed_timing *timing; struct detailed_non_pixel *data; struct detailed_data_monitor_range *range; @@ -9697,6 +10215,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); bool freesync_capable = false; + struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; if (!connector->state) { DRM_ERROR("%s - Connector has no state", __func__); @@ -9715,60 +10234,75 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, dm_con_state = to_dm_connector_state(connector->state); - edid_check_required = false; if (!amdgpu_dm_connector->dc_sink) { DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); goto update; } if (!adev->dm.freesync_module) goto update; - /* - * if edid non zero restrict freesync only for dp and edp - */ - if (edid) { - if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT - || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { + + + if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT + || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { + bool edid_check_required = false; + + if (edid) { edid_check_required = is_dp_capable_without_timing_msa( adev->dm.dc, amdgpu_dm_connector); } - } - if (edid_check_required == true && (edid->version > 1 || - (edid->version == 1 && edid->revision > 1))) { - for (i = 0; i < 4; i++) { - timing = &edid->detailed_timings[i]; - data = &timing->data.other_data; - range = &data->data.range; - /* - * Check if monitor has continuous frequency mode - */ - if (data->type != EDID_DETAIL_MONITOR_RANGE) - continue; - /* - * Check for flag range limits only. If flag == 1 then - * no additional timing information provided. - * Default GTF, GTF Secondary curve and CVT are not - * supported - */ - if (range->flags != 1) - continue; + if (edid_check_required == true && (edid->version > 1 || + (edid->version == 1 && edid->revision > 1))) { + for (i = 0; i < 4; i++) { - amdgpu_dm_connector->min_vfreq = range->min_vfreq; - amdgpu_dm_connector->max_vfreq = range->max_vfreq; - amdgpu_dm_connector->pixel_clock_mhz = - range->pixel_clock_mhz * 10; + timing = &edid->detailed_timings[i]; + data = &timing->data.other_data; + range = &data->data.range; + /* + * Check if monitor has continuous frequency mode + */ + if (data->type != EDID_DETAIL_MONITOR_RANGE) + continue; + /* + * Check for flag range limits only. If flag == 1 then + * no additional timing information provided. + * Default GTF, GTF Secondary curve and CVT are not + * supported + */ + if (range->flags != 1) + continue; - connector->display_info.monitor_range.min_vfreq = range->min_vfreq; - connector->display_info.monitor_range.max_vfreq = range->max_vfreq; + amdgpu_dm_connector->min_vfreq = range->min_vfreq; + amdgpu_dm_connector->max_vfreq = range->max_vfreq; + amdgpu_dm_connector->pixel_clock_mhz = + range->pixel_clock_mhz * 10; - break; - } + connector->display_info.monitor_range.min_vfreq = range->min_vfreq; + connector->display_info.monitor_range.max_vfreq = range->max_vfreq; + + break; + } - if (amdgpu_dm_connector->max_vfreq - - amdgpu_dm_connector->min_vfreq > 10) { + if (amdgpu_dm_connector->max_vfreq - + amdgpu_dm_connector->min_vfreq > 10) { - freesync_capable = true; + freesync_capable = true; + } + } + } else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { + i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); + if (i >= 0 && vsdb_info.freesync_supported) { + timing = &edid->detailed_timings[i]; + data = &timing->data.other_data; + + amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; + amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; + if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) + freesync_capable = true; + + connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; + connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 8bfe901cf237426cbcff64e857a8ed33396f855f..8f98d44490aa0748e945df0d7e0fa69afa79e5ad 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -68,18 +68,6 @@ struct common_irq_params { enum dc_irq_source irq_src; }; -/** - * struct irq_list_head - Linked-list for low context IRQ handlers. - * - * @head: The list_head within &struct handler_data - * @work: A work_struct containing the deferred handler work - */ -struct irq_list_head { - struct list_head head; - /* In case this interrupt needs post-processing, 'work' will be queued*/ - struct work_struct work; -}; - /** * struct dm_compressor_info - Buffer info used by frame buffer compression * @cpu_addr: MMIO cpu addr @@ -144,6 +132,16 @@ struct amdgpu_dm_backlight_caps { bool aux_support; }; +/** + * struct dal_allocation - Tracks mapped FB memory for SMU communication + */ +struct dal_allocation { + struct list_head list; + struct amdgpu_bo *bo; + void *cpu_ptr; + u64 gpu_addr; +}; + /** * struct amdgpu_display_manager - Central amdgpu display manager device * @@ -257,12 +255,12 @@ struct amdgpu_display_manager { */ struct mutex audio_lock; +#if defined(CONFIG_DRM_AMD_DC_DCN) /** - * @vblank_work_lock: + * @vblank_lock: * * Guards access to deferred vblank work state. */ -#if defined(CONFIG_DRM_AMD_DC_DCN) spinlock_t vblank_lock; #endif @@ -293,7 +291,7 @@ struct amdgpu_display_manager { * Note that handlers are called in the same order as they were * registered (FIFO). */ - struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; + struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; /** * @irq_handler_list_high_tab: @@ -323,6 +321,15 @@ struct amdgpu_display_manager { struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; + /** + * @vline0_params: + * + * OTG vertical interrupt0 IRQ parameters, passed to registered + * handlers when triggered. + */ + struct common_irq_params + vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; + /** * @vupdate_params: * @@ -345,6 +352,11 @@ struct amdgpu_display_manager { #endif #if defined(CONFIG_DRM_AMD_DC_DCN) + /** + * @vblank_workqueue: + * + * amdgpu workqueue during vblank + */ struct vblank_workqueue *vblank_workqueue; #endif @@ -363,12 +375,18 @@ struct amdgpu_display_manager { */ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +#if defined(CONFIG_DRM_AMD_DC_DCN) /** * @active_vblank_irq_count: * * number of currently active vblank irqs */ uint32_t active_vblank_irq_count; +#endif + +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + struct crc_rd_work *crc_rd_wrk; +#endif /** * @mst_encoders: @@ -377,6 +395,13 @@ struct amdgpu_display_manager { */ struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; + bool dmcub_trace_event_en; + /** + * @da_list: + * + * DAL fb memory allocation list, for communication with SMU. + */ + struct list_head da_list; }; enum dsc_clock_force_state { @@ -440,6 +465,8 @@ struct amdgpu_dm_connector { #endif bool force_yuv420_output; struct dsc_preferred_settings dsc_settings; + /* Cached display modes */ + struct drm_display_mode freesync_vid_base; }; #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) @@ -462,7 +489,6 @@ struct dm_crtc_state { int active_planes; int crc_skip_count; - enum amdgpu_dm_pipe_crc_source crc_src; bool freesync_timing_changed; bool freesync_vrr_info_changed; @@ -501,6 +527,14 @@ struct dm_connector_state { uint64_t pbn; }; +struct amdgpu_hdmi_vsdb_info { + unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ + bool freesync_supported; /* FreeSync Supported */ + unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ + unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ +}; + + #define to_dm_connector_state(x)\ container_of((x), struct dm_connector_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 66cb8730586b1c0b520024bbb501b6b83e536c99..c6d6baab106ed1205061544997c640437f1eda12 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -29,6 +29,7 @@ #include "amdgpu.h" #include "amdgpu_dm.h" #include "dc.h" +#include "amdgpu_securedisplay.h" static const char *const pipe_crc_sources[] = { "none", @@ -81,6 +82,73 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, return pipe_crc_sources; } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) +{ + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_window.x_start = 0; + acrtc->dm_irq_params.crc_window.y_start = 0; + acrtc->dm_irq_params.crc_window.x_end = 0; + acrtc->dm_irq_params.crc_window.y_end = 0; + acrtc->dm_irq_params.crc_window.activated = false; + acrtc->dm_irq_params.crc_window.update_win = false; + acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; + spin_unlock_irq(&drm_dev->event_lock); +} + +static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) +{ + struct crc_rd_work *crc_rd_wrk; + struct amdgpu_device *adev; + struct psp_context *psp; + struct securedisplay_cmd *securedisplay_cmd; + struct drm_crtc *crtc; + uint8_t phy_id; + int ret; + + crc_rd_wrk = container_of(work, struct crc_rd_work, notify_ta_work); + spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); + crtc = crc_rd_wrk->crtc; + + if (!crtc) { + spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); + return; + } + + adev = drm_to_adev(crtc->dev); + psp = &adev->psp; + phy_id = crc_rd_wrk->phy_inst; + spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); + + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); + securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = + phy_id; + ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); + if (!ret) { + if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + } + } +} + +bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) +{ + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool ret = false; + + spin_lock_irq(&drm_dev->event_lock); + ret = acrtc->dm_irq_params.crc_window.activated; + spin_unlock_irq(&drm_dev->event_lock); + + return ret; +} +#endif + int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, size_t *values_cnt) @@ -114,6 +182,20 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, /* Enable CRTC CRC generation if necessary. */ if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + if (!enable) { + if (adev->dm.crc_rd_wrk) { + flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); + spin_lock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); + if (adev->dm.crc_rd_wrk->crtc == crtc) { + dc_stream_stop_dmcu_crc_win_update(stream_state->ctx->dc, + dm_crtc_state->stream); + adev->dm.crc_rd_wrk->crtc = NULL; + } + spin_unlock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); + } + } +#endif if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state, NULL, enable, enable)) { ret = -EINVAL; @@ -142,8 +224,11 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) { enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); + enum amdgpu_dm_pipe_crc_source cur_crc_src; struct drm_crtc_commit *commit; struct dm_crtc_state *crtc_state; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_dp_aux *aux = NULL; bool enable = false; bool enabled = false; @@ -182,6 +267,9 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) enable = amdgpu_dm_is_valid_crc_source(source); crtc_state = to_dm_crtc_state(crtc->state); + spin_lock_irq(&drm_dev->event_lock); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irq(&drm_dev->event_lock); /* * USER REQ SRC | CURRENT SRC | BEHAVIOR @@ -198,7 +286,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) */ if (dm_is_crc_source_dprx(source) || (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && - dm_is_crc_source_dprx(crtc_state->crc_src))) { + dm_is_crc_source_dprx(cur_crc_src))) { struct amdgpu_dm_connector *aconn = NULL; struct drm_connector *connector; struct drm_connector_list_iter conn_iter; @@ -228,6 +316,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) } } +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + amdgpu_dm_set_crc_window_default(crtc); +#endif + if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { ret = -EINVAL; goto cleanup; @@ -237,7 +329,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) * Reading the CRC requires the vblank interrupt handler to be * enabled. Keep a reference until CRC capture stops. */ - enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); + enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); if (!enabled && enable) { ret = drm_crtc_vblank_get(crtc); if (ret) @@ -261,7 +353,9 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) } } - crtc_state->crc_src = source; + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_src = source; + spin_unlock_irq(&drm_dev->event_lock); /* Reset crc_skipped on dm state */ crtc_state->crc_skip_count = 0; @@ -286,16 +380,26 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) { struct dm_crtc_state *crtc_state; struct dc_stream_state *stream_state; + struct drm_device *drm_dev = NULL; + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct amdgpu_crtc *acrtc = NULL; uint32_t crcs[3]; + unsigned long flags; if (crtc == NULL) return; crtc_state = to_dm_crtc_state(crtc->state); stream_state = crtc_state->stream; + acrtc = to_amdgpu_crtc(crtc); + drm_dev = crtc->dev; + + spin_lock_irqsave(&drm_dev->event_lock, flags); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irqrestore(&drm_dev->event_lock, flags); /* Early return if CRC capture is not enabled. */ - if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src)) + if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) return; /* @@ -309,7 +413,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) return; } - if (dm_is_crc_source_crtc(crtc_state->crc_src)) { + if (dm_is_crc_source_crtc(cur_crc_src)) { if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, &crcs[0], &crcs[1], &crcs[2])) return; @@ -318,3 +422,182 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) drm_crtc_accurate_vblank_count(crtc), crcs); } } + +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) +{ + struct dc_stream_state *stream_state; + struct drm_device *drm_dev = NULL; + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct amdgpu_crtc *acrtc = NULL; + struct amdgpu_device *adev = NULL; + struct crc_rd_work *crc_rd_wrk = NULL; + struct crc_params *crc_window = NULL, tmp_window; + unsigned long flags1, flags2; + struct crtc_position position; + uint32_t v_blank; + uint32_t v_back_porch; + uint32_t crc_window_latch_up_line; + struct dc_crtc_timing *timing_out; + + if (crtc == NULL) + return; + + acrtc = to_amdgpu_crtc(crtc); + adev = drm_to_adev(crtc->dev); + drm_dev = crtc->dev; + + spin_lock_irqsave(&drm_dev->event_lock, flags1); + stream_state = acrtc->dm_irq_params.stream; + cur_crc_src = acrtc->dm_irq_params.crc_src; + timing_out = &stream_state->timing; + + /* Early return if CRC capture is not enabled. */ + if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) + goto cleanup; + + if (dm_is_crc_source_crtc(cur_crc_src)) { + if (acrtc->dm_irq_params.crc_window.activated) { + if (acrtc->dm_irq_params.crc_window.update_win) { + if (acrtc->dm_irq_params.crc_window.skip_frame_cnt) { + acrtc->dm_irq_params.crc_window.skip_frame_cnt -= 1; + goto cleanup; + } + crc_window = &tmp_window; + + tmp_window.windowa_x_start = + acrtc->dm_irq_params.crc_window.x_start; + tmp_window.windowa_y_start = + acrtc->dm_irq_params.crc_window.y_start; + tmp_window.windowa_x_end = + acrtc->dm_irq_params.crc_window.x_end; + tmp_window.windowa_y_end = + acrtc->dm_irq_params.crc_window.y_end; + tmp_window.windowb_x_start = + acrtc->dm_irq_params.crc_window.x_start; + tmp_window.windowb_y_start = + acrtc->dm_irq_params.crc_window.y_start; + tmp_window.windowb_x_end = + acrtc->dm_irq_params.crc_window.x_end; + tmp_window.windowb_y_end = + acrtc->dm_irq_params.crc_window.y_end; + + dc_stream_forward_dmcu_crc_window(stream_state->ctx->dc, + stream_state, crc_window); + + acrtc->dm_irq_params.crc_window.update_win = false; + + dc_stream_get_crtc_position(stream_state->ctx->dc, &stream_state, 1, + &position.vertical_count, + &position.nominal_vcount); + + v_blank = timing_out->v_total - timing_out->v_border_top - + timing_out->v_addressable - timing_out->v_border_bottom; + + v_back_porch = v_blank - timing_out->v_front_porch - + timing_out->v_sync_width; + + crc_window_latch_up_line = v_back_porch + timing_out->v_sync_width; + + /* take 3 lines margin*/ + if ((position.vertical_count + 3) >= crc_window_latch_up_line) + acrtc->dm_irq_params.crc_window.skip_frame_cnt = 1; + else + acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; + } else { + if (acrtc->dm_irq_params.crc_window.skip_frame_cnt == 0) { + if (adev->dm.crc_rd_wrk) { + crc_rd_wrk = adev->dm.crc_rd_wrk; + spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2); + crc_rd_wrk->phy_inst = + stream_state->link->link_enc_hw_inst; + spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2); + schedule_work(&crc_rd_wrk->notify_ta_work); + } + } else { + acrtc->dm_irq_params.crc_window.skip_frame_cnt -= 1; + } + } + } + } + +cleanup: + spin_unlock_irqrestore(&drm_dev->event_lock, flags1); +} + +void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev) +{ + struct drm_crtc *crtc; + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; + struct crc_window_parm cur_crc_window; + struct amdgpu_crtc *acrtc = NULL; + + drm_for_each_crtc(crtc, &adev->ddev) { + acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&adev_to_drm(adev)->event_lock); + cur_crc_src = acrtc->dm_irq_params.crc_src; + cur_crc_window = acrtc->dm_irq_params.crc_window; + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + + if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { + amdgpu_dm_crtc_set_crc_source(crtc, + pipe_crc_sources[cur_crc_src]); + spin_lock_irq(&adev_to_drm(adev)->event_lock); + acrtc->dm_irq_params.crc_window = cur_crc_window; + if (acrtc->dm_irq_params.crc_window.activated) { + acrtc->dm_irq_params.crc_window.update_win = true; + acrtc->dm_irq_params.crc_window.skip_frame_cnt = 1; + spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); + crc_rd_wrk->crtc = crtc; + spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); + } + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + } + } +} + +void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev) +{ + struct drm_crtc *crtc; + struct crc_window_parm cur_crc_window; + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct amdgpu_crtc *acrtc = NULL; + + drm_for_each_crtc(crtc, &adev->ddev) { + acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&adev_to_drm(adev)->event_lock); + cur_crc_src = acrtc->dm_irq_params.crc_src; + cur_crc_window = acrtc->dm_irq_params.crc_window; + cur_crc_window.update_win = false; + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + + if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { + amdgpu_dm_crtc_set_crc_source(crtc, NULL); + spin_lock_irq(&adev_to_drm(adev)->event_lock); + /* For resume to set back crc source*/ + acrtc->dm_irq_params.crc_src = cur_crc_src; + acrtc->dm_irq_params.crc_window = cur_crc_window; + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + } + } + +} + +struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void) +{ + struct crc_rd_work *crc_rd_wrk = NULL; + + crc_rd_wrk = kzalloc(sizeof(*crc_rd_wrk), GFP_KERNEL); + + if (!crc_rd_wrk) + return NULL; + + spin_lock_init(&crc_rd_wrk->crc_rd_work_lock); + INIT_WORK(&crc_rd_wrk->notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); + + return crc_rd_wrk; +} +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index f7d731797d3fc339389ace86c5b27c56b6152b51..737e701fb0f0a028797687061b6a6a6ce1bf72ea 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -39,6 +39,29 @@ enum amdgpu_dm_pipe_crc_source { AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, }; +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +struct crc_window_parm { + uint16_t x_start; + uint16_t y_start; + uint16_t x_end; + uint16_t y_end; + /* CRC windwo is activated or not*/ + bool activated; + /* Update crc window during vertical blank or not */ + bool update_win; + /* skip reading/writing for few frames */ + int skip_frame_cnt; +}; + +struct crc_rd_work { + struct work_struct notify_ta_work; + /* To protect crc_rd_work carried fields*/ + spinlock_t crc_rd_work_lock; + struct drm_crtc *crtc; + uint8_t phy_inst; +}; +#endif + static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source) { return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) && @@ -64,4 +87,18 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #define amdgpu_dm_crtc_handle_crc_irq(x) #endif +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); +void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); +struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void); +void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev); +void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev); +#else +#define amdgpu_dm_crc_window_is_activated(x) +#define amdgpu_dm_crtc_handle_crc_window_irq(x) +#define amdgpu_dm_crtc_secure_display_create_work() +#define amdgpu_dm_crtc_secure_display_resume(x) +#define amdgpu_dm_crtc_secure_display_suspend(x) +#endif + #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 360952129b6d5a2b6ffe6bbc3a3004a4c1e20946..927de7678a4f8742109d926261a0d7980d63700a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -25,8 +25,6 @@ #include -#include - #include "dc.h" #include "amdgpu.h" #include "amdgpu_dm.h" @@ -36,6 +34,7 @@ #include "resource.h" #include "dsc.h" #include "dc_link_dp.h" +#include "dc/dc_dmub_srv.h" struct dmub_debugfs_trace_header { uint32_t entry_count; @@ -2154,6 +2153,149 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, return result; } + +/* + * function description: Read max_requested_bpc property from the connector + * + * Access it with the following command: + * + * cat /sys/kernel/debug/dri/0/DP-X/max_bpc + * + */ +static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; + struct drm_connector *connector = &aconnector->base; + struct drm_device *dev = connector->dev; + struct dm_connector_state *state; + ssize_t result = 0; + char *rd_buf = NULL; + char *rd_buf_ptr = NULL; + const uint32_t rd_buf_size = 10; + int r; + + rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); + + if (!rd_buf) + return -ENOMEM; + + mutex_lock(&dev->mode_config.mutex); + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + + if (connector->state == NULL) + goto unlock; + + state = to_dm_connector_state(connector->state); + + rd_buf_ptr = rd_buf; + snprintf(rd_buf_ptr, rd_buf_size, + "%u\n", + state->base.max_requested_bpc); + + while (size) { + if (*pos >= rd_buf_size) + break; + + r = put_user(*(rd_buf + result), buf); + if (r) { + result = r; /* r = -EFAULT */ + goto unlock; + } + buf += 1; + size -= 1; + *pos += 1; + result += 1; + } +unlock: + drm_modeset_unlock(&dev->mode_config.connection_mutex); + mutex_unlock(&dev->mode_config.mutex); + kfree(rd_buf); + return result; +} + + +/* + * function description: Set max_requested_bpc property on the connector + * + * This function will not force the input BPC on connector, it will only + * change the max value. This is equivalent to setting max_bpc through + * xrandr. + * + * The BPC value written must be >= 6 and <= 16. Values outside of this + * range will result in errors. + * + * BPC values: + * 0x6 - 6 BPC + * 0x8 - 8 BPC + * 0xa - 10 BPC + * 0xc - 12 BPC + * 0x10 - 16 BPC + * + * Write the max_bpc in the following way: + * + * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc + * + */ +static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; + struct drm_connector *connector = &aconnector->base; + struct dm_connector_state *state; + struct drm_device *dev = connector->dev; + char *wr_buf = NULL; + uint32_t wr_buf_size = 42; + int max_param_num = 1; + long param[1] = {0}; + uint8_t param_nums = 0; + + if (size == 0) + return -EINVAL; + + wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); + + if (!wr_buf) { + DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); + return -ENOSPC; + } + + if (parse_write_buffer_into_params(wr_buf, size, + (long *)param, buf, + max_param_num, + ¶m_nums)) { + kfree(wr_buf); + return -EINVAL; + } + + if (param_nums <= 0) { + DRM_DEBUG_DRIVER("user data not be read\n"); + kfree(wr_buf); + return -EINVAL; + } + + if (param[0] < 6 || param[0] > 16) { + DRM_DEBUG_DRIVER("bad max_bpc value\n"); + kfree(wr_buf); + return -EINVAL; + } + + mutex_lock(&dev->mode_config.mutex); + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + + if (connector->state == NULL) + goto unlock; + + state = to_dm_connector_state(connector->state); + state->base.max_requested_bpc = param[0]; +unlock: + drm_modeset_unlock(&dev->mode_config.connection_mutex); + mutex_unlock(&dev->mode_config.mutex); + + kfree(wr_buf); + return size; +} + DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); @@ -2265,6 +2407,13 @@ static const struct file_operations dp_dpcd_data_debugfs_fops = { .llseek = default_llseek }; +static const struct file_operations dp_max_bpc_debugfs_fops = { + .owner = THIS_MODULE, + .read = dp_max_bpc_read, + .write = dp_max_bpc_write, + .llseek = default_llseek +}; + static const struct { char *name; const struct file_operations *fops; @@ -2287,7 +2436,8 @@ static const struct { {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, - {"dp_dsc_fec_support", &dp_dsc_fec_support_fops} + {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, + {"max_bpc", &dp_max_bpc_debugfs_fops} }; #ifdef CONFIG_DRM_AMD_DC_HDCP @@ -2341,9 +2491,51 @@ static int psr_get(void *data, u64 *val) return 0; } +/* + * Set dmcub trace event IRQ enable or disable. + * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en + * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en + */ +static int dmcub_trace_event_state_set(void *data, u64 val) +{ + struct amdgpu_device *adev = data; + + if (val == 1 || val == 0) { + dc_dmub_trace_event_control(adev->dm.dc, val); + adev->dm.dmcub_trace_event_en = (bool)val; + } else + return 0; + + return 0; +} + +/* + * The interface doesn't need get function, so it will return the + * value of zero + * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en + */ +static int dmcub_trace_event_state_get(void *data, u64 *val) +{ + struct amdgpu_device *adev = data; + + *val = adev->dm.dmcub_trace_event_en; + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, + dmcub_trace_event_state_set, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); +static const struct { + char *name; + const struct file_operations *fops; +} connector_debugfs_entries[] = { + {"force_yuv420_output", &force_yuv420_output_fops}, + {"output_bpc", &output_bpc_fops}, + {"trigger_hotplug", &trigger_hotplug_debugfs_fops} +}; + void connector_debugfs_init(struct amdgpu_dm_connector *connector) { int i; @@ -2360,14 +2552,11 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); - debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector, - &force_yuv420_output_fops); - - debugfs_create_file("output_bpc", 0644, dir, connector, - &output_bpc_fops); - - debugfs_create_file("trigger_hotplug", 0644, dir, connector, - &trigger_hotplug_debugfs_fops); + for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { + debugfs_create_file(connector_debugfs_entries[i].name, + 0644, dir, connector, + connector_debugfs_entries[i].fops); + } connector->debugfs_dpcd_address = 0; connector->debugfs_dpcd_size = 0; @@ -2383,6 +2572,225 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) #endif } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +/* + * Set crc window coordinate x start + */ +static int crc_win_x_start_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; + acrtc->dm_irq_params.crc_window.update_win = false; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +/* + * Get crc window coordinate x start + */ +static int crc_win_x_start_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_window.x_start; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, + crc_win_x_start_set, "%llu\n"); + + +/* + * Set crc window coordinate y start + */ +static int crc_win_y_start_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; + acrtc->dm_irq_params.crc_window.update_win = false; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +/* + * Get crc window coordinate y start + */ +static int crc_win_y_start_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_window.y_start; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, + crc_win_y_start_set, "%llu\n"); + +/* + * Set crc window coordinate x end + */ +static int crc_win_x_end_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; + acrtc->dm_irq_params.crc_window.update_win = false; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +/* + * Get crc window coordinate x end + */ +static int crc_win_x_end_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_window.x_end; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, + crc_win_x_end_set, "%llu\n"); + +/* + * Set crc window coordinate y end + */ +static int crc_win_y_end_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; + acrtc->dm_irq_params.crc_window.update_win = false; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +/* + * Get crc window coordinate y end + */ +static int crc_win_y_end_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_window.y_end; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, + crc_win_y_end_set, "%llu\n"); +/* + * Trigger to commit crc window + */ +static int crc_win_update_set(void *data, u64 val) +{ + struct drm_crtc *new_crtc = data; + struct drm_crtc *old_crtc = NULL; + struct amdgpu_crtc *new_acrtc, *old_acrtc; + struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); + struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; + + if (val) { + spin_lock_irq(&adev_to_drm(adev)->event_lock); + spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); + if (crc_rd_wrk && crc_rd_wrk->crtc) { + old_crtc = crc_rd_wrk->crtc; + old_acrtc = to_amdgpu_crtc(old_crtc); + } + new_acrtc = to_amdgpu_crtc(new_crtc); + + if (old_crtc && old_crtc != new_crtc) { + old_acrtc->dm_irq_params.crc_window.activated = false; + old_acrtc->dm_irq_params.crc_window.update_win = false; + old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; + + new_acrtc->dm_irq_params.crc_window.activated = true; + new_acrtc->dm_irq_params.crc_window.update_win = true; + new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; + crc_rd_wrk->crtc = new_crtc; + } else { + new_acrtc->dm_irq_params.crc_window.activated = true; + new_acrtc->dm_irq_params.crc_window.update_win = true; + new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; + crc_rd_wrk->crtc = new_crtc; + } + spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + } + + return 0; +} + +/* + * Get crc window update flag + */ +static int crc_win_update_get(void *data, u64 *val) +{ + *val = 0; + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, + crc_win_update_set, "%llu\n"); + +void crtc_debugfs_init(struct drm_crtc *crtc) +{ + struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); + + if (!dir) + return; + + debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, + &crc_win_x_start_fops); + debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, + &crc_win_y_start_fops); + debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, + &crc_win_x_end_fops); + debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, + &crc_win_y_end_fops); + debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, + &crc_win_update_fops); + +} +#endif /* * Writes DTN log state to the user supplied buffer. * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log @@ -2450,11 +2858,9 @@ static ssize_t dtn_log_write( * As written to display, taking ABM and backlight lut into account. * Ranges from 0x0 to 0x10000 (= 100% PWM) */ -static int current_backlight_read(struct seq_file *m, void *data) +static int current_backlight_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct amdgpu_display_manager *dm = &adev->dm; unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link); @@ -2468,11 +2874,9 @@ static int current_backlight_read(struct seq_file *m, void *data) * As written to display, taking ABM and backlight lut into account. * Ranges from 0x0 to 0x10000 (= 100% PWM) */ -static int target_backlight_read(struct seq_file *m, void *data) +static int target_backlight_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct amdgpu_display_manager *dm = &adev->dm; unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link); @@ -2481,10 +2885,10 @@ static int target_backlight_read(struct seq_file *m, void *data) return 0; } -static int mst_topo(struct seq_file *m, void *unused) +static int mst_topo_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; struct drm_connector_list_iter conn_iter; struct amdgpu_dm_connector *aconnector; @@ -2504,12 +2908,6 @@ static int mst_topo(struct seq_file *m, void *unused) return 0; } -static const struct drm_info_list amdgpu_dm_debugfs_list[] = { - {"amdgpu_current_backlight_pwm", ¤t_backlight_read}, - {"amdgpu_target_backlight_pwm", &target_backlight_read}, - {"amdgpu_mst_topology", &mst_topo}, -}; - /* * Sets the force_timing_sync debug optino from the given string. * All connected displays will be force synchronized immediately. @@ -2568,10 +2966,13 @@ static int visual_confirm_get(void *data, u64 *val) return 0; } +DEFINE_SHOW_ATTRIBUTE(current_backlight); +DEFINE_SHOW_ATTRIBUTE(target_backlight); +DEFINE_SHOW_ATTRIBUTE(mst_topo); DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); -int dtn_debugfs_init(struct amdgpu_device *adev) +void dtn_debugfs_init(struct amdgpu_device *adev) { static const struct file_operations dtn_log_fops = { .owner = THIS_MODULE, @@ -2582,13 +2983,13 @@ int dtn_debugfs_init(struct amdgpu_device *adev) struct drm_minor *minor = adev_to_drm(adev)->primary; struct dentry *root = minor->debugfs_root; - int ret; - - ret = amdgpu_debugfs_add_files(adev, amdgpu_dm_debugfs_list, - ARRAY_SIZE(amdgpu_dm_debugfs_list)); - if (ret) - return ret; + debugfs_create_file("amdgpu_current_backlight_pwm", 0444, + root, adev, ¤t_backlight_fops); + debugfs_create_file("amdgpu_target_backlight_pwm", 0444, + root, adev, &target_backlight_fops); + debugfs_create_file("amdgpu_mst_topology", 0444, root, + adev, &mst_topo_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); @@ -2604,5 +3005,6 @@ int dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, adev, &force_timing_sync_ops); - return 0; + debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, + adev, &dmcub_trace_event_state_fops); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h index 5e5b2b2afa31cdd2f9cf43daba7d48b08b25f585..3366cb644053c286361a1731a864f43bd09ddd26 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h @@ -30,6 +30,9 @@ #include "amdgpu_dm.h" void connector_debugfs_init(struct amdgpu_dm_connector *connector); -int dtn_debugfs_init(struct amdgpu_device *adev); +void dtn_debugfs_init(struct amdgpu_device *adev); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +void crtc_debugfs_init(struct drm_crtc *crtc); +#endif #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 5750818db8f6fe47e3b3b73444ec359f951fc0e5..09bdffb3a09e93c9b230cb58f38e5b198a715923 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -652,14 +652,54 @@ void *dm_helpers_allocate_gpu_mem( size_t size, long long *addr) { - // TODO - return NULL; + struct amdgpu_device *adev = ctx->driver_context; + struct dal_allocation *da; + u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? + AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; + int ret; + + da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); + if (!da) + return NULL; + + ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, + domain, &da->bo, + &da->gpu_addr, &da->cpu_ptr); + + *addr = da->gpu_addr; + + if (ret) { + kfree(da); + return NULL; + } + + /* add da to list in dm */ + list_add(&da->list, &adev->dm.da_list); + + return da->cpu_ptr; } void dm_helpers_free_gpu_mem( struct dc_context *ctx, enum dc_gpu_mem_alloc_type type, void *pvMem) +{ + struct amdgpu_device *adev = ctx->driver_context; + struct dal_allocation *da; + + /* walk the da list in DM */ + list_for_each_entry(da, &adev->dm.da_list, list) { + if (pvMem == da->cpu_ptr) { + amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); + list_del(&da->list); + kfree(da); + break; + } + } +} + +bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable) { // TODO + return true; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index e0000c180ed1f035b37263c8e8d8e14e059fefa9..d3c687d07ee66e3330bc22770eb8a275c7c19699 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -82,6 +82,7 @@ struct amdgpu_dm_irq_handler_data { struct amdgpu_display_manager *dm; /* DAL irq source which registered for this interrupt. */ enum dc_irq_source irq_source; + struct work_struct work; }; #define DM_IRQ_TABLE_LOCK(adev, flags) \ @@ -111,20 +112,10 @@ static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd, */ static void dm_irq_work_func(struct work_struct *work) { - struct irq_list_head *irq_list_head = - container_of(work, struct irq_list_head, work); - struct list_head *handler_list = &irq_list_head->head; - struct amdgpu_dm_irq_handler_data *handler_data; - - list_for_each_entry(handler_data, handler_list, list) { - DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n", - handler_data->irq_source); + struct amdgpu_dm_irq_handler_data *handler_data = + container_of(work, struct amdgpu_dm_irq_handler_data, work); - DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n", - handler_data->irq_source); - - handler_data->handler(handler_data->handler_arg); - } + handler_data->handler(handler_data->handler_arg); /* Call a DAL subcomponent which registered for interrupt notification * at INTERRUPT_LOW_IRQ_CONTEXT. @@ -156,7 +147,7 @@ static struct list_head *remove_irq_handler(struct amdgpu_device *adev, break; case INTERRUPT_LOW_IRQ_CONTEXT: default: - hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head; + hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source]; break; } @@ -290,7 +281,8 @@ void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev, break; case INTERRUPT_LOW_IRQ_CONTEXT: default: - hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head; + hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source]; + INIT_WORK(&handler_data->work, dm_irq_work_func); break; } @@ -372,7 +364,7 @@ void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, int amdgpu_dm_irq_init(struct amdgpu_device *adev) { int src; - struct irq_list_head *lh; + struct list_head *lh; DRM_DEBUG_KMS("DM_IRQ\n"); @@ -381,9 +373,7 @@ int amdgpu_dm_irq_init(struct amdgpu_device *adev) for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) { /* low context handler list init */ lh = &adev->dm.irq_handler_list_low_tab[src]; - INIT_LIST_HEAD(&lh->head); - INIT_WORK(&lh->work, dm_irq_work_func); - + INIT_LIST_HEAD(lh); /* high context handler init */ INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]); } @@ -400,8 +390,11 @@ int amdgpu_dm_irq_init(struct amdgpu_device *adev) void amdgpu_dm_irq_fini(struct amdgpu_device *adev) { int src; - struct irq_list_head *lh; + struct list_head *lh; + struct list_head *entry, *tmp; + struct amdgpu_dm_irq_handler_data *handler; unsigned long irq_table_flags; + DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n"); for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) { DM_IRQ_TABLE_LOCK(adev, irq_table_flags); @@ -410,7 +403,16 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev) * (because no code can schedule a new one). */ lh = &adev->dm.irq_handler_list_low_tab[src]; DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); - flush_work(&lh->work); + + if (!list_empty(lh)) { + list_for_each_safe(entry, tmp, lh) { + handler = list_entry( + entry, + struct amdgpu_dm_irq_handler_data, + list); + flush_work(&handler->work); + } + } } } @@ -420,6 +422,8 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev) struct list_head *hnd_list_h; struct list_head *hnd_list_l; unsigned long irq_table_flags; + struct list_head *entry, *tmp; + struct amdgpu_dm_irq_handler_data *handler; DM_IRQ_TABLE_LOCK(adev, irq_table_flags); @@ -430,14 +434,22 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev) * will be disabled from manage_dm_interrupts on disable CRTC. */ for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) { - hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; + hnd_list_l = &adev->dm.irq_handler_list_low_tab[src]; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) dc_interrupt_set(adev->dm.dc, src, false); DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); - flush_work(&adev->dm.irq_handler_list_low_tab[src].work); + if (!list_empty(hnd_list_l)) { + list_for_each_safe (entry, tmp, hnd_list_l) { + handler = list_entry( + entry, + struct amdgpu_dm_irq_handler_data, + list); + flush_work(&handler->work); + } + } DM_IRQ_TABLE_LOCK(adev, irq_table_flags); } @@ -457,7 +469,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) /* re-enable short pulse interrupts HW interrupt */ for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) { - hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; + hnd_list_l = &adev->dm.irq_handler_list_low_tab[src]; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) dc_interrupt_set(adev->dm.dc, src, true); @@ -483,7 +495,7 @@ int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) * will be enabled from manage_dm_interrupts on enable CRTC. */ for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) { - hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; + hnd_list_l = &adev->dm.irq_handler_list_low_tab[src]; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) dc_interrupt_set(adev->dm.dc, src, true); @@ -500,22 +512,51 @@ int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev, enum dc_irq_source irq_source) { - unsigned long irq_table_flags; - struct work_struct *work = NULL; + struct list_head *handler_list = &adev->dm.irq_handler_list_low_tab[irq_source]; + struct amdgpu_dm_irq_handler_data *handler_data; + bool work_queued = false; - DM_IRQ_TABLE_LOCK(adev, irq_table_flags); + if (list_empty(handler_list)) + return; - if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head)) - work = &adev->dm.irq_handler_list_low_tab[irq_source].work; + list_for_each_entry (handler_data, handler_list, list) { + if (queue_work(system_highpri_wq, &handler_data->work)) { + work_queued = true; + break; + } + } - DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); + if (!work_queued) { + struct amdgpu_dm_irq_handler_data *handler_data_add; + /*get the amdgpu_dm_irq_handler_data of first item pointed by handler_list*/ + handler_data = container_of(handler_list->next, struct amdgpu_dm_irq_handler_data, list); - if (work) { - if (!schedule_work(work)) - DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n", - irq_source); - } + /*allocate a new amdgpu_dm_irq_handler_data*/ + handler_data_add = kzalloc(sizeof(*handler_data), GFP_KERNEL); + if (!handler_data_add) { + DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n"); + return; + } + + /*copy new amdgpu_dm_irq_handler_data members from handler_data*/ + handler_data_add->handler = handler_data->handler; + handler_data_add->handler_arg = handler_data->handler_arg; + handler_data_add->dm = handler_data->dm; + handler_data_add->irq_source = irq_source; + list_add_tail(&handler_data_add->list, handler_list); + + INIT_WORK(&handler_data_add->work, dm_irq_work_func); + + if (queue_work(system_highpri_wq, &handler_data_add->work)) + DRM_DEBUG("Queued work for handling interrupt from " + "display for IRQ source %d\n", + irq_source); + else + DRM_ERROR("Failed to queue work for handling interrupt " + "from display for IRQ source %d\n", + irq_source); + } } /* diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h index 45825a34f8ebb11b731c227e174865a67390011f..f3b93ba69a27031eaec628321ee1859f746f0282 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h @@ -26,12 +26,21 @@ #ifndef __AMDGPU_DM_IRQ_PARAMS_H__ #define __AMDGPU_DM_IRQ_PARAMS_H__ +#include "amdgpu_dm_crc.h" + struct dm_irq_params { u32 last_flip_vblank; struct mod_vrr_params vrr_params; struct dc_stream_state *stream; int active_planes; struct mod_freesync_config freesync_config; + +#ifdef CONFIG_DEBUG_FS + enum amdgpu_dm_pipe_crc_source crc_src; +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + struct crc_window_parm crc_window; +#endif +#endif }; #endif /* __AMDGPU_DM_IRQ_PARAMS_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 41b09ab22233a438674807a746a31d1fa7570647..73cdb9fe981a3f9fd6fc4e5af6f349c0c0dd6801 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -38,6 +38,7 @@ #include "dc_link_ddc.h" #include "i2caux_interface.h" +#include "dmub_cmd.h" #if defined(CONFIG_DEBUG_FS) #include "amdgpu_dm_debugfs.h" #endif @@ -51,7 +52,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, { ssize_t result = 0; struct aux_payload payload; - enum aux_channel_operation_result operation_result; + enum aux_return_code_type operation_result; if (WARN_ON(msg->size > 16)) return -E2BIG; @@ -73,17 +74,19 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, if (result < 0) switch (operation_result) { - case AUX_CHANNEL_OPERATION_SUCCEEDED: + case AUX_RET_SUCCESS: break; - case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON: - case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN: + case AUX_RET_ERROR_HPD_DISCON: + case AUX_RET_ERROR_UNKNOWN: + case AUX_RET_ERROR_INVALID_OPERATION: + case AUX_RET_ERROR_PROTOCOL_ERROR: result = -EIO; break; - case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY: - case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE: + case AUX_RET_ERROR_INVALID_REPLY: + case AUX_RET_ERROR_ENGINE_ACQUIRE: result = -EBUSY; break; - case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT: + case AUX_RET_ERROR_TIMEOUT: result = -ETIMEDOUT; break; } diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 5bf2f2375b40df208e3f41572bffc84134e1ac23..bbde6e6a4e4350a7ac00bb6fe8a8fbff48b21d8e 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -54,7 +54,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI include $(AMD_DC) -DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ +DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o ifdef CONFIG_DRM_AMD_DC_DCN diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c index ad04ef98e652b1a214d73207245f40adc57fafde..b2fc4f8e64825086855b28a11099312f2d06e5f8 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c @@ -49,24 +49,20 @@ bool is_rgb_cspace(enum dc_color_space output_color_space) } } -bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx) +bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) return true; - if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe)) - return true; - if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe)) + if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; return false; } -bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx) +bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) return true; - if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe)) - return true; - if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe)) + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; return false; } @@ -75,13 +71,9 @@ bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) return true; - if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe)) - return true; - if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe)) - return true; - if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe)) + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; - if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe)) + if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; return false; } diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h index b061497480b8d1ec151d3159571e8c8b905945c0..7c0cbf47e8cebabb05244a00f7f8b121fd78dc1a 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h +++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h @@ -30,9 +30,9 @@ bool is_rgb_cspace(enum dc_color_space output_color_space); -bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx); +bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx); -bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx); +bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx); bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 9f9fda3118d1fbc730983f6c1c0f7cea839af408..b208f06ed5149121dc394d9e42de1f38cc714333 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -1180,14 +1180,15 @@ static enum bp_result bios_parser_enable_disp_power_gating( static enum bp_result bios_parser_enable_lvtma_control( struct dc_bios *dcb, - uint8_t uc_pwr_on) + uint8_t uc_pwr_on, + uint8_t panel_instance) { struct bios_parser *bp = BP_FROM_DCB(dcb); if (!bp->cmd_tbl.enable_lvtma_control) return BP_RESULT_FAILURE; - return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on); + return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); } static bool bios_parser_is_accelerated_mode( diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c index fce46ab54c5436e92bd8175835e9edca199f256b..53d7513b50832a66251a626d08900149bf3bda17 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c @@ -64,9 +64,10 @@ bool bios_is_accelerated_mode( void bios_set_scratch_acc_mode_change( - struct dc_bios *bios) + struct dc_bios *bios, + uint32_t state) { - REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1); + REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, state); } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h index 75a29e68fb2782ad667f858b4f235aeccdcc8ace..e1b4a40a353db1cc3a56840f6999f6e9a84c1cc2 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h @@ -32,7 +32,7 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset, uint32_t size); bool bios_is_accelerated_mode(struct dc_bios *bios); -void bios_set_scratch_acc_mode_change(struct dc_bios *bios); +void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state); void bios_set_scratch_critical_state(struct dc_bios *bios, bool state); uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios); diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index afc10b954ffa7b67cb52131e6ac32e3bb0036e1f..ad13e4e36d779047634c6bc2fcc1b677ba9a436b 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -1531,6 +1531,27 @@ static enum bp_result adjust_display_pll_v2( params.ucEncodeMode = (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom( bp_params->signal_type, false); + + if (EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) { + /* Convert output pixel clock back 10KHz-->KHz: multiply + * original pixel clock in KHz by ratio + * [output pxlClk/input pxlClk] */ + uint64_t pixel_clk_10_khz_out = + (uint64_t)le16_to_cpu(params.usPixelClock); + uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; + + if (pixel_clock_10KHz_in != 0) { + bp_params->adjusted_pixel_clock = + div_u64(pixel_clk * pixel_clk_10_khz_out, + pixel_clock_10KHz_in); + } else { + bp_params->adjusted_pixel_clock = 0; + BREAK_TO_DEBUGGER(); + } + + result = BP_RESULT_OK; + } + return result; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 25bdf1c38e0ad8ffd905b736fdb911ce1e42d97b..f1f672a997d7db4d02e4ceff21dc4b842df708ab 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -218,6 +218,10 @@ static enum bp_result transmitter_control_v1_6( struct bios_parser *bp, struct bp_transmitter_control *cntl); +static enum bp_result transmitter_control_v1_7( + struct bios_parser *bp, + struct bp_transmitter_control *cntl); + static enum bp_result transmitter_control_fallback( struct bios_parser *bp, struct bp_transmitter_control *cntl); @@ -233,6 +237,9 @@ static void init_transmitter_control(struct bios_parser *bp) case 6: bp->cmd_tbl.transmitter_control = transmitter_control_v1_6; break; + case 7: + bp->cmd_tbl.transmitter_control = transmitter_control_v1_7; + break; default: dm_output_to_console("Don't have transmitter_control for v%d\n", crev); bp->cmd_tbl.transmitter_control = transmitter_control_fallback; @@ -304,13 +311,76 @@ static enum bp_result transmitter_control_v1_6( return result; } +static void transmitter_control_dmcub_v1_7( + struct dc_dmub_srv *dmcub, + struct dmub_dig_transmitter_control_data_v1_7 *dig) +{ + union dmub_rb_cmd cmd; + + memset(&cmd, 0, sizeof(cmd)); + + cmd.dig1_transmitter_control.header.type = DMUB_CMD__VBIOS; + cmd.dig1_transmitter_control.header.sub_type = + DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL; + cmd.dig1_transmitter_control.header.payload_bytes = + sizeof(cmd.dig1_transmitter_control) - + sizeof(cmd.dig1_transmitter_control.header); + cmd.dig1_transmitter_control.transmitter_control.dig_v1_7 = *dig; + + dc_dmub_srv_cmd_queue(dmcub, &cmd); + dc_dmub_srv_cmd_execute(dmcub); + dc_dmub_srv_wait_idle(dmcub); +} + +static enum bp_result transmitter_control_v1_7( + struct bios_parser *bp, + struct bp_transmitter_control *cntl) +{ + enum bp_result result = BP_RESULT_FAILURE; + const struct command_table_helper *cmd = bp->cmd_helper; + struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0}; + + dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter); + dig_v1_7.action = (uint8_t)cntl->action; + + if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS) + dig_v1_7.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; + else + dig_v1_7.mode_laneset.digmode = + cmd->signal_type_to_atom_dig_mode(cntl->signal); + + dig_v1_7.lanenum = (uint8_t)cntl->lanes_number; + dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel); + dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id); + dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id; + dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10; + + if (cntl->action == TRANSMITTER_CONTROL_ENABLE || + cntl->action == TRANSMITTER_CONTROL_ACTIAVATE || + cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) { + DC_LOG_BIOS("%s:dig_v1_7.symclk_units.symclk_10khz = %d\n", + __func__, dig_v1_7.symclk_units.symclk_10khz); + } + + if (bp->base.ctx->dc->ctx->dmub_srv && + bp->base.ctx->dc->debug.dmub_command_table) { + transmitter_control_dmcub_v1_7(bp->base.ctx->dmub_srv, &dig_v1_7); + return BP_RESULT_OK; + } + +/*color_depth not used any more, driver has deep color factor in the Phyclk*/ + if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, dig_v1_7)) + result = BP_RESULT_OK; + return result; +} + static enum bp_result transmitter_control_fallback( struct bios_parser *bp, struct bp_transmitter_control *cntl) { if (bp->base.ctx->dc->ctx->dmub_srv && bp->base.ctx->dc->debug.dmub_command_table) { - return transmitter_control_v1_6(bp, cntl); + return transmitter_control_v1_7(bp, cntl); } return BP_RESULT_FAILURE; @@ -911,7 +981,8 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id) static enum bp_result enable_lvtma_control( struct bios_parser *bp, - uint8_t uc_pwr_on); + uint8_t uc_pwr_on, + uint8_t panel_instance); static void init_enable_lvtma_control(struct bios_parser *bp) { @@ -922,19 +993,21 @@ static void init_enable_lvtma_control(struct bios_parser *bp) static void enable_lvtma_control_dmcub( struct dc_dmub_srv *dmcub, - uint8_t uc_pwr_on) + uint8_t uc_pwr_on, + uint8_t panel_instance) { union dmub_rb_cmd cmd; memset(&cmd, 0, sizeof(cmd)); - cmd.cmd_common.header.type = DMUB_CMD__VBIOS; - cmd.cmd_common.header.sub_type = + cmd.lvtma_control.header.type = DMUB_CMD__VBIOS; + cmd.lvtma_control.header.sub_type = DMUB_CMD__VBIOS_LVTMA_CONTROL; - cmd.cmd_common.cmd_buffer[0] = + cmd.lvtma_control.data.uc_pwr_action = uc_pwr_on; - + cmd.lvtma_control.data.panel_inst = + panel_instance; dc_dmub_srv_cmd_queue(dmcub, &cmd); dc_dmub_srv_cmd_execute(dmcub); dc_dmub_srv_wait_idle(dmcub); @@ -943,14 +1016,16 @@ static void enable_lvtma_control_dmcub( static enum bp_result enable_lvtma_control( struct bios_parser *bp, - uint8_t uc_pwr_on) + uint8_t uc_pwr_on, + uint8_t panel_instance) { enum bp_result result = BP_RESULT_FAILURE; if (bp->base.ctx->dc->ctx->dmub_srv && bp->base.ctx->dc->debug.dmub_command_table) { enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv, - uc_pwr_on); + uc_pwr_on, + panel_instance); return BP_RESULT_OK; } return result; diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h index 7bdce013cde5ab781a58b2fa832968a5ab6a1b7e..be060b4b87db6ab6af023fde4c42ef8cba6ebc74 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h @@ -95,7 +95,8 @@ struct cmd_tbl { unsigned int (*get_smu_clock_info)( struct bios_parser *bp, uint8_t id); enum bp_result (*enable_lvtma_control)(struct bios_parser *bp, - uint8_t uc_pwr_on); + uint8_t uc_pwr_on, + uint8_t panel_instance); }; void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 995ffbbf64e7ca104f5205f84b1b6c24796e04a4..f7c728d4f50a0c75f57cb1a442ea20f57eb4d37b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -87,12 +87,16 @@ int clk_mgr_helper_get_active_plane_cnt( void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) { - struct dc_link *edp_link = get_edp_link(dc); + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link = NULL; + int edp_num; + get_edp_links(dc, edp_links, &edp_num); if (dc->hwss.exit_optimized_pwr_state) dc->hwss.exit_optimized_pwr_state(dc, dc->current_state); - if (edp_link) { + if (edp_num) { + edp_link = edp_links[0]; clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; dc_link_set_psr_allow_active(edp_link, false, false, false); } @@ -101,11 +105,16 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) { - struct dc_link *edp_link = get_edp_link(dc); + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link = NULL; + int edp_num; - if (edp_link) + get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + edp_link = edp_links[0]; dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false, false); + } if (dc->hwss.optimize_pwr_state) dc->hwss.optimize_pwr_state(dc, dc->current_state); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index ec9dc265cde0c4d2def10eeb8f353074e219bd35..372d53b5a34d4506f616d6cfa50d22ddeccf0098 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -361,7 +361,7 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); - dpp_divider = dentist_get_divider_from_did(dispclk_wdivider); + dpp_divider = dentist_get_divider_from_did(dppclk_wdivider); if (disp_divider && dpp_divider) { /* Calculate the current DFS clock, in kHz.*/ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index c7e5a64e06afb0a5735c5b33ce0a90ac2e938bb0..81ea5d3a1947bba1f0806cb456ad6fd699a86b99 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -252,6 +252,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, bool force_reset = false; bool update_uclk = false; bool p_state_change_support; + int total_plane_count; if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present) return; @@ -292,7 +293,8 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; - p_state_change_support = new_clocks->p_state_change_support || (display_count == 0); + total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); + p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { clk_mgr_base->clks.p_state_change_support = p_state_change_support; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8f8a13c7cf73d6bdc6efca08cc63c143d3be607b..8e6c815b55d2dc590f5f27a579bb210679587816 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -41,6 +41,7 @@ #include "dc_bios_types.h" #include "bios_parser_interface.h" +#include "bios/bios_parser_helper.h" #include "include/irq_service_interface.h" #include "transform.h" #include "dmcu.h" @@ -68,6 +69,7 @@ #include "dmub/dmub_srv.h" +#include "i2caux_interface.h" #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" @@ -163,6 +165,18 @@ static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_li return count; } +static int get_seamless_boot_stream_count(struct dc_state *ctx) +{ + uint8_t i; + uint8_t seamless_boot_stream_count = 0; + + for (i = 0; i < ctx->stream_count; i++) + if (ctx->streams[i]->apply_seamless_boot_optimization) + seamless_boot_stream_count++; + + return seamless_boot_stream_count; +} + static bool create_links( struct dc *dc, uint32_t num_virtual_links) @@ -334,6 +348,88 @@ bool dc_stream_get_crtc_position(struct dc *dc, return ret; } +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream, + struct crc_params *crc_window) +{ + int i; + struct dmcu *dmcu = dc->res_pool->dmcu; + struct pipe_ctx *pipe; + struct crc_region tmp_win, *crc_win; + struct otg_phy_mux mapping_tmp, *mux_mapping; + + /*crc window can't be null*/ + if (!crc_window) + return false; + + if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) { + crc_win = &tmp_win; + mux_mapping = &mapping_tmp; + /*set crc window*/ + tmp_win.x_start = crc_window->windowa_x_start; + tmp_win.y_start = crc_window->windowa_y_start; + tmp_win.x_end = crc_window->windowa_x_end; + tmp_win.y_end = crc_window->windowa_y_end; + + for (i = 0; i < MAX_PIPES; i++) { + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) + break; + } + + /* Stream not found */ + if (i == MAX_PIPES) + return false; + + + /*set mux routing info*/ + mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; + mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; + + dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping); + } else { + DC_LOG_DC("dmcu is not initialized"); + return false; + } + + return true; +} + +bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream) +{ + int i; + struct dmcu *dmcu = dc->res_pool->dmcu; + struct pipe_ctx *pipe; + struct otg_phy_mux mapping_tmp, *mux_mapping; + + if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) { + mux_mapping = &mapping_tmp; + + for (i = 0; i < MAX_PIPES; i++) { + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) + break; + } + + /* Stream not found */ + if (i == MAX_PIPES) + return false; + + + /*set mux routing info*/ + mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; + mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; + + dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping); + } else { + DC_LOG_DC("dmcu is not initialized"); + return false; + } + + return true; +} +#endif + /** * dc_stream_configure_crc() - Configure CRC capture for the given stream. * @dc: DC Object @@ -970,7 +1066,6 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count, dc->res_pool->stream_enc_count); - dc->optimize_seamless_boot_streams = 0; dc->caps.max_links = dc->link_count; dc->caps.max_audios = dc->res_pool->audio_count; dc->caps.linear_pitch_alignment = 64; @@ -1000,22 +1095,25 @@ struct dc *dc_create(const struct dc_init_data *init_params) static void detect_edp_presence(struct dc *dc) { - struct dc_link *edp_link = get_edp_link(dc); - bool edp_sink_present = true; + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link = NULL; + enum dc_connection_type type; + int i; + int edp_num; - if (!edp_link) + get_edp_links(dc, edp_links, &edp_num); + if (!edp_num) return; - if (dc->config.edp_not_connected) { - edp_sink_present = false; - } else { - enum dc_connection_type type; - dc_link_detect_sink(edp_link, &type); - if (type == dc_connection_none) - edp_sink_present = false; + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (dc->config.edp_not_connected) { + edp_link->edp_sink_present = false; + } else { + dc_link_detect_sink(edp_link, &type); + edp_link->edp_sink_present = (type != dc_connection_none); + } } - - edp_link->edp_sink_present = edp_sink_present; } void dc_hardware_init(struct dc *dc) @@ -1091,6 +1189,7 @@ static void program_timing_sync( for (i = 0; i < pipe_count; i++) { int group_size = 1; + enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE; struct pipe_ctx *pipe_set[MAX_PIPES]; if (!unsynced_pipes[i]) @@ -1105,10 +1204,22 @@ static void program_timing_sync( for (j = i + 1; j < pipe_count; j++) { if (!unsynced_pipes[j]) continue; - - if (resource_are_streams_timing_synchronizable( + if (sync_type != TIMING_SYNCHRONIZABLE && + dc->hwss.enable_vblanks_synchronization && + unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks && + resource_are_vblanks_synchronizable( + unsynced_pipes[j]->stream, + pipe_set[0]->stream)) { + sync_type = VBLANK_SYNCHRONIZABLE; + pipe_set[group_size] = unsynced_pipes[j]; + unsynced_pipes[j] = NULL; + group_size++; + } else + if (sync_type != VBLANK_SYNCHRONIZABLE && + resource_are_streams_timing_synchronizable( unsynced_pipes[j]->stream, pipe_set[0]->stream)) { + sync_type = TIMING_SYNCHRONIZABLE; pipe_set[group_size] = unsynced_pipes[j]; unsynced_pipes[j] = NULL; group_size++; @@ -1134,7 +1245,6 @@ static void program_timing_sync( } } - for (k = 0; k < group_size; k++) { struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream); @@ -1164,8 +1274,14 @@ static void program_timing_sync( } if (group_size > 1) { - dc->hwss.enable_timing_synchronization( - dc, group_index, group_size, pipe_set); + if (sync_type == TIMING_SYNCHRONIZABLE) { + dc->hwss.enable_timing_synchronization( + dc, group_index, group_size, pipe_set); + } else + if (sync_type == VBLANK_SYNCHRONIZABLE) { + dc->hwss.enable_vblanks_synchronization( + dc, group_index, group_size, pipe_set); + } group_index++; } num_group++; @@ -1202,8 +1318,9 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc, unsigned int i, enc_inst, tg_inst = 0; // Seamless port only support single DP and EDP so far - if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT && - sink->sink_signal != SIGNAL_TYPE_EDP) + if ((sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT && + sink->sink_signal != SIGNAL_TYPE_EDP) || + sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) return false; /* Check for enabled DIG to identify enabled display */ @@ -1377,11 +1494,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc->hwss.enable_accelerated_mode(dc, context); } - for (i = 0; i < context->stream_count; i++) - if (context->streams[i]->apply_seamless_boot_optimization) - dc->optimize_seamless_boot_streams++; - - if (context->stream_count > dc->optimize_seamless_boot_streams || + if (context->stream_count > get_seamless_boot_stream_count(context) || context->stream_count == 0) dc->hwss.prepare_bandwidth(dc, context); @@ -1464,7 +1577,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - if (context->stream_count > dc->optimize_seamless_boot_streams || + if (context->stream_count > get_seamless_boot_stream_count(context) || context->stream_count == 0) { /* Must wait for no flips to be pending before doing optimize bw */ wait_for_no_pipes_pending(dc, context); @@ -1578,7 +1691,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) int i; struct dc_state *context = dc->current_state; - if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0) + if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0) return; post_surface_trace(dc); @@ -2277,8 +2390,6 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->dither_option) stream->dither_option = *update->dither_option; - if (update->pending_test_pattern) - stream->test_pattern = *update->pending_test_pattern; /* update current stream with writeback info */ if (update->wb_update) { int i; @@ -2324,7 +2435,6 @@ static void commit_planes_do_stream_update(struct dc *dc, struct dc_state *context) { int j; - bool should_program_abm; // Stream updates for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -2375,15 +2485,6 @@ static void commit_planes_do_stream_update(struct dc *dc, } } - if (stream_update->pending_test_pattern) { - dc_link_dp_set_test_pattern(stream->link, - stream->test_pattern.type, - stream->test_pattern.color_space, - stream->test_pattern.p_link_settings, - stream->test_pattern.p_custom_pattern, - stream->test_pattern.cust_pattern_size); - } - /* Full fe update*/ if (update_type == UPDATE_TYPE_FAST) continue; @@ -2398,9 +2499,10 @@ static void commit_planes_do_stream_update(struct dc *dc, if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); - dc->hwss.optimize_bandwidth(dc, dc->current_state); + dc->optimized_required = true; + } else { - if (dc->optimize_seamless_boot_streams == 0) + if (get_seamless_boot_stream_count(context) == 0) dc->hwss.prepare_bandwidth(dc, dc->current_state); core_link_enable_stream(dc->current_state, pipe_ctx); @@ -2408,7 +2510,7 @@ static void commit_planes_do_stream_update(struct dc *dc, } if (stream_update->abm_level && pipe_ctx->stream_res.abm) { - should_program_abm = true; + bool should_program_abm = true; // if otg funcs defined check if blanked before programming if (pipe_ctx->stream_res.tg->funcs->is_blanked) @@ -2439,7 +2541,7 @@ static void commit_planes_for_stream(struct dc *dc, int i, j; struct pipe_ctx *top_pipe_to_program = NULL; - if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) { + if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower * bandwidth. Important to note that it is expected UEFI will @@ -2448,9 +2550,8 @@ static void commit_planes_for_stream(struct dc *dc, */ if (stream->apply_seamless_boot_optimization) { stream->apply_seamless_boot_optimization = false; - dc->optimize_seamless_boot_streams--; - if (dc->optimize_seamless_boot_streams == 0) + if (get_seamless_boot_stream_count(context) == 0) dc->optimized_required = true; } } @@ -2460,7 +2561,7 @@ static void commit_planes_for_stream(struct dc *dc, dc_allow_idle_optimizations(dc, false); #endif - if (dc->optimize_seamless_boot_streams == 0) + if (get_seamless_boot_stream_count(context) == 0) dc->hwss.prepare_bandwidth(dc, context); context_clock_trace(dc, context); @@ -2868,6 +2969,9 @@ void dc_set_power_state( struct kref refcount; struct display_mode_lib *dml; + if (!dc->current_state) + return; + switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: dc_resource_state_construct(dc, dc->current_state); @@ -3176,3 +3280,113 @@ void dc_hardware_release(struct dc *dc) dc->hwss.hardware_release(dc); } #endif + +/** + ***************************************************************************** + * Function: dc_enable_dmub_notifications + * + * @brief + * Returns whether dmub notification can be enabled + * + * @param + * [in] dc: dc structure + * + * @return + * True to enable dmub notifications, False otherwise + ***************************************************************************** + */ +bool dc_enable_dmub_notifications(struct dc *dc) +{ + /* dmub aux needs dmub notifications to be enabled */ + return dc->debug.enable_dmub_aux_for_legacy_ddc; +} + +/** + ***************************************************************************** + * Function: dc_process_dmub_aux_transfer_async + * + * @brief + * Submits aux command to dmub via inbox message + * Sets port index appropriately for legacy DDC + * + * @param + * [in] dc: dc structure + * [in] link_index: link index + * [in] payload: aux payload + * + * @return + * True if successful, False if failure + ***************************************************************************** + */ +bool dc_process_dmub_aux_transfer_async(struct dc *dc, + uint32_t link_index, + struct aux_payload *payload) +{ + uint8_t action; + union dmub_rb_cmd cmd = {0}; + struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; + + ASSERT(payload->length <= 16); + + cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS; + cmd.dp_aux_access.header.payload_bytes = 0; + cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC; + cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.dp_aux_access.aux_control.sw_crc_enabled = 0; + cmd.dp_aux_access.aux_control.timeout = 0; + cmd.dp_aux_access.aux_control.dpaux.address = payload->address; + cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; + cmd.dp_aux_access.aux_control.dpaux.length = payload->length; + + /* set aux action */ + if (payload->i2c_over_aux) { + if (payload->write) { + if (payload->mot) + action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT; + else + action = DP_AUX_REQ_ACTION_I2C_WRITE; + } else { + if (payload->mot) + action = DP_AUX_REQ_ACTION_I2C_READ_MOT; + else + action = DP_AUX_REQ_ACTION_I2C_READ; + } + } else { + if (payload->write) + action = DP_AUX_REQ_ACTION_DPCD_WRITE; + else + action = DP_AUX_REQ_ACTION_DPCD_READ; + } + + cmd.dp_aux_access.aux_control.dpaux.action = action; + + if (payload->length && payload->write) { + memcpy(cmd.dp_aux_access.aux_control.dpaux.data, + payload->data, + payload->length + ); + } + + dc_dmub_srv_cmd_queue(dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dmub_srv); + dc_dmub_srv_wait_idle(dmub_srv); + + return true; +} + +/** + ***************************************************************************** + * Function: dc_disable_accelerated_mode + * + * @brief + * disable accelerated mode + * + * @param + * [in] dc: dc structure + * + ***************************************************************************** + */ +void dc_disable_accelerated_mode(struct dc *dc) +{ + bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0); +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fa5059f71727a16463d990e1ebd54c7fcc480634..f9a33dc52c4555ad6ac992cfe5c159f4e0838460 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -91,8 +91,14 @@ static void dc_link_destruct(struct dc_link *link) if (link->panel_cntl) link->panel_cntl->funcs->destroy(&link->panel_cntl); - if (link->link_enc) + if (link->link_enc) { + /* Update link encoder tracking variables. These are used for the dynamic + * assignment of link encoders to streams. + */ + link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = NULL; + link->dc->res_pool->dig_link_enc_count--; link->link_enc->funcs->destroy(&link->link_enc); + } if (link->local_sink) dc_sink_release(link->local_sink); @@ -1500,7 +1506,7 @@ static bool dc_link_construct(struct dc_link *link, (link->link_id.id == CONNECTOR_ID_EDP || link->link_id.id == CONNECTOR_ID_LVDS)) { panel_cntl_init_data.ctx = dc_ctx; - panel_cntl_init_data.inst = 0; + panel_cntl_init_data.inst = link->link_index; link->panel_cntl = link->dc->res_pool->funcs->panel_cntl_create( &panel_cntl_init_data); @@ -1532,6 +1538,12 @@ static bool dc_link_construct(struct dc_link *link, DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C); + /* Update link encoder tracking variables. These are used for the dynamic + * assignment of link encoders to streams. + */ + link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = link->link_enc; + link->dc->res_pool->dig_link_enc_count++; + link->link_enc_hw_inst = link->link_enc->transmitter; for (i = 0; i < 4; i++) { @@ -1603,6 +1615,7 @@ static bool dc_link_construct(struct dc_link *link, link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); + kfree(info); return true; device_tag_fail: link->link_enc->funcs->destroy(&link->link_enc); @@ -2602,7 +2615,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link, if (pipe_ctx->plane_state == NULL) frame_ramp = 0; } else { - ASSERT(false); return false; } @@ -3258,6 +3270,16 @@ void core_link_enable_stream( /* Do not touch link on seamless boot optimization. */ if (pipe_ctx->stream->apply_seamless_boot_optimization) { pipe_ctx->stream->dpms_off = false; + + /* Still enable stream features & audio on seamless boot for DP external displays */ + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { + enable_stream_features(pipe_ctx); + if (pipe_ctx->stream_res.audio != NULL) { + pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); + dc->hwss.enable_audio_stream(pipe_ctx); + } + } + #if defined(CONFIG_DRM_AMD_DC_HDCP) update_psp_stream_config(pipe_ctx, false); #endif @@ -3481,15 +3503,12 @@ uint32_t dc_bandwidth_in_kbps_from_timing( { uint32_t bits_per_channel = 0; uint32_t kbps; - struct fixed31_32 link_bw_kbps; +#if defined(CONFIG_DRM_AMD_DC_DCN) if (timing->flags.DSC) { - link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz); - link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160); - link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel); - kbps = dc_fixpt_ceil(link_bw_kbps); - return kbps; + return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel); } +#endif switch (timing->display_color_depth) { case COLOR_DEPTH_666: diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index ae6484ab567b7a2a2d2ea348fa835d0ab8a6b818..64414c51312dec3638f74f41bb8248e62e73f8c4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -36,6 +36,7 @@ #include "core_types.h" #include "dc_link_ddc.h" #include "dce/dce_aux.h" +#include "dmub/inc/dmub_cmd.h" #define DC_LOGGER_INIT(logger) @@ -558,7 +559,7 @@ bool dal_ddc_service_query_ddc_data( /* should not set mot (middle of transaction) to 0 * if there are pending read payloads */ - payload.mot = read_size == 0 ? false : true; + payload.mot = !(read_size == 0); payload.length = write_size; payload.data = write_buf; @@ -655,7 +656,7 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc, */ int dc_link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, - enum aux_channel_operation_result *operation_result) + enum aux_return_code_type *operation_result) { return dce_aux_transfer_raw(ddc, payload, operation_result); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c1391bfb7a9bc58de9460bc778e2f4fac0120318..47e6c33f73cbad613b85014f864d703b32c62aa0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1669,6 +1669,22 @@ bool perform_link_training_with_retries( msleep(delay_dp_power_up_in_ms); } +#ifdef CONFIG_DRM_AMD_DC_HDCP + if (panel_mode == DP_PANEL_MODE_EDP) { + struct cp_psp *cp_psp = &stream->ctx->cp_psp; + + if (cp_psp && cp_psp->funcs.enable_assr) { + if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) { + /* since eDP implies ASSR on, change panel + * mode to disable ASSR + */ + panel_mode = DP_PANEL_MODE_DEFAULT; + } + } else + panel_mode = DP_PANEL_MODE_DEFAULT; + } +#endif + dp_set_panel_mode(link, panel_mode); if (link->aux_access_disabled) { @@ -4265,7 +4281,7 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) if (edp_config_set.bits.PANEL_MODE_EDP != panel_mode_edp) { - enum dc_status result = DC_ERROR_UNEXPECTED; + enum dc_status result; edp_config_set.bits.PANEL_MODE_EDP = panel_mode_edp; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 0c26c2ade782c4ea69713e814d186e06ca755e39..3c91d16c271053e5506e901de65ce8eb144bf7b5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -417,6 +417,49 @@ int resource_get_clock_source_reference( return -1; } +bool resource_are_vblanks_synchronizable( + struct dc_stream_state *stream1, + struct dc_stream_state *stream2) +{ + uint32_t base60_refresh_rates[] = {10, 20, 5}; + uint8_t i; + uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]); + uint64_t frame_time_diff; + + if (stream1->ctx->dc->config.vblank_alignment_dto_params && + stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && + dc_is_dp_signal(stream1->signal) && + dc_is_dp_signal(stream2->signal) && + false == stream1->has_non_synchronizable_pclk && + false == stream2->has_non_synchronizable_pclk && + stream1->timing.flags.VBLANK_SYNCHRONIZABLE && + stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { + /* disable refresh rates higher than 60Hz for now */ + if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ + stream1->timing.v_total > 60) + return false; + if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ + stream2->timing.v_total > 60) + return false; + frame_time_diff = (uint64_t)10000 * + stream1->timing.h_total * + stream1->timing.v_total * + stream2->timing.pix_clk_100hz; + frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); + frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); + frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); + for (i = 0; i < rr_count; i++) { + int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; + + if (diff < 0) + diff = -diff; + if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) + return true; + } + } + return false; +} + bool resource_are_streams_timing_synchronizable( struct dc_stream_state *stream1, struct dc_stream_state *stream2) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c new file mode 100644 index 0000000000000000000000000000000000000000..31761f3595a6a609f7c984df69b494b9850fadf3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c @@ -0,0 +1,64 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#include "dc/dc_stat.h" +#include "dmub/dmub_srv_stat.h" +#include "dc_dmub_srv.h" + +/** + * DOC: DC STAT Interface + * + * These interfaces are called without acquiring DAL and DC locks. + * Hence, there is limitations on whese interfaces can access. Only + * variables exclusively defined for these interfaces can be modified. + */ + +/** + ***************************************************************************** + * Function: dc_stat_get_dmub_notification + * + * @brief + * Calls dmub layer to retrieve dmub notification + * + * @param + * [in] dc: dc structure + * [in] notify: dmub notification structure + * + * @return + * None + ***************************************************************************** + */ +void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify) +{ + /** + * This function is called without dal and dc locks, so + * we shall not modify any dc, dc_dmub_srv or dmub variables + * except variables exclusively accessed by this function + */ + struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; + enum dmub_status status; + + status = dmub_srv_stat_get_notification(dmub, notify); + ASSERT(status == DMUB_STATUS_OK); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4eee3a55fa3018ad0f65bfe50f1e949fbf4de7ac..d163007e057c877c89c18890e0de23f4a1e5fb02 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,13 +42,17 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.122" +/* forward declaration */ +struct aux_payload; + +#define DC_VER "3.2.127" #define MAX_SURFACES 3 #define MAX_PLANES 6 #define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 #define MIN_VIEWPORT_SIZE 12 +#define MAX_NUM_EDP 2 /******************************************************************************* * Display Core Interfaces @@ -151,6 +155,8 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; + uint32_t max_slave_yuv_planes; + uint32_t max_slave_rgb_planes; uint32_t max_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; @@ -301,6 +307,8 @@ struct dc_config { #if defined(CONFIG_DRM_AMD_DC_DCN) bool clamp_min_dcfclk; #endif + uint64_t vblank_alignment_dto_params; + uint8_t vblank_alignment_max_frame_time_diff; }; enum visual_confirm { @@ -528,6 +536,10 @@ struct dc_debug_options { bool disable_dsc; bool enable_dram_clock_change_one_display_vactive; union mem_low_power_enable_options enable_mem_low_power; + bool force_vblank_alignment; + + /* Enable dmub aux for legacy ddc */ + bool enable_dmub_aux_for_legacy_ddc; }; struct dc_debug_data { @@ -628,7 +640,6 @@ struct dc { #endif /* Require to maintain clocks and bandwidth for UEFI enabled HW */ - int optimize_seamless_boot_streams; /* FBC compressor */ struct compressor *fbc_compressor; @@ -887,6 +898,7 @@ struct dc_plane_state { int layer_index; union surface_update_flags update_flags; + bool flip_int_enabled; /* private to DC core */ struct dc_plane_status status; struct dc_context *ctx; @@ -1291,8 +1303,20 @@ void dc_hardware_release(struct dc *dc); bool dc_set_psr_allow_active(struct dc *dc, bool enable); +bool dc_enable_dmub_notifications(struct dc *dc); + +bool dc_process_dmub_aux_transfer_async(struct dc *dc, + uint32_t link_index, + struct aux_payload *payload); + /******************************************************************************* * DSC Interfaces ******************************************************************************/ #include "dc_dsc.h" + +/******************************************************************************* + * Disable acc mode Interfaces + ******************************************************************************/ +void dc_disable_accelerated_mode(struct dc *dc); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 509d23fdd3c9bb7b6e3c1cb6f970b4dd7880c709..86ab8f16f6213b57cf6329059838ed3e31969fe2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -139,7 +139,8 @@ struct dc_vbios_funcs { enum bp_result (*enable_lvtma_control)( struct dc_bios *bios, - uint8_t uc_pwr_on); + uint8_t uc_pwr_on, + uint8_t panel_instance); enum bp_result (*get_soc_bb_info)( struct dc_bios *dcb, diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h index 4f8f576d5fcfb6ebc3845e0db3a49bbf98ed73ec..7769bd099a5a03dc0ad4990b7c53452ae3c03db9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h @@ -44,16 +44,6 @@ enum i2caux_transaction_action { I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90 }; -enum aux_channel_operation_result { - AUX_CHANNEL_OPERATION_SUCCEEDED, - AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN, - AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY, - AUX_CHANNEL_OPERATION_FAILED_TIMEOUT, - AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON, - AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE -}; - - struct aux_request_transaction_data { enum aux_transaction_type type; enum i2caux_transaction_action action; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index b987548119772544db73e9c0d7ac0c4278d0327d..6b72af2b3f4c34cb62bc666784fd03b51c14223f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -26,6 +26,10 @@ #include "dc.h" #include "dc_dmub_srv.h" #include "../dmub/dmub_srv.h" +#include "dm_helpers.h" + +#define CTX dc_dmub_srv->ctx +#define DC_LOGGER CTX->logger static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, struct dmub_srv *dmub) @@ -106,6 +110,25 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); } +bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) +{ + struct dmub_srv *dmub; + enum dmub_status status; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return false; + + dmub = dc_dmub_srv->dmub; + + status = dmub_srv_cmd_with_reply_data(dmub, cmd); + if (status != DMUB_STATUS_OK) { + DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); + return false; + } + + return true; +} + void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) { struct dmub_srv *dmub = dc_dmub_srv->dmub; @@ -148,3 +171,14 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, stream_mask, timeout) == DMUB_STATUS_OK; } + +bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) +{ + struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; + return dmub_srv_get_outbox0_msg(dmub, entry); +} + +void dc_dmub_trace_event_control(struct dc *dc, bool enable) +{ + dm_helpers_dmub_outbox0_interrupt_control(dc->ctx, enable); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index bb4ab61887e4cc8d9373ea37ccd2b236540e9f8a..338f776990dbb6effda063205704d593d9951a9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -30,6 +30,7 @@ #include "dmub/dmub_srv.h" struct dmub_srv; +struct dc; struct dc_reg_helper_state { bool gather_in_progress; @@ -56,6 +57,13 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv); void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv); +bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd); + bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, unsigned int stream_mask); + +bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry); + +void dc_dmub_trace_event_control(struct dc *dc, bool enable); + #endif /* _DMUB_DC_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index ec55b77727d50d1dc28cfadbd777ffe30ee8a4c8..c51d2d961b7a531c11cc97150ecc3e67c2918ea0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -51,6 +51,7 @@ struct dc_dsc_policy { int min_slice_height; // Must not be less than 8 uint32_t max_target_bpp; uint32_t min_target_bpp; + uint32_t preferred_bpp_x16; bool enable_dsc_when_not_needed; }; @@ -62,8 +63,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, bool dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, uint32_t dsc_min_slice_height_override, - uint32_t min_bpp, - uint32_t max_bpp, + uint32_t min_bpp_x16, + uint32_t max_bpp_x16, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range); @@ -77,12 +78,16 @@ bool dc_dsc_compute_config( const struct dc_crtc_timing *timing, struct dc_dsc_config *dsc_cfg); +uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16); + void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, - uint32_t max_target_bpp_limit_override, + uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy); void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable); +uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index b41e6367b15ef967ad8e89c59dc8232e4df497de..bcec019efa6f02fdc49dd665fc98b917a51d854f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -705,6 +705,7 @@ struct dc_crtc_timing_flags { #ifndef TRIM_FSFT uint32_t FAST_TRANSPORT: 1; #endif + uint32_t VBLANK_SYNCHRONIZABLE: 1; }; enum dc_timing_3d_format { @@ -769,6 +770,7 @@ struct dc_crtc_timing { #endif struct dc_crtc_timing_flags flags; + uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ struct dc_dsc_config dsc_cfg; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index e189f16bc026bbf2e670a991a365fd86dd281123..c50ef5a909a635dbadff6d4d9192ccfb0e9df38e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -103,6 +103,10 @@ struct dc_link { bool lttpr_non_transparent_mode; bool is_internal_display; + /* TODO: Rename. Flag an endpoint as having a programmable mapping to a + * DIG encoder. */ + bool is_dig_mapping_flexible; + bool edp_sink_present; /* caps is the same as reported_link_cap. link_traing use @@ -183,16 +187,21 @@ static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_ return dc->links[link_index]; } -static inline struct dc_link *get_edp_link(const struct dc *dc) +static inline void get_edp_links(const struct dc *dc, + struct dc_link **edp_links, + int *edp_num) { int i; - // report any eDP links, even unconnected DDI's + *edp_num = 0; for (i = 0; i < dc->link_count; i++) { - if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) - return dc->links[i]; + // report any eDP links, even unconnected DDI's + if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) { + edp_links[*edp_num] = dc->links[i]; + if (++(*edp_num) == MAX_NUM_EDP) + return; + } } - return NULL; } /* Set backlight level of an embedded panel (eDP, LVDS). diff --git a/drivers/gpu/drm/amd/display/dc/dc_stat.h b/drivers/gpu/drm/amd/display/dc/dc_stat.h new file mode 100644 index 0000000000000000000000000000000000000000..2a000ba54ddb8603212b874674056c10bc332f62 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_stat.h @@ -0,0 +1,42 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DC_STAT_H_ +#define _DC_STAT_H_ + +/** + * DOC: DC STAT Interface + * + * These interfaces are called without acquiring DAL and DC locks. + * Hence, there is limitations on whese interfaces can access. Only + * variables exclusively defined for these interfaces can be modified. + */ + +#include "dc.h" +#include "dmub/dmub_srv.h" + +void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify); + +#endif /* _DC_STAT_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 80b67b860091eeaedc82aa6760e9a1a8b694f8a8..e747370fc43b8a8cdc8b285a4cf3cfc7262c677a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -130,14 +130,6 @@ union stream_update_flags { uint32_t raw; }; -struct test_pattern { - enum dp_test_pattern type; - enum dp_test_pattern_color_space color_space; - struct link_training_settings const *p_link_settings; - unsigned char const *p_custom_pattern; - unsigned int cust_pattern_size; -}; - struct dc_stream_state { // sink is deprecated, new code should not reference // this pointer @@ -235,9 +227,10 @@ struct dc_stream_state { uint32_t stream_id; bool is_dsc_enabled; - - struct test_pattern test_pattern; union stream_update_flags update_flags; + + bool has_non_synchronizable_pclk; + bool vblank_synchronized; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -271,7 +264,6 @@ struct dc_stream_update { struct dc_dsc_config *dsc_config; struct dc_transfer_func *func_shaper; struct dc_3dlut *lut3d_func; - struct test_pattern *pending_test_pattern; }; bool dc_is_stream_unchanged( @@ -461,6 +453,13 @@ bool dc_stream_get_crtc_position(struct dc *dc, unsigned int *v_pos, unsigned int *nom_v_pos); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream, + struct crc_params *crc_window); +bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, + struct dc_stream_state *stream); +#endif + bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, struct crc_params *crc_window, diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 973be8f9fd10761e06ba5f51e73dc37ab35e1d7f..0d7db132a20fe048106129d743bd7eb3613285a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -30,7 +30,7 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \ dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel_cntl.o \ -dmub_hw_lock_mgr.o +dmub_hw_lock_mgr.o dmub_outbox.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index d51b5fe91287ddbe015e4aba12a23652e19ac2a3..87d57e81de1207fdf90d15a57bd09c3fecfdad1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -31,6 +31,8 @@ #include "dce_aux.h" #include "dce/dce_11_0_sh_mask.h" #include "dm_event_log.h" +#include "dm_helpers.h" +#include "dmub/inc/dmub_cmd.h" #define CTX \ aux110->base.ctx @@ -324,7 +326,7 @@ static int read_channel_reply(struct dce_aux *engine, uint32_t size, return 0; } -static enum aux_channel_operation_result get_channel_status( +static enum aux_return_code_type get_channel_status( struct dce_aux *engine, uint8_t *returned_bytes) { @@ -335,7 +337,7 @@ static enum aux_channel_operation_result get_channel_status( if (returned_bytes == NULL) { /*caller pass NULL pointer*/ ASSERT_CRITICAL(false); - return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN; + return AUX_RET_ERROR_UNKNOWN; } *returned_bytes = 0; @@ -346,7 +348,7 @@ static enum aux_channel_operation_result get_channel_status( value = REG_READ(AUX_SW_STATUS); /* in case HPD is LOW, exit AUX transaction */ if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) - return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; + return AUX_RET_ERROR_HPD_DISCON; /* Note that the following bits are set in 'status.bits' * during CTS 4.2.1.2 (FW 3.3.1): @@ -359,14 +361,14 @@ static enum aux_channel_operation_result get_channel_status( if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) { if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) || (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK)) - return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT; + return AUX_RET_ERROR_TIMEOUT; else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) || (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) || (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) || (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) - return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY; + return AUX_RET_ERROR_INVALID_REPLY; *returned_bytes = get_reg_field_value(value, AUX_SW_STATUS, @@ -374,17 +376,17 @@ static enum aux_channel_operation_result get_channel_status( if (*returned_bytes == 0) return - AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY; + AUX_RET_ERROR_INVALID_REPLY; else { *returned_bytes -= 1; - return AUX_CHANNEL_OPERATION_SUCCEEDED; + return AUX_RET_SUCCESS; } } else { /*time_elapsed >= aux_engine->timeout_period * AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point */ ASSERT_CRITICAL(false); - return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT; + return AUX_RET_ERROR_TIMEOUT; } } @@ -541,7 +543,7 @@ static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payl int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, - enum aux_channel_operation_result *operation_result) + enum aux_return_code_type *operation_result) { struct ddc *ddc_pin = ddc->ddc_pin; struct dce_aux *aux_engine; @@ -556,7 +558,7 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; if (!acquire(aux_engine, ddc_pin)) { - *operation_result = AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE; + *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; return -1; } @@ -575,8 +577,9 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, submit_channel_request(aux_engine, &aux_req); *operation_result = get_channel_status(aux_engine, &returned_bytes); - if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) { + if (*operation_result == AUX_RET_SUCCESS) { int __maybe_unused bytes_replied = 0; + bytes_replied = read_channel_reply(aux_engine, payload->length, payload->data, payload->reply, &status); @@ -604,7 +607,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, int i, ret = 0; uint8_t reply; bool payload_reply = true; - enum aux_channel_operation_result operation_result; + enum aux_return_code_type operation_result; bool retry_on_defer = false; int aux_ack_retries = 0, @@ -620,8 +623,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, for (i = 0; i < AUX_MAX_RETRIES; i++) { ret = dce_aux_transfer_raw(ddc, payload, &operation_result); + switch (operation_result) { - case AUX_CHANNEL_OPERATION_SUCCEEDED: + case AUX_RET_SUCCESS: aux_timeout_retries = 0; aux_invalid_reply_retries = 0; @@ -667,14 +671,14 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, } break; - case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY: + case AUX_RET_ERROR_INVALID_REPLY: if (++aux_invalid_reply_retries >= AUX_MAX_INVALID_REPLY_RETRIES) goto fail; else udelay(400); break; - case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT: + case AUX_RET_ERROR_TIMEOUT: // Check whether a DEFER had occurred before the timeout. // If so, treat timeout as a DEFER. if (retry_on_defer) { @@ -696,9 +700,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, } break; - case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON: - case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE: - case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN: + case AUX_RET_ERROR_HPD_DISCON: + case AUX_RET_ERROR_ENGINE_ACQUIRE: + case AUX_RET_ERROR_UNKNOWN: default: goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h index 277484cf853e483663df86a61bf7d1cf77747b1e..566b1bddd8cc6a95d689f6f54778031f79c68bfb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h @@ -29,6 +29,7 @@ #include "i2caux_interface.h" #include "inc/hw/aux_engine.h" +enum aux_return_code_type; #define AUX_COMMON_REG_LIST0(id)\ SRI(AUX_CONTROL, DP_AUX, id), \ @@ -99,7 +100,6 @@ struct dce110_aux_registers { AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ - AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ @@ -302,7 +302,7 @@ bool dce110_aux_engine_acquire( int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *cmd, - enum aux_channel_operation_result *operation_result); + enum aux_return_code_type *operation_result); bool dce_aux_transfer_with_retries(struct ddc_service *ddc, struct aux_payload *cmd); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index dec58b3c42e4d52badf8054933f43a18f5b19706..2c7eb982eabcabf7164fc802769220c3d43238bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1002,15 +1002,27 @@ static bool get_pixel_clk_frequency_100hz( { struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); unsigned int clock_hz = 0; + unsigned int modulo_hz = 0; if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { clock_hz = REG_READ(PHASE[inst]); - /* NOTE: There is agreement with VBIOS here that MODULO is - * programmed equal to DPREFCLK, in which case PHASE will be - * equivalent to pixel clock. - */ - *pixel_clk_khz = clock_hz / 100; + if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && + clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { + /* NOTE: In case VBLANK syncronization is enabled, MODULO may + * not be programmed equal to DPREFCLK + */ + modulo_hz = REG_READ(MODULO[inst]); + *pixel_clk_khz = div_u64((uint64_t)clock_hz* + clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, + modulo_hz); + } else { + /* NOTE: There is agreement with VBIOS here that MODULO is + * programmed equal to DPREFCLK, in which case PHASE will be + * equivalent to pixel clock. + */ + *pixel_clk_khz = clock_hz / 100; + } return true; } @@ -1074,8 +1086,35 @@ static bool dcn20_program_pix_clk( struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) { + struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); + unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; + dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); + if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && + clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { + /* NOTE: In case VBLANK syncronization is enabled, + * we need to set modulo to default DPREFCLK first + * dce112_program_pix_clk does not set default DPREFCLK + */ + REG_WRITE(MODULO[inst], + clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); + } + return true; +} + +static bool dcn20_override_dp_pix_clk( + struct clock_source *clock_source, + unsigned int inst, + unsigned int pixel_clk, + unsigned int ref_clk) +{ + struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); + + REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0); + REG_WRITE(PHASE[inst], pixel_clk); + REG_WRITE(MODULO[inst], ref_clk); + REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); return true; } @@ -1083,7 +1122,8 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = { .cs_power_down = dce110_clock_source_power_down, .program_pix_clk = dcn20_program_pix_clk, .get_pix_clk_dividers = dce112_get_pix_clk_dividers, - .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz + .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz, + .override_dp_pix_clk = dcn20_override_dp_pix_clk }; #if defined(CONFIG_DRM_AMD_DC_DCN) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index ddc789daf3b13a38ad67c6d05509902f156cdadd..4f864501e046c1abfd5760488c854f60f87c7eeb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -57,6 +57,8 @@ #define MCP_SYNC_PHY_LOCK 0x90 #define MCP_SYNC_PHY_UNLOCK 0x91 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ +#define CRC_WIN_NOTIFY 0x92 +#define CRC_STOP_UPDATE 0x93 #define MCP_SEND_EDID_CEA 0xA0 #define EDID_CEA_CMD_ACK 1 #define EDID_CEA_CMD_NACK 2 @@ -930,6 +932,84 @@ static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) #endif //(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +static void dcn10_forward_crc_window(struct dmcu *dmcu, + struct crc_region *crc_win, + struct otg_phy_mux *mux_mapping) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + + if (!crc_win) + return; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* build up nitification data */ + crc_start = (((unsigned int) crc_win->x_start) << 16) | crc_win->y_start; + crc_end = (((unsigned int) crc_win->x_end) << 16) | crc_win->y_end; + otg_phy_mux = + (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; + + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), + crc_start); + + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), + crc_end); + + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), + otg_phy_mux); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + CRC_WIN_NOTIFY); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +static void dcn10_stop_crc_win_update(struct dmcu *dmcu, + struct otg_phy_mux *mux_mapping) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + unsigned int otg_phy_mux = 0; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* build up nitification data */ + otg_phy_mux = + (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; + + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), + otg_phy_mux); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + CRC_STOP_UPDATE); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} +#endif + static const struct dmcu_funcs dce_funcs = { .dmcu_init = dce_dmcu_init, .load_iram = dce_dmcu_load_iram, @@ -953,6 +1033,10 @@ static const struct dmcu_funcs dcn10_funcs = { .send_edid_cea = dcn10_send_edid_cea, .recv_amd_vsdb = dcn10_recv_amd_vsdb, .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + .forward_crc_window = dcn10_forward_crc_window, + .stop_crc_win_update = dcn10_stop_crc_win_update, +#endif .is_dmcu_initialized = dcn10_is_dmcu_initialized }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 4600231da6cbb2637aa0469710ca1740ec604e33..895b015b02e8b5687ef13f3366741054d20ac547 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -216,9 +216,7 @@ static void set_spatial_dither( REG_UPDATE(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, 0); - /* no 10bpc on DCE11*/ - if (params->flags.SPATIAL_DITHER_ENABLED == 0 || - params->flags.SPATIAL_DITHER_DEPTH == 2) + if (params->flags.SPATIAL_DITHER_ENABLED == 0) return; /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c index 453aaa5757bd003b90610dd331b051f858350c16..eb1698d54a482f6e61b42d5a6111ef572faaf4c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c @@ -72,11 +72,11 @@ static void dmub_abm_init(struct abm *abm, uint32_t backlight) { struct dce_abm *dce_abm = TO_DMUB_ABM(abm); - REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); - REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); - REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); - REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); - REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); + REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3); + REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1); + REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3); + REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1); + REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1); REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, ABM1_HG_NUM_OF_BINS_SEL, 0, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c new file mode 100644 index 0000000000000000000000000000000000000000..295596d1f47f2b9a2919ef2c5c546c1c09d24314 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c @@ -0,0 +1,60 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#include "dmub_outbox.h" +#include "dc_dmub_srv.h" +#include "dmub/inc/dmub_cmd.h" + +/** + ***************************************************************************** + * Function: dmub_enable_outbox_notification + * + * @brief + * Sends inbox cmd to dmub to enable outbox1 messages with interrupt. + * Dmub sends outbox1 message and triggers outbox1 interrupt. + * + * @param + * [in] dc: dc structure + * + * @return + * None + ***************************************************************************** + */ +void dmub_enable_outbox_notification(struct dc *dc) +{ + union dmub_rb_cmd cmd; + struct dc_context *dc_ctx = dc->ctx; + + memset(&cmd, 0x0, sizeof(cmd)); + cmd.outbox1_enable.header.type = DMUB_CMD__OUTBOX1_ENABLE; + cmd.outbox1_enable.header.sub_type = 0; + cmd.outbox1_enable.header.payload_bytes = + sizeof(cmd.outbox1_enable) - + sizeof(cmd.outbox1_enable.header); + cmd.outbox1_enable.enable = true; + + dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv); + dc_dmub_srv_wait_idle(dc_ctx->dmub_srv); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h new file mode 100644 index 0000000000000000000000000000000000000000..4e0aa0d1a2d5c15bd48a72cb271ba55956b4102b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h @@ -0,0 +1,33 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_OUTBOX_H_ +#define _DMUB_OUTBOX_H_ + +#include "dc.h" + +void dmub_enable_outbox_notification(struct dc *dc); + +#endif /* _DMUB_OUTBOX_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 69e34bef274c1a28c177e0c5824247e2fc3524be..15ed09b7a452e650ef1e5a955dba14fa17ed0eec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -81,13 +81,18 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state) { struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; uint32_t raw_state; + enum dmub_status status; // Send gpint command and wait for ack - dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30); - - dmub_srv_get_gpint_response(srv, &raw_state); - - *state = convert_psr_state(raw_state); + status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30); + + if (status == DMUB_STATUS_OK) { + // GPINT was executed, get response + dmub_srv_get_gpint_response(srv, &raw_state); + *state = convert_psr_state(raw_state); + } else + // Return invalid state when GPINT times out + *state = 0xFF; } /* @@ -216,6 +221,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, res_ctx->pipe_ctx[i].stream->link == link && res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { pipe_ctx = &res_ctx->pipe_ctx[i]; + //TODO: refactor for multi edp support break; } } @@ -269,8 +275,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; copy_settings_data->debug.u32All = 0; - copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ? - true : false; + copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index caee1c9f54bdb2c873913b5632efc2fc9de384fa..804092f81f85807e4cc10729f69f78a6ff5fffb9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -797,6 +797,7 @@ void dce110_edp_power_control( struct dc_context *ctx = link->ctx; struct bp_transmitter_control cntl = { 0 }; enum bp_result bp_result; + uint8_t panel_instance; if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) @@ -807,7 +808,6 @@ void dce110_edp_power_control( if (!link->panel_cntl) return; - if (power_up != link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { @@ -880,15 +880,18 @@ void dce110_edp_power_control( cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; cntl.hpd_sel = link->link_enc->hpd_source; + panel_instance = link->panel_cntl->inst; if (ctx->dc->ctx->dmub_srv && ctx->dc->debug.dmub_command_table) { if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, - LVTMA_CONTROL_POWER_ON); + LVTMA_CONTROL_POWER_ON, + panel_instance); else bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, - LVTMA_CONTROL_POWER_OFF); + LVTMA_CONTROL_POWER_OFF, + panel_instance); } bp_result = link_transmitter_control(ctx->dc_bios, &cntl); @@ -963,6 +966,7 @@ void dce110_edp_backlight_control( { struct dc_context *ctx = link->ctx; struct bp_transmitter_control cntl = { 0 }; + uint8_t panel_instance; if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { @@ -1011,6 +1015,7 @@ void dce110_edp_backlight_control( */ /* dc_service_sleep_in_milliseconds(50); */ /*edp 1.2*/ + panel_instance = link->panel_cntl->inst; if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) edp_receiver_ready_T7(link); @@ -1018,10 +1023,12 @@ void dce110_edp_backlight_control( ctx->dc->debug.dmub_command_table) { if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, - LVTMA_CONTROL_LCD_BLON); + LVTMA_CONTROL_LCD_BLON, + panel_instance); else ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, - LVTMA_CONTROL_LCD_BLOFF); + LVTMA_CONTROL_LCD_BLOFF, + panel_instance); } link_transmitter_control(ctx->dc_bios, &cntl); @@ -1629,34 +1636,39 @@ static void disable_vga_and_power_gate_all_controllers( } -static struct dc_stream_state *get_edp_stream(struct dc_state *context) +static void get_edp_streams(struct dc_state *context, + struct dc_stream_state **edp_streams, + int *edp_stream_num) { int i; + *edp_stream_num = 0; for (i = 0; i < context->stream_count; i++) { - if (context->streams[i]->signal == SIGNAL_TYPE_EDP) - return context->streams[i]; + if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { + edp_streams[*edp_stream_num] = context->streams[i]; + if (++(*edp_stream_num) == MAX_NUM_EDP) + return; + } } - return NULL; } -static struct dc_link *get_edp_link_with_sink( +static void get_edp_links_with_sink( struct dc *dc, - struct dc_state *context) + struct dc_link **edp_links_with_sink, + int *edp_with_sink_num) { int i; - struct dc_link *link = NULL; /* check if there is an eDP panel not in use */ + *edp_with_sink_num = 0; for (i = 0; i < dc->link_count; i++) { if (dc->links[i]->local_sink && dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { - link = dc->links[i]; - break; + edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; + if (++(*edp_with_sink_num) == MAX_NUM_EDP) + return; } } - - return link; } /* @@ -1668,36 +1680,48 @@ static struct dc_link *get_edp_link_with_sink( */ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) { - int i; - struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context); - struct dc_link *edp_link = get_edp_link(dc); + struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_stream_state *edp_streams[MAX_NUM_EDP]; + struct dc_link *edp_link_with_sink = NULL; + struct dc_link *edp_link = NULL; struct dc_stream_state *edp_stream = NULL; + struct dce_hwseq *hws = dc->hwseq; + int edp_with_sink_num; + int edp_num; + int edp_stream_num; + int i; bool can_apply_edp_fast_boot = false; bool can_apply_seamless_boot = false; bool keep_edp_vdd_on = false; - struct dce_hwseq *hws = dc->hwseq; + + get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); + get_edp_links(dc, edp_links, &edp_num); if (hws->funcs.init_pipes) hws->funcs.init_pipes(dc, context); - edp_stream = get_edp_stream(context); + get_edp_streams(context, edp_streams, &edp_stream_num); // Check fastboot support, disable on DCE8 because of blank screens - if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 && + if (edp_num && dc->ctx->dce_version != DCE_VERSION_8_0 && dc->ctx->dce_version != DCE_VERSION_8_1 && dc->ctx->dce_version != DCE_VERSION_8_3) { - - // enable fastboot if backend is enabled on eDP - if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { - /* Set optimization flag on eDP stream*/ - if (edp_stream && edp_link->link_status.link_active) { - edp_stream->apply_edp_fast_boot_optimization = true; - can_apply_edp_fast_boot = true; + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + // enable fastboot if backend is enabled on eDP + if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { + /* Set optimization flag on eDP stream*/ + if (edp_stream_num && edp_link->link_status.link_active) { + edp_stream = edp_streams[0]; + edp_stream->apply_edp_fast_boot_optimization = true; + can_apply_edp_fast_boot = true; + break; + } } } - // We are trying to enable eDP, don't power down VDD - if (edp_stream) + if (edp_stream_num) keep_edp_vdd_on = true; } @@ -1712,6 +1736,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) /* eDP should not have stream in resume from S4 and so even with VBios post * it should get turned off */ + if (edp_with_sink_num) + edp_link_with_sink = edp_links_with_sink[0]; + if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { if (edp_link_with_sink && !keep_edp_vdd_on) { /*turn off backlight before DP_blank and encoder powered down*/ @@ -1723,7 +1750,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) if (edp_link_with_sink && !keep_edp_vdd_on) dc->hwss.edp_power_control(edp_link_with_sink, false); } - bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); + bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); } static uint32_t compute_pstate_blackout_duration( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index d7fcc5cccdce11a6f7a8d65f3db108916754618d..ef56eab4e5daa451217e5d0f967eba005b7d1533 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1272,6 +1272,8 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) /* update the public caps to indicate an underlay is available */ ctx->dc->caps.max_slave_planes = 1; + ctx->dc->caps.max_slave_yuv_planes = 1; + ctx->dc->caps.max_slave_rgb_planes = 0; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 9e796dfeac2040ea26699b0505c980aaa504c28e..714c71a5fbde3f34e1e16915b5a00583f99fa221 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -1257,6 +1257,16 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset) REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); } +void hubp1_set_flip_int(struct hubp *hubp) +{ + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + + REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT, + SURFACE_FLIP_INT_MASK, 1); + + return; +} + void hubp1_init(struct hubp *hubp) { //do nothing @@ -1290,6 +1300,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = { .dmdata_load = NULL, .hubp_soft_reset = hubp1_soft_reset, .hubp_in_blank = hubp1_in_blank, + .hubp_set_flip_int = hubp1_set_flip_int, }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h index a9a6ed7f4f9932345954fbbdd78dd49760330131..e2f2f6995935f062f09443f73d63dca626badc30 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h @@ -74,6 +74,7 @@ SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\ SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\ SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\ + SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\ SRI(HUBPRET_CONTROL, HUBPRET, id),\ SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\ SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\ @@ -183,6 +184,7 @@ uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ uint32_t DCSURF_SURFACE_CONTROL; \ + uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \ uint32_t HUBPRET_CONTROL; \ uint32_t DCN_EXPANSION_MODE; \ uint32_t DCHUBP_REQ_SIZE_CONFIG; \ @@ -332,6 +334,7 @@ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ @@ -531,6 +534,7 @@ type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ type SECONDARY_SURFACE_DCC_EN;\ type SECONDARY_SURFACE_DCC_IND_64B_BLK;\ + type SURFACE_FLIP_INT_MASK;\ type DET_BUF_PLANE1_BASE_ADDRESS;\ type CROSSBAR_SRC_CB_B;\ type CROSSBAR_SRC_CR_R;\ @@ -777,4 +781,6 @@ void hubp1_read_state_common(struct hubp *hubp); bool hubp1_in_blank(struct hubp *hubp); void hubp1_soft_reset(struct hubp *hubp, bool reset); +void hubp1_set_flip_int(struct hubp *hubp); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 89912bb5014f86fe5c57d756b6c209ea8eb02155..9eb33eae0e817c3c7f25ead1eee3b44ca259fa2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -53,6 +53,7 @@ #include "dsc.h" #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" +#include "dce/dmub_outbox.h" #define DC_LOGGER_INIT(logger) @@ -1355,6 +1356,10 @@ void dcn10_init_hw(struct dc *dc) hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); } + /* Enable outbox notification feature of dmub */ + if (dc->debug.enable_dmub_aux_for_legacy_ddc) + dmub_enable_outbox_notification(dc); + /* we want to turn off all dp displays before doing detection */ if (dc->config.power_down_display_on_boot) { uint8_t dpcd_power_state = '\0'; @@ -1457,19 +1462,26 @@ void dcn10_init_hw(struct dc *dc) */ void dcn10_power_down_on_boot(struct dc *dc) { - int i = 0; + struct dc_link *edp_links[MAX_NUM_EDP]; struct dc_link *edp_link; + int edp_num; + int i = 0; - edp_link = get_edp_link(dc); - if (edp_link && - edp_link->link_enc->funcs->is_dig_enabled && - edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && - dc->hwseq->funcs.edp_backlight_control && - dc->hwss.power_down && - dc->hwss.edp_power_control) { - dc->hwseq->funcs.edp_backlight_control(edp_link, false); - dc->hwss.power_down(dc); - dc->hwss.edp_power_control(edp_link, false); + get_edp_links(dc, edp_links, &edp_num); + + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwseq->funcs.edp_backlight_control && + dc->hwss.power_down && + dc->hwss.edp_power_control) { + dc->hwseq->funcs.edp_backlight_control(edp_link, false); + dc->hwss.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } } else { for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; @@ -1851,6 +1863,230 @@ static bool wait_for_reset_trigger_to_occur( return rc; } +uint64_t reduceSizeAndFraction( + uint64_t *numerator, + uint64_t *denominator, + bool checkUint32Bounary) +{ + int i; + bool ret = checkUint32Bounary == false; + uint64_t max_int32 = 0xffffffff; + uint64_t num, denom; + static const uint16_t prime_numbers[] = { + 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, + 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, + 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, + 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, + 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, + 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, + 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, + 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, + 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, + 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, + 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, + 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, + 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, + 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, + 941, 947, 953, 967, 971, 977, 983, 991, 997}; + int count = ARRAY_SIZE(prime_numbers); + + num = *numerator; + denom = *denominator; + for (i = 0; i < count; i++) { + uint32_t num_reminder, denom_reminder; + uint64_t num_result, denom_result; + if (checkUint32Bounary && + num <= max_int32 && denom <= max_int32) { + ret = true; + break; + } + do { + num_result = div_u64_rem(num, prime_numbers[i], &num_reminder); + denom_result = div_u64_rem(denom, prime_numbers[i], &denom_reminder); + if (num_reminder == 0 && denom_reminder == 0) { + num = num_result; + denom = denom_result; + } + } while (num_reminder == 0 && denom_reminder == 0); + } + *numerator = num; + *denominator = denom; + return ret; +} + +bool is_low_refresh_rate(struct pipe_ctx *pipe) +{ + uint32_t master_pipe_refresh_rate = + pipe->stream->timing.pix_clk_100hz * 100 / + pipe->stream->timing.h_total / + pipe->stream->timing.v_total; + return master_pipe_refresh_rate <= 30; +} + +uint8_t get_clock_divider(struct pipe_ctx *pipe, bool account_low_refresh_rate) +{ + uint32_t clock_divider = 1; + uint32_t numpipes = 1; + + if (account_low_refresh_rate && is_low_refresh_rate(pipe)) + clock_divider *= 2; + + if (pipe->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) + clock_divider *= 2; + + while (pipe->next_odm_pipe) { + pipe = pipe->next_odm_pipe; + numpipes++; + } + clock_divider *= numpipes; + + return clock_divider; +} + +int dcn10_align_pixel_clocks( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + int i, master = -1, embedded = -1; + struct dc_crtc_timing hw_crtc_timing[MAX_PIPES] = {0}; + uint64_t phase[MAX_PIPES]; + uint64_t modulo[MAX_PIPES]; + unsigned int pclk; + + uint32_t embedded_pix_clk_100hz; + uint16_t embedded_h_total; + uint16_t embedded_v_total; + bool clamshell_closed = false; + uint32_t dp_ref_clk_100hz = + dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; + + if (dc->config.vblank_alignment_dto_params && + dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) { + clamshell_closed = + (dc->config.vblank_alignment_dto_params >> 63); + embedded_h_total = + (dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF; + embedded_v_total = + (dc->config.vblank_alignment_dto_params >> 48) & 0x7FFF; + embedded_pix_clk_100hz = + dc->config.vblank_alignment_dto_params & 0xFFFFFFFF; + + for (i = 0; i < group_size; i++) { + grouped_pipes[i]->stream_res.tg->funcs->get_hw_timing( + grouped_pipes[i]->stream_res.tg, + &hw_crtc_timing[i]); + dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( + dc->res_pool->dp_clock_source, + grouped_pipes[i]->stream_res.tg->inst, + &pclk); + hw_crtc_timing[i].pix_clk_100hz = pclk; + if (dc_is_embedded_signal( + grouped_pipes[i]->stream->signal)) { + embedded = i; + master = i; + phase[i] = embedded_pix_clk_100hz*100; + modulo[i] = dp_ref_clk_100hz*100; + } else { + + phase[i] = (uint64_t)embedded_pix_clk_100hz* + hw_crtc_timing[i].h_total* + hw_crtc_timing[i].v_total; + phase[i] = div_u64(phase[i], get_clock_divider(grouped_pipes[i], true)); + modulo[i] = (uint64_t)dp_ref_clk_100hz* + embedded_h_total* + embedded_v_total; + + if (reduceSizeAndFraction(&phase[i], + &modulo[i], true) == false) { + /* + * this will help to stop reporting + * this timing synchronizable + */ + DC_SYNC_INFO("Failed to reduce DTO parameters\n"); + grouped_pipes[i]->stream->has_non_synchronizable_pclk = true; + } + } + } + + for (i = 0; i < group_size; i++) { + if (i != embedded && !grouped_pipes[i]->stream->has_non_synchronizable_pclk) { + dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk( + dc->res_pool->dp_clock_source, + grouped_pipes[i]->stream_res.tg->inst, + phase[i], modulo[i]); + dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( + dc->res_pool->dp_clock_source, + grouped_pipes[i]->stream_res.tg->inst, &pclk); + grouped_pipes[i]->stream->timing.pix_clk_100hz = + pclk*get_clock_divider(grouped_pipes[i], false); + if (master == -1) + master = i; + } + } + + } + return master; +} + +void dcn10_enable_vblanks_synchronization( + struct dc *dc, + int group_index, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + struct output_pixel_processor *opp; + struct timing_generator *tg; + int i, width, height, master; + + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1); + } + + for (i = 0; i < group_size; i++) { + if (grouped_pipes[i]->stream == NULL) + continue; + grouped_pipes[i]->stream->vblank_synchronized = false; + grouped_pipes[i]->stream->has_non_synchronizable_pclk = false; + } + + DC_SYNC_INFO("Aligning DP DTOs\n"); + + master = dcn10_align_pixel_clocks(dc, group_size, grouped_pipes); + + DC_SYNC_INFO("Synchronizing VBlanks\n"); + + if (master >= 0) { + for (i = 0; i < group_size; i++) { + if (i != master && !grouped_pipes[i]->stream->has_non_synchronizable_pclk) + grouped_pipes[i]->stream_res.tg->funcs->align_vblanks( + grouped_pipes[master]->stream_res.tg, + grouped_pipes[i]->stream_res.tg, + grouped_pipes[master]->stream->timing.pix_clk_100hz, + grouped_pipes[i]->stream->timing.pix_clk_100hz, + get_clock_divider(grouped_pipes[master], false), + get_clock_divider(grouped_pipes[i], false)); + grouped_pipes[i]->stream->vblank_synchronized = true; + } + grouped_pipes[master]->stream->vblank_synchronized = true; + DC_SYNC_INFO("Sync complete\n"); + } + + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, height); + } +} + void dcn10_enable_timing_synchronization( struct dc *dc, int group_index, @@ -1872,6 +2108,12 @@ void dcn10_enable_timing_synchronization( opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1); } + for (i = 0; i < group_size; i++) { + if (grouped_pipes[i]->stream == NULL) + continue; + grouped_pipes[i]->stream->vblank_synchronized = false; + } + for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( grouped_pipes[i]->stream_res.tg, @@ -2196,6 +2438,13 @@ static void dcn10_enable_plane( if (dc->debug.sanity_checks) { hws->funcs.verify_allow_pstate_change_high(dc); } + + if (!pipe_ctx->top_pipe + && pipe_ctx->plane_state + && pipe_ctx->plane_state->flip_int_enabled + && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) + pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); + } void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) @@ -2635,7 +2884,7 @@ static void dcn10_update_dchubp_dpp( hws->funcs.update_plane_addr(dc, pipe_ctx); if (is_pipe_tree_visible(pipe_ctx)) - dc->hwss.set_hubp_blank(dc, pipe_ctx, false); + hubp->funcs->set_blank(hubp, false); } void dcn10_blank_pixel_data( @@ -3146,16 +3395,13 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) return; } -static struct pipe_ctx *get_pipe_ctx_by_hubp_inst(struct dc_state *context, int mpcc_inst) +static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { int i; - for (i = 0; i < MAX_PIPES; i++) { - if (context->res_ctx.pipe_ctx[i].plane_res.hubp - && context->res_ctx.pipe_ctx[i].plane_res.hubp->inst == mpcc_inst) { - return &context->res_ctx.pipe_ctx[i]; - } - + for (i = 0; i < res_pool->pipe_count; i++) { + if (res_pool->hubps[i]->inst == mpcc_inst) + return res_pool->hubps[i]; } ASSERT(false); return NULL; @@ -3178,23 +3424,11 @@ void dcn10_wait_for_mpcc_disconnect( for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { - struct pipe_ctx *restore_bottom_pipe; - struct pipe_ctx *restore_top_pipe; - struct pipe_ctx *inst_pipe_ctx = get_pipe_ctx_by_hubp_inst(dc->current_state, mpcc_inst); + struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); - ASSERT(inst_pipe_ctx); res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; - /* - * Set top and bottom pipes NULL, as we don't want - * to blank those pipes when disconnecting from MPCC - */ - restore_bottom_pipe = inst_pipe_ctx->bottom_pipe; - restore_top_pipe = inst_pipe_ctx->top_pipe; - inst_pipe_ctx->top_pipe = inst_pipe_ctx->bottom_pipe = NULL; - dc->hwss.set_hubp_blank(dc, inst_pipe_ctx, true); - inst_pipe_ctx->top_pipe = restore_top_pipe; - inst_pipe_ctx->bottom_pipe = restore_bottom_pipe; + hubp->funcs->set_blank(hubp, true); } } @@ -3747,10 +3981,3 @@ void dcn10_get_clock(struct dc *dc, dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg); } - -void dcn10_set_hubp_blank(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank_enable) -{ - pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, blank_enable); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 89e6dfb63da0c1990ef4705aaa4f132ca7aec725..e0800cd1cc02091fec2a3589e152bb8a9905ef59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -123,6 +123,11 @@ void dcn10_enable_timing_synchronization( int group_index, int group_size, struct pipe_ctx *grouped_pipes[]); +void dcn10_enable_vblanks_synchronization( + struct dc *dc, + int group_index, + int group_size, + struct pipe_ctx *grouped_pipes[]); void dcn10_enable_per_frame_crtc_position_reset( struct dc *dc, int group_size, @@ -204,8 +209,5 @@ void dcn10_wait_for_pending_cleared(struct dc *dc, struct dc_state *context); void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx); void dcn10_verify_allow_pstate_change_high(struct dc *dc); -void dcn10_set_hubp_blank(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank_enable); #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c index 2f1b802e66a13e7afab10a6fa1ca1f104e643188..254300b06b434b0332df1f93e5c56a18d17fcc58 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c @@ -79,7 +79,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_backlight_level = dce110_set_backlight_level, .set_abm_immediate_disable = dce110_set_abm_immediate_disable, .set_pipe = dce110_set_pipe, - .set_hubp_blank = dcn10_set_hubp_blank, }; static const struct hwseq_private_funcs dcn10_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index b222c67973d469e0c65a56bdee9a2ef743cd3f2c..2529723beeb15c6bb2f47261bb3c6614a8f5b555 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -212,6 +212,7 @@ struct dcn_optc_registers { SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ @@ -352,6 +353,7 @@ struct dcn_optc_registers { type OTG_START_POINT_CNTL;\ type OTG_DISABLE_POINT_CNTL;\ type OTG_FIELD_NUMBER_CNTL;\ + type OTG_CURRENT_MASTER_EN_STATE;\ type OTG_STEREO_EN;\ type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 90e912fef2b36c069142e570bea412bb151486f4..d079f4e491e59ff92c19026fad4b4b5539f201a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -82,7 +82,7 @@ const struct _vcs_dpi_ip_params_st dcn1_0_ip = { .meta_chunk_size_kbytes = 2, .writeback_chunk_size_kbytes = 2, .line_buffer_size_bits = 589824, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .IsLineBufferBppFixed = 0, .LineBufferFixedBpp = -1, .writeback_luma_buffer_size_kbytes = 12, @@ -619,6 +619,7 @@ static const struct dc_debug_options debug_defaults_drv = { .recovery_enabled = false, /*enable this by default after testing.*/ .max_downscale_src_width = 3840, .underflow_assert_delay_us = 0xFFFFFFFF, + .use_max_lb = true }; static const struct dc_debug_options debug_defaults_diags = { @@ -630,6 +631,7 @@ static const struct dc_debug_options debug_defaults_diags = { .disable_pplib_clock_request = true, .disable_pplib_wm_range = true, .underflow_assert_delay_us = 0xFFFFFFFF, + .use_max_lb = true }; static void dcn10_dpp_destroy(struct dpp **dpp) @@ -1420,6 +1422,8 @@ static bool dcn10_resource_construct( dc->caps.max_cursor_size = 256; dc->caps.min_horizontal_blanking_period = 80; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 0; dc->caps.is_apu = true; dc->caps.post_blend_color_processing = false; dc->caps.extended_aux_timeout_support = false; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 73ac78b16bd4ffa214bcc3de1db11f5292e99218..f1a08a7736ac65423a34fcedd3785b34034761da 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -738,7 +738,6 @@ void enc1_stream_encoder_update_dp_info_packets( REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); - /* This bit is the master enable bit. * When enabling secondary stream engine, * this master bit must also be set. diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index 0df0da2e6a4d05f3c3256913273e41d066bf165f..bec7059f6d5d1579ed84b905f4f2bcd993bfd579 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -1597,6 +1597,7 @@ static struct hubp_funcs dcn20_hubp_funcs = { .validate_dml_output = hubp2_validate_dml_output, .hubp_in_blank = hubp1_in_blank, .hubp_soft_reset = hubp1_soft_reset, + .hubp_set_flip_int = hubp1_set_flip_int, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 0726fb435e2a3c175138262f9f3151223aabf77e..6a10daec15ccd03b096755f3cee40eccf12edf45 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1146,6 +1146,12 @@ void dcn20_enable_plane( pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); } + if (!pipe_ctx->top_pipe + && pipe_ctx->plane_state + && pipe_ctx->plane_state->flip_int_enabled + && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) + pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); + // if (dc->debug.sanity_checks) { // dcn10_verify_allow_pstate_change_high(dc); // } @@ -1501,38 +1507,8 @@ static void dcn20_update_dchubp_dpp( if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || pipe_ctx->stream->update_flags.bits.gamut_remap || pipe_ctx->stream->update_flags.bits.out_csc) { - struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; - - if (mpc->funcs->set_gamut_remap) { - int i; - int mpcc_id = hubp->inst; - struct mpc_grph_gamut_adjustment adjust; - bool enable_remap_dpp = false; - - memset(&adjust, 0, sizeof(adjust)); - adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - - /* save the enablement of gamut remap for dpp */ - enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap; - - /* force bypass gamut remap for dpp/cm */ - pipe_ctx->stream->gamut_remap_matrix.enable_remap = false; - dc->hwss.program_gamut_remap(pipe_ctx); - - /* restore gamut remap flag and use this remap into mpc */ - pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp; - - /* build remap matrix for top plane if enabled */ - if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) { - adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; - for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) - adjust.temperature_matrix[i] = - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; - } - mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust); - } else - /* dpp/cm gamut remap*/ - dc->hwss.program_gamut_remap(pipe_ctx); + /* dpp/cm gamut remap*/ + dc->hwss.program_gamut_remap(pipe_ctx); /*call the dcn2 method which uses mpc csc*/ dc->hwss.program_output_csc(dc, @@ -1575,8 +1551,8 @@ static void dcn20_update_dchubp_dpp( - if (is_pipe_tree_visible(pipe_ctx)) - dc->hwss.set_hubp_blank(dc, pipe_ctx, false); + if (pipe_ctx->update_flags.bits.enable) + hubp->funcs->set_blank(hubp, false); } @@ -1772,10 +1748,19 @@ void dcn20_post_unlock_program_front_end( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *mpcc_pipe; if (pipe->vtp_locked) { - dc->hwss.set_hubp_blank(dc, pipe, true); + dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); + pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); pipe->vtp_locked = false; + + for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) + mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); + + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) + dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); } } /* WA to apply WM setting*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c index 51a4166e975079caa604c2d9414d59d80a15a9fe..7218ed9e43dc5c79d8b6a689f7387b7004820dab 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c @@ -42,6 +42,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = { .program_output_csc = dcn20_program_output_csc, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_vblanks_synchronization = dcn10_enable_vblanks_synchronization, .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, @@ -94,7 +95,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = { .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft, #endif .set_disp_pattern_generator = dcn20_set_disp_pattern_generator, - .set_hubp_blank = dcn10_set_hubp_blank, }; static const struct hwseq_private_funcs dcn20_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index d8b18c515d067cd3ad7b4ba923f8dedddafbf88a..ea7eaf7d755f291ef4b817f055783c229adfe5e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -309,6 +309,129 @@ void optc2_set_dwb_source(struct timing_generator *optc, OPTC_DWB1_SOURCE_SELECT, optc->inst); } +void optc2_align_vblanks( + struct timing_generator *optc_master, + struct timing_generator *optc_slave, + uint32_t master_pixel_clock_100Hz, + uint32_t slave_pixel_clock_100Hz, + uint8_t master_clock_divider, + uint8_t slave_clock_divider) +{ + /* accessing slave OTG registers */ + struct optc *optc1 = DCN10TG_FROM_TG(optc_slave); + + uint32_t master_v_active = 0; + uint32_t master_h_total = 0; + uint32_t slave_h_total = 0; + uint64_t L, XY; + uint32_t X, Y, p = 10000; + uint32_t master_update_lock; + + /* disable slave OTG */ + REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); + /* wait until disabled */ + REG_WAIT(OTG_CONTROL, + OTG_CURRENT_MASTER_EN_STATE, + 0, 10, 5000); + + REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); + + /* assign slave OTG to be controlled by master update lock */ + REG_SET(OTG_GLOBAL_CONTROL0, 0, + OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst); + + /* accessing master OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_master); + + /* saving update lock state, not sure if it's needed */ + REG_GET(OTG_MASTER_UPDATE_LOCK, + OTG_MASTER_UPDATE_LOCK, &master_update_lock); + /* unlocking master OTG */ + REG_SET(OTG_MASTER_UPDATE_LOCK, 0, + OTG_MASTER_UPDATE_LOCK, 0); + + REG_GET(OTG_V_BLANK_START_END, + OTG_V_BLANK_START, &master_v_active); + REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); + + /* calculate when to enable slave OTG */ + L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz; + L = div_u64(L, master_h_total); + L = div_u64(L, slave_pixel_clock_100Hz); + XY = div_u64(L, p); + Y = master_v_active - XY - 1; + X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); + + /* + * set master OTG to unlock when V/H + * counters reach calculated values + */ + REG_UPDATE(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_EN, 1); + REG_UPDATE_2(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_X, + X, + MASTER_UPDATE_LOCK_DB_Y, + Y); + + /* lock master OTG */ + REG_SET(OTG_MASTER_UPDATE_LOCK, 0, + OTG_MASTER_UPDATE_LOCK, 1); + REG_WAIT(OTG_MASTER_UPDATE_LOCK, + UPDATE_LOCK_STATUS, 1, 1, 10); + + /* accessing slave OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_slave); + + /* + * enable slave OTG, the OTG is locked with + * master's update lock, so it will not run + */ + REG_UPDATE(OTG_CONTROL, + OTG_MASTER_EN, 1); + + /* accessing master OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_master); + + /* + * unlock master OTG. When master H/V counters reach + * DB_XY point, slave OTG will start + */ + REG_SET(OTG_MASTER_UPDATE_LOCK, 0, + OTG_MASTER_UPDATE_LOCK, 0); + + /* accessing slave OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_slave); + + /* wait for slave OTG to start running*/ + REG_WAIT(OTG_CONTROL, + OTG_CURRENT_MASTER_EN_STATE, + 1, 10, 5000); + + /* accessing master OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_master); + + /* disable the XY point*/ + REG_UPDATE(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_EN, 0); + REG_UPDATE_2(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_X, + 0, + MASTER_UPDATE_LOCK_DB_Y, + 0); + + /*restore master update lock*/ + REG_SET(OTG_MASTER_UPDATE_LOCK, 0, + OTG_MASTER_UPDATE_LOCK, master_update_lock); + + /* accessing slave OTG registers */ + optc1 = DCN10TG_FROM_TG(optc_slave); + /* restore slave to be controlled by it's own */ + REG_SET(OTG_GLOBAL_CONTROL0, 0, + OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst); + +} + void optc2_triplebuffer_lock(struct timing_generator *optc) { struct optc *optc1 = DCN10TG_FROM_TG(optc); @@ -468,6 +591,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = { .program_manual_trigger = optc2_program_manual_trigger, .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, + .align_vblanks = optc2_align_vblanks, }; void dcn20_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 2c2dbfcd89571089741f14f84e366343aeb34657..2307b3517821da946f2de5a9bf356cad71825c53 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -112,7 +112,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = { .is_line_buffer_bpp_fixed = 0, .line_buffer_fixed_bpp = 0, .dcc_supported = true, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -180,7 +180,7 @@ static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { .is_line_buffer_bpp_fixed = 0, .line_buffer_fixed_bpp = 0, .dcc_supported = true, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -1075,6 +1075,7 @@ static const struct dc_debug_options debug_defaults_drv = { .scl_reset_length10 = true, .sanity_checks = false, .underflow_assert_delay_us = 0xFFFFFFFF, + .use_max_lb = true }; static const struct dc_debug_options debug_defaults_diags = { @@ -1091,6 +1092,7 @@ static const struct dc_debug_options debug_defaults_diags = { .scl_reset_length10 = true, .underflow_assert_delay_us = 0xFFFFFFFF, .enable_tri_buf = true, + .use_max_lb = true }; void dcn20_dpp_destroy(struct dpp **dpp) @@ -2033,9 +2035,13 @@ int dcn20_populate_dml_pipes_from_context( if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) continue; - if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( + if (dc->debug.disable_timing_sync || + (!resource_are_streams_timing_synchronizable( res_ctx->pipe_ctx[pipe_cnt].stream, - res_ctx->pipe_ctx[i].stream)) { + res_ctx->pipe_ctx[i].stream) && + !resource_are_vblanks_synchronizable( + res_ctx->pipe_ctx[pipe_cnt].stream, + res_ctx->pipe_ctx[i].stream))) { synchronized_vblank = false; break; } @@ -3697,6 +3703,8 @@ static bool dcn20_resource_construct( dc->caps.dmdata_alloc_size = 2048; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.extended_aux_timeout_support = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c index f9045852728fe5fb0a0b6f8416a0ac188e51a737..b0c9180b808f6cf577bde2704331cad17b173451 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c @@ -838,6 +838,7 @@ static struct hubp_funcs dcn21_hubp_funcs = { .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, .hubp_init = hubp21_init, .validate_dml_output = hubp21_validate_dml_output, + .hubp_set_flip_int = hubp1_set_flip_int, }; bool hubp21_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c index 0597391b21716bd89a138a9930c6a5f5415974e7..074e2713257f179dbc8cc642665e3d50765db686 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c @@ -99,7 +99,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = { #endif .is_abm_supported = dcn21_is_abm_supported, .set_disp_pattern_generator = dcn20_set_disp_pattern_generator, - .set_hubp_blank = dcn10_set_hubp_blank, }; static const struct hwseq_private_funcs dcn21_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 072f8c880924366ffd42477a3ffd79886611748a..e62f931fc269fcfb7e9c04798a17924fd4bd32c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -61,7 +61,6 @@ #include "dcn21/dcn21_dccg.h" #include "dcn21_hubbub.h" #include "dcn10/dcn10_resource.h" -#include "dce110/dce110_resource.h" #include "dce/dce_panel_cntl.h" #include "dcn20/dcn20_dwb.h" @@ -116,7 +115,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = { .is_line_buffer_bpp_fixed = 0, .line_buffer_fixed_bpp = 0, .dcc_supported = true, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -296,7 +295,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .num_banks = 8, .num_chans = 4, .vmm_page_size_bytes = 4096, - .dram_clock_change_latency_us = 11.72, + .dram_clock_change_latency_us = 23.84, .return_bus_width_bytes = 64, .dispclk_dppclk_vco_speed_mhz = 3600, .xfc_bus_transport_time_us = 4, @@ -883,7 +882,9 @@ static const struct dc_debug_options debug_defaults_drv = { .scl_reset_length10 = true, .sanity_checks = true, .disable_48mhz_pwrdwn = false, - .usbc_combo_phy_reset_wa = true + .usbc_combo_phy_reset_wa = true, + .dmub_command_table = true, + .use_max_lb = true }; static const struct dc_debug_options debug_defaults_diags = { @@ -899,7 +900,8 @@ static const struct dc_debug_options debug_defaults_diags = { .disable_stutter = true, .disable_48mhz_pwrdwn = true, .disable_psr = true, - .enable_tri_buf = true + .enable_tri_buf = true, + .use_max_lb = true }; enum dcn20_clk_src_array_id { @@ -1062,8 +1064,6 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s { int i; - DC_FP_START(); - if (dc->bb_overrides.sr_exit_time_ns) { for (i = 0; i < WM_SET_COUNT; i++) { dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = @@ -1088,8 +1088,6 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; } } - - DC_FP_END(); } void dcn21_calculate_wm( @@ -1339,7 +1337,7 @@ static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); + display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); BW_VAL_TRACE_COUNT(); @@ -1599,6 +1597,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param dcn2_1_soc.num_chans = bw_params->num_channels; ASSERT(clk_table->num_entries); + /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ + for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { + clock_limits[i] = dcn2_1_soc.clock_limits[i]; + } + for (i = 0; i < clk_table->num_entries; i++) { /* loop backwards*/ for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { @@ -1632,11 +1635,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param dcn2_1_soc.clock_limits[i] = clock_limits[i]; if (clk_table->num_entries) { dcn2_1_soc.num_states = clk_table->num_entries + 1; + /* fill in min DF PState */ + dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); /* duplicate last level */ dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; - /* fill in min DF PState */ - dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); } dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); @@ -1979,6 +1982,8 @@ static bool dcn21_resource_construct( dc->caps.dmdata_alloc_size = 2048; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.extended_aux_timeout_support = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index 41a1d0e9b7e207bb855bc268f897eba21078b769..e0df9b0065f9c05a528c7eec66a187ba126d80ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -113,6 +113,7 @@ bool cm3_helper_translate_curve_to_hw_format( struct pwl_result_data *rgb_resulted; struct pwl_result_data *rgb; struct pwl_result_data *rgb_plus_1; + struct pwl_result_data *rgb_minus_1; struct fixed31_32 end_value; int32_t region_start, region_end; @@ -140,7 +141,7 @@ bool cm3_helper_translate_curve_to_hw_format( region_start = -MAX_LOW_POINT; region_end = NUMBER_REGIONS - MAX_LOW_POINT; } else { - /* 10 segments + /* 11 segments * segment is from 2^-10 to 2^0 * There are less than 256 points, for optimization */ @@ -154,9 +155,10 @@ bool cm3_helper_translate_curve_to_hw_format( seg_distr[7] = 4; seg_distr[8] = 4; seg_distr[9] = 4; + seg_distr[10] = 1; region_start = -10; - region_end = 0; + region_end = 1; } for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) @@ -189,6 +191,10 @@ bool cm3_helper_translate_curve_to_hw_format( rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red; + rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green; + rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue; + // All 3 color channels have same x corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), dc_fixpt_from_int(region_start)); @@ -259,15 +265,18 @@ bool cm3_helper_translate_curve_to_hw_format( rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; + rgb_minus_1 = rgb; i = 1; while (i != hw_points + 1) { - if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) - rgb_plus_1->red = rgb->red; - if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) - rgb_plus_1->green = rgb->green; - if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) - rgb_plus_1->blue = rgb->blue; + if (i >= hw_points - 1) { + if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) + rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red); + if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) + rgb_plus_1->green = dc_fixpt_add(rgb->green, rgb_minus_1->delta_green); + if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) + rgb_plus_1->blue = dc_fixpt_add(rgb->blue, rgb_minus_1->delta_blue); + } rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); @@ -283,6 +292,7 @@ bool cm3_helper_translate_curve_to_hw_format( } ++rgb_plus_1; + rgb_minus_1 = rgb; ++rgb; ++i; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index 6c0f7ef0a3dfafc281ab39af98620b4d08d89ea1..72bee637c1e48c78e02bb9dd0730498bbc3a2c6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -454,7 +454,6 @@ static void enc3_stream_encoder_update_dp_info_packets( REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); - /* This bit is the master enable bit. * When enabling secondary stream engine, * this master bit must also be set. diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index 6e864b1a95c41077f48d7410009540acd3b9d854..434d3c46cad480774989ed226e2d2654e8492101 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -718,7 +718,7 @@ bool dpp3_program_blnd_lut( next_mode = LUT_RAM_B; dpp3_power_on_blnd_lut(dpp_base, true); - dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); + dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) dpp3_program_blnd_luta_settings(dpp_base, params); @@ -1136,7 +1136,7 @@ bool dpp3_program_shaper( else next_mode = LUT_RAM_A; - dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); + dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) dpp3_program_shaper_luta_settings(dpp_base, params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c index 33985401f25cba88b822bc15ad3d26c9cd70a09e..72c5687adc681c9a2b3edcd03580af178a988d53 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c @@ -240,7 +240,7 @@ bool dpp3_program_gamcor_lut( next_mode = LUT_RAM_A; dpp3_power_on_gamcor_lut(dpp_base, true); - dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); + dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_B) { gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); @@ -295,7 +295,7 @@ bool dpp3_program_gamcor_lut( cm_helper_program_gamcor_xfer_func(dpp_base->ctx, params, &gam_regs); dpp3_program_gammcor_lut(dpp_base, params->rgb_resulted, params->hw_points_num, - next_mode == LUT_RAM_A ? true:false); + next_mode == LUT_RAM_A); //select Gamma LUT to use for next frame REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c index 8593145379d99d81f2bd4203beb3e3d6769ecd2c..3fe9e41e4dbd7627e474caa9e348097bce32c489 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c @@ -217,7 +217,7 @@ static bool dwb3_program_ogam_lut( else next_mode = LUT_RAM_A; - dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A ? true : false); + dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) dwb3_program_ogam_luta_settings(dwbc30, params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c index 88ffa9ff1ed15bd5d7e8e7184832fa6c5bd840e6..f246125232482c894f5440c9c6682924577c7f49 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c @@ -511,6 +511,7 @@ static struct hubp_funcs dcn30_hubp_funcs = { .hubp_init = hubp3_init, .hubp_in_blank = hubp1_in_blank, .hubp_soft_reset = hubp1_soft_reset, + .hubp_set_flip_int = hubp1_set_flip_int, }; bool hubp3_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 06dc1e2e8383acdb2bc8d3819e07e3df8dbf763e..d53f8b39699b33abf375174d18ec1af42401ae3a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -421,11 +421,12 @@ void dcn30_program_all_writeback_pipes_in_tree( void dcn30_init_hw(struct dc *dc) { - int i, j; struct abm **abms = dc->res_pool->multiple_abms; struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; + int i, j; + int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) @@ -574,17 +575,23 @@ void dcn30_init_hw(struct dc *dc) * if DIG is turned on and seamless boot not enabled */ if (dc->config.power_down_display_on_boot) { - struct dc_link *edp_link = get_edp_link(dc); - - if (edp_link && - edp_link->link_enc->funcs->is_dig_enabled && - edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && - dc->hwss.edp_backlight_control && - dc->hwss.power_down && - dc->hwss.edp_power_control) { - dc->hwss.edp_backlight_control(edp_link, false); - dc->hwss.power_down(dc); - dc->hwss.edp_power_control(edp_link, false); + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link; + + get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwss.edp_backlight_control && + dc->hwss.power_down && + dc->hwss.edp_power_control) { + dc->hwss.edp_backlight_control(edp_link, false); + dc->hwss.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } } else { for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; @@ -651,7 +658,7 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) if (pipe_ctx == NULL) return; - if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) + if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) pipe_ctx->stream_res.stream_enc->funcs->set_avmute( pipe_ctx->stream_res.stream_enc, enable); @@ -848,7 +855,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; cmd.mall.cursor_copy_dst.quad_part = - plane->address.grph.cursor_cache_addr.quad_part; + (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; cmd.mall.cursor_width = cursor_attr.width; cmd.mall.cursor_height = cursor_attr.height; cmd.mall.cursor_pitch = cursor_attr.pitch; @@ -858,8 +865,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); /* Use copied cursor, and it's okay to not switch back */ - cursor_attr.address.quad_part = - plane->address.grph.cursor_cache_addr.quad_part; + cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part; dc_stream_set_cursor_attributes(stream, &cursor_attr); } @@ -940,53 +946,6 @@ void dcn30_hardware_release(struct dc *dc) dc->res_pool->hubbub, true, true); } -void dcn30_set_hubp_blank(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank_enable) -{ - struct pipe_ctx *mpcc_pipe; - struct pipe_ctx *odm_pipe; - - if (blank_enable) { - struct plane_resource *plane_res = &pipe_ctx->plane_res; - struct stream_resource *stream_res = &pipe_ctx->stream_res; - - /* Wait for enter vblank */ - stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK); - - /* Blank HUBP to allow p-state during blank on all timings */ - pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true); - /* Confirm hubp in blank */ - ASSERT(plane_res->hubp->funcs->hubp_in_blank(plane_res->hubp)); - /* Toggle HUBP_DISABLE */ - plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, true); - plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, false); - for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) { - mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); - /* Confirm hubp in blank */ - ASSERT(mpcc_pipe->plane_res.hubp->funcs->hubp_in_blank(mpcc_pipe->plane_res.hubp)); - /* Toggle HUBP_DISABLE */ - mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, true); - mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, false); - - } - for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { - odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, true); - /* Confirm hubp in blank */ - ASSERT(odm_pipe->plane_res.hubp->funcs->hubp_in_blank(odm_pipe->plane_res.hubp)); - /* Toggle HUBP_DISABLE */ - odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, true); - odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, false); - } - } else { - pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false); - for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) - mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false); - for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) - odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, false); - } -} - void dcn30_set_disp_pattern_generator(const struct dc *dc, struct pipe_ctx *pipe_ctx, enum controller_dp_test_pattern test_pattern, @@ -996,6 +955,7 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, int width, int height, int offset) { struct stream_resource *stream_res = &pipe_ctx->stream_res; + struct pipe_ctx *mpcc_pipe; if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) { pipe_ctx->vtp_locked = false; @@ -1007,12 +967,20 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) { if (stream_res->tg->funcs->is_locked(stream_res->tg)) pipe_ctx->vtp_locked = true; - else - dc->hwss.set_hubp_blank(dc, pipe_ctx, true); + else { + /* Blank HUBP to allow p-state during blank on all timings */ + pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true); + + for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) + mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); + } } } else { - dc->hwss.set_hubp_blank(dc, pipe_ctx, false); /* turning off DPG */ + pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false); + for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) + mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false); + stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, color_depth, solid_color, width, height, offset); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h index 3b7d4812e3119b1008f081f8da156a2aa6318c1a..e9a0005288d32168d1995353725cffca1918adbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h @@ -80,8 +80,4 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, const struct tg_color *solid_color, int width, int height, int offset); -void dcn30_set_hubp_blank(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank_enable); - #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index 204444fead9777cb4399fd97244380b0c7979165..c4c14e9c1309c2653bbbab16e0843f8fecd0dd24 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -98,7 +98,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .hardware_release = dcn30_hardware_release, .set_pipe = dcn21_set_pipe, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, - .set_hubp_blank = dcn30_set_hubp_blank, }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c index 3e6f76096119c8cbe2e1fc9709b9a20bfc13e2a5..910c17fd42789326500d5dc979b39402d8253fa8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c @@ -143,16 +143,18 @@ static void mpc3_power_on_ogam_lut( { struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { - // Force power on - REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0); - // Wait for confirmation when powering on - if (power_on) - REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); - } else { - REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, - MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); - } + /* + * Powering on: force memory active so the LUT can be updated. + * Powering off: allow entering memory low power mode + * + * Memory low power mode is controlled during MPC OGAM LUT init. + */ + REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], + MPCC_OGAM_MEM_PWR_DIS, power_on != 0); + + /* Wait for memory to be powered on - we won't be able to write to it otherwise. */ + if (power_on) + REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); } static void mpc3_configure_ogam_lut( @@ -355,7 +357,7 @@ void mpc3_set_output_gamma( next_mode = LUT_RAM_A; mpc3_power_on_ogam_lut(mpc, mpcc_id, true); - mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? true:false); + mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) mpc3_program_luta(mpc, mpcc_id, params); @@ -1427,7 +1429,7 @@ const struct mpc_funcs dcn30_mpc_funcs = { .acquire_rmu = mpcc3_acquire_rmu, .program_3dlut = mpc3_program_3dlut, .release_rmu = mpcc3_release_rmu, - .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, + .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 8d0f663489ac5a915330f7f1d689d299daed647f..263c2986682d2521b9450093e8e72d706d6b6d11 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -120,7 +120,7 @@ struct _vcs_dpi_ip_params_st dcn3_0_ip = { .dcc_supported = true, .writeback_interface_buffer_size_kbytes = 90, .writeback_line_buffer_buffer_size = 0, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -181,7 +181,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { }, .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ .num_states = 1, - .sr_exit_time_us = 12, + .sr_exit_time_us = 15.5, .sr_enter_plus_exit_time_us = 20, .urgent_latency_us = 4.0, .urgent_latency_pixel_data_only_us = 4.0, @@ -852,6 +852,7 @@ static const struct dc_debug_options debug_defaults_drv = { .dwb_fi_phase = -1, // -1 = disable, .dmub_command_table = true, .disable_psr = false, + .use_max_lb = true }; static const struct dc_debug_options debug_defaults_diags = { @@ -870,6 +871,7 @@ static const struct dc_debug_options debug_defaults_diags = { .dmub_command_table = true, .disable_psr = true, .enable_tri_buf = true, + .use_max_lb = true }; void dcn30_dpp_destroy(struct dpp **dpp) @@ -1874,6 +1876,7 @@ static noinline bool dcn30_internal_validate_bw( if (!pipes) return false; + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); DC_FP_START(); @@ -2223,11 +2226,7 @@ static noinline void dcn30_calculate_wm_and_dlg_fp( * * Set A calculated last so that following calculations are based on Set A */ - if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; - context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; - } + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; @@ -2270,6 +2269,15 @@ static noinline void dcn30_calculate_wm_and_dlg_fp( dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; } +void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) +{ + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; + } +} + void dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, @@ -2494,6 +2502,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .panel_cntl_create = dcn30_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx = dcn30_add_stream_to_ctx, @@ -2508,6 +2517,19 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, }; +#define CTX ctx + +#define REG(reg_name) \ + (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) + +static uint32_t read_pipe_fuses(struct dc_context *ctx) +{ + uint32_t value = REG_READ(CC_DC_PIPE_DIS); + /* Support for max 6 pipes */ + value = value & 0x3f; + return value; +} + static bool dcn30_resource_construct( uint8_t num_virtual_links, struct dc *dc, @@ -2517,6 +2539,15 @@ static bool dcn30_resource_construct( struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; struct ddc_service_init_data ddc_init_data; + uint32_t pipe_fuses = read_pipe_fuses(ctx); + uint32_t num_pipes = 0; + + if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: Unexpected fuse recipe for navi2x !\n"); + /* fault to single pipe */ + pipe_fuses = 0x3e; + } DC_FP_START(); @@ -2544,6 +2575,8 @@ static bool dcn30_resource_construct( dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.extended_aux_timeout_support = true; @@ -2650,6 +2683,15 @@ static bool dcn30_resource_construct( /* PP Lib and SMU interfaces */ init_soc_bounding_box(dc, pool); + num_pipes = dcn3_0_ip.max_num_dpp; + + for (i = 0; i < dcn3_0_ip.max_num_dpp; i++) + if (pipe_fuses & 1 << i) + num_pipes--; + + dcn3_0_ip.max_num_dpp = num_pipes; + dcn3_0_ip.max_num_otg = num_pipes; + dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); /* IRQ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h index 8ce7f6d39a204b115c65e63af2b82ae41744927b..b754b89beadfb9d55826f5999e06eca6e69585c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h @@ -60,6 +60,7 @@ void dcn30_calculate_wm_and_dlg( display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel); +void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); void dcn30_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c index b8bf6d61005b070cf66923b01be618753dd3fce3..bdad72140cbcec03fe2b61a6b544ec150904d4f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c @@ -98,7 +98,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, .set_pipe = dcn21_set_pipe, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, - .set_hubp_blank = dcn30_set_hubp_blank, }; static const struct hwseq_private_funcs dcn301_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index 5d4b2c60192ee49763f318777ce4271cf5554feb..622a5bf9737f713240f14641cce2c090d372c47d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -116,7 +116,7 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = { .dcc_supported = true, .writeback_interface_buffer_size_kbytes = 90, .writeback_line_buffer_buffer_size = 656640, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -873,6 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = { .underflow_assert_delay_us = 0xFFFFFFFF, .dwb_fi_phase = -1, // -1 = disable .dmub_command_table = true, + .use_max_lb = false, }; static const struct dc_debug_options debug_defaults_diags = { @@ -889,6 +890,7 @@ static const struct dc_debug_options debug_defaults_diags = { .scl_reset_length10 = true, .dwb_fi_phase = -1, // -1 = disable .dmub_command_table = true, + .use_max_lb = false, }; void dcn301_dpp_destroy(struct dpp **dpp) @@ -1619,12 +1621,107 @@ static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); } +static void calculate_wm_set_for_vlevel( + int vlevel, + struct wm_range_table_entry *table_entry, + struct dcn_watermarks *wm_set, + struct display_mode_lib *dml, + display_e2e_pipe_params_st *pipes, + int pipe_cnt) +{ + double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; + + ASSERT(vlevel < dml->soc.num_states); + /* only pipe 0 is read for voltage and dcf/soc clocks */ + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; + pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; + + dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; + dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; + dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; + + wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; + wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; + wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; + wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; + wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; + wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; + wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; + dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; + +} + +static void dcn301_calculate_wm_and_dlg( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel_req) +{ + int i, pipe_idx; + int vlevel, vlevel_max; + struct wm_range_table_entry *table_entry; + struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; + + ASSERT(bw_params); + + vlevel_max = bw_params->clk_table.num_entries - 1; + + /* WM Set D */ + table_entry = &bw_params->wm_table.entries[WM_D]; + if (table_entry->wm_type == WM_TYPE_RETRAINING) + vlevel = 0; + else + vlevel = vlevel_max; + calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, + &context->bw_ctx.dml, pipes, pipe_cnt); + /* WM Set C */ + table_entry = &bw_params->wm_table.entries[WM_C]; + vlevel = min(max(vlevel_req, 2), vlevel_max); + calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, + &context->bw_ctx.dml, pipes, pipe_cnt); + /* WM Set B */ + table_entry = &bw_params->wm_table.entries[WM_B]; + vlevel = min(max(vlevel_req, 1), vlevel_max); + calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, + &context->bw_ctx.dml, pipes, pipe_cnt); + + /* WM Set A */ + table_entry = &bw_params->wm_table.entries[WM_A]; + vlevel = min(vlevel_req, vlevel_max); + calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, + &context->bw_ctx.dml, pipes, pipe_cnt); + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + + pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); + pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + + if (dc->config.forced_clocks) { + pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; + pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; + } + if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; + if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; + + pipe_idx++; + } + + dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); +} + static struct resource_funcs dcn301_res_pool_funcs = { .destroy = dcn301_destroy_resource_pool, .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx = dcn30_add_stream_to_ctx, @@ -1670,6 +1767,8 @@ static bool dcn301_resource_construct( dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; dc->caps.is_apu = true; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c index 4b659b63f75b3d3aea15df00bb218d25957904a9..0723e29fd42e305a5b0dcf2f05a230d11ba61f43 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c @@ -101,7 +101,7 @@ struct _vcs_dpi_ip_params_st dcn3_02_ip = { .dcc_supported = true, .writeback_interface_buffer_size_kbytes = 90, .writeback_line_buffer_buffer_size = 0, - .max_line_buffer_lines = 12, + .max_line_buffer_lines = 32, .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 .writeback_chroma_buffer_size_kbytes = 8, .writeback_chroma_line_buffer_width_pixels = 4, @@ -223,6 +223,7 @@ static const struct dc_debug_options debug_defaults_drv = { .underflow_assert_delay_us = 0xFFFFFFFF, .dwb_fi_phase = -1, // -1 = disable, .dmub_command_table = true, + .use_max_lb = true }; static const struct dc_debug_options debug_defaults_diags = { @@ -241,6 +242,7 @@ static const struct dc_debug_options debug_defaults_diags = { .dmub_command_table = true, .enable_tri_buf = true, .disable_psr = true, + .use_max_lb = true }; enum dcn302_clk_src_array_id { @@ -1395,6 +1397,7 @@ static struct resource_funcs dcn302_res_pool_funcs = { .panel_cntl_create = dcn302_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx = dcn30_add_stream_to_ctx, @@ -1481,6 +1484,8 @@ static bool dcn302_resource_construct( dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.extended_aux_timeout_support = true; diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 07e349b1067b61ab904c0915c83b11080d583be5..f41db27c44de5e05666e4b89ab642ca2e8773e6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -156,4 +156,6 @@ void dm_set_dcn_clocks( struct dc_context *ctx, struct dc_clocks *clks); +bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable); + #endif /* __DM_HELPERS__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 0f3f510fd83b8a0b54542145df9c44a90507eed7..9729cf292e8494a848bfeba92e180a3e9110b943 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -3437,6 +3437,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DCCEnabledInAnyPlane = true; } } + mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly; for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { locals->FabricAndDRAMBandwidthPerState[i] = dml_min( mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 210c96cd5b03b5bfe4277f84e3562c4f51e42fc4..51098c2c9854867ad4d8a6460051a64f887831d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -3544,6 +3544,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.DCCEnabledInAnyPlane = true; } } + mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly; for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { locals->FabricAndDRAMBandwidthPerState[i] = dml_min( mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index bc07082c135755950e31b63af9bec7356907db1d..cb3f70a71b51258e159f3f939a17606d67328219 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -4050,7 +4050,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2; v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1; - v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1; + v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1; } } if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index bc0485a59018ad2622e3c19c2895b340cbe44c2f..94036a9612cf8f11b4c08d4991e8683e60ae7ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -599,7 +599,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) { display_pipe_source_params_st *src_k = &pipes[k].pipe.src; display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest; - display_output_params_st *dout_k = &pipes[j].dout; if (src_k->is_hsplit && !visited[k] && src->hsplit_grp == src_k->hsplit_grp) { @@ -620,8 +619,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] += src_k->viewport_height_c; } - mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] += - dout_k->dsc_slices; visited[k] = true; } diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index c62d0eddc9c61164afb68b12099155b1105ff9a5..be57088d185dcd46f7ad5f6f26e922d97a3fedfa 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -37,59 +37,6 @@ static uint32_t dsc_policy_max_target_bpp_limit = 16; /* default DSC policy enables DSC only when needed */ static bool dsc_policy_enable_dsc_when_not_needed; -static uint32_t dc_dsc_bandwidth_in_kbps_from_timing( - const struct dc_crtc_timing *timing) -{ - uint32_t bits_per_channel = 0; - uint32_t kbps; - - if (timing->flags.DSC) { - kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); - kbps = kbps / 160 + ((kbps % 160) ? 1 : 0); - return kbps; - } - - switch (timing->display_color_depth) { - case COLOR_DEPTH_666: - bits_per_channel = 6; - break; - case COLOR_DEPTH_888: - bits_per_channel = 8; - break; - case COLOR_DEPTH_101010: - bits_per_channel = 10; - break; - case COLOR_DEPTH_121212: - bits_per_channel = 12; - break; - case COLOR_DEPTH_141414: - bits_per_channel = 14; - break; - case COLOR_DEPTH_161616: - bits_per_channel = 16; - break; - default: - break; - } - - ASSERT(bits_per_channel != 0); - - kbps = timing->pix_clk_100hz / 10; - kbps *= bits_per_channel; - - if (timing->flags.Y_ONLY != 1) { - /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/ - kbps *= 3; - if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) - kbps /= 2; - else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) - kbps = kbps * 2 / 3; - } - - return kbps; - -} - static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size) { @@ -315,18 +262,18 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value) * and uncompressed bandwidth. */ static void get_dsc_bandwidth_range( - const uint32_t min_bpp, - const uint32_t max_bpp, + const uint32_t min_bpp_x16, + const uint32_t max_bpp_x16, const struct dsc_enc_caps *dsc_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) { /* native stream bandwidth */ - range->stream_kbps = dc_dsc_bandwidth_in_kbps_from_timing(timing); + range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing); /* max dsc target bpp */ - range->max_kbps = dsc_div_by_10_round_up(max_bpp * timing->pix_clk_100hz); - range->max_target_bpp_x16 = max_bpp * 16; + range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, max_bpp_x16); + range->max_target_bpp_x16 = max_bpp_x16; if (range->max_kbps > range->stream_kbps) { /* max dsc target bpp is capped to native bandwidth */ range->max_kbps = range->stream_kbps; @@ -334,8 +281,8 @@ static void get_dsc_bandwidth_range( } /* min dsc target bpp */ - range->min_kbps = dsc_div_by_10_round_up(min_bpp * timing->pix_clk_100hz); - range->min_target_bpp_x16 = min_bpp * 16; + range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, min_bpp_x16); + range->min_target_bpp_x16 = min_bpp_x16; if (range->min_kbps > range->max_kbps) { /* min dsc target bpp is capped to max dsc bandwidth*/ range->min_kbps = range->max_kbps; @@ -363,12 +310,17 @@ static bool decide_dsc_target_bpp_x16( memset(&range, 0, sizeof(range)); - get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp, + get_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16, dsc_common_caps, timing, &range); if (!policy->enable_dsc_when_not_needed && target_bandwidth_kbps >= range.stream_kbps) { /* enough bandwidth without dsc */ *target_bpp_x16 = 0; should_use_dsc = false; + } else if (policy->preferred_bpp_x16 > 0 && + policy->preferred_bpp_x16 <= range.max_target_bpp_x16 && + policy->preferred_bpp_x16 >= range.min_target_bpp_x16) { + *target_bpp_x16 = policy->preferred_bpp_x16; + should_use_dsc = true; } else if (target_bandwidth_kbps >= range.max_kbps) { /* use max target bpp allowed */ *target_bpp_x16 = range.max_target_bpp_x16; @@ -545,7 +497,7 @@ static bool setup_dsc_config( int target_bandwidth_kbps, const struct dc_crtc_timing *timing, int min_slice_height_override, - int max_dsc_target_bpp_limit_override, + int max_dsc_target_bpp_limit_override_x16, struct dc_dsc_config *dsc_cfg) { struct dsc_enc_caps dsc_common_caps; @@ -564,7 +516,7 @@ static bool setup_dsc_config( memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); - dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy); + dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override_x16, &policy); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; @@ -865,8 +817,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da bool dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, uint32_t dsc_min_slice_height_override, - uint32_t min_bpp, - uint32_t max_bpp, + uint32_t min_bpp_x16, + uint32_t max_bpp_x16, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) @@ -883,10 +835,10 @@ bool dc_dsc_compute_bandwidth_range( if (is_dsc_possible) is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing, - dsc_min_slice_height_override, max_bpp, &config); + dsc_min_slice_height_override, max_bpp_x16, &config); if (is_dsc_possible) - get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range); + get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range); return is_dsc_possible; } @@ -908,11 +860,20 @@ bool dc_dsc_compute_config( &dsc_enc_caps, target_bandwidth_kbps, timing, dsc_min_slice_height_override, - max_target_bpp_limit_override, dsc_cfg); + max_target_bpp_limit_override * 16, dsc_cfg); return is_dsc_possible; } -void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy) +uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16) +{ + struct fixed31_32 link_bw_kbps; + link_bw_kbps = dc_fixpt_from_int(pix_clk_100hz); + link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160); + link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, bpp_x16); + return dc_fixpt_ceil(link_bw_kbps); +} + +void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy) { uint32_t bpc = 0; @@ -967,13 +928,15 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t return; } + policy->preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16; + /* internal upper limit, default 16 bpp */ if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit) policy->max_target_bpp = dsc_policy_max_target_bpp_limit; /* apply override */ - if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override) - policy->max_target_bpp = max_target_bpp_limit_override; + if (max_target_bpp_limit_override_x16 && policy->max_target_bpp > max_target_bpp_limit_override_x16 / 16) + policy->max_target_bpp = max_target_bpp_limit_override_x16 / 16; /* enable DSC when not needed, default false */ if (dsc_policy_enable_dsc_when_not_needed) diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c index 66e4841f41e4e2021e7b456e457b143e1f033998..ca335ea60412c5a4f10f44de52889a1c9c6da9b3 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c @@ -48,10 +48,6 @@ #define REGI(reg_name, block, id)\ mm ## block ## id ## _ ## reg_name -#include "../hw_gpio.h" -#include "../hw_ddc.h" -#include "../hw_hpd.h" - #include "reg_helper.h" #include "../hpd_regs.h" diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c index 5e384a8a83dc21713d1a8bde89b779826713fca4..51855a2624cf4356b1ba32650d49731e1ac72fda 100644 --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c @@ -39,7 +39,7 @@ #define HDCP14_KSV_SIZE 5 #define HDCP14_MAX_KSV_FIFO_SIZE 127*HDCP14_KSV_SIZE -static const bool hdcp_cmd_is_read[] = { +static const bool hdcp_cmd_is_read[HDCP_MESSAGE_ID_MAX] = { [HDCP_MESSAGE_ID_READ_BKSV] = true, [HDCP_MESSAGE_ID_READ_RI_R0] = true, [HDCP_MESSAGE_ID_READ_PJ] = true, @@ -75,7 +75,7 @@ static const bool hdcp_cmd_is_read[] = { [HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false }; -static const uint8_t hdcp_i2c_offsets[] = { +static const uint8_t hdcp_i2c_offsets[HDCP_MESSAGE_ID_MAX] = { [HDCP_MESSAGE_ID_READ_BKSV] = 0x0, [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8, [HDCP_MESSAGE_ID_READ_PJ] = 0xA, @@ -106,7 +106,8 @@ static const uint8_t hdcp_i2c_offsets[] = { [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60, [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60, [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80, - [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70 + [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70, + [HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x0, }; struct protection_properties { @@ -184,7 +185,7 @@ static const struct protection_properties hdmi_14_protection = { .process_transaction = hdmi_14_process_transaction }; -static const uint32_t hdcp_dpcd_addrs[] = { +static const uint32_t hdcp_dpcd_addrs[HDCP_MESSAGE_ID_MAX] = { [HDCP_MESSAGE_ID_READ_BKSV] = 0x68000, [HDCP_MESSAGE_ID_READ_RI_R0] = 0x68005, [HDCP_MESSAGE_ID_READ_PJ] = 0xFFFFFFFF, diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h index 1b01a9a58d14427d0625e4c31ecf7c56326d915e..e2b3a2c7a927009c05bdd0e1a7dda1cf9781ae79 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h @@ -170,6 +170,11 @@ struct clock_source_funcs { const struct clock_source *clock_source, unsigned int inst, unsigned int *pixel_clk_khz); + bool (*override_dp_pix_clk)( + struct clock_source *clock_source, + unsigned int inst, + unsigned int pixel_clk, + unsigned int ref_clk); }; struct clock_source { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 8efa1b80546deaa03f0a93c7d610a45d6830f3ca..eb1a19bf0d81ff959af1615fb5b581cae77954f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -97,6 +97,10 @@ struct resource_funcs { const struct panel_cntl_init_data *panel_cntl_init_data); struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); + /* Create a minimal link encoder object with no dc_link object + * associated with it. */ + struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); + bool (*validate_bandwidth)( struct dc *dc, struct dc_state *context, @@ -106,6 +110,8 @@ struct resource_funcs { display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel); + void (*update_soc_for_wm_a)( + struct dc *dc, struct dc_state *context); int (*populate_dml_pipes)( struct dc *dc, struct dc_state *context, @@ -210,6 +216,15 @@ struct resource_pool { unsigned int underlay_pipe_index; unsigned int stream_enc_count; + /* An array for accessing the link encoder objects that have been created. + * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA + */ + struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; + /* Number of DIG link encoder objects created - i.e. number of valid + * entries in link_encoders array. + */ + unsigned int dig_link_enc_count; + #if defined(CONFIG_DRM_AMD_DC_DCN) struct dc_3dlut *mpc_lut[MAX_PIPES]; struct dc_transfer_func *mpc_shaper[MAX_PIPES]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h index b324e13f3f782b7c8883bfaff55f8533f64c00b4..4d7b271b64097ccaf1d184bf0fc2f583a120a1dd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h @@ -56,6 +56,7 @@ struct dp_receiver_id_info; struct i2c_payloads; struct aux_payloads; +enum aux_return_code_type; void dal_ddc_i2c_payloads_add( struct i2c_payloads *payloads, @@ -100,7 +101,7 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc, int dc_link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, - enum aux_channel_operation_result *operation_result); + enum aux_return_code_type *operation_result); bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, struct aux_payload *payload); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h index e77b3a76766d12cdfd331235af217fd129d148a6..2ae630bf2aee48484ac5c1499b3e792225084888 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h @@ -29,6 +29,8 @@ #include "dc_ddc_types.h" #include "include/i2caux_interface.h" +enum aux_return_code_type; + enum i2caux_transaction_operation { I2CAUX_TRANSACTION_READ, I2CAUX_TRANSACTION_WRITE @@ -162,7 +164,7 @@ struct aux_engine_funcs { uint8_t *buffer, uint8_t *reply_result, uint32_t *sw_status); - enum aux_channel_operation_result (*get_channel_status)( + enum aux_return_code_type (*get_channel_status)( struct aux_engine *engine, uint8_t *returned_bytes); bool (*is_engine_available)(struct aux_engine *engine); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index cd1c0dc32bf8a8dd5e695ee2f67aebde062d5f07..8df2765cce78b2f8e067180932e1d09c4c974e04 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -56,6 +56,20 @@ struct dmcu { bool auto_load_dmcu; }; +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +struct crc_region { + uint16_t x_start; + uint16_t y_start; + uint16_t x_end; + uint16_t y_end; +}; + +struct otg_phy_mux { + uint8_t phy_output_num; + uint8_t otg_output_num; +}; +#endif + struct dmcu_funcs { bool (*dmcu_init)(struct dmcu *dmcu); bool (*load_iram)(struct dmcu *dmcu, @@ -84,6 +98,13 @@ struct dmcu_funcs { int *min_frame_rate, int *max_frame_rate); bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + void (*forward_crc_window)(struct dmcu *dmcu, + struct crc_region *crc_win, + struct otg_phy_mux *mux_mapping); + void (*stop_crc_win_update)(struct dmcu *dmcu, + struct otg_phy_mux *mux_mapping); +#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 22f3f643ed1b865ea64af0aadae66a580271bb35..346dcd87dc10651b28bab509b314f21cb89f4c8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -191,6 +191,8 @@ struct hubp_funcs { bool (*hubp_in_blank)(struct hubp *hubp); void (*hubp_soft_reset)(struct hubp *hubp, bool reset); + void (*hubp_set_flip_int)(struct hubp *hubp); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 43e33f47734d5d72da51b3228ce665410b57b02c..31a1713bb49ffc648b7687bc074dae22991e0690 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -36,6 +36,7 @@ #define MAX_AUDIOS 7 #define MAX_PIPES 6 +#define MAX_DIG_LINK_ENCODERS 7 #define MAX_DWB_PIPES 1 struct gamma_curve { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 754832d216fdabbdfa5c65fede5f12e7285964ab..9ff68b67780c208825bc439038e0c920f5ff6cb2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -109,6 +109,12 @@ enum h_timing_div_mode { H_TIMING_DIV_BY4, }; +enum timing_synchronization_type { + NOT_SYNCHRONIZABLE, + TIMING_SYNCHRONIZABLE, + VBLANK_SYNCHRONIZABLE +}; + struct crc_params { /* Regions used to calculate CRC*/ uint16_t windowa_x_start; @@ -292,6 +298,12 @@ struct timing_generator_funcs { uint32_t window_start, uint32_t window_end); void (*set_vtotal_change_limit)(struct timing_generator *optc, uint32_t limit); + void (*align_vblanks)(struct timing_generator *master_optc, + struct timing_generator *slave_optc, + uint32_t master_pixel_clock_100Hz, + uint32_t slave_pixel_clock_100Hz, + uint8_t master_clock_divider, + uint8_t slave_clock_divider); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 0586ab2ffd6ab46d9001f0ed9fa0cdc244676f7e..2fedfcac6705076307eba58d942f5ec6b47ebb90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -111,6 +111,9 @@ struct hw_sequencer_funcs { void (*enable_timing_synchronization)(struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]); + void (*enable_vblanks_synchronization)(struct dc *dc, + int group_index, int group_size, + struct pipe_ctx *grouped_pipes[]); void (*setup_periodic_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx, enum vline_select vline); @@ -231,10 +234,6 @@ struct hw_sequencer_funcs { enum dc_color_depth color_depth, const struct tg_color *solid_color, int width, int height, int offset); - - void (*set_hubp_blank)(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank_enable); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index d89815a4619018e6f4f60f52637d5db9670e8e21..fe1e5833c96a0927aacd20f4e112d8be1a5ecb80 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -48,6 +48,7 @@ struct resource_caps { int num_ddc; int num_vmid; int num_dsc; + unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output). int num_mpc_3dlut; }; @@ -115,6 +116,10 @@ bool resource_are_streams_timing_synchronizable( struct dc_stream_state *stream1, struct dc_stream_state *stream2); +bool resource_are_vblanks_synchronizable( + struct dc_stream_state *stream1, + struct dc_stream_state *stream2); + struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c index 3f1e7a196a23ab301bf7d3442ae1a730fc4fb340..c4b067d0189565f8801a8c3d35be2529fb07e9b0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c @@ -58,6 +58,18 @@ enum dc_irq_source to_dal_irq_source_dcn20( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP1; case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: @@ -172,6 +184,11 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .ack = NULL }; +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + #undef BASE_INNER #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg @@ -245,6 +262,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } + #define dummy_irq_entry() \ {\ .funcs = &dummy_irq_info_funcs\ @@ -353,6 +378,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = { vblank_int_entry(3), vblank_int_entry(4), vblank_int_entry(5), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline0_int_entry(4), + vline0_int_entry(5), }; static const struct irq_service_funcs irq_service_funcs_dcn20 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c index 0e0f494fbb5e138b1f739cd664252d2899c2fc12..6ee9dd833b85c2a5a58593bd55e7043f00f31aa7 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c @@ -58,6 +58,20 @@ enum dc_irq_source to_dal_irq_source_dcn21( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX0; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP1; case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: @@ -173,6 +187,12 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .ack = NULL }; + +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + #undef BASE_INNER #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg @@ -254,6 +274,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } + #define dummy_irq_entry() \ {\ .funcs = &dummy_irq_info_funcs\ @@ -366,6 +394,12 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = { vblank_int_entry(3), vblank_int_entry(4), vblank_int_entry(5), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline0_int_entry(4), + vline0_int_entry(5), }; static const struct irq_service_funcs irq_service_funcs_dcn21 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c index a35b76772b9dfb5144b71655dc761687d7e945cd..4ec6f6ad8c4837765b0f9d84fb0bc72ef26214f0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c @@ -65,6 +65,20 @@ enum dc_irq_source to_dal_irq_source_dcn30( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX0; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP1; case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: @@ -179,6 +193,16 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .ack = NULL }; +static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + #undef BASE_INNER #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg @@ -252,6 +276,14 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } + #define dummy_irq_entry() \ {\ .funcs = &dummy_irq_info_funcs\ @@ -360,6 +392,12 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = { vblank_int_entry(3), vblank_int_entry(4), vblank_int_entry(5), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline0_int_entry(4), + vline0_int_entry(5), }; static const struct irq_service_funcs irq_service_funcs_dcn30 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c index 927fdc43fb9f0670809af2b06af4cfed61bdc228..2313a5664f44ba93230a35e28a8801aa784e7f8d 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c @@ -50,6 +50,18 @@ static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_servi return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP1; case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: @@ -154,6 +166,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .ack = NULL }; +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + #undef BASE_INNER #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg @@ -222,6 +239,14 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } + #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs } #define i2c_int_entry(reg_num) \ @@ -318,6 +343,11 @@ static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBE vblank_int_entry(2), vblank_int_entry(3), vblank_int_entry(4), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline0_int_entry(4), }; static const struct irq_service_funcs irq_service_funcs_dcn302 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h index 87812d81fed3c9501bc220547172795acebfbfd1..ae8f47ec0f8c338b5b41787dd95dfc4a525c5e3d 100644 --- a/drivers/gpu/drm/amd/display/dc/irq_types.h +++ b/drivers/gpu/drm/amd/display/dc/irq_types.h @@ -150,7 +150,8 @@ enum dc_irq_source { DC_IRQ_SOURCE_DC4_VLINE1, DC_IRQ_SOURCE_DC5_VLINE1, DC_IRQ_SOURCE_DC6_VLINE1, - + DC_IRQ_DMCUB_OUTBOX1, + DC_IRQ_SOURCE_DMCUB_OUTBOX0, DAL_IRQ_SOURCES_NUMBER }; diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 863cd9cc93ff3916c024d3d855c92aba3ebc0e00..b4e14960b164dd896c6ceca34e239efba0fb2e22 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -74,6 +74,8 @@ extern "C" { struct dmub_srv; struct dmub_srv_common_regs; +struct dmcub_trace_buf_entry; + /* enum dmub_status - return code for dmcub functions */ enum dmub_status { DMUB_STATUS_OK = 0, @@ -107,6 +109,15 @@ enum dmub_window_id { DMUB_WINDOW_TOTAL, }; +/* enum dmub_notification_type - dmub outbox notification identifier */ +enum dmub_notification_type { + DMUB_NOTIFICATION_NO_DATA = 0, + DMUB_NOTIFICATION_AUX_REPLY, + DMUB_NOTIFICATION_HPD, + DMUB_NOTIFICATION_HPD_IRQ, + DMUB_NOTIFICATION_MAX +}; + /** * struct dmub_region - dmub hw memory region * @base: base address for region, must be 256 byte aligned @@ -256,6 +267,20 @@ struct dmub_srv_hw_funcs { void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); + void (*setup_out_mailbox)(struct dmub_srv *dmub, + const struct dmub_region *outbox1); + + uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); + + void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); + + void (*setup_outbox0)(struct dmub_srv *dmub, + const struct dmub_region *outbox0); + + uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); + + void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); + uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); @@ -279,6 +304,7 @@ struct dmub_srv_hw_funcs { union dmub_gpint_data_register reg); uint32_t (*get_gpint_response)(struct dmub_srv *dmub); + }; /** @@ -338,6 +364,13 @@ struct dmub_srv { struct dmub_srv_base_funcs funcs; struct dmub_srv_hw_funcs hw_funcs; struct dmub_rb inbox1_rb; + /** + * outbox1_rb is accessed without locks (dal & dc) + * and to be used only in dmub_srv_stat_get_notification() + */ + struct dmub_rb outbox1_rb; + + struct dmub_rb outbox0_rb; bool sw_init; bool hw_init; @@ -350,6 +383,26 @@ struct dmub_srv { struct dmub_feature_caps feature_caps; }; +/** + * struct dmub_notification - dmub notification data + * @type: dmub notification type + * @link_index: link index to identify aux connection + * @result: USB4 status returned from dmub + * @pending_notification: Indicates there are other pending notifications + * @aux_reply: aux reply + * @hpd_status: hpd status + */ +struct dmub_notification { + enum dmub_notification_type type; + uint8_t link_index; + uint8_t result; + bool pending_notification; + union { + struct aux_reply_data aux_reply; + enum dp_hpd_status hpd_status; + }; +}; + /** * DMUB firmware version helper macro - useful for checking if the version * of a firmware to know if feature or functionality is supported or present. @@ -614,6 +667,8 @@ enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); +bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); + #if defined(__cplusplus) } #endif diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv_stat.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv_stat.h new file mode 100644 index 0000000000000000000000000000000000000000..6c78aa406e90c68bed5a30e2ce2e811f2cee3080 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv_stat.h @@ -0,0 +1,41 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_SRV_STAT_H_ +#define _DMUB_SRV_STAT_H_ + +/** + * DOC: DMUB_SRV STAT Interface + * + * These interfaces are called without acquiring DAL and DC locks. + * Hence, there is limitations on whese interfaces can access. Only + * variables exclusively defined for these interfaces can be modified. + */ +#include "dmub_srv.h" + +enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, + struct dmub_notification *notify); + +#endif /* _DMUB_SRV_STAT_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 072b4e7e624b006aa0eced5f99fd3824b73e8f9a..f07b348f7c29d50c2be1baef966a44a3af935436 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x6444c02e7 +#define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 51 +#define DMUB_FW_VERSION_REVISION 56 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 @@ -68,25 +68,75 @@ #define __forceinline inline +/** + * Flag from driver to indicate that ABM should be disabled gradually + * by slowly reversing all backlight programming and pixel compensation. + */ #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 + +/** + * Flag from driver to indicate that ABM should be disabled immediately + * and undo all backlight programming and pixel compensation. + */ #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 + +/** + * Flag from driver to indicate that ABM should be disabled immediately + * and keep the current backlight programming and pixel compensation. + */ #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 + +/** + * Flag from driver to set the current ABM pipe index or ABM operating level. + */ #define SET_ABM_PIPE_NORMAL 1 +/** + * Number of ambient light levels in ABM algorithm. + */ +#define NUM_AMBI_LEVEL 5 + +/** + * Number of operating/aggression levels in ABM algorithm. + */ +#define NUM_AGGR_LEVEL 4 + +/** + * Number of segments in the gamma curve. + */ +#define NUM_POWER_FN_SEGS 8 + +/** + * Number of segments in the backlight curve. + */ +#define NUM_BL_CURVE_SEGS 16 + /* Maximum number of streams on any ASIC. */ #define DMUB_MAX_STREAMS 6 /* Maximum number of planes on any ASIC. */ #define DMUB_MAX_PLANES 6 +/* Trace buffer offset for entry */ +#define TRACE_BUFFER_ENTRY_OFFSET 16 + +/** + * Physical framebuffer address location, 64-bit. + */ #ifndef PHYSICAL_ADDRESS_LOC #define PHYSICAL_ADDRESS_LOC union large_integer #endif +/** + * OS/FW agnostic memcpy + */ #ifndef dmub_memcpy #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) #endif +/** + * OS/FW agnostic memset + */ #ifndef dmub_memset #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) #endif @@ -95,31 +145,69 @@ extern "C" { #endif +/** + * OS/FW agnostic udelay + */ #ifndef dmub_udelay #define dmub_udelay(microseconds) udelay(microseconds) #endif +/** + * union dmub_addr - DMUB physical/virtual 64-bit address. + */ union dmub_addr { struct { - uint32_t low_part; - uint32_t high_part; - } u; - uint64_t quad_part; + uint32_t low_part; /**< Lower 32 bits */ + uint32_t high_part; /**< Upper 32 bits */ + } u; /*<< Low/high bit access */ + uint64_t quad_part; /*<< 64 bit address */ }; +/** + * Flags that can be set by driver to change some PSR behaviour. + */ union dmub_psr_debug_flags { + /** + * Debug flags. + */ struct { + /** + * Enable visual confirm in FW. + */ uint32_t visual_confirm : 1; + /** + * Use HW Lock Mgr object to do HW locking in FW. + */ uint32_t use_hw_lock_mgr : 1; + + /** + * Unused. + * TODO: Remove. + */ uint32_t log_line_nums : 1; } bitfields; + /** + * Union for debug flags. + */ uint32_t u32All; }; +/** + * DMUB feature capabilities. + * After DMUB init, driver will query FW capabilities prior to enabling certain features. + */ struct dmub_feature_caps { + /** + * Max PSR version supported by FW. + */ uint8_t psr; +#ifndef TRIM_FAMS + uint8_t fw_assisted_mclk_switch; + uint8_t reserved[6]; +#else uint8_t reserved[7]; +#endif }; #if defined(__cplusplus) @@ -153,22 +241,42 @@ struct dmub_feature_caps { * @dal_fw: 1 if the firmware is DAL */ struct dmub_fw_meta_info { - uint32_t magic_value; - uint32_t fw_region_size; - uint32_t trace_buffer_size; - uint32_t fw_version; - uint8_t dal_fw; - uint8_t reserved[3]; + uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ + uint32_t fw_region_size; /**< size of the firmware state region */ + uint32_t trace_buffer_size; /**< size of the tracebuffer region */ + uint32_t fw_version; /**< the firmware version information */ + uint8_t dal_fw; /**< 1 if the firmware is DAL */ + uint8_t reserved[3]; /**< padding bits */ }; -/* Ensure that the structure remains 64 bytes. */ +/** + * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes + */ union dmub_fw_meta { - struct dmub_fw_meta_info info; - uint8_t reserved[64]; + struct dmub_fw_meta_info info; /**< metadata info */ + uint8_t reserved[64]; /**< padding bits */ }; #pragma pack(pop) +//============================================================================== +//< DMUB Trace Buffer>================================================================ +//============================================================================== +/** + * dmub_trace_code_t - firmware trace code, 32-bits + */ +typedef uint32_t dmub_trace_code_t; + +/** + * struct dmcub_trace_buf_entry - Firmware trace entry + */ +struct dmcub_trace_buf_entry { + dmub_trace_code_t trace_code; /**< trace code for the event */ + uint32_t tick_count; /**< the tick count at time of trace */ + uint32_t param0; /**< trace defined parameter 0 */ + uint32_t param1; /**< trace defined parameter 1 */ +}; + //============================================================================== //< DMUB_STATUS>================================================================ //============================================================================== @@ -181,42 +289,49 @@ union dmub_fw_meta { * SCRATCH15: FW Boot Options register */ -/* Register bit definition for SCRATCH0 */ +/** + * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. + */ union dmub_fw_boot_status { struct { - uint32_t dal_fw : 1; - uint32_t mailbox_rdy : 1; - uint32_t optimized_init_done : 1; - uint32_t restore_required : 1; - } bits; - uint32_t all; + uint32_t dal_fw : 1; /**< 1 if DAL FW */ + uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ + uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ + uint32_t restore_required : 1; /**< 1 if driver should call restore */ + } bits; /**< status bits */ + uint32_t all; /**< 32-bit access to status bits */ }; +/** + * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. + */ enum dmub_fw_boot_status_bit { - DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), - DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), - DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), - DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), + DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ + DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ + DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ + DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ }; -/* Register bit definition for SCRATCH15 */ +/** + * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 + */ union dmub_fw_boot_options { struct { - uint32_t pemu_env : 1; - uint32_t fpga_env : 1; - uint32_t optimized_init : 1; - uint32_t skip_phy_access : 1; - uint32_t disable_clk_gate: 1; - uint32_t skip_phy_init_panel_sequence: 1; - uint32_t reserved : 26; - } bits; - uint32_t all; + uint32_t pemu_env : 1; /**< 1 if PEMU */ + uint32_t fpga_env : 1; /**< 1 if FPGA */ + uint32_t optimized_init : 1; /**< 1 if optimized init */ + uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ + uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ + uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ + uint32_t reserved : 26; /**< reserved */ + } bits; /**< boot bits */ + uint32_t all; /**< 32-bit access to bits */ }; enum dmub_fw_boot_options_bit { - DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), - DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), - DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), + DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ + DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ + DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ }; //============================================================================== @@ -226,14 +341,27 @@ enum dmub_fw_boot_options_bit { //============================================================================== /* + * enum dmub_cmd_vbios_type - VBIOS commands. + * * Command IDs should be treated as stable ABI. * Do not reuse or modify IDs. */ - enum dmub_cmd_vbios_type { + /** + * Configures the DIG encoder. + */ DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, + /** + * Controls the PHY. + */ DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, + /** + * Sets the pixel clock/symbol clock. + */ DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, + /** + * Enables or disables power gating. + */ DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, }; @@ -262,35 +390,60 @@ enum dmub_cmd_vbios_type { * Command responses. */ +/** + * Return response for DMUB_GPINT__STOP_FW command. + */ #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD /** - * The register format for sending a command via the GPINT. + * union dmub_gpint_data_register - Format for sending a command via the GPINT. */ union dmub_gpint_data_register { struct { - uint32_t param : 16; - uint32_t command_code : 12; - uint32_t status : 4; - } bits; - uint32_t all; + uint32_t param : 16; /**< 16-bit parameter */ + uint32_t command_code : 12; /**< GPINT command */ + uint32_t status : 4; /**< Command status bit */ + } bits; /**< GPINT bit access */ + uint32_t all; /**< GPINT 32-bit access */ }; /* + * enum dmub_gpint_command - GPINT command to DMCUB FW + * * Command IDs should be treated as stable ABI. * Do not reuse or modify IDs. */ - enum dmub_gpint_command { + /** + * Invalid command, ignored. + */ DMUB_GPINT__INVALID_COMMAND = 0, + /** + * DESC: Queries the firmware version. + * RETURN: Firmware version. + */ DMUB_GPINT__GET_FW_VERSION = 1, + /** + * DESC: Halts the firmware. + * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted + */ DMUB_GPINT__STOP_FW = 2, + /** + * DESC: Get PSR state from FW. + * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. + */ DMUB_GPINT__GET_PSR_STATE = 7, /** * DESC: Notifies DMCUB of the currently active streams. * ARGS: Stream mask, 1 bit per active stream index. */ DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, + /** + * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. + * ARGS: We can measure residency from various points. The argument will specify the residency mode. + * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. + * RETURN: PSR residency in milli-percent. + */ DMUB_GPINT__PSR_RESIDENCY = 9, }; @@ -300,52 +453,129 @@ enum dmub_gpint_command { //< DMUB_CMD>=================================================================== //============================================================================== +/** + * Size in bytes of each DMUB command. + */ #define DMUB_RB_CMD_SIZE 64 + +/** + * Maximum number of items in the DMUB ringbuffer. + */ #define DMUB_RB_MAX_ENTRY 128 + +/** + * Ringbuffer size in bytes. + */ #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) + +/** + * REG_SET mask for reg offload. + */ #define REG_SET_MASK 0xFFFF /* + * enum dmub_cmd_type - DMUB inbox command. + * * Command IDs should be treated as stable ABI. * Do not reuse or modify IDs. */ - enum dmub_cmd_type { + /** + * Invalid command. + */ DMUB_CMD__NULL = 0, + /** + * Read modify write register sequence offload. + */ DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, + /** + * Field update register sequence offload. + */ DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, + /** + * Burst write sequence offload. + */ DMUB_CMD__REG_SEQ_BURST_WRITE = 3, + /** + * Reg wait sequence offload. + */ DMUB_CMD__REG_REG_WAIT = 4, + /** + * Workaround to avoid HUBP underflow during NV12 playback. + */ DMUB_CMD__PLAT_54186_WA = 5, + /** + * Command type used to query FW feature caps. + */ DMUB_CMD__QUERY_FEATURE_CAPS = 6, + /** + * Command type used for all PSR commands. + */ DMUB_CMD__PSR = 64, + /** + * Command type used for all MALL commands. + */ DMUB_CMD__MALL = 65, + /** + * Command type used for all ABM commands. + */ DMUB_CMD__ABM = 66, + /** + * Command type used for HW locking in FW. + */ DMUB_CMD__HW_LOCK = 69, + /** + * Command type used to access DP AUX. + */ DMUB_CMD__DP_AUX_ACCESS = 70, + /** + * Command type used for OUTBOX1 notification enable + */ DMUB_CMD__OUTBOX1_ENABLE = 71, +#ifndef TRIM_FAMS + DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, +#endif + + /** + * Command type used for all VBIOS interface commands. + */ DMUB_CMD__VBIOS = 128, }; +/** + * enum dmub_out_cmd_type - DMUB outbox commands. + */ enum dmub_out_cmd_type { + /** + * Invalid outbox command, ignored. + */ DMUB_OUT_CMD__NULL = 0, + /** + * Command type used for DP AUX Reply data notification + */ DMUB_OUT_CMD__DP_AUX_REPLY = 1, + /** + * Command type used for DP HPD event notification + */ DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, }; #pragma pack(push, 1) +/** + * struct dmub_cmd_header - Common command header fields. + */ struct dmub_cmd_header { - unsigned int type : 8; - unsigned int sub_type : 8; - unsigned int ret_status : 1; - unsigned int reserved0 : 7; - unsigned int payload_bytes : 6; /* up to 60 bytes */ - unsigned int reserved1 : 2; + unsigned int type : 8; /**< command type */ + unsigned int sub_type : 8; /**< command sub type */ + unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ + unsigned int reserved0 : 7; /**< reserved bits */ + unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ + unsigned int reserved1 : 2; /**< reserved bits */ }; /* - * Read modify write + * struct dmub_cmd_read_modify_write_sequence - Read modify write * * 60 payload bytes can hold up to 5 sets of read modify writes, * each take 3 dwords. @@ -356,14 +586,24 @@ struct dmub_cmd_header { * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write */ struct dmub_cmd_read_modify_write_sequence { - uint32_t addr; - uint32_t modify_mask; - uint32_t modify_value; + uint32_t addr; /**< register address */ + uint32_t modify_mask; /**< modify mask */ + uint32_t modify_value; /**< modify value */ }; -#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 +/** + * Maximum number of ops in read modify write sequence. + */ +#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 + +/** + * struct dmub_cmd_read_modify_write_sequence - Read modify write command. + */ struct dmub_rb_cmd_read_modify_write { - struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE + struct dmub_cmd_header header; /**< command header */ + /** + * Read modify write sequence. + */ struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; }; @@ -381,19 +621,35 @@ struct dmub_rb_cmd_read_modify_write { */ struct dmub_cmd_reg_field_update_sequence { - uint32_t modify_mask; // 0xffff'ffff to skip initial read - uint32_t modify_value; + uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ + uint32_t modify_value; /**< value to update with */ }; -#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 +/** + * Maximum number of ops in field update sequence. + */ +#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 + +/** + * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. + */ struct dmub_rb_cmd_reg_field_update_sequence { - struct dmub_cmd_header header; - uint32_t addr; + struct dmub_cmd_header header; /**< command header */ + uint32_t addr; /**< register address */ + /** + * Field update sequence. + */ struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; }; + +/** + * Maximum number of burst write values. + */ +#define DMUB_BURST_WRITE_VALUES__MAX 14 + /* - * Burst write + * struct dmub_rb_cmd_burst_write - Burst write * * support use case such as writing out LUTs. * @@ -401,96 +657,141 @@ struct dmub_rb_cmd_reg_field_update_sequence { * * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) */ -#define DMUB_BURST_WRITE_VALUES__MAX 14 struct dmub_rb_cmd_burst_write { - struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE - uint32_t addr; + struct dmub_cmd_header header; /**< command header */ + uint32_t addr; /**< register start address */ + /** + * Burst write register values. + */ uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; }; - +/** + * struct dmub_rb_cmd_common - Common command header + */ struct dmub_rb_cmd_common { - struct dmub_cmd_header header; + struct dmub_cmd_header header; /**< command header */ + /** + * Padding to RB_CMD_SIZE + */ uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; }; +/** + * struct dmub_cmd_reg_wait_data - Register wait data + */ struct dmub_cmd_reg_wait_data { - uint32_t addr; - uint32_t mask; - uint32_t condition_field_value; - uint32_t time_out_us; + uint32_t addr; /**< Register address */ + uint32_t mask; /**< Mask for register bits */ + uint32_t condition_field_value; /**< Value to wait for */ + uint32_t time_out_us; /**< Time out for reg wait in microseconds */ }; +/** + * struct dmub_rb_cmd_reg_wait - Register wait command + */ struct dmub_rb_cmd_reg_wait { - struct dmub_cmd_header header; - struct dmub_cmd_reg_wait_data reg_wait; + struct dmub_cmd_header header; /**< Command header */ + struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ }; +/** + * struct dmub_cmd_PLAT_54186_wa - Underflow workaround + * + * Reprograms surface parameters to avoid underflow. + */ struct dmub_cmd_PLAT_54186_wa { - uint32_t DCSURF_SURFACE_CONTROL; - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; + uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ struct { - uint8_t hubp_inst : 4; - uint8_t tmz_surface : 1; - uint8_t immediate :1; - uint8_t vmid : 4; - uint8_t grph_stereo : 1; - uint32_t reserved : 21; - } flip_params; - uint32_t reserved[9]; + uint8_t hubp_inst : 4; /**< HUBP instance */ + uint8_t tmz_surface : 1; /**< TMZ enable or disable */ + uint8_t immediate :1; /**< Immediate flip */ + uint8_t vmid : 4; /**< VMID */ + uint8_t grph_stereo : 1; /**< 1 if stereo */ + uint32_t reserved : 21; /**< Reserved */ + } flip_params; /**< Pageflip parameters */ + uint32_t reserved[9]; /**< Reserved bits */ }; +/** + * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command + */ struct dmub_rb_cmd_PLAT_54186_wa { - struct dmub_cmd_header header; - struct dmub_cmd_PLAT_54186_wa flip; + struct dmub_cmd_header header; /**< Command header */ + struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ }; +/** + * struct dmub_rb_cmd_mall - MALL command data. + */ struct dmub_rb_cmd_mall { - struct dmub_cmd_header header; - union dmub_addr cursor_copy_src; - union dmub_addr cursor_copy_dst; - uint32_t tmr_delay; - uint32_t tmr_scale; - uint16_t cursor_width; - uint16_t cursor_pitch; - uint16_t cursor_height; - uint8_t cursor_bpp; - uint8_t debug_bits; + struct dmub_cmd_header header; /**< Common command header */ + union dmub_addr cursor_copy_src; /**< Cursor copy address */ + union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ + uint32_t tmr_delay; /**< Timer delay */ + uint32_t tmr_scale; /**< Timer scale */ + uint16_t cursor_width; /**< Cursor width in pixels */ + uint16_t cursor_pitch; /**< Cursor pitch in pixels */ + uint16_t cursor_height; /**< Cursor height in pixels */ + uint8_t cursor_bpp; /**< Cursor bits per pixel */ + uint8_t debug_bits; /**< Debug bits */ - uint8_t reserved1; - uint8_t reserved2; + uint8_t reserved1; /**< Reserved bits */ + uint8_t reserved2; /**< Reserved bits */ }; +/** + * struct dmub_cmd_digx_encoder_control_data - Encoder control data. + */ struct dmub_cmd_digx_encoder_control_data { - union dig_encoder_control_parameters_v1_5 dig; + union dig_encoder_control_parameters_v1_5 dig; /**< payload */ }; +/** + * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. + */ struct dmub_rb_cmd_digx_encoder_control { - struct dmub_cmd_header header; - struct dmub_cmd_digx_encoder_control_data encoder_control; + struct dmub_cmd_header header; /**< header */ + struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ }; +/** + * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. + */ struct dmub_cmd_set_pixel_clock_data { - struct set_pixel_clock_parameter_v1_7 clk; + struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ }; +/** + * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. + */ struct dmub_rb_cmd_set_pixel_clock { - struct dmub_cmd_header header; - struct dmub_cmd_set_pixel_clock_data pixel_clock; + struct dmub_cmd_header header; /**< header */ + struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ }; +/** + * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. + */ struct dmub_cmd_enable_disp_power_gating_data { - struct enable_disp_power_gating_parameters_v2_1 pwr; + struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ }; +/** + * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. + */ struct dmub_rb_cmd_enable_disp_power_gating { - struct dmub_cmd_header header; - struct dmub_cmd_enable_disp_power_gating_data power_gating; + struct dmub_cmd_header header; /**< header */ + struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ }; +/** + * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. + */ struct dmub_dig_transmitter_control_data_v1_7 { uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ @@ -511,118 +812,266 @@ struct dmub_dig_transmitter_control_data_v1_7 { uint32_t reserved3[11]; /**< For future use */ }; +/** + * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. + */ union dmub_cmd_dig1_transmitter_control_data { - struct dig_transmitter_control_parameters_v1_6 dig; - struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; + struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ + struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ }; +/** + * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. + */ struct dmub_rb_cmd_dig1_transmitter_control { - struct dmub_cmd_header header; - union dmub_cmd_dig1_transmitter_control_data transmitter_control; + struct dmub_cmd_header header; /**< header */ + union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ }; +/** + * struct dmub_rb_cmd_dpphy_init - DPPHY init. + */ struct dmub_rb_cmd_dpphy_init { - struct dmub_cmd_header header; - uint8_t reserved[60]; + struct dmub_cmd_header header; /**< header */ + uint8_t reserved[60]; /**< reserved bits */ }; +/** + * enum dp_aux_request_action - DP AUX request command listing. + * + * 4 AUX request command bits are shifted to high nibble. + */ enum dp_aux_request_action { + /** I2C-over-AUX write request */ DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, + /** I2C-over-AUX read request */ DP_AUX_REQ_ACTION_I2C_READ = 0x10, + /** I2C-over-AUX write status request */ DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, + /** I2C-over-AUX write request with MOT=1 */ DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, + /** I2C-over-AUX read request with MOT=1 */ DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, + /** I2C-over-AUX write status request with MOT=1 */ DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, + /** Native AUX write request */ DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, + /** Native AUX read request */ DP_AUX_REQ_ACTION_DPCD_READ = 0x90 }; +/** + * enum aux_return_code_type - DP AUX process return code listing. + */ enum aux_return_code_type { + /** AUX process succeeded */ AUX_RET_SUCCESS = 0, + /** AUX process failed with unknown reason */ AUX_RET_ERROR_UNKNOWN, + /** AUX process completed with invalid reply */ AUX_RET_ERROR_INVALID_REPLY, + /** AUX process timed out */ AUX_RET_ERROR_TIMEOUT, + /** HPD was low during AUX process */ AUX_RET_ERROR_HPD_DISCON, + /** Failed to acquire AUX engine */ AUX_RET_ERROR_ENGINE_ACQUIRE, + /** AUX request not supported */ AUX_RET_ERROR_INVALID_OPERATION, + /** AUX process not available */ AUX_RET_ERROR_PROTOCOL_ERROR, }; +/** + * enum aux_channel_type - DP AUX channel type listing. + */ enum aux_channel_type { + /** AUX thru Legacy DP AUX */ AUX_CHANNEL_LEGACY_DDC, + /** AUX thru DPIA DP tunneling */ AUX_CHANNEL_DPIA }; -/* DP AUX command */ +/** + * struct aux_transaction_parameters - DP AUX request transaction data + */ struct aux_transaction_parameters { - uint8_t is_i2c_over_aux; - uint8_t action; - uint8_t length; - uint8_t pad; - uint32_t address; - uint8_t data[16]; + uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ + uint8_t action; /**< enum dp_aux_request_action */ + uint8_t length; /**< DP AUX request data length */ + uint8_t reserved; /**< For future use */ + uint32_t address; /**< DP AUX address */ + uint8_t data[16]; /**< DP AUX write data */ }; +/** + * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. + */ struct dmub_cmd_dp_aux_control_data { - uint32_t handle; - uint8_t instance; - uint8_t sw_crc_enabled; - uint16_t timeout; - enum aux_channel_type type; - struct aux_transaction_parameters dpaux; + uint8_t instance; /**< AUX instance or DPIA instance */ + uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ + uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ + uint8_t reserved0; /**< For future use */ + uint16_t timeout; /**< timeout time in us */ + uint16_t reserved1; /**< For future use */ + enum aux_channel_type type; /**< enum aux_channel_type */ + struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ }; +/** + * Definition of a DMUB_CMD__DP_AUX_ACCESS command. + */ struct dmub_rb_cmd_dp_aux_access { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. + */ struct dmub_cmd_dp_aux_control_data aux_control; }; +/** + * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. + */ struct dmub_rb_cmd_outbox1_enable { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * enable: 0x0 -> disable outbox1 notification (default value) + * 0x1 -> enable outbox1 notification + */ uint32_t enable; }; /* DP AUX Reply command - OutBox Cmd */ +/** + * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. + */ struct aux_reply_data { + /** + * Aux cmd + */ uint8_t command; + /** + * Aux reply data length (max: 16 bytes) + */ uint8_t length; + /** + * Alignment only + */ uint8_t pad[2]; + /** + * Aux reply data + */ uint8_t data[16]; }; -struct aux_reply_control_data { +/** + * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. + */ +struct aux_reply_control_data { + /** + * Reserved for future use + */ uint32_t handle; + /** + * Aux Instance + */ uint8_t instance; + /** + * Aux transaction result: definition in enum aux_return_code_type + */ uint8_t result; + /** + * Alignment only + */ uint16_t pad; }; +/** + * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. + */ struct dmub_rb_cmd_dp_aux_reply { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. + */ struct aux_reply_control_data control; + /** + * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. + */ struct aux_reply_data reply_data; }; /* DP HPD Notify command - OutBox Cmd */ +/** + * DP HPD Type + */ enum dp_hpd_type { + /** + * Normal DP HPD + */ DP_HPD = 0, + /** + * DP HPD short pulse + */ DP_IRQ }; +/** + * DP HPD Status + */ enum dp_hpd_status { + /** + * DP_HPD status low + */ DP_HPD_UNPLUG = 0, + /** + * DP_HPD status high + */ DP_HPD_PLUG }; +/** + * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. + */ struct dp_hpd_data { + /** + * DP HPD instance + */ uint8_t instance; + /** + * HPD type + */ uint8_t hpd_type; + /** + * HPD status: only for type: DP_HPD to indicate status + */ uint8_t hpd_status; + /** + * Alignment only + */ uint8_t pad; }; +/** + * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. + */ struct dmub_rb_cmd_dp_hpd_notify { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. + */ struct dp_hpd_data hpd_data; }; @@ -631,270 +1080,901 @@ struct dmub_rb_cmd_dp_hpd_notify { * Do not reuse or modify IDs. */ +/** + * PSR command sub-types. + */ enum dmub_cmd_psr_type { + /** + * Set PSR version support. + */ DMUB_CMD__PSR_SET_VERSION = 0, + /** + * Copy driver-calculated parameters to PSR state. + */ DMUB_CMD__PSR_COPY_SETTINGS = 1, + /** + * Enable PSR. + */ DMUB_CMD__PSR_ENABLE = 2, + + /** + * Disable PSR. + */ DMUB_CMD__PSR_DISABLE = 3, + + /** + * Set PSR level. + * PSR level is a 16-bit value dicated by driver that + * will enable/disable different functionality. + */ DMUB_CMD__PSR_SET_LEVEL = 4, + + /** + * Forces PSR enabled until an explicit PSR disable call. + */ DMUB_CMD__PSR_FORCE_STATIC = 5, }; +#ifndef TRIM_FAMS +enum dmub_cmd_fams_type { + DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, + DMUB_CMD__FAMS_DRR_UPDATE = 1, +}; +#endif + +/** + * PSR versions. + */ enum psr_version { + /** + * PSR version 1. + */ PSR_VERSION_1 = 0, + /** + * PSR not supported. + */ PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, }; +/** + * enum dmub_cmd_mall_type - MALL commands + */ enum dmub_cmd_mall_type { + /** + * Allows display refresh from MALL. + */ DMUB_CMD__MALL_ACTION_ALLOW = 0, + /** + * Disallows display refresh from MALL. + */ DMUB_CMD__MALL_ACTION_DISALLOW = 1, + /** + * Cursor copy for MALL. + */ DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, + /** + * Controls DF requests. + */ DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, }; + +/** + * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. + */ struct dmub_cmd_psr_copy_settings_data { + /** + * Flags that can be set by driver to change some PSR behaviour. + */ union dmub_psr_debug_flags debug; + /** + * 16-bit value dicated by driver that will enable/disable different functionality. + */ uint16_t psr_level; + /** + * DPP HW instance. + */ uint8_t dpp_inst; - /* opp_inst and mpcc_inst will not be used in dmub fw, + /** + * MPCC HW instance. + * Not used in dmub fw, * dmub fw will get active opp by reading odm registers. */ uint8_t mpcc_inst; + /** + * OPP HW instance. + * Not used in dmub fw, + * dmub fw will get active opp by reading odm registers. + */ uint8_t opp_inst; - + /** + * OTG HW instance. + */ uint8_t otg_inst; + /** + * DIG FE HW instance. + */ uint8_t digfe_inst; + /** + * DIG BE HW instance. + */ uint8_t digbe_inst; + /** + * DP PHY HW instance. + */ uint8_t dpphy_inst; + /** + * AUX HW instance. + */ uint8_t aux_inst; + /** + * Determines if SMU optimzations are enabled/disabled. + */ uint8_t smu_optimizations_en; + /** + * Unused. + * TODO: Remove. + */ uint8_t frame_delay; + /** + * If RFB setup time is greater than the total VBLANK time, + * it is not possible for the sink to capture the video frame + * in the same frame the SDP is sent. In this case, + * the frame capture indication bit should be set and an extra + * static frame should be transmitted to the sink. + */ uint8_t frame_cap_ind; + /** + * Explicit padding to 4 byte boundary. + */ uint8_t pad[2]; + /** + * Multi-display optimizations are implemented on certain ASICs. + */ uint8_t multi_disp_optimizations_en; + /** + * The last possible line SDP may be transmitted without violating + * the RFB setup time or entering the active video frame. + */ uint16_t init_sdp_deadline; + /** + * Explicit padding to 4 byte boundary. + */ uint16_t pad2; + /** + * Length of each horizontal line in us. + */ uint32_t line_time_in_us; }; +/** + * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. + */ struct dmub_rb_cmd_psr_copy_settings { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. + */ struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. + */ struct dmub_cmd_psr_set_level_data { + /** + * 16-bit value dicated by driver that will enable/disable different functionality. + */ uint16_t psr_level; + /** + * Explicit padding to 4 byte boundary. + */ uint8_t pad[2]; }; +/** + * Definition of a DMUB_CMD__PSR_SET_LEVEL command. + */ struct dmub_rb_cmd_psr_set_level { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Definition of a DMUB_CMD__PSR_SET_LEVEL command. + */ struct dmub_cmd_psr_set_level_data psr_set_level_data; }; +/** + * Definition of a DMUB_CMD__PSR_ENABLE command. + * PSR enable/disable is controlled using the sub_type. + */ struct dmub_rb_cmd_psr_enable { + /** + * Command header. + */ struct dmub_cmd_header header; }; +/** + * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. + */ struct dmub_cmd_psr_set_version_data { - enum psr_version version; // PSR version 1 or 2 + /** + * PSR version that FW should implement. + */ + enum psr_version version; }; +/** + * Definition of a DMUB_CMD__PSR_SET_VERSION command. + */ struct dmub_rb_cmd_psr_set_version { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. + */ struct dmub_cmd_psr_set_version_data psr_set_version_data; }; +/** + * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. + */ struct dmub_rb_cmd_psr_force_static { + /** + * Command header. + */ struct dmub_cmd_header header; }; +/** + * Set of HW components that can be locked. + */ union dmub_hw_lock_flags { + /** + * Set of HW components that can be locked. + */ struct { + /** + * Lock/unlock OTG master update lock. + */ uint8_t lock_pipe : 1; + /** + * Lock/unlock cursor. + */ uint8_t lock_cursor : 1; + /** + * Lock/unlock global update lock. + */ uint8_t lock_dig : 1; + /** + * Triple buffer lock requires additional hw programming to usual OTG master lock. + */ uint8_t triple_buffer_lock : 1; } bits; + /** + * Union for HW Lock flags. + */ uint8_t u8All; }; +/** + * Instances of HW to be locked. + */ struct dmub_hw_lock_inst_flags { + /** + * OTG HW instance for OTG master update lock. + */ uint8_t otg_inst; + /** + * OPP instance for cursor lock. + */ uint8_t opp_inst; + /** + * OTG HW instance for global update lock. + * TODO: Remove, and re-use otg_inst. + */ uint8_t dig_inst; + /** + * Explicit pad to 4 byte boundary. + */ uint8_t pad; }; +/** + * Clients that can acquire the HW Lock Manager. + */ enum hw_lock_client { + /** + * Driver is the client of HW Lock Manager. + */ HW_LOCK_CLIENT_DRIVER = 0, + /** + * FW is the client of HW Lock Manager. + */ HW_LOCK_CLIENT_FW, + /** + * Invalid client. + */ HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, }; +/** + * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. + */ struct dmub_cmd_lock_hw_data { + /** + * Specifies the client accessing HW Lock Manager. + */ enum hw_lock_client client; + /** + * HW instances to be locked. + */ struct dmub_hw_lock_inst_flags inst_flags; + /** + * Which components to be locked. + */ union dmub_hw_lock_flags hw_locks; + /** + * Specifies lock/unlock. + */ uint8_t lock; + /** + * HW can be unlocked separately from releasing the HW Lock Mgr. + * This flag is set if the client wishes to release the object. + */ uint8_t should_release; + /** + * Explicit padding to 4 byte boundary. + */ uint8_t pad; }; +/** + * Definition of a DMUB_CMD__HW_LOCK command. + * Command is used by driver and FW. + */ struct dmub_rb_cmd_lock_hw { + /** + * Command header. + */ struct dmub_cmd_header header; + /** + * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. + */ struct dmub_cmd_lock_hw_data lock_hw_data; }; +/** + * ABM command sub-types. + */ enum dmub_cmd_abm_type { + /** + * Initialize parameters for ABM algorithm. + * Data is passed through an indirect buffer. + */ DMUB_CMD__ABM_INIT_CONFIG = 0, + /** + * Set OTG and panel HW instance. + */ DMUB_CMD__ABM_SET_PIPE = 1, + /** + * Set user requested backklight level. + */ DMUB_CMD__ABM_SET_BACKLIGHT = 2, + /** + * Set ABM operating/aggression level. + */ DMUB_CMD__ABM_SET_LEVEL = 3, + /** + * Set ambient light level. + */ DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, + /** + * Enable/disable fractional duty cycle for backlight PWM. + */ DMUB_CMD__ABM_SET_PWM_FRAC = 5, }; -#define NUM_AMBI_LEVEL 5 -#define NUM_AGGR_LEVEL 4 -#define NUM_POWER_FN_SEGS 8 -#define NUM_BL_CURVE_SEGS 16 - -/* - * Parameters for ABM2.4 algorithm. - * Padded explicitly to 32-bit boundary. +/** + * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. + * Requirements: + * - Padded explicitly to 32-bit boundary. + * - Must ensure this structure matches the one on driver-side, + * otherwise it won't be aligned. */ struct abm_config_table { - /* Parameters for crgb conversion */ + /** + * Gamma curve thresholds, used for crgb conversion. + */ uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B + /** + * Gamma curve offsets, used for crgb conversion. + */ uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B + /** + * Gamma curve slopes, used for crgb conversion. + */ uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B - - /* Parameters for custom curve */ + /** + * Custom backlight curve thresholds. + */ uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B + /** + * Custom backlight curve offsets. + */ uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B - + /** + * Ambient light thresholds. + */ uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B + /** + * Minimum programmable backlight. + */ uint16_t min_abm_backlight; // 122B - + /** + * Minimum reduction values. + */ uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B + /** + * Maximum reduction values. + */ uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B + /** + * Bright positive gain. + */ uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B + /** + * Dark negative gain. + */ uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B + /** + * Hybrid factor. + */ uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B + /** + * Contrast factor. + */ uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B + /** + * Deviation gain. + */ uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B + /** + * Minimum knee. + */ uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B + /** + * Maximum knee. + */ uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B + /** + * Unused. + */ uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B + /** + * Explicit padding to 4 byte boundary. + */ uint8_t pad3[3]; // 229B - + /** + * Backlight ramp reduction. + */ uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B + /** + * Backlight ramp start. + */ uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. + */ struct dmub_cmd_abm_set_pipe_data { + /** + * OTG HW instance. + */ uint8_t otg_inst; + + /** + * Panel Control HW instance. + */ uint8_t panel_inst; + + /** + * Controls how ABM will interpret a set pipe or set level command. + */ uint8_t set_pipe_option; - uint8_t ramping_boundary; // TODO: Remove this + + /** + * Unused. + * TODO: Remove. + */ + uint8_t ramping_boundary; }; +/** + * Definition of a DMUB_CMD__ABM_SET_PIPE command. + */ struct dmub_rb_cmd_abm_set_pipe { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. + */ struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. + */ struct dmub_cmd_abm_set_backlight_data { + /** + * Number of frames to ramp to backlight user level. + */ uint32_t frame_ramp; + + /** + * Requested backlight level from user. + */ uint32_t backlight_user_level; }; +/** + * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. + */ struct dmub_rb_cmd_abm_set_backlight { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. + */ struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. + */ struct dmub_cmd_abm_set_level_data { + /** + * Set current ABM operating/aggression level. + */ uint32_t level; }; +/** + * Definition of a DMUB_CMD__ABM_SET_LEVEL command. + */ struct dmub_rb_cmd_abm_set_level { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. + */ struct dmub_cmd_abm_set_level_data abm_set_level_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. + */ struct dmub_cmd_abm_set_ambient_level_data { + /** + * Ambient light sensor reading from OS. + */ uint32_t ambient_lux; }; +/** + * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. + */ struct dmub_rb_cmd_abm_set_ambient_level { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. + */ struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. + */ struct dmub_cmd_abm_set_pwm_frac_data { + /** + * Enable/disable fractional duty cycle for backlight PWM. + * TODO: Convert to uint8_t. + */ uint32_t fractional_pwm; }; +/** + * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. + */ struct dmub_rb_cmd_abm_set_pwm_frac { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. + */ struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. + */ struct dmub_cmd_abm_init_config_data { + /** + * Location of indirect buffer used to pass init data to ABM. + */ union dmub_addr src; + + /** + * Indirect buffer length. + */ uint16_t bytes; }; +/** + * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. + */ struct dmub_rb_cmd_abm_init_config { + /** + * Command header. + */ struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. + */ struct dmub_cmd_abm_init_config_data abm_init_config_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. + */ struct dmub_cmd_query_feature_caps_data { - struct dmub_feature_caps feature_caps; + /** + * DMUB feature capabilities. + * After DMUB init, driver will query FW capabilities prior to enabling certain features. + */ + struct dmub_feature_caps feature_caps; }; +/** + * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. + */ struct dmub_rb_cmd_query_feature_caps { - struct dmub_cmd_header header; - struct dmub_cmd_query_feature_caps_data query_feature_caps_data; + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. + */ + struct dmub_cmd_query_feature_caps_data query_feature_caps_data; +}; + +struct dmub_optc_state { + uint32_t v_total_max; + uint32_t v_total_min; + uint32_t v_total_mid; + uint32_t v_total_mid_frame_num; + uint32_t tg_inst; + uint32_t enable_manual_trigger; + uint32_t clear_force_vsync; +}; + +struct dmub_rb_cmd_drr_update { + struct dmub_cmd_header header; + struct dmub_optc_state dmub_optc_state_req; +}; + +#ifndef TRIM_FAMS +struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { + uint32_t pix_clk_100hz; + uint32_t min_refresh_in_uhz; + uint32_t max_ramp_step; +}; + +struct dmub_cmd_fw_assisted_mclk_switch_config { + uint32_t fams_enabled; + struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; +}; + +struct dmub_rb_cmd_fw_assisted_mclk_switch { + struct dmub_cmd_header header; + struct dmub_cmd_fw_assisted_mclk_switch_config config_data; +}; +#endif + +/** + * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. + */ +struct dmub_cmd_lvtma_control_data { + uint8_t uc_pwr_action; /**< LVTMA_ACTION */ + uint8_t reserved_0[3]; /**< For future use */ + uint8_t panel_inst; /**< LVTMA control instance */ + uint8_t reserved_1[3]; /**< For future use */ +}; + +/** + * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. + */ +struct dmub_rb_cmd_lvtma_control { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. + */ + struct dmub_cmd_lvtma_control_data data; }; - union dmub_rb_cmd { +/** + * union dmub_rb_cmd - DMUB inbox command. + */ +union dmub_rb_cmd { struct dmub_rb_cmd_lock_hw lock_hw; + /** + * Elements shared with all commands. + */ + struct dmub_rb_cmd_common cmd_common; + /** + * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. + */ struct dmub_rb_cmd_read_modify_write read_modify_write; + /** + * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. + */ struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; + /** + * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. + */ struct dmub_rb_cmd_burst_write burst_write; + /** + * Definition of a DMUB_CMD__REG_REG_WAIT command. + */ struct dmub_rb_cmd_reg_wait reg_wait; - struct dmub_rb_cmd_common cmd_common; + /** + * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. + */ struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; + /** + * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. + */ struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; + /** + * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. + */ struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; + /** + * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. + */ struct dmub_rb_cmd_dpphy_init dpphy_init; + /** + * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. + */ struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; + /** + * Definition of a DMUB_CMD__PSR_SET_VERSION command. + */ struct dmub_rb_cmd_psr_set_version psr_set_version; + /** + * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. + */ struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; + /** + * Definition of a DMUB_CMD__PSR_ENABLE command. + */ struct dmub_rb_cmd_psr_enable psr_enable; + /** + * Definition of a DMUB_CMD__PSR_SET_LEVEL command. + */ struct dmub_rb_cmd_psr_set_level psr_set_level; + /** + * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. + */ struct dmub_rb_cmd_psr_force_static psr_force_static; + /** + * Definition of a DMUB_CMD__PLAT_54186_WA command. + */ struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; + /** + * Definition of a DMUB_CMD__MALL command. + */ struct dmub_rb_cmd_mall mall; + /** + * Definition of a DMUB_CMD__ABM_SET_PIPE command. + */ struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; + + /** + * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. + */ struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; + + /** + * Definition of a DMUB_CMD__ABM_SET_LEVEL command. + */ struct dmub_rb_cmd_abm_set_level abm_set_level; + + /** + * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. + */ struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; + + /** + * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. + */ struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; + + /** + * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. + */ struct dmub_rb_cmd_abm_init_config abm_init_config; + + /** + * Definition of a DMUB_CMD__DP_AUX_ACCESS command. + */ struct dmub_rb_cmd_dp_aux_access dp_aux_access; + + /** + * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. + */ struct dmub_rb_cmd_outbox1_enable outbox1_enable; + + /** + * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. + */ struct dmub_rb_cmd_query_feature_caps query_feature_caps; + struct dmub_rb_cmd_drr_update drr_update; +#ifndef TRIM_FAMS + struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; +#endif + /** + * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. + */ + struct dmub_rb_cmd_lvtma_control lvtma_control; }; +/** + * union dmub_rb_out_cmd - Outbox command + */ union dmub_rb_out_cmd { + /** + * Parameters common to every command. + */ struct dmub_rb_cmd_common cmd_common; + /** + * AUX reply command. + */ struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; + /** + * HPD notify command. + */ struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; }; #pragma pack(pop) @@ -910,31 +1990,49 @@ union dmub_rb_out_cmd { extern "C" { #endif +/** + * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer + */ struct dmub_rb_init_params { - void *ctx; - void *base_address; - uint32_t capacity; - uint32_t read_ptr; - uint32_t write_ptr; + void *ctx; /**< Caller provided context pointer */ + void *base_address; /**< CPU base address for ring's data */ + uint32_t capacity; /**< Ringbuffer capacity in bytes */ + uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ + uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ }; +/** + * struct dmub_rb - Inbox or outbox DMUB ringbuffer + */ struct dmub_rb { - void *base_address; - uint32_t data_count; - uint32_t rptr; - uint32_t wrpt; - uint32_t capacity; + void *base_address; /**< CPU address for the ring's data */ + uint32_t rptr; /**< Read pointer for consumer in bytes */ + uint32_t wrpt; /**< Write pointer for producer in bytes */ + uint32_t capacity; /**< Ringbuffer capacity in bytes */ - void *ctx; - void *dmub; + void *ctx; /**< Caller provided context pointer */ + void *dmub; /**< Pointer to the DMUB interface */ }; - +/** + * @brief Checks if the ringbuffer is empty. + * + * @param rb DMUB Ringbuffer + * @return true if empty + * @return false otherwise + */ static inline bool dmub_rb_empty(struct dmub_rb *rb) { return (rb->wrpt == rb->rptr); } +/** + * @brief Checks if the ringbuffer is full + * + * @param rb DMUB Ringbuffer + * @return true if full + * @return false otherwise + */ static inline bool dmub_rb_full(struct dmub_rb *rb) { uint32_t data_count; @@ -947,6 +2045,14 @@ static inline bool dmub_rb_full(struct dmub_rb *rb) return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); } +/** + * @brief Pushes a command into the ringbuffer + * + * @param rb DMUB ringbuffer + * @param cmd The command to push + * @return true if the ringbuffer was not full + * @return false otherwise + */ static inline bool dmub_rb_push_front(struct dmub_rb *rb, const union dmub_rb_cmd *cmd) { @@ -969,6 +2075,14 @@ static inline bool dmub_rb_push_front(struct dmub_rb *rb, return true; } +/** + * @brief Pushes a command into the DMUB outbox ringbuffer + * + * @param rb DMUB outbox ringbuffer + * @param cmd Outbox command + * @return true if not full + * @return false otherwise + */ static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, const union dmub_rb_out_cmd *cmd) { @@ -988,6 +2102,14 @@ static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, return true; } +/** + * @brief Returns the next unprocessed command in the ringbuffer. + * + * @param rb DMUB ringbuffer + * @param cmd The command to return + * @return true if not empty + * @return false otherwise + */ static inline bool dmub_rb_front(struct dmub_rb *rb, union dmub_rb_cmd **cmd) { @@ -1001,6 +2123,14 @@ static inline bool dmub_rb_front(struct dmub_rb *rb, return true; } +/** + * @brief Returns the next unprocessed command in the outbox. + * + * @param rb DMUB outbox ringbuffer + * @param cmd The outbox command to return + * @return true if not empty + * @return false otherwise + */ static inline bool dmub_rb_out_front(struct dmub_rb *rb, union dmub_rb_out_cmd *cmd) { @@ -1018,6 +2148,13 @@ static inline bool dmub_rb_out_front(struct dmub_rb *rb, return true; } +/** + * @brief Removes the front entry in the ringbuffer. + * + * @param rb DMUB ringbuffer + * @return true if the command was removed + * @return false if there were no commands + */ static inline bool dmub_rb_pop_front(struct dmub_rb *rb) { if (dmub_rb_empty(rb)) @@ -1031,6 +2168,14 @@ static inline bool dmub_rb_pop_front(struct dmub_rb *rb) return true; } +/** + * @brief Flushes commands in the ringbuffer to framebuffer memory. + * + * Avoids a race condition where DMCUB accesses memory while + * there are still writes in flight to framebuffer. + * + * @param rb DMUB ringbuffer + */ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) { uint32_t rptr = rb->rptr; @@ -1049,6 +2194,12 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) } } +/** + * @brief Initializes a DMCUB ringbuffer + * + * @param rb DMUB ringbuffer + * @param init_params initial configuration for the ringbuffer + */ static inline void dmub_rb_init(struct dmub_rb *rb, struct dmub_rb_init_params *init_params) { @@ -1058,6 +2209,12 @@ static inline void dmub_rb_init(struct dmub_rb *rb, rb->wrpt = init_params->write_ptr; } +/** + * @brief Copies output data from in/out commands into the given command. + * + * @param rb DMUB ringbuffer + * @param cmd Command to copy data into + */ static inline void dmub_rb_get_return_data(struct dmub_rb *rb, union dmub_rb_cmd *cmd) { diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h index 6b3ee42db350cddc601f83ddbaf0085d7b589194..8a122ceabb3aae53db6c0408e2cbd769469bc8f7 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h @@ -25,7 +25,7 @@ #ifndef _DMUB_TRACE_BUFFER_H_ #define _DMUB_TRACE_BUFFER_H_ -#include "dmub_types.h" +#include "dmub_cmd.h" #define LOAD_DMCU_FW 1 #define LOAD_PHY_FW 2 @@ -65,5 +65,4 @@ struct dmcub_trace_buf { struct dmcub_trace_buf_entry entries[PERF_TRACE_MAX_ENTRY]; }; - #endif /* _DMUB_TRACE_BUFFER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index 945287164cf2853f7f7c2d1eb21a21bbd50ca489..7495c23c73a98465d8957bb7f5218f9a29f15e28 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -20,7 +20,7 @@ # OTHER DEALINGS IN THE SOFTWARE. # -DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o +DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o DMUB += dmub_dcn30.o dmub_dcn301.o DMUB += dmub_dcn302.o diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index 8e8e65fa83c020619bd048dc4b191e16a3bb321d..6934906c665ebc56a7751efb4f2d9ebe063a456e 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -135,6 +135,8 @@ void dmub_dcn20_reset(struct dmub_srv *dmub) REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); REG_WRITE(DMCUB_INBOX1_RPTR, 0); REG_WRITE(DMCUB_INBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); REG_WRITE(DMCUB_SCRATCH0, 0); } @@ -248,6 +250,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, DMCUB_REGION3_CW5_ENABLE, 1); + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); @@ -280,6 +289,54 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); } +void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1) +{ + /* New firmware can support CW4 for the outbox. */ + if (dmub_dcn20_use_cached_inbox(dmub)) + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); + else + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000); + + REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); +} + +uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub) +{ + /** + * outbox1 wptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + return REG_READ(DMCUB_OUTBOX1_WPTR); +} + +void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + /** + * outbox1 rptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); +} + +void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0) +{ + REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); + + REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); +} + +uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_OUTBOX0_WPTR); +} + +void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); +} + bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub) { uint32_t is_hw_init; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h index a62be9c0652e3ec19332b8ae3ffbcb5677c5a695..de5351cd5abc409575a517632ce20c4b13defc32 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h @@ -40,6 +40,14 @@ struct dmub_srv; DMUB_SR(DMCUB_INBOX1_SIZE) \ DMUB_SR(DMCUB_INBOX1_RPTR) \ DMUB_SR(DMCUB_INBOX1_WPTR) \ + DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX0_SIZE) \ + DMUB_SR(DMCUB_OUTBOX0_RPTR) \ + DMUB_SR(DMCUB_OUTBOX0_WPTR) \ + DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX1_SIZE) \ + DMUB_SR(DMCUB_OUTBOX1_RPTR) \ + DMUB_SR(DMCUB_OUTBOX1_WPTR) \ DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \ DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \ DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \ @@ -75,6 +83,9 @@ struct dmub_srv; DMUB_SR(DMCUB_REGION4_OFFSET) \ DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \ DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION5_OFFSET) \ + DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \ DMUB_SR(DMCUB_SCRATCH0) \ DMUB_SR(DMCUB_SCRATCH1) \ DMUB_SR(DMCUB_SCRATCH2) \ @@ -95,7 +106,8 @@ struct dmub_srv; DMUB_SR(CC_DC_PIPE_DIS) \ DMUB_SR(MMHUBBUB_SOFT_RESET) \ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ - DMUB_SR(DCN_VM_FB_OFFSET) + DMUB_SR(DCN_VM_FB_OFFSET) \ + DMUB_SR(DMCUB_INTERRUPT_ACK) #define DMUB_COMMON_FIELDS() \ DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ @@ -123,10 +135,13 @@ struct dmub_srv; DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ - DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) + DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \ + DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK) struct dmub_srv_common_reg_offset { #define DMUB_SR(reg) uint32_t reg; @@ -180,6 +195,20 @@ uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub); void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); +void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1); + +uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub); + +void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0); + +uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub); + +void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub); bool dmub_dcn20_is_supported(struct dmub_srv *dmub); @@ -200,4 +229,6 @@ union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub); bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub); +bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub); + #endif /* _DMUB_DCN20_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c index b4bc0df2f14a3e66ff169c449f43fbb888d89004..fb11c8d392081d4bf718c2fe3e475a9327ac44dc 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c @@ -180,6 +180,13 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub, DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, DMCUB_REGION3_CW5_ENABLE, 1); + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + offset = cw6->offset; REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 61f64a295f06aa82c4dfb6092eb3d0be295dc067..8ba0a9e2da541ec07088ff2b7ffc5883253a6210 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -46,8 +46,8 @@ /* Context size. */ #define DMUB_CONTEXT_SIZE (512 * 1024) -/* Mailbox size */ -#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) +/* Mailbox size : Ring buffers are required for both inbox and outbox */ +#define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) /* Default state size if meta is absent. */ #define DMUB_FW_STATE_SIZE (64 * 1024) @@ -55,6 +55,7 @@ /* Default tracebuffer size if meta is absent. */ #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) + /* Default scratch mem size. */ #define DMUB_SCRATCH_MEM_SIZE (256) @@ -69,6 +70,8 @@ #define DMUB_CW5_BASE (0x65000000) #define DMUB_CW6_BASE (0x66000000) +#define DMUB_REGION5_BASE (0xA0000000) + static inline uint32_t dmub_align(uint32_t val, uint32_t factor) { return (val + factor - 1) / factor * factor; @@ -157,6 +160,16 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; + // Out mailbox register access functions for RN and above + funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; + funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; + funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; + + //outbox0 call stacks + funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; + funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; + funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; + if (asic == DMUB_ASIC_DCN21) { dmub->regs = &dmub_srv_dcn21_regs; @@ -395,9 +408,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; - struct dmub_rb_init_params rb_params; + struct dmub_rb_init_params rb_params, outbox0_rb_params; struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; - struct dmub_region inbox1; + struct dmub_region inbox1, outbox1, outbox0; if (!dmub->sw_init) return DMUB_STATUS_INVALID; @@ -444,13 +457,26 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, cw4.region.base = DMUB_CW4_BASE; cw4.region.top = cw4.region.base + mail_fb->size; + /** + * Doubled the mailbox region to accomodate inbox and outbox. + * Note: Currently, currently total mailbox size is 16KB. It is split + * equally into 8KB between inbox and outbox. If this config is + * changed, then uncached base address configuration of outbox1 + * has to be updated in funcs->setup_out_mailbox. + */ inbox1.base = cw4.region.base; - inbox1.top = cw4.region.top; + inbox1.top = cw4.region.base + DMUB_RB_SIZE; + outbox1.base = inbox1.top; + outbox1.top = cw4.region.top; cw5.offset.quad_part = tracebuff_fb->gpu_addr; cw5.region.base = DMUB_CW5_BASE; cw5.region.top = cw5.region.base + tracebuff_fb->size; + outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; + outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; + + cw6.offset.quad_part = fw_state_fb->gpu_addr; cw6.region.base = DMUB_CW6_BASE; cw6.region.top = cw6.region.base + fw_state_fb->size; @@ -463,8 +489,13 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); + if (dmub->hw_funcs.setup_outbox0) + dmub->hw_funcs.setup_outbox0(dmub, &outbox0); + if (dmub->hw_funcs.setup_mailbox) dmub->hw_funcs.setup_mailbox(dmub, &inbox1); + if (dmub->hw_funcs.setup_out_mailbox) + dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); } if (mail_fb) { @@ -474,8 +505,21 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, rb_params.capacity = DMUB_RB_SIZE; dmub_rb_init(&dmub->inbox1_rb, &rb_params); + + // Initialize outbox1 ring buffer + rb_params.ctx = dmub; + rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); + rb_params.capacity = DMUB_RB_SIZE; + dmub_rb_init(&dmub->outbox1_rb, &rb_params); + } + dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); + outbox0_rb_params.ctx = dmub; + outbox0_rb_params.base_address = (void *)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); + outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); + dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); + if (dmub->hw_funcs.reset_release) dmub->hw_funcs.reset_release(dmub); @@ -674,3 +718,33 @@ enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, return status; } + +static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, + void *entry) +{ + const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); + uint64_t *dst = (uint64_t *)entry; + uint8_t i; + uint8_t loop_count; + + if (rb->rptr == rb->wrpt) + return false; + + loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); + // copying data + for (i = 0; i < loop_count; i++) + *dst++ = *src++; + + rb->rptr += sizeof(struct dmcub_trace_buf_entry); + + rb->rptr %= rb->capacity; + + return true; +} + +bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) +{ + dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); + + return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c new file mode 100644 index 0000000000000000000000000000000000000000..e6f3bfab33d3ea13e1119dd34bab55e8954cbff5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c @@ -0,0 +1,105 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dmub/dmub_srv_stat.h" +#include "dmub/inc/dmub_cmd.h" + +/** + * DOC: DMUB_SRV STAT Interface + * + * These interfaces are called without acquiring DAL and DC locks. + * Hence, there is limitations on whese interfaces can access. Only + * variables exclusively defined for these interfaces can be modified. + */ + +/** + ***************************************************************************** + * Function: dmub_srv_stat_get_notification + * + * @brief + * Retrieves a dmub outbox notification, set up dmub notification + * structure with message information. Also a pending bit if queue + * is having more notifications + * + * @param [in] dmub: dmub srv structure + * @param [out] pnotify: dmub notification structure to be filled up + * + * @return + * dmub_status + ***************************************************************************** + */ +enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, + struct dmub_notification *notify) +{ + /** + * This function is called without dal and dc locks, so + * we shall not modify any dmub variables, only dmub->outbox1_rb + * is exempted as it is exclusively accessed by this function + */ + union dmub_rb_out_cmd cmd = {0}; + + if (!dmub->hw_init) { + notify->type = DMUB_NOTIFICATION_NO_DATA; + notify->pending_notification = false; + return DMUB_STATUS_INVALID; + } + + /* Get write pointer which is updated by dmub */ + dmub->outbox1_rb.wrpt = dmub->hw_funcs.get_outbox1_wptr(dmub); + + if (!dmub_rb_out_front(&dmub->outbox1_rb, &cmd)) { + notify->type = DMUB_NOTIFICATION_NO_DATA; + notify->pending_notification = false; + return DMUB_STATUS_OK; + } + + switch (cmd.cmd_common.header.type) { + case DMUB_OUT_CMD__DP_AUX_REPLY: + notify->type = DMUB_NOTIFICATION_AUX_REPLY; + notify->link_index = cmd.dp_aux_reply.control.instance; + notify->result = cmd.dp_aux_reply.control.result; + dmub_memcpy((void *)¬ify->aux_reply, + (void *)&cmd.dp_aux_reply.reply_data, sizeof(struct aux_reply_data)); + break; + default: + notify->type = DMUB_NOTIFICATION_NO_DATA; + break; + } + + /* Pop outbox1 ringbuffer and update read pointer */ + dmub_rb_pop_front(&dmub->outbox1_rb); + dmub->hw_funcs.set_outbox1_rptr(dmub, dmub->outbox1_rb.rptr); + + /** + * Notify dc whether dmub has a pending outbox message, + * this is to avoid one more call to dmub_srv_stat_get_notification + */ + if (dmub_rb_empty(&dmub->outbox1_rb)) + notify->pending_notification = false; + else + notify->pending_notification = true; + + return DMUB_STATUS_OK; +} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 4762273b5bb9f2f750c4d3942d286a8aa571910e..e5f9d7704a63e4e4144a9db209ceddb0382013dd 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -903,12 +903,31 @@ static void build_vrr_infopacket_v3(enum signal_type signal, infopacket->valid = true; } +static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type, + struct dc_info_packet *infopacket) +{ + uint8_t idx = 0, size = 0; + + size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 : + (packet_type == PACKET_TYPE_FS_V3) ? 0x10 : + 0x09); + + for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B + infopacket->sb[idx] = infopacket->sb[idx-1]; + + infopacket->sb[1] = size; // Length + infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version + infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3 + infopacket->hb2 = 0x1D; +} + void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, const struct dc_stream_state *stream, const struct mod_vrr_params *vrr, enum vrr_packet_type packet_type, enum color_transfer_func app_tf, - struct dc_info_packet *infopacket) + struct dc_info_packet *infopacket, + bool pack_sdp_v1_3) { /* SPD info packet for FreeSync * VTEM info packet for HdmiVRR @@ -941,6 +960,12 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, default: build_vrr_infopacket_v1(stream->signal, vrr, infopacket); } + + if (true == pack_sdp_v1_3 && + true == dc_is_dp_signal(stream->signal) && + packet_type != PACKET_TYPE_VRR && + packet_type != PACKET_TYPE_VTEM) + build_vrr_infopacket_sdp_v1_3(packet_type, infopacket); } void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, @@ -1304,4 +1329,3 @@ bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, return true; } - diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index c80fc10d732c27021acdc4489ab98ba1abeb36d0..b64cd5bdc7b5051fc7d75781ee5ef2bf24681a49 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -150,7 +150,8 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, const struct mod_vrr_params *vrr, enum vrr_packet_type packet_type, enum color_transfer_func app_tf, - struct dc_info_packet *infopacket); + struct dc_info_packet *infopacket, + bool pack_sdp_v1_3); void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, const struct dc_stream_state *stream, diff --git a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..644ffec2b0ce84d6567f28751cb7dae8f48e9c40 --- /dev/null +++ b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h @@ -0,0 +1,1738 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _aldebaran_ip_offset_HEADER +#define _aldebaran_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 6 + +struct IP_BASE_INSTANCE { + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE { + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } }, + { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } }, + { { 0x00000280, 0x02416000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } }, + { { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } }, + { { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } }, + { { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, + { { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } }, + { { 0x04740000, 0x04A00000, 0, 0, 0, 0 } }, + { { 0x04780000, 0x04A40000, 0, 0, 0, 0 } }, + { { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } }, + { { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } }, + { { 0x04840000, 0x04B00000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + + +#define ATHUB_BASE__INST0_SEG0 0x00000C20 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 +#define ATHUB_BASE__INST0_SEG5 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 +#define ATHUB_BASE__INST1_SEG5 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 +#define ATHUB_BASE__INST2_SEG5 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 +#define ATHUB_BASE__INST3_SEG5 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 +#define ATHUB_BASE__INST4_SEG5 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 +#define ATHUB_BASE__INST5_SEG5 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 +#define ATHUB_BASE__INST6_SEG5 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 +#define CLK_BASE__INST0_SEG5 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 +#define CLK_BASE__INST1_SEG5 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 +#define CLK_BASE__INST2_SEG5 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 +#define CLK_BASE__INST3_SEG5 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 +#define CLK_BASE__INST4_SEG5 0 + +#define CLK_BASE__INST5_SEG0 0x0001B200 +#define CLK_BASE__INST5_SEG1 0x0242DC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 +#define CLK_BASE__INST5_SEG5 0 + +#define CLK_BASE__INST6_SEG0 0x00017E00 +#define CLK_BASE__INST6_SEG1 0x0240BC00 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 +#define CLK_BASE__INST6_SEG5 0 + +#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 +#define DBGU_IO0_BASE__INST0_SEG2 0 +#define DBGU_IO0_BASE__INST0_SEG3 0 +#define DBGU_IO0_BASE__INST0_SEG4 0 +#define DBGU_IO0_BASE__INST0_SEG5 0 + +#define DBGU_IO0_BASE__INST1_SEG0 0x00000260 +#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00 +#define DBGU_IO0_BASE__INST1_SEG2 0 +#define DBGU_IO0_BASE__INST1_SEG3 0 +#define DBGU_IO0_BASE__INST1_SEG4 0 +#define DBGU_IO0_BASE__INST1_SEG5 0 + +#define DBGU_IO0_BASE__INST2_SEG0 0x00000280 +#define DBGU_IO0_BASE__INST2_SEG1 0x02416000 +#define DBGU_IO0_BASE__INST2_SEG2 0 +#define DBGU_IO0_BASE__INST2_SEG3 0 +#define DBGU_IO0_BASE__INST2_SEG4 0 +#define DBGU_IO0_BASE__INST2_SEG5 0 + +#define DBGU_IO0_BASE__INST3_SEG0 0 +#define DBGU_IO0_BASE__INST3_SEG1 0 +#define DBGU_IO0_BASE__INST3_SEG2 0 +#define DBGU_IO0_BASE__INST3_SEG3 0 +#define DBGU_IO0_BASE__INST3_SEG4 0 +#define DBGU_IO0_BASE__INST3_SEG5 0 + +#define DBGU_IO0_BASE__INST4_SEG0 0 +#define DBGU_IO0_BASE__INST4_SEG1 0 +#define DBGU_IO0_BASE__INST4_SEG2 0 +#define DBGU_IO0_BASE__INST4_SEG3 0 +#define DBGU_IO0_BASE__INST4_SEG4 0 +#define DBGU_IO0_BASE__INST4_SEG5 0 + +#define DBGU_IO0_BASE__INST5_SEG0 0 +#define DBGU_IO0_BASE__INST5_SEG1 0 +#define DBGU_IO0_BASE__INST5_SEG2 0 +#define DBGU_IO0_BASE__INST5_SEG3 0 +#define DBGU_IO0_BASE__INST5_SEG4 0 +#define DBGU_IO0_BASE__INST5_SEG5 0 + +#define DBGU_IO0_BASE__INST6_SEG0 0 +#define DBGU_IO0_BASE__INST6_SEG1 0 +#define DBGU_IO0_BASE__INST6_SEG2 0 +#define DBGU_IO0_BASE__INST6_SEG3 0 +#define DBGU_IO0_BASE__INST6_SEG4 0 +#define DBGU_IO0_BASE__INST6_SEG5 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0x07C00000 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 +#define DF_BASE__INST0_SEG5 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 +#define DF_BASE__INST1_SEG5 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 +#define DF_BASE__INST2_SEG5 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 +#define DF_BASE__INST3_SEG5 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 +#define DF_BASE__INST4_SEG5 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 +#define DF_BASE__INST5_SEG5 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 +#define DF_BASE__INST6_SEG5 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 +#define FUSE_BASE__INST0_SEG5 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 +#define FUSE_BASE__INST1_SEG5 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 +#define FUSE_BASE__INST2_SEG5 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 +#define FUSE_BASE__INST3_SEG5 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 +#define FUSE_BASE__INST4_SEG5 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 +#define FUSE_BASE__INST5_SEG5 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 +#define FUSE_BASE__INST6_SEG5 0 + +#define GC_BASE__INST0_SEG0 0x00002000 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 +#define GC_BASE__INST0_SEG5 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 +#define GC_BASE__INST1_SEG5 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 +#define GC_BASE__INST2_SEG5 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 +#define GC_BASE__INST3_SEG5 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 +#define GC_BASE__INST4_SEG5 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 +#define GC_BASE__INST5_SEG5 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 +#define GC_BASE__INST6_SEG5 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 +#define HDP_BASE__INST0_SEG5 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 +#define HDP_BASE__INST1_SEG5 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 +#define HDP_BASE__INST2_SEG5 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 +#define HDP_BASE__INST3_SEG5 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 +#define HDP_BASE__INST4_SEG5 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 +#define HDP_BASE__INST5_SEG5 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 +#define HDP_BASE__INST6_SEG5 0 + +#define IOAGR0_BASE__INST0_SEG0 0x02419000 +#define IOAGR0_BASE__INST0_SEG1 0x056C0000 +#define IOAGR0_BASE__INST0_SEG2 0 +#define IOAGR0_BASE__INST0_SEG3 0 +#define IOAGR0_BASE__INST0_SEG4 0 +#define IOAGR0_BASE__INST0_SEG5 0 + +#define IOAGR0_BASE__INST1_SEG0 0 +#define IOAGR0_BASE__INST1_SEG1 0 +#define IOAGR0_BASE__INST1_SEG2 0 +#define IOAGR0_BASE__INST1_SEG3 0 +#define IOAGR0_BASE__INST1_SEG4 0 +#define IOAGR0_BASE__INST1_SEG5 0 + +#define IOAGR0_BASE__INST2_SEG0 0 +#define IOAGR0_BASE__INST2_SEG1 0 +#define IOAGR0_BASE__INST2_SEG2 0 +#define IOAGR0_BASE__INST2_SEG3 0 +#define IOAGR0_BASE__INST2_SEG4 0 +#define IOAGR0_BASE__INST2_SEG5 0 + +#define IOAGR0_BASE__INST3_SEG0 0 +#define IOAGR0_BASE__INST3_SEG1 0 +#define IOAGR0_BASE__INST3_SEG2 0 +#define IOAGR0_BASE__INST3_SEG3 0 +#define IOAGR0_BASE__INST3_SEG4 0 +#define IOAGR0_BASE__INST3_SEG5 0 + +#define IOAGR0_BASE__INST4_SEG0 0 +#define IOAGR0_BASE__INST4_SEG1 0 +#define IOAGR0_BASE__INST4_SEG2 0 +#define IOAGR0_BASE__INST4_SEG3 0 +#define IOAGR0_BASE__INST4_SEG4 0 +#define IOAGR0_BASE__INST4_SEG5 0 + +#define IOAGR0_BASE__INST5_SEG0 0 +#define IOAGR0_BASE__INST5_SEG1 0 +#define IOAGR0_BASE__INST5_SEG2 0 +#define IOAGR0_BASE__INST5_SEG3 0 +#define IOAGR0_BASE__INST5_SEG4 0 +#define IOAGR0_BASE__INST5_SEG5 0 + +#define IOAGR0_BASE__INST6_SEG0 0 +#define IOAGR0_BASE__INST6_SEG1 0 +#define IOAGR0_BASE__INST6_SEG2 0 +#define IOAGR0_BASE__INST6_SEG3 0 +#define IOAGR0_BASE__INST6_SEG4 0 +#define IOAGR0_BASE__INST6_SEG5 0 + +#define IOAPIC0_BASE__INST0_SEG0 0x00A00000 +#define IOAPIC0_BASE__INST0_SEG1 0x0241F000 +#define IOAPIC0_BASE__INST0_SEG2 0x050C0000 +#define IOAPIC0_BASE__INST0_SEG3 0 +#define IOAPIC0_BASE__INST0_SEG4 0 +#define IOAPIC0_BASE__INST0_SEG5 0 + +#define IOAPIC0_BASE__INST1_SEG0 0 +#define IOAPIC0_BASE__INST1_SEG1 0 +#define IOAPIC0_BASE__INST1_SEG2 0 +#define IOAPIC0_BASE__INST1_SEG3 0 +#define IOAPIC0_BASE__INST1_SEG4 0 +#define IOAPIC0_BASE__INST1_SEG5 0 + +#define IOAPIC0_BASE__INST2_SEG0 0 +#define IOAPIC0_BASE__INST2_SEG1 0 +#define IOAPIC0_BASE__INST2_SEG2 0 +#define IOAPIC0_BASE__INST2_SEG3 0 +#define IOAPIC0_BASE__INST2_SEG4 0 +#define IOAPIC0_BASE__INST2_SEG5 0 + +#define IOAPIC0_BASE__INST3_SEG0 0 +#define IOAPIC0_BASE__INST3_SEG1 0 +#define IOAPIC0_BASE__INST3_SEG2 0 +#define IOAPIC0_BASE__INST3_SEG3 0 +#define IOAPIC0_BASE__INST3_SEG4 0 +#define IOAPIC0_BASE__INST3_SEG5 0 + +#define IOAPIC0_BASE__INST4_SEG0 0 +#define IOAPIC0_BASE__INST4_SEG1 0 +#define IOAPIC0_BASE__INST4_SEG2 0 +#define IOAPIC0_BASE__INST4_SEG3 0 +#define IOAPIC0_BASE__INST4_SEG4 0 +#define IOAPIC0_BASE__INST4_SEG5 0 + +#define IOAPIC0_BASE__INST5_SEG0 0 +#define IOAPIC0_BASE__INST5_SEG1 0 +#define IOAPIC0_BASE__INST5_SEG2 0 +#define IOAPIC0_BASE__INST5_SEG3 0 +#define IOAPIC0_BASE__INST5_SEG4 0 +#define IOAPIC0_BASE__INST5_SEG5 0 + +#define IOAPIC0_BASE__INST6_SEG0 0 +#define IOAPIC0_BASE__INST6_SEG1 0 +#define IOAPIC0_BASE__INST6_SEG2 0 +#define IOAPIC0_BASE__INST6_SEG3 0 +#define IOAPIC0_BASE__INST6_SEG4 0 +#define IOAPIC0_BASE__INST6_SEG5 0 + +#define IOHC0_BASE__INST0_SEG0 0x00010000 +#define IOHC0_BASE__INST0_SEG1 0x02406000 +#define IOHC0_BASE__INST0_SEG2 0x04EC0000 +#define IOHC0_BASE__INST0_SEG3 0 +#define IOHC0_BASE__INST0_SEG4 0 +#define IOHC0_BASE__INST0_SEG5 0 + +#define IOHC0_BASE__INST1_SEG0 0 +#define IOHC0_BASE__INST1_SEG1 0 +#define IOHC0_BASE__INST1_SEG2 0 +#define IOHC0_BASE__INST1_SEG3 0 +#define IOHC0_BASE__INST1_SEG4 0 +#define IOHC0_BASE__INST1_SEG5 0 + +#define IOHC0_BASE__INST2_SEG0 0 +#define IOHC0_BASE__INST2_SEG1 0 +#define IOHC0_BASE__INST2_SEG2 0 +#define IOHC0_BASE__INST2_SEG3 0 +#define IOHC0_BASE__INST2_SEG4 0 +#define IOHC0_BASE__INST2_SEG5 0 + +#define IOHC0_BASE__INST3_SEG0 0 +#define IOHC0_BASE__INST3_SEG1 0 +#define IOHC0_BASE__INST3_SEG2 0 +#define IOHC0_BASE__INST3_SEG3 0 +#define IOHC0_BASE__INST3_SEG4 0 +#define IOHC0_BASE__INST3_SEG5 0 + +#define IOHC0_BASE__INST4_SEG0 0 +#define IOHC0_BASE__INST4_SEG1 0 +#define IOHC0_BASE__INST4_SEG2 0 +#define IOHC0_BASE__INST4_SEG3 0 +#define IOHC0_BASE__INST4_SEG4 0 +#define IOHC0_BASE__INST4_SEG5 0 + +#define IOHC0_BASE__INST5_SEG0 0 +#define IOHC0_BASE__INST5_SEG1 0 +#define IOHC0_BASE__INST5_SEG2 0 +#define IOHC0_BASE__INST5_SEG3 0 +#define IOHC0_BASE__INST5_SEG4 0 +#define IOHC0_BASE__INST5_SEG5 0 + +#define IOHC0_BASE__INST6_SEG0 0 +#define IOHC0_BASE__INST6_SEG1 0 +#define IOHC0_BASE__INST6_SEG2 0 +#define IOHC0_BASE__INST6_SEG3 0 +#define IOHC0_BASE__INST6_SEG4 0 +#define IOHC0_BASE__INST6_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST0_SEG0 0x0240CC00 +#define L1IMUIOAGR0_BASE__INST0_SEG1 0x05200000 +#define L1IMUIOAGR0_BASE__INST0_SEG2 0 +#define L1IMUIOAGR0_BASE__INST0_SEG3 0 +#define L1IMUIOAGR0_BASE__INST0_SEG4 0 +#define L1IMUIOAGR0_BASE__INST0_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST1_SEG0 0 +#define L1IMUIOAGR0_BASE__INST1_SEG1 0 +#define L1IMUIOAGR0_BASE__INST1_SEG2 0 +#define L1IMUIOAGR0_BASE__INST1_SEG3 0 +#define L1IMUIOAGR0_BASE__INST1_SEG4 0 +#define L1IMUIOAGR0_BASE__INST1_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST2_SEG0 0 +#define L1IMUIOAGR0_BASE__INST2_SEG1 0 +#define L1IMUIOAGR0_BASE__INST2_SEG2 0 +#define L1IMUIOAGR0_BASE__INST2_SEG3 0 +#define L1IMUIOAGR0_BASE__INST2_SEG4 0 +#define L1IMUIOAGR0_BASE__INST2_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST3_SEG0 0 +#define L1IMUIOAGR0_BASE__INST3_SEG1 0 +#define L1IMUIOAGR0_BASE__INST3_SEG2 0 +#define L1IMUIOAGR0_BASE__INST3_SEG3 0 +#define L1IMUIOAGR0_BASE__INST3_SEG4 0 +#define L1IMUIOAGR0_BASE__INST3_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST4_SEG0 0 +#define L1IMUIOAGR0_BASE__INST4_SEG1 0 +#define L1IMUIOAGR0_BASE__INST4_SEG2 0 +#define L1IMUIOAGR0_BASE__INST4_SEG3 0 +#define L1IMUIOAGR0_BASE__INST4_SEG4 0 +#define L1IMUIOAGR0_BASE__INST4_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST5_SEG0 0 +#define L1IMUIOAGR0_BASE__INST5_SEG1 0 +#define L1IMUIOAGR0_BASE__INST5_SEG2 0 +#define L1IMUIOAGR0_BASE__INST5_SEG3 0 +#define L1IMUIOAGR0_BASE__INST5_SEG4 0 +#define L1IMUIOAGR0_BASE__INST5_SEG5 0 + +#define L1IMUIOAGR0_BASE__INST6_SEG0 0 +#define L1IMUIOAGR0_BASE__INST6_SEG1 0 +#define L1IMUIOAGR0_BASE__INST6_SEG2 0 +#define L1IMUIOAGR0_BASE__INST6_SEG3 0 +#define L1IMUIOAGR0_BASE__INST6_SEG4 0 +#define L1IMUIOAGR0_BASE__INST6_SEG5 0 + +#define L1IMUPCIE0_BASE__INST0_SEG0 0x0240C800 +#define L1IMUPCIE0_BASE__INST0_SEG1 0x051C0000 +#define L1IMUPCIE0_BASE__INST0_SEG2 0 +#define L1IMUPCIE0_BASE__INST0_SEG3 0 +#define L1IMUPCIE0_BASE__INST0_SEG4 0 +#define L1IMUPCIE0_BASE__INST0_SEG5 0 + +#define L1IMUPCIE0_BASE__INST1_SEG0 0 +#define L1IMUPCIE0_BASE__INST1_SEG1 0 +#define L1IMUPCIE0_BASE__INST1_SEG2 0 +#define L1IMUPCIE0_BASE__INST1_SEG3 0 +#define L1IMUPCIE0_BASE__INST1_SEG4 0 +#define L1IMUPCIE0_BASE__INST1_SEG5 0 + +#define L1IMUPCIE0_BASE__INST2_SEG0 0 +#define L1IMUPCIE0_BASE__INST2_SEG1 0 +#define L1IMUPCIE0_BASE__INST2_SEG2 0 +#define L1IMUPCIE0_BASE__INST2_SEG3 0 +#define L1IMUPCIE0_BASE__INST2_SEG4 0 +#define L1IMUPCIE0_BASE__INST2_SEG5 0 + +#define L1IMUPCIE0_BASE__INST3_SEG0 0 +#define L1IMUPCIE0_BASE__INST3_SEG1 0 +#define L1IMUPCIE0_BASE__INST3_SEG2 0 +#define L1IMUPCIE0_BASE__INST3_SEG3 0 +#define L1IMUPCIE0_BASE__INST3_SEG4 0 +#define L1IMUPCIE0_BASE__INST3_SEG5 0 + +#define L1IMUPCIE0_BASE__INST4_SEG0 0 +#define L1IMUPCIE0_BASE__INST4_SEG1 0 +#define L1IMUPCIE0_BASE__INST4_SEG2 0 +#define L1IMUPCIE0_BASE__INST4_SEG3 0 +#define L1IMUPCIE0_BASE__INST4_SEG4 0 +#define L1IMUPCIE0_BASE__INST4_SEG5 0 + +#define L1IMUPCIE0_BASE__INST5_SEG0 0 +#define L1IMUPCIE0_BASE__INST5_SEG1 0 +#define L1IMUPCIE0_BASE__INST5_SEG2 0 +#define L1IMUPCIE0_BASE__INST5_SEG3 0 +#define L1IMUPCIE0_BASE__INST5_SEG4 0 +#define L1IMUPCIE0_BASE__INST5_SEG5 0 + +#define L1IMUPCIE0_BASE__INST6_SEG0 0 +#define L1IMUPCIE0_BASE__INST6_SEG1 0 +#define L1IMUPCIE0_BASE__INST6_SEG2 0 +#define L1IMUPCIE0_BASE__INST6_SEG3 0 +#define L1IMUPCIE0_BASE__INST6_SEG4 0 +#define L1IMUPCIE0_BASE__INST6_SEG5 0 + +#define L2IMU0_BASE__INST0_SEG0 0x00007DC0 +#define L2IMU0_BASE__INST0_SEG1 0x00900000 +#define L2IMU0_BASE__INST0_SEG2 0x02407000 +#define L2IMU0_BASE__INST0_SEG3 0x04FC0000 +#define L2IMU0_BASE__INST0_SEG4 0x055C0000 +#define L2IMU0_BASE__INST0_SEG5 0 + +#define L2IMU0_BASE__INST1_SEG0 0 +#define L2IMU0_BASE__INST1_SEG1 0 +#define L2IMU0_BASE__INST1_SEG2 0 +#define L2IMU0_BASE__INST1_SEG3 0 +#define L2IMU0_BASE__INST1_SEG4 0 +#define L2IMU0_BASE__INST1_SEG5 0 + +#define L2IMU0_BASE__INST2_SEG0 0 +#define L2IMU0_BASE__INST2_SEG1 0 +#define L2IMU0_BASE__INST2_SEG2 0 +#define L2IMU0_BASE__INST2_SEG3 0 +#define L2IMU0_BASE__INST2_SEG4 0 +#define L2IMU0_BASE__INST2_SEG5 0 + +#define L2IMU0_BASE__INST3_SEG0 0 +#define L2IMU0_BASE__INST3_SEG1 0 +#define L2IMU0_BASE__INST3_SEG2 0 +#define L2IMU0_BASE__INST3_SEG3 0 +#define L2IMU0_BASE__INST3_SEG4 0 +#define L2IMU0_BASE__INST3_SEG5 0 + +#define L2IMU0_BASE__INST4_SEG0 0 +#define L2IMU0_BASE__INST4_SEG1 0 +#define L2IMU0_BASE__INST4_SEG2 0 +#define L2IMU0_BASE__INST4_SEG3 0 +#define L2IMU0_BASE__INST4_SEG4 0 +#define L2IMU0_BASE__INST4_SEG5 0 + +#define L2IMU0_BASE__INST5_SEG0 0 +#define L2IMU0_BASE__INST5_SEG1 0 +#define L2IMU0_BASE__INST5_SEG2 0 +#define L2IMU0_BASE__INST5_SEG3 0 +#define L2IMU0_BASE__INST5_SEG4 0 +#define L2IMU0_BASE__INST5_SEG5 0 + +#define L2IMU0_BASE__INST6_SEG0 0 +#define L2IMU0_BASE__INST6_SEG1 0 +#define L2IMU0_BASE__INST6_SEG2 0 +#define L2IMU0_BASE__INST6_SEG3 0 +#define L2IMU0_BASE__INST6_SEG4 0 +#define L2IMU0_BASE__INST6_SEG5 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 +#define MMHUB_BASE__INST0_SEG5 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 +#define MMHUB_BASE__INST1_SEG5 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 +#define MMHUB_BASE__INST2_SEG5 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 +#define MMHUB_BASE__INST3_SEG5 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 +#define MMHUB_BASE__INST4_SEG5 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 +#define MMHUB_BASE__INST5_SEG5 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 +#define MMHUB_BASE__INST6_SEG5 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 +#define MP0_BASE__INST0_SEG5 0 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 +#define MP0_BASE__INST1_SEG5 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 +#define MP0_BASE__INST2_SEG5 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 +#define MP0_BASE__INST3_SEG5 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 +#define MP0_BASE__INST4_SEG5 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 +#define MP0_BASE__INST5_SEG5 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 +#define MP0_BASE__INST6_SEG5 0 + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00DC0000 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E40000 +#define MP1_BASE__INST0_SEG4 0x0243FC00 +#define MP1_BASE__INST0_SEG5 0 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 +#define MP1_BASE__INST1_SEG5 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 +#define MP1_BASE__INST2_SEG5 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 +#define MP1_BASE__INST3_SEG5 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 +#define MP1_BASE__INST4_SEG5 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 +#define MP1_BASE__INST5_SEG5 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 +#define MP1_BASE__INST6_SEG5 0 + +#define NBIO_BASE__INST0_SEG0 0x00000000 +#define NBIO_BASE__INST0_SEG1 0x00000014 +#define NBIO_BASE__INST0_SEG2 0x00000D20 +#define NBIO_BASE__INST0_SEG3 0x00010400 +#define NBIO_BASE__INST0_SEG4 0x0241B000 +#define NBIO_BASE__INST0_SEG5 0x04040000 + +#define NBIO_BASE__INST1_SEG0 0 +#define NBIO_BASE__INST1_SEG1 0 +#define NBIO_BASE__INST1_SEG2 0 +#define NBIO_BASE__INST1_SEG3 0 +#define NBIO_BASE__INST1_SEG4 0 +#define NBIO_BASE__INST1_SEG5 0 + +#define NBIO_BASE__INST2_SEG0 0 +#define NBIO_BASE__INST2_SEG1 0 +#define NBIO_BASE__INST2_SEG2 0 +#define NBIO_BASE__INST2_SEG3 0 +#define NBIO_BASE__INST2_SEG4 0 +#define NBIO_BASE__INST2_SEG5 0 + +#define NBIO_BASE__INST3_SEG0 0 +#define NBIO_BASE__INST3_SEG1 0 +#define NBIO_BASE__INST3_SEG2 0 +#define NBIO_BASE__INST3_SEG3 0 +#define NBIO_BASE__INST3_SEG4 0 +#define NBIO_BASE__INST3_SEG5 0 + +#define NBIO_BASE__INST4_SEG0 0 +#define NBIO_BASE__INST4_SEG1 0 +#define NBIO_BASE__INST4_SEG2 0 +#define NBIO_BASE__INST4_SEG3 0 +#define NBIO_BASE__INST4_SEG4 0 +#define NBIO_BASE__INST4_SEG5 0 + +#define NBIO_BASE__INST5_SEG0 0 +#define NBIO_BASE__INST5_SEG1 0 +#define NBIO_BASE__INST5_SEG2 0 +#define NBIO_BASE__INST5_SEG3 0 +#define NBIO_BASE__INST5_SEG4 0 +#define NBIO_BASE__INST5_SEG5 0 + +#define NBIO_BASE__INST6_SEG0 0 +#define NBIO_BASE__INST6_SEG1 0 +#define NBIO_BASE__INST6_SEG2 0 +#define NBIO_BASE__INST6_SEG3 0 +#define NBIO_BASE__INST6_SEG4 0 +#define NBIO_BASE__INST6_SEG5 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 +#define OSSSYS_BASE__INST0_SEG5 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 +#define OSSSYS_BASE__INST1_SEG5 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 +#define OSSSYS_BASE__INST2_SEG5 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 +#define OSSSYS_BASE__INST3_SEG5 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 +#define OSSSYS_BASE__INST4_SEG5 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 +#define OSSSYS_BASE__INST5_SEG5 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 +#define OSSSYS_BASE__INST6_SEG5 0 + +#define PCIE0_BASE__INST0_SEG0 0x02411800 +#define PCIE0_BASE__INST0_SEG1 0x04440000 +#define PCIE0_BASE__INST0_SEG2 0 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 +#define PCIE0_BASE__INST0_SEG5 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 +#define PCIE0_BASE__INST1_SEG5 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 +#define PCIE0_BASE__INST2_SEG5 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 +#define PCIE0_BASE__INST3_SEG5 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 +#define PCIE0_BASE__INST4_SEG5 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 +#define PCIE0_BASE__INST5_SEG5 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 +#define PCIE0_BASE__INST6_SEG5 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x02445400 +#define SDMA0_BASE__INST0_SEG2 0 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 +#define SDMA0_BASE__INST0_SEG5 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 +#define SDMA0_BASE__INST1_SEG5 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 +#define SDMA0_BASE__INST2_SEG5 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 +#define SDMA0_BASE__INST3_SEG5 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 +#define SDMA0_BASE__INST4_SEG5 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 +#define SDMA0_BASE__INST5_SEG5 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 +#define SDMA0_BASE__INST6_SEG5 0 + +#define SDMA1_BASE__INST0_SEG0 0x00001860 +#define SDMA1_BASE__INST0_SEG1 0x02445800 +#define SDMA1_BASE__INST0_SEG2 0 +#define SDMA1_BASE__INST0_SEG3 0 +#define SDMA1_BASE__INST0_SEG4 0 +#define SDMA1_BASE__INST0_SEG5 0 + +#define SDMA1_BASE__INST1_SEG0 0x0001E000 +#define SDMA1_BASE__INST1_SEG1 0x02446400 +#define SDMA1_BASE__INST1_SEG2 0 +#define SDMA1_BASE__INST1_SEG3 0 +#define SDMA1_BASE__INST1_SEG4 0 +#define SDMA1_BASE__INST1_SEG5 0 + +#define SDMA1_BASE__INST2_SEG0 0x0001E400 +#define SDMA1_BASE__INST2_SEG1 0x02446800 +#define SDMA1_BASE__INST2_SEG2 0 +#define SDMA1_BASE__INST2_SEG3 0 +#define SDMA1_BASE__INST2_SEG4 0 +#define SDMA1_BASE__INST2_SEG5 0 + +#define SDMA1_BASE__INST3_SEG0 0x0001E800 +#define SDMA1_BASE__INST3_SEG1 0x02446C00 +#define SDMA1_BASE__INST3_SEG2 0 +#define SDMA1_BASE__INST3_SEG3 0 +#define SDMA1_BASE__INST3_SEG4 0 +#define SDMA1_BASE__INST3_SEG5 0 + +#define SDMA1_BASE__INST4_SEG0 0 +#define SDMA1_BASE__INST4_SEG1 0 +#define SDMA1_BASE__INST4_SEG2 0 +#define SDMA1_BASE__INST4_SEG3 0 +#define SDMA1_BASE__INST4_SEG4 0 +#define SDMA1_BASE__INST4_SEG5 0 + +#define SDMA1_BASE__INST5_SEG0 0 +#define SDMA1_BASE__INST5_SEG1 0 +#define SDMA1_BASE__INST5_SEG2 0 +#define SDMA1_BASE__INST5_SEG3 0 +#define SDMA1_BASE__INST5_SEG4 0 +#define SDMA1_BASE__INST5_SEG5 0 + +#define SDMA1_BASE__INST6_SEG0 0 +#define SDMA1_BASE__INST6_SEG1 0 +#define SDMA1_BASE__INST6_SEG2 0 +#define SDMA1_BASE__INST6_SEG3 0 +#define SDMA1_BASE__INST6_SEG4 0 +#define SDMA1_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x02401000 +#define SMUIO_BASE__INST0_SEG3 0x03440000 +#define SMUIO_BASE__INST0_SEG4 0 +#define SMUIO_BASE__INST0_SEG5 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 +#define SMUIO_BASE__INST1_SEG5 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 +#define SMUIO_BASE__INST2_SEG5 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 +#define SMUIO_BASE__INST3_SEG5 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 +#define SMUIO_BASE__INST4_SEG5 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 +#define SMUIO_BASE__INST5_SEG5 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 +#define SMUIO_BASE__INST6_SEG5 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 +#define THM_BASE__INST0_SEG5 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 +#define THM_BASE__INST1_SEG5 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 +#define THM_BASE__INST2_SEG5 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 +#define THM_BASE__INST3_SEG5 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 +#define THM_BASE__INST4_SEG5 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 +#define THM_BASE__INST5_SEG5 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 +#define THM_BASE__INST6_SEG5 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x00054000 +#define UMC_BASE__INST0_SEG2 0x02425800 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 +#define UMC_BASE__INST0_SEG5 0 + +#define UMC_BASE__INST1_SEG0 0x00094000 +#define UMC_BASE__INST1_SEG1 0x000D4000 +#define UMC_BASE__INST1_SEG2 0x02425C00 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 +#define UMC_BASE__INST1_SEG5 0 + +#define UMC_BASE__INST2_SEG0 0x00114000 +#define UMC_BASE__INST2_SEG1 0x00154000 +#define UMC_BASE__INST2_SEG2 0x02426000 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 +#define UMC_BASE__INST2_SEG5 0 + +#define UMC_BASE__INST3_SEG0 0x00194000 +#define UMC_BASE__INST3_SEG1 0x001D4000 +#define UMC_BASE__INST3_SEG2 0x02426400 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 +#define UMC_BASE__INST3_SEG5 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 +#define UMC_BASE__INST4_SEG5 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 +#define UMC_BASE__INST5_SEG5 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 +#define UMC_BASE__INST6_SEG5 0 + +#define VCN_BASE__INST0_SEG0 0x00007800 +#define VCN_BASE__INST0_SEG1 0x00007E00 +#define VCN_BASE__INST0_SEG2 0x02403000 +#define VCN_BASE__INST0_SEG3 0 +#define VCN_BASE__INST0_SEG4 0 +#define VCN_BASE__INST0_SEG5 0 + +#define VCN_BASE__INST1_SEG0 0x00007A00 +#define VCN_BASE__INST1_SEG1 0x00009000 +#define VCN_BASE__INST1_SEG2 0x02445000 +#define VCN_BASE__INST1_SEG3 0 +#define VCN_BASE__INST1_SEG4 0 +#define VCN_BASE__INST1_SEG5 0 + +#define VCN_BASE__INST2_SEG0 0 +#define VCN_BASE__INST2_SEG1 0 +#define VCN_BASE__INST2_SEG2 0 +#define VCN_BASE__INST2_SEG3 0 +#define VCN_BASE__INST2_SEG4 0 +#define VCN_BASE__INST2_SEG5 0 + +#define VCN_BASE__INST3_SEG0 0 +#define VCN_BASE__INST3_SEG1 0 +#define VCN_BASE__INST3_SEG2 0 +#define VCN_BASE__INST3_SEG3 0 +#define VCN_BASE__INST3_SEG4 0 +#define VCN_BASE__INST3_SEG5 0 + +#define VCN_BASE__INST4_SEG0 0 +#define VCN_BASE__INST4_SEG1 0 +#define VCN_BASE__INST4_SEG2 0 +#define VCN_BASE__INST4_SEG3 0 +#define VCN_BASE__INST4_SEG4 0 +#define VCN_BASE__INST4_SEG5 0 + +#define VCN_BASE__INST5_SEG0 0 +#define VCN_BASE__INST5_SEG1 0 +#define VCN_BASE__INST5_SEG2 0 +#define VCN_BASE__INST5_SEG3 0 +#define VCN_BASE__INST5_SEG4 0 +#define VCN_BASE__INST5_SEG5 0 + +#define VCN_BASE__INST6_SEG0 0 +#define VCN_BASE__INST6_SEG1 0 +#define VCN_BASE__INST6_SEG2 0 +#define VCN_BASE__INST6_SEG3 0 +#define VCN_BASE__INST6_SEG4 0 +#define VCN_BASE__INST6_SEG5 0 + +#define WAFL0_BASE__INST0_SEG0 0x02438000 +#define WAFL0_BASE__INST0_SEG1 0x04880000 +#define WAFL0_BASE__INST0_SEG2 0 +#define WAFL0_BASE__INST0_SEG3 0 +#define WAFL0_BASE__INST0_SEG4 0 +#define WAFL0_BASE__INST0_SEG5 0 + +#define WAFL0_BASE__INST1_SEG0 0 +#define WAFL0_BASE__INST1_SEG1 0 +#define WAFL0_BASE__INST1_SEG2 0 +#define WAFL0_BASE__INST1_SEG3 0 +#define WAFL0_BASE__INST1_SEG4 0 +#define WAFL0_BASE__INST1_SEG5 0 + +#define WAFL0_BASE__INST2_SEG0 0 +#define WAFL0_BASE__INST2_SEG1 0 +#define WAFL0_BASE__INST2_SEG2 0 +#define WAFL0_BASE__INST2_SEG3 0 +#define WAFL0_BASE__INST2_SEG4 0 +#define WAFL0_BASE__INST2_SEG5 0 + +#define WAFL0_BASE__INST3_SEG0 0 +#define WAFL0_BASE__INST3_SEG1 0 +#define WAFL0_BASE__INST3_SEG2 0 +#define WAFL0_BASE__INST3_SEG3 0 +#define WAFL0_BASE__INST3_SEG4 0 +#define WAFL0_BASE__INST3_SEG5 0 + +#define WAFL0_BASE__INST4_SEG0 0 +#define WAFL0_BASE__INST4_SEG1 0 +#define WAFL0_BASE__INST4_SEG2 0 +#define WAFL0_BASE__INST4_SEG3 0 +#define WAFL0_BASE__INST4_SEG4 0 +#define WAFL0_BASE__INST4_SEG5 0 + +#define WAFL0_BASE__INST5_SEG0 0 +#define WAFL0_BASE__INST5_SEG1 0 +#define WAFL0_BASE__INST5_SEG2 0 +#define WAFL0_BASE__INST5_SEG3 0 +#define WAFL0_BASE__INST5_SEG4 0 +#define WAFL0_BASE__INST5_SEG5 0 + +#define WAFL0_BASE__INST6_SEG0 0 +#define WAFL0_BASE__INST6_SEG1 0 +#define WAFL0_BASE__INST6_SEG2 0 +#define WAFL0_BASE__INST6_SEG3 0 +#define WAFL0_BASE__INST6_SEG4 0 +#define WAFL0_BASE__INST6_SEG5 0 + +#define WAFL1_BASE__INST0_SEG0 0 +#define WAFL1_BASE__INST0_SEG1 0x01300000 +#define WAFL1_BASE__INST0_SEG2 0x02410800 +#define WAFL1_BASE__INST0_SEG3 0 +#define WAFL1_BASE__INST0_SEG4 0 +#define WAFL1_BASE__INST0_SEG5 0 + +#define WAFL1_BASE__INST1_SEG0 0 +#define WAFL1_BASE__INST1_SEG1 0 +#define WAFL1_BASE__INST1_SEG2 0 +#define WAFL1_BASE__INST1_SEG3 0 +#define WAFL1_BASE__INST1_SEG4 0 +#define WAFL1_BASE__INST1_SEG5 0 + +#define WAFL1_BASE__INST2_SEG0 0 +#define WAFL1_BASE__INST2_SEG1 0 +#define WAFL1_BASE__INST2_SEG2 0 +#define WAFL1_BASE__INST2_SEG3 0 +#define WAFL1_BASE__INST2_SEG4 0 +#define WAFL1_BASE__INST2_SEG5 0 + +#define WAFL1_BASE__INST3_SEG0 0 +#define WAFL1_BASE__INST3_SEG1 0 +#define WAFL1_BASE__INST3_SEG2 0 +#define WAFL1_BASE__INST3_SEG3 0 +#define WAFL1_BASE__INST3_SEG4 0 +#define WAFL1_BASE__INST3_SEG5 0 + +#define WAFL1_BASE__INST4_SEG0 0 +#define WAFL1_BASE__INST4_SEG1 0 +#define WAFL1_BASE__INST4_SEG2 0 +#define WAFL1_BASE__INST4_SEG3 0 +#define WAFL1_BASE__INST4_SEG4 0 +#define WAFL1_BASE__INST4_SEG5 0 + +#define WAFL1_BASE__INST5_SEG0 0 +#define WAFL1_BASE__INST5_SEG1 0 +#define WAFL1_BASE__INST5_SEG2 0 +#define WAFL1_BASE__INST5_SEG3 0 +#define WAFL1_BASE__INST5_SEG4 0 +#define WAFL1_BASE__INST5_SEG5 0 + +#define WAFL1_BASE__INST6_SEG0 0 +#define WAFL1_BASE__INST6_SEG1 0 +#define WAFL1_BASE__INST6_SEG2 0 +#define WAFL1_BASE__INST6_SEG3 0 +#define WAFL1_BASE__INST6_SEG4 0 +#define WAFL1_BASE__INST6_SEG5 0 + +#define XGMI0_BASE__INST0_SEG0 0x02438C00 +#define XGMI0_BASE__INST0_SEG1 0x04680000 +#define XGMI0_BASE__INST0_SEG2 0x04940000 +#define XGMI0_BASE__INST0_SEG3 0 +#define XGMI0_BASE__INST0_SEG4 0 +#define XGMI0_BASE__INST0_SEG5 0 + +#define XGMI0_BASE__INST1_SEG0 0 +#define XGMI0_BASE__INST1_SEG1 0 +#define XGMI0_BASE__INST1_SEG2 0 +#define XGMI0_BASE__INST1_SEG3 0 +#define XGMI0_BASE__INST1_SEG4 0 +#define XGMI0_BASE__INST1_SEG5 0 + +#define XGMI0_BASE__INST2_SEG0 0 +#define XGMI0_BASE__INST2_SEG1 0 +#define XGMI0_BASE__INST2_SEG2 0 +#define XGMI0_BASE__INST2_SEG3 0 +#define XGMI0_BASE__INST2_SEG4 0 +#define XGMI0_BASE__INST2_SEG5 0 + +#define XGMI0_BASE__INST3_SEG0 0 +#define XGMI0_BASE__INST3_SEG1 0 +#define XGMI0_BASE__INST3_SEG2 0 +#define XGMI0_BASE__INST3_SEG3 0 +#define XGMI0_BASE__INST3_SEG4 0 +#define XGMI0_BASE__INST3_SEG5 0 + +#define XGMI0_BASE__INST4_SEG0 0 +#define XGMI0_BASE__INST4_SEG1 0 +#define XGMI0_BASE__INST4_SEG2 0 +#define XGMI0_BASE__INST4_SEG3 0 +#define XGMI0_BASE__INST4_SEG4 0 +#define XGMI0_BASE__INST4_SEG5 0 + +#define XGMI0_BASE__INST5_SEG0 0 +#define XGMI0_BASE__INST5_SEG1 0 +#define XGMI0_BASE__INST5_SEG2 0 +#define XGMI0_BASE__INST5_SEG3 0 +#define XGMI0_BASE__INST5_SEG4 0 +#define XGMI0_BASE__INST5_SEG5 0 + +#define XGMI0_BASE__INST6_SEG0 0 +#define XGMI0_BASE__INST6_SEG1 0 +#define XGMI0_BASE__INST6_SEG2 0 +#define XGMI0_BASE__INST6_SEG3 0 +#define XGMI0_BASE__INST6_SEG4 0 +#define XGMI0_BASE__INST6_SEG5 0 + +#define XGMI1_BASE__INST0_SEG0 0x02439000 +#define XGMI1_BASE__INST0_SEG1 0x046C0000 +#define XGMI1_BASE__INST0_SEG2 0x04980000 +#define XGMI1_BASE__INST0_SEG3 0 +#define XGMI1_BASE__INST0_SEG4 0 +#define XGMI1_BASE__INST0_SEG5 0 + +#define XGMI1_BASE__INST1_SEG0 0 +#define XGMI1_BASE__INST1_SEG1 0 +#define XGMI1_BASE__INST1_SEG2 0 +#define XGMI1_BASE__INST1_SEG3 0 +#define XGMI1_BASE__INST1_SEG4 0 +#define XGMI1_BASE__INST1_SEG5 0 + +#define XGMI1_BASE__INST2_SEG0 0 +#define XGMI1_BASE__INST2_SEG1 0 +#define XGMI1_BASE__INST2_SEG2 0 +#define XGMI1_BASE__INST2_SEG3 0 +#define XGMI1_BASE__INST2_SEG4 0 +#define XGMI1_BASE__INST2_SEG5 0 + +#define XGMI1_BASE__INST3_SEG0 0 +#define XGMI1_BASE__INST3_SEG1 0 +#define XGMI1_BASE__INST3_SEG2 0 +#define XGMI1_BASE__INST3_SEG3 0 +#define XGMI1_BASE__INST3_SEG4 0 +#define XGMI1_BASE__INST3_SEG5 0 + +#define XGMI1_BASE__INST4_SEG0 0 +#define XGMI1_BASE__INST4_SEG1 0 +#define XGMI1_BASE__INST4_SEG2 0 +#define XGMI1_BASE__INST4_SEG3 0 +#define XGMI1_BASE__INST4_SEG4 0 +#define XGMI1_BASE__INST4_SEG5 0 + +#define XGMI1_BASE__INST5_SEG0 0 +#define XGMI1_BASE__INST5_SEG1 0 +#define XGMI1_BASE__INST5_SEG2 0 +#define XGMI1_BASE__INST5_SEG3 0 +#define XGMI1_BASE__INST5_SEG4 0 +#define XGMI1_BASE__INST5_SEG5 0 + +#define XGMI1_BASE__INST6_SEG0 0 +#define XGMI1_BASE__INST6_SEG1 0 +#define XGMI1_BASE__INST6_SEG2 0 +#define XGMI1_BASE__INST6_SEG3 0 +#define XGMI1_BASE__INST6_SEG4 0 +#define XGMI1_BASE__INST6_SEG5 0 + +#define XGMI2_BASE__INST0_SEG0 0x04700000 +#define XGMI2_BASE__INST0_SEG1 0x049C0000 +#define XGMI2_BASE__INST0_SEG2 0 +#define XGMI2_BASE__INST0_SEG3 0 +#define XGMI2_BASE__INST0_SEG4 0 +#define XGMI2_BASE__INST0_SEG5 0 + +#define XGMI2_BASE__INST1_SEG0 0x04740000 +#define XGMI2_BASE__INST1_SEG1 0x04A00000 +#define XGMI2_BASE__INST1_SEG2 0 +#define XGMI2_BASE__INST1_SEG3 0 +#define XGMI2_BASE__INST1_SEG4 0 +#define XGMI2_BASE__INST1_SEG5 0 + +#define XGMI2_BASE__INST2_SEG0 0x04780000 +#define XGMI2_BASE__INST2_SEG1 0x04A40000 +#define XGMI2_BASE__INST2_SEG2 0 +#define XGMI2_BASE__INST2_SEG3 0 +#define XGMI2_BASE__INST2_SEG4 0 +#define XGMI2_BASE__INST2_SEG5 0 + +#define XGMI2_BASE__INST3_SEG0 0x047C0000 +#define XGMI2_BASE__INST3_SEG1 0x04A80000 +#define XGMI2_BASE__INST3_SEG2 0 +#define XGMI2_BASE__INST3_SEG3 0 +#define XGMI2_BASE__INST3_SEG4 0 +#define XGMI2_BASE__INST3_SEG5 0 + +#define XGMI2_BASE__INST4_SEG0 0x04800000 +#define XGMI2_BASE__INST4_SEG1 0x04AC0000 +#define XGMI2_BASE__INST4_SEG2 0 +#define XGMI2_BASE__INST4_SEG3 0 +#define XGMI2_BASE__INST4_SEG4 0 +#define XGMI2_BASE__INST4_SEG5 0 + +#define XGMI2_BASE__INST5_SEG0 0x04840000 +#define XGMI2_BASE__INST5_SEG1 0x04B00000 +#define XGMI2_BASE__INST5_SEG2 0 +#define XGMI2_BASE__INST5_SEG3 0 +#define XGMI2_BASE__INST5_SEG4 0 +#define XGMI2_BASE__INST5_SEG5 0 + +#define XGMI2_BASE__INST6_SEG0 0 +#define XGMI2_BASE__INST6_SEG1 0 +#define XGMI2_BASE__INST6_SEG2 0 +#define XGMI2_BASE__INST6_SEG3 0 +#define XGMI2_BASE__INST6_SEG4 0 +#define XGMI2_BASE__INST6_SEG5 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index cf166b591bc5d6fd0a7b75317e80d0498c63a955..483769fb1736b3e2809238e65baf70926875b811 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -8922,7 +8922,7 @@ #define mmOTG1_OTG_CONTROL 0x1bc1 #define mmOTG1_OTG_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 -#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX +#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..a9ad00e017a566fb9a66f85ef53a31aab907fef5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h @@ -0,0 +1,7683 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_9_4_2_OFFSET_HEADER +#define _gc_9_4_2_OFFSET_HEADER + + + +// addressBlock: didtind +// base address: 0x0 +#define ixDIDT_SQ_CTRL0 0x0000 +#define ixDIDT_SQ_CTRL2 0x0002 +#define ixDIDT_SQ_STALL_CTRL 0x0004 +#define ixDIDT_SQ_TUNING_CTRL 0x0005 +#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 +#define ixDIDT_SQ_CTRL3 0x0007 +#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 +#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 +#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a +#define ixDIDT_SQ_STALL_PATTERN_7 0x000b +#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c +#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d +#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e +#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f +#define ixDIDT_SQ_WEIGHT0_3 0x0010 +#define ixDIDT_SQ_WEIGHT4_7 0x0011 +#define ixDIDT_SQ_WEIGHT8_11 0x0012 +#define ixDIDT_SQ_EDC_CTRL 0x0013 +#define ixDIDT_SQ_THROTTLE_CTRL 0x0014 +#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 +#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 +#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 +#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 +#define ixDIDT_SQ_EDC_STATUS 0x0019 +#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a +#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b +#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c +#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d +#define ixDIDT_SQ_EDC_OVERFLOW 0x001e +#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f +#define ixDIDT_DB_CTRL0 0x0020 +#define ixDIDT_DB_CTRL2 0x0022 +#define ixDIDT_DB_STALL_CTRL 0x0024 +#define ixDIDT_DB_TUNING_CTRL 0x0025 +#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 +#define ixDIDT_DB_CTRL3 0x0027 +#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 +#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 +#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a +#define ixDIDT_DB_STALL_PATTERN_7 0x002b +#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c +#define ixDIDT_DB_THROTTLE_CNTL0 0x002d +#define ixDIDT_DB_THROTTLE_CNTL1 0x002e +#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f +#define ixDIDT_DB_WEIGHT0_3 0x0030 +#define ixDIDT_DB_WEIGHT4_7 0x0031 +#define ixDIDT_DB_WEIGHT8_11 0x0032 +#define ixDIDT_DB_EDC_CTRL 0x0033 +#define ixDIDT_DB_THROTTLE_CTRL 0x0034 +#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 +#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 +#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 +#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 +#define ixDIDT_DB_EDC_STATUS 0x0039 +#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a +#define ixDIDT_DB_EDC_OVERFLOW 0x003e +#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f +#define ixDIDT_TD_CTRL0 0x0040 +#define ixDIDT_TD_CTRL2 0x0042 +#define ixDIDT_TD_STALL_CTRL 0x0044 +#define ixDIDT_TD_TUNING_CTRL 0x0045 +#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 +#define ixDIDT_TD_CTRL3 0x0047 +#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 +#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 +#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a +#define ixDIDT_TD_STALL_PATTERN_7 0x004b +#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c +#define ixDIDT_TD_THROTTLE_CNTL0 0x004d +#define ixDIDT_TD_THROTTLE_CNTL1 0x004e +#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f +#define ixDIDT_TD_WEIGHT0_3 0x0050 +#define ixDIDT_TD_WEIGHT4_7 0x0051 +#define ixDIDT_TD_WEIGHT8_11 0x0052 +#define ixDIDT_TD_EDC_CTRL 0x0053 +#define ixDIDT_TD_THROTTLE_CTRL 0x0054 +#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 +#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 +#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 +#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 +#define ixDIDT_TD_EDC_STATUS 0x0059 +#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a +#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b +#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c +#define ixDIDT_TD_EDC_STALL_DELAY_4 0x005d +#define ixDIDT_TD_EDC_OVERFLOW 0x005e +#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f +#define ixDIDT_TCP_CTRL0 0x0060 +#define ixDIDT_TCP_CTRL2 0x0062 +#define ixDIDT_TCP_STALL_CTRL 0x0064 +#define ixDIDT_TCP_TUNING_CTRL 0x0065 +#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 +#define ixDIDT_TCP_CTRL3 0x0067 +#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 +#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 +#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a +#define ixDIDT_TCP_STALL_PATTERN_7 0x006b +#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x006c +#define ixDIDT_TCP_THROTTLE_CNTL0 0x006d +#define ixDIDT_TCP_THROTTLE_CNTL1 0x006e +#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0x006f +#define ixDIDT_TCP_WEIGHT0_3 0x0070 +#define ixDIDT_TCP_WEIGHT4_7 0x0071 +#define ixDIDT_TCP_WEIGHT8_11 0x0072 +#define ixDIDT_TCP_EDC_CTRL 0x0073 +#define ixDIDT_TCP_THROTTLE_CTRL 0x0074 +#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 +#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 +#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 +#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 +#define ixDIDT_TCP_EDC_STATUS 0x0079 +#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a +#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b +#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c +#define ixDIDT_TCP_EDC_STALL_DELAY_4 0x007d +#define ixDIDT_TCP_EDC_OVERFLOW 0x007e +#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f +#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 +#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 +#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 +#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 +#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 +#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0x00a5 +#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0x00a6 +#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0x00a7 +#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0x00a8 +#define ixDIDT_DBR_EDC_PCC_PERF_COUNTER 0x00a9 +#define ixDIDT_SQ_CTRL1 0x00b0 +#define ixDIDT_SQ_EDC_THRESHOLD 0x00b1 +#define ixDIDT_DB_CTRL1 0x00b2 +#define ixDIDT_DB_EDC_THRESHOLD 0x00b3 +#define ixDIDT_TD_CTRL1 0x00b4 +#define ixDIDT_TD_EDC_THRESHOLD 0x00b5 +#define ixDIDT_TCP_CTRL1 0x00b6 +#define ixDIDT_TCP_EDC_THRESHOLD 0x00b7 + + +// addressBlock: gc_cpdec +// base address: 0x8200 +#define regCP_CPC_STATUS 0x0084 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0085 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0086 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0087 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0088 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0089 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x008b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_MEC_CNTL 0x008d +#define regCP_MEC_CNTL_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x008e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_MEC_ME2_HEADER_DUMP 0x008f +#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0090 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0091 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0092 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x00a7 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_CE_COMPARE_COUNT 0x00c0 +#define regCP_CE_COMPARE_COUNT_BASE_IDX 0 +#define regCP_CE_DE_COUNT 0x00c1 +#define regCP_CE_DE_COUNT_BASE_IDX 0 +#define regCP_DE_CE_COUNT 0x00c2 +#define regCP_DE_CE_COUNT_BASE_IDX 0 +#define regCP_DE_LAST_INVAL_COUNT 0x00c3 +#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 +#define regCP_DE_DE_COUNT 0x00c4 +#define regCP_DE_DE_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x019c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x019d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x019e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x019f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x01a0 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x01a1 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x01a2 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x01a3 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CE_HEADER_DUMP 0x01a4 +#define regCP_CE_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x01a5 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x01a6 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_CE_INSTR_PNTR 0x01a7 +#define regCP_CE_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC1_INSTR_PNTR 0x01a8 +#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC2_INSTR_PNTR 0x01a9 +#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x01b4 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_ME_CNTL 0x01b6 +#define regCP_ME_CNTL_BASE_IDX 0 +#define regCP_CNTX_STAT 0x01b8 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x01b9 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_ROQ_THRESHOLDS 0x01bc +#define regCP_ROQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_STQ_THRESHOLD 0x01bd +#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 +#define regCP_RB2_RPTR 0x01be +#define regCP_RB2_RPTR_BASE_IDX 0 +#define regCP_RB1_RPTR 0x01bf +#define regCP_RB1_RPTR_BASE_IDX 0 +#define regCP_RB0_RPTR 0x01c0 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x01c0 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x01c1 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x01c2 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x01d5 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x01d6 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x01d7 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_QUEUE_THRESHOLDS 0x01d8 +#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x01d9 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x01da +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x01db +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x01dc +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x01dd +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x01de +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x01df +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x01e0 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x01e1 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x01e2 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x01e3 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x01e4 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x01e5 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_CEQ1_AVAIL 0x01e6 +#define regCP_CEQ1_AVAIL_BASE_IDX 0 +#define regCP_CEQ2_AVAIL 0x01e7 +#define regCP_CEQ2_AVAIL_BASE_IDX 0 +#define regCP_CE_ROQ_RB_STAT 0x01e8 +#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_CE_ROQ_IB1_STAT 0x01e9 +#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_CE_ROQ_IB2_STAT 0x01ea +#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x01fa +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 + + +// addressBlock: gc_cppdec +// base address: 0xc080 +#define regCP_EOPQ_WAIT_TIME 0x1035 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1036 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1037 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1038 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1039 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x103a +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x103b +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x103c +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x103d +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x103e +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x103f +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1040 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1040 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1041 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1041 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1042 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1043 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1043 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1044 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1044 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1045 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1045 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1046 +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1047 +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_INT_CNTL 0x1049 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x104a +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x104b +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x104c +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x104c +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x104d +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x104d +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE1_PRIORITY 0x104e +#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_RING1_PRIORITY 0x104e +#define regCP_RING1_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE2_PRIORITY 0x104f +#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_RING2_PRIORITY 0x104f +#define regCP_RING2_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1050 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1051 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1052 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE1_VMID 0x1053 +#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1054 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1054 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1055 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1055 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_RB1_WPTR 0x1056 +#define regCP_RB1_WPTR_BASE_IDX 0 +#define regCP_RB1_WPTR_HI 0x1057 +#define regCP_RB1_WPTR_HI_BASE_IDX 0 +#define regCP_RB2_WPTR 0x1058 +#define regCP_RB2_WPTR_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1059 +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x105a +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x105b +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x105c +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x105d +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x105e +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x105f +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCP_RB1_BASE 0x1060 +#define regCP_RB1_BASE_BASE_IDX 0 +#define regCP_RB1_CNTL 0x1061 +#define regCP_RB1_CNTL_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR 0x1062 +#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR_HI 0x1063 +#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB2_BASE 0x1065 +#define regCP_RB2_BASE_BASE_IDX 0 +#define regCP_RB2_CNTL 0x1066 +#define regCP_RB2_CNTL_BASE_IDX 0 +#define regCP_RB2_RPTR_ADDR 0x1067 +#define regCP_RB2_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB2_RPTR_ADDR_HI 0x1068 +#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1069 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1069 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x106a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_INT_CNTL_RING1 0x106b +#define regCP_INT_CNTL_RING1_BASE_IDX 0 +#define regCP_INT_CNTL_RING2 0x106c +#define regCP_INT_CNTL_RING2_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x106d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_INT_STATUS_RING1 0x106e +#define regCP_INT_STATUS_RING1_BASE_IDX 0 +#define regCP_INT_STATUS_RING2 0x106f +#define regCP_INT_STATUS_RING2_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1073 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1074 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_CE_F32_INTERRUPT 0x1075 +#define regCP_CE_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1076 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC2_F32_INTERRUPT 0x1077 +#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1078 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_MEM_SLP_CNTL 0x1079 +#define regCP_MEM_SLP_CNTL_BASE_IDX 0 +#define regCP_ECC_DMA_FIRST_OCCURRENCE 0x107a +#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x107a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x107b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x107c +#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING2 0x107d +#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 +#define regGB_EDC_MODE 0x107e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1083 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1084 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1085 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1086 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1087 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1088 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_CNTL 0x1089 +#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_CNTL 0x108a +#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_CNTL 0x108b +#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_CNTL 0x108c +#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x108d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x108e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x108f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1090 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_STATUS 0x1091 +#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_STATUS 0x1092 +#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_STATUS 0x1093 +#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_STATUS 0x1094 +#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1098 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1099 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x109a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x109b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x109c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x109d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE_PRIORITY_CNTS 0x109e +#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME2_PIPE0_PRIORITY 0x109f +#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE1_PRIORITY 0x10a0 +#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE2_PRIORITY 0x10a1 +#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE3_PRIORITY 0x10a2 +#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_CE_PRGRM_CNTR_START 0x10a3 +#define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x10a4 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x10a5 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x10a6 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC2_PRGRM_CNTR_START 0x10a7 +#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_CE_INTR_ROUTINE_START 0x10a8 +#define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x10a9 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x10aa +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x10ab +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC2_INTR_ROUTINE_START 0x10ac +#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x10ad +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x10ae +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x10af +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x10b0 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x10b1 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_RB1_BASE_HI 0x10b2 +#define regCP_RB1_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x10b3 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x10b4 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x10b5 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x10b6 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x10b7 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x10b8 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_CPC_IC_BASE_LO 0x10b9 +#define regCP_CPC_IC_BASE_LO_BASE_IDX 0 +#define regCP_CPC_IC_BASE_HI 0x10ba +#define regCP_CPC_IC_BASE_HI_BASE_IDX 0 +#define regCP_CPC_IC_BASE_CNTL 0x10bb +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0 +#define regCP_CPC_IC_OP_CNTL 0x10bc +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 0 +#define regCP_MEC1_F32_INT_DIS 0x10bd +#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 +#define regCP_MEC2_F32_INT_DIS 0x10be +#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 +#define regCP_VMID_STATUS 0x10bf +#define regCP_VMID_STATUS_BASE_IDX 0 + + +// addressBlock: gc_cppdec2 +// base address: 0xc600 +#define regCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 +#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 +#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 +#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 +#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 +#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 +#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 +#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 +#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1188 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCPF_EDC_TAG_CNT 0x1189 +#define regCPF_EDC_TAG_CNT_BASE_IDX 0 +#define regCPF_EDC_ROQ_CNT 0x118a +#define regCPF_EDC_ROQ_CNT_BASE_IDX 0 +#define regCPG_EDC_TAG_CNT 0x118b +#define regCPG_EDC_TAG_CNT_BASE_IDX 0 +#define regCPG_EDC_DMA_CNT 0x118d +#define regCPG_EDC_DMA_CNT_BASE_IDX 0 +#define regCPC_EDC_SCRATCH_CNT 0x118e +#define regCPC_EDC_SCRATCH_CNT_BASE_IDX 0 +#define regCPC_EDC_UCODE_CNT 0x118f +#define regCPC_EDC_UCODE_CNT_BASE_IDX 0 +#define regDC_EDC_STATE_CNT 0x1191 +#define regDC_EDC_STATE_CNT_BASE_IDX 0 +#define regDC_EDC_CSINVOC_CNT 0x1192 +#define regDC_EDC_CSINVOC_CNT_BASE_IDX 0 +#define regDC_EDC_RESTORE_CNT 0x1193 +#define regDC_EDC_RESTORE_CNT_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL 0x1194 +#define regCP_CPF_DSM_CNTL_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL 0x1195 +#define regCP_CPG_DSM_CNTL_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL 0x1196 +#define regCP_CPC_DSM_CNTL_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL2 0x1197 +#define regCP_CPF_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL2 0x1198 +#define regCP_CPG_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL2 0x1199 +#define regCP_CPC_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL2A 0x119a +#define regCP_CPF_DSM_CNTL2A_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL2A 0x119b +#define regCP_CPG_DSM_CNTL2A_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL2A 0x119c +#define regCP_CPC_DSM_CNTL2A_BASE_IDX 0 +#define regCP_EDC_FUE_CNTL 0x119d +#define regCP_EDC_FUE_CNTL_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x11a0 +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x11a1 +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x11a2 +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_RB_STATUS 0x11a3 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x11b4 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x11b5 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x11b6 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x11b7 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x11b9 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x11ba +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: gc_cpphqddec +// base address: 0xc800 +#define regCP_HQD_GFX_CONTROL 0x123e +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x123f +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_HPD_ROQ_OFFSETS 0x1240 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0 +#define regCP_HPD_STATUS0 0x1241 +#define regCP_HPD_STATUS0_BASE_IDX 0 +#define regCP_HPD_UTCL1_CNTL 0x1242 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1243 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1244 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1245 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1246 +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1247 +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1248 +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1249 +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x124a +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x124b +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x124c +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x124d +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x124e +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x124f +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1256 +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1257 +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1258 +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1259 +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x125a +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x125b +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x125c +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x125d +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x125e +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x125e +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_SEMA_CMD 0x125f +#define regCP_HQD_SEMA_CMD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1260 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1261 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1262 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1263 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1264 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1265 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1265 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1266 +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1266 +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1267 +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1268 +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1269 +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x126a +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x126b +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x126c +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x126d +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x126e +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x126f +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1272 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1273 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1274 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1275 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1276 +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1277 +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1278 +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1279 +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x127a +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x127b +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x127c +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 + + +// addressBlock: gc_didtdec +// base address: 0xca00 +#define regDIDT_IND_INDEX 0x1280 +#define regDIDT_IND_INDEX_BASE_IDX 0 +#define regDIDT_IND_DATA 0x1281 +#define regDIDT_IND_DATA_BASE_IDX 0 +#define regDIDT_INDEX_AUTO_INCR_EN 0x1282 +#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 + + +// addressBlock: gc_ea_gceadec +// base address: 0xa800 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 +#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 +#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_RD_LAZY 0x0a06 +#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_WR_LAZY 0x0a07 +#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_RD_CAM_CNTL 0x0a08 +#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_WR_CAM_CNTL 0x0a09 +#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_PAGE_BURST 0x0a0a +#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_AGE 0x0a0b +#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_AGE 0x0a0c +#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUEUING 0x0a0d +#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUEUING 0x0a0e +#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_FIXED 0x0a0f +#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_FIXED 0x0a10 +#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_URGENCY 0x0a11 +#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_URGENCY 0x0a12 +#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_ADDRNORM_BASE_ADDR0 0x0a34 +#define regGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regGCEA_ADDRNORM_LIMIT_ADDR0 0x0a35 +#define regGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regGCEA_ADDRNORM_BASE_ADDR1 0x0a36 +#define regGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORM_LIMIT_ADDR1 0x0a37 +#define regGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORM_OFFSET_ADDR1 0x0a38 +#define regGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORM_BASE_ADDR2 0x0a39 +#define regGCEA_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regGCEA_ADDRNORM_LIMIT_ADDR2 0x0a3a +#define regGCEA_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regGCEA_ADDRNORM_BASE_ADDR3 0x0a3b +#define regGCEA_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regGCEA_ADDRNORM_LIMIT_ADDR3 0x0a3c +#define regGCEA_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regGCEA_ADDRNORM_OFFSET_ADDR3 0x0a3d +#define regGCEA_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGABASE_ADDR0 0x0a3e +#define regGCEA_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0 0x0a3f +#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGABASE_ADDR1 0x0a40 +#define regGCEA_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1 0x0a41 +#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORMDRAM_HOLE_CNTL 0x0a43 +#define regGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regGCEA_ADDRNORMGMI_HOLE_CNTL 0x0a44 +#define regGCEA_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0a45 +#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0a46 +#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regGCEA_ADDRDEC_BANK_CFG 0x0a47 +#define regGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regGCEA_ADDRDEC_MISC_CFG 0x0a48 +#define regGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a53 +#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regGCEA_ADDRDECGMI_HARVEST_ENABLE 0x0a5e +#define regGCEA_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a5f +#define regGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a60 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a61 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a62 +#define regGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a63 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a64 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a65 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a66 +#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a67 +#define regGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a68 +#define regGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a69 +#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a6a +#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a6b +#define regGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a6c +#define regGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a6d +#define regGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a6e +#define regGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01 0x0a6f +#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23 0x0a70 +#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a71 +#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a72 +#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a73 +#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a74 +#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_RM_SEL_CS01 0x0a75 +#define regGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_RM_SEL_CS23 0x0a76 +#define regGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a77 +#define regGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a78 +#define regGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a79 +#define regGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a7a +#define regGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a7b +#define regGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a7c +#define regGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a7d +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a7e +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a7f +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a80 +#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a81 +#define regGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a82 +#define regGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a83 +#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a84 +#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a85 +#define regGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a86 +#define regGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a87 +#define regGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a88 +#define regGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01 0x0a89 +#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23 0x0a8a +#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a8b +#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a8c +#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a8d +#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a8e +#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_RM_SEL_CS01 0x0a8f +#define regGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_RM_SEL_CS23 0x0a90 +#define regGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a91 +#define regGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a92 +#define regGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS0 0x0a93 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS1 0x0a94 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS2 0x0a95 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS3 0x0a96 +#define regGCEA_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0 0x0a97 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1 0x0a98 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2 0x0a99 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3 0x0a9a +#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_MASK_CS01 0x0a9b +#define regGCEA_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_MASK_CS23 0x0a9c +#define regGCEA_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01 0x0a9d +#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23 0x0a9e +#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_CFG_CS01 0x0a9f +#define regGCEA_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_CFG_CS23 0x0aa0 +#define regGCEA_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_SEL_CS01 0x0aa1 +#define regGCEA_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_SEL_CS23 0x0aa2 +#define regGCEA_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01 0x0aa3 +#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23 0x0aa4 +#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01 0x0aa5 +#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23 0x0aa6 +#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01 0x0aa7 +#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23 0x0aa8 +#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_RM_SEL_CS01 0x0aa9 +#define regGCEA_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_RM_SEL_CS23 0x0aaa +#define regGCEA_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regGCEA_ADDRDEC2_RM_SEL_SECCS01 0x0aab +#define regGCEA_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regGCEA_ADDRDEC2_RM_SEL_SECCS23 0x0aac +#define regGCEA_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL 0x0aad +#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL 0x0aae +#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0 0x0ad1 +#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1 0x0ad2 +#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regGCEA_ADDRNORMDRAM_MASKING 0x0ad3 +#define regGCEA_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regGCEA_ADDRNORMGMI_MASKING 0x0ad4 +#define regGCEA_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 +#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 +#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 +#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 +#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 +#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_WR_COMBINE_FLUSH 0x0ada +#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_GROUP_BURST 0x0adb +#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_AGE 0x0adc +#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_AGE 0x0add +#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUEUING 0x0ade +#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUEUING 0x0adf +#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_FIXED 0x0ae0 +#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_FIXED 0x0ae1 +#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY 0x0ae2 +#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY 0x0ae3 +#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x0ae4 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x0ae5 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 +#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 +#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 +#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 +#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea +#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb +#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_MISC 0x0afa +#define regGCEA_MISC_BASE_IDX 0 +#define regGCEA_LATENCY_SAMPLING 0x0afb +#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 +#define regGCEA_PERFCOUNTER_LO 0x0afc +#define regGCEA_PERFCOUNTER_LO_BASE_IDX 0 +#define regGCEA_PERFCOUNTER_HI 0x0afd +#define regGCEA_PERFCOUNTER_HI_BASE_IDX 0 +#define regGCEA_PERFCOUNTER0_CFG 0x0afe +#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regGCEA_PERFCOUNTER1_CFG 0x0aff +#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 + + +// addressBlock: gc_ea_gceadec2 +// base address: 0x9c00 +#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 +#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regGCEA_EDC_CNT 0x0706 +#define regGCEA_EDC_CNT_BASE_IDX 0 +#define regGCEA_EDC_CNT2 0x0707 +#define regGCEA_EDC_CNT2_BASE_IDX 0 +#define regGCEA_DSM_CNTL 0x0708 +#define regGCEA_DSM_CNTL_BASE_IDX 0 +#define regGCEA_DSM_CNTLA 0x0709 +#define regGCEA_DSM_CNTLA_BASE_IDX 0 +#define regGCEA_DSM_CNTLB 0x070a +#define regGCEA_DSM_CNTLB_BASE_IDX 0 +#define regGCEA_DSM_CNTL2 0x070b +#define regGCEA_DSM_CNTL2_BASE_IDX 0 +#define regGCEA_DSM_CNTL2A 0x070c +#define regGCEA_DSM_CNTL2A_BASE_IDX 0 +#define regGCEA_DSM_CNTL2B 0x070d +#define regGCEA_DSM_CNTL2B_BASE_IDX 0 +#define regGCEA_TCC_XBR_CREDITS 0x070e +#define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0 +#define regGCEA_TCC_XBR_MAXBURST 0x070f +#define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 +#define regGCEA_PROBE_CNTL 0x0710 +#define regGCEA_PROBE_CNTL_BASE_IDX 0 +#define regGCEA_PROBE_MAP 0x0711 +#define regGCEA_PROBE_MAP_BASE_IDX 0 +#define regGCEA_ERR_STATUS 0x0712 +#define regGCEA_ERR_STATUS_BASE_IDX 0 +#define regGCEA_MISC2 0x0713 +#define regGCEA_MISC2_BASE_IDX 0 +#define regGCEA_DRAM_BANK_ARB 0x0714 +#define regGCEA_DRAM_BANK_ARB_BASE_IDX 0 +#define regGCEA_ADDRDEC_SELECT 0x071a +#define regGCEA_ADDRDEC_SELECT_BASE_IDX 0 +#define regGCEA_EDC_CNT3 0x071b +#define regGCEA_EDC_CNT3_BASE_IDX 0 + +// addressBlock: gc_ea_pwrdec +// base address: 0x3c000 +#define regGCEA_CGTT_CLK_CTRL 0x50c4 +#define regGCEA_CGTT_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_gccacdec +// base address: 0xca10 +#define regGC_CAC_CTRL_1 0x1284 +#define regGC_CAC_CTRL_1_BASE_IDX 0 +#define regGC_CAC_CTRL_2 0x1285 +#define regGC_CAC_CTRL_2_BASE_IDX 0 +#define regGC_CAC_INDEX_AUTO_INCR_EN 0x1286 +#define regGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0 +#define regGC_CAC_AGGR_LOWER 0x1287 +#define regGC_CAC_AGGR_LOWER_BASE_IDX 0 +#define regGC_CAC_AGGR_UPPER 0x1288 +#define regGC_CAC_AGGR_UPPER_BASE_IDX 0 +#define regGC_EDC_PERF_COUNTER 0x1289 +#define regGC_EDC_PERF_COUNTER_BASE_IDX 0 +#define regPCC_PERF_COUNTER 0x128a +#define regPCC_PERF_COUNTER_BASE_IDX 0 +#define regGC_CAC_SOFT_CTRL 0x128d +#define regGC_CAC_SOFT_CTRL_BASE_IDX 0 +#define regGC_DIDT_CTRL0 0x128e +#define regGC_DIDT_CTRL0_BASE_IDX 0 +#define regGC_DIDT_CTRL1 0x128f +#define regGC_DIDT_CTRL1_BASE_IDX 0 +#define regGC_DIDT_CTRL2 0x1290 +#define regGC_DIDT_CTRL2_BASE_IDX 0 +#define regGC_DIDT_WEIGHT 0x1291 +#define regGC_DIDT_WEIGHT_BASE_IDX 0 +#define regGC_THROTTLE_CTRL1 0x1292 +#define regGC_THROTTLE_CTRL1_BASE_IDX 0 +#define regGC_EDC_CTRL 0x1293 +#define regGC_EDC_CTRL_BASE_IDX 0 +#define regGC_EDC_THRESHOLD 0x1294 +#define regGC_EDC_THRESHOLD_BASE_IDX 0 +#define regGC_EDC_STATUS 0x1295 +#define regGC_EDC_STATUS_BASE_IDX 0 +#define regGC_EDC_OVERFLOW 0x1296 +#define regGC_EDC_OVERFLOW_BASE_IDX 0 +#define regGC_EDC_ROLLING_POWER_DELTA 0x1297 +#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 +#define regGC_EDC_CTRL1 0x1298 +#define regGC_EDC_CTRL1_BASE_IDX 0 +#define regGC_THROTTLE_CTRL2 0x1299 +#define regGC_THROTTLE_CTRL2_BASE_IDX 0 +#define regPWRBRK_PERF_COUNTER 0x129a +#define regPWRBRK_PERF_COUNTER_BASE_IDX 0 +#define regGC_THROTTLE_CTRL 0x129b +#define regGC_THROTTLE_CTRL_BASE_IDX 0 +#define regGC_CAC_IND_INDEX 0x129c +#define regGC_CAC_IND_INDEX_BASE_IDX 0 +#define regGC_CAC_IND_DATA 0x129d +#define regGC_CAC_IND_DATA_BASE_IDX 0 +#define regSE_CAC_IND_INDEX 0x129e +#define regSE_CAC_IND_INDEX_BASE_IDX 0 +#define regSE_CAC_IND_DATA 0x129f +#define regSE_CAC_IND_DATA_BASE_IDX 0 + + +// addressBlock: gc_gdsdec +// base address: 0x9700 +#define regGDS_CONFIG 0x05c0 +#define regGDS_CONFIG_BASE_IDX 0 +#define regGDS_CNTL_STATUS 0x05c1 +#define regGDS_CNTL_STATUS_BASE_IDX 0 +#define regGDS_ENHANCE2 0x05c2 +#define regGDS_ENHANCE2_BASE_IDX 0 +#define regGDS_PROTECTION_FAULT 0x05c3 +#define regGDS_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_VM_PROTECTION_FAULT 0x05c4 +#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_EDC_CNT 0x05c5 +#define regGDS_EDC_CNT_BASE_IDX 0 +#define regGDS_EDC_GRBM_CNT 0x05c6 +#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_DED 0x05c7 +#define regGDS_EDC_OA_DED_BASE_IDX 0 +#define regGDS_DSM_CNTL 0x05ca +#define regGDS_DSM_CNTL_BASE_IDX 0 +#define regGDS_EDC_OA_PHY_CNT 0x05cb +#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_PIPE_CNT 0x05cc +#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 +#define regGDS_DSM_CNTL2 0x05cd +#define regGDS_DSM_CNTL2_BASE_IDX 0 +#define regGDS_WD_GDS_CSB 0x05ce +#define regGDS_WD_GDS_CSB_BASE_IDX 0 + + +// addressBlock: gc_gdspdec +// base address: 0xcc00 +#define regGDS_VMID0_BASE 0x1300 +#define regGDS_VMID0_BASE_BASE_IDX 0 +#define regGDS_VMID0_SIZE 0x1301 +#define regGDS_VMID0_SIZE_BASE_IDX 0 +#define regGDS_VMID1_BASE 0x1302 +#define regGDS_VMID1_BASE_BASE_IDX 0 +#define regGDS_VMID1_SIZE 0x1303 +#define regGDS_VMID1_SIZE_BASE_IDX 0 +#define regGDS_VMID2_BASE 0x1304 +#define regGDS_VMID2_BASE_BASE_IDX 0 +#define regGDS_VMID2_SIZE 0x1305 +#define regGDS_VMID2_SIZE_BASE_IDX 0 +#define regGDS_VMID3_BASE 0x1306 +#define regGDS_VMID3_BASE_BASE_IDX 0 +#define regGDS_VMID3_SIZE 0x1307 +#define regGDS_VMID3_SIZE_BASE_IDX 0 +#define regGDS_VMID4_BASE 0x1308 +#define regGDS_VMID4_BASE_BASE_IDX 0 +#define regGDS_VMID4_SIZE 0x1309 +#define regGDS_VMID4_SIZE_BASE_IDX 0 +#define regGDS_VMID5_BASE 0x130a +#define regGDS_VMID5_BASE_BASE_IDX 0 +#define regGDS_VMID5_SIZE 0x130b +#define regGDS_VMID5_SIZE_BASE_IDX 0 +#define regGDS_VMID6_BASE 0x130c +#define regGDS_VMID6_BASE_BASE_IDX 0 +#define regGDS_VMID6_SIZE 0x130d +#define regGDS_VMID6_SIZE_BASE_IDX 0 +#define regGDS_VMID7_BASE 0x130e +#define regGDS_VMID7_BASE_BASE_IDX 0 +#define regGDS_VMID7_SIZE 0x130f +#define regGDS_VMID7_SIZE_BASE_IDX 0 +#define regGDS_VMID8_BASE 0x1310 +#define regGDS_VMID8_BASE_BASE_IDX 0 +#define regGDS_VMID8_SIZE 0x1311 +#define regGDS_VMID8_SIZE_BASE_IDX 0 +#define regGDS_VMID9_BASE 0x1312 +#define regGDS_VMID9_BASE_BASE_IDX 0 +#define regGDS_VMID9_SIZE 0x1313 +#define regGDS_VMID9_SIZE_BASE_IDX 0 +#define regGDS_VMID10_BASE 0x1314 +#define regGDS_VMID10_BASE_BASE_IDX 0 +#define regGDS_VMID10_SIZE 0x1315 +#define regGDS_VMID10_SIZE_BASE_IDX 0 +#define regGDS_VMID11_BASE 0x1316 +#define regGDS_VMID11_BASE_BASE_IDX 0 +#define regGDS_VMID11_SIZE 0x1317 +#define regGDS_VMID11_SIZE_BASE_IDX 0 +#define regGDS_VMID12_BASE 0x1318 +#define regGDS_VMID12_BASE_BASE_IDX 0 +#define regGDS_VMID12_SIZE 0x1319 +#define regGDS_VMID12_SIZE_BASE_IDX 0 +#define regGDS_VMID13_BASE 0x131a +#define regGDS_VMID13_BASE_BASE_IDX 0 +#define regGDS_VMID13_SIZE 0x131b +#define regGDS_VMID13_SIZE_BASE_IDX 0 +#define regGDS_VMID14_BASE 0x131c +#define regGDS_VMID14_BASE_BASE_IDX 0 +#define regGDS_VMID14_SIZE 0x131d +#define regGDS_VMID14_SIZE_BASE_IDX 0 +#define regGDS_VMID15_BASE 0x131e +#define regGDS_VMID15_BASE_BASE_IDX 0 +#define regGDS_VMID15_SIZE 0x131f +#define regGDS_VMID15_SIZE_BASE_IDX 0 +#define regGDS_GWS_VMID0 0x1320 +#define regGDS_GWS_VMID0_BASE_IDX 0 +#define regGDS_GWS_VMID1 0x1321 +#define regGDS_GWS_VMID1_BASE_IDX 0 +#define regGDS_GWS_VMID2 0x1322 +#define regGDS_GWS_VMID2_BASE_IDX 0 +#define regGDS_GWS_VMID3 0x1323 +#define regGDS_GWS_VMID3_BASE_IDX 0 +#define regGDS_GWS_VMID4 0x1324 +#define regGDS_GWS_VMID4_BASE_IDX 0 +#define regGDS_GWS_VMID5 0x1325 +#define regGDS_GWS_VMID5_BASE_IDX 0 +#define regGDS_GWS_VMID6 0x1326 +#define regGDS_GWS_VMID6_BASE_IDX 0 +#define regGDS_GWS_VMID7 0x1327 +#define regGDS_GWS_VMID7_BASE_IDX 0 +#define regGDS_GWS_VMID8 0x1328 +#define regGDS_GWS_VMID8_BASE_IDX 0 +#define regGDS_GWS_VMID9 0x1329 +#define regGDS_GWS_VMID9_BASE_IDX 0 +#define regGDS_GWS_VMID10 0x132a +#define regGDS_GWS_VMID10_BASE_IDX 0 +#define regGDS_GWS_VMID11 0x132b +#define regGDS_GWS_VMID11_BASE_IDX 0 +#define regGDS_GWS_VMID12 0x132c +#define regGDS_GWS_VMID12_BASE_IDX 0 +#define regGDS_GWS_VMID13 0x132d +#define regGDS_GWS_VMID13_BASE_IDX 0 +#define regGDS_GWS_VMID14 0x132e +#define regGDS_GWS_VMID14_BASE_IDX 0 +#define regGDS_GWS_VMID15 0x132f +#define regGDS_GWS_VMID15_BASE_IDX 0 +#define regGDS_OA_VMID0 0x1330 +#define regGDS_OA_VMID0_BASE_IDX 0 +#define regGDS_OA_VMID1 0x1331 +#define regGDS_OA_VMID1_BASE_IDX 0 +#define regGDS_OA_VMID2 0x1332 +#define regGDS_OA_VMID2_BASE_IDX 0 +#define regGDS_OA_VMID3 0x1333 +#define regGDS_OA_VMID3_BASE_IDX 0 +#define regGDS_OA_VMID4 0x1334 +#define regGDS_OA_VMID4_BASE_IDX 0 +#define regGDS_OA_VMID5 0x1335 +#define regGDS_OA_VMID5_BASE_IDX 0 +#define regGDS_OA_VMID6 0x1336 +#define regGDS_OA_VMID6_BASE_IDX 0 +#define regGDS_OA_VMID7 0x1337 +#define regGDS_OA_VMID7_BASE_IDX 0 +#define regGDS_OA_VMID8 0x1338 +#define regGDS_OA_VMID8_BASE_IDX 0 +#define regGDS_OA_VMID9 0x1339 +#define regGDS_OA_VMID9_BASE_IDX 0 +#define regGDS_OA_VMID10 0x133a +#define regGDS_OA_VMID10_BASE_IDX 0 +#define regGDS_OA_VMID11 0x133b +#define regGDS_OA_VMID11_BASE_IDX 0 +#define regGDS_OA_VMID12 0x133c +#define regGDS_OA_VMID12_BASE_IDX 0 +#define regGDS_OA_VMID13 0x133d +#define regGDS_OA_VMID13_BASE_IDX 0 +#define regGDS_OA_VMID14 0x133e +#define regGDS_OA_VMID14_BASE_IDX 0 +#define regGDS_OA_VMID15 0x133f +#define regGDS_OA_VMID15_BASE_IDX 0 +#define regGDS_GWS_RESET0 0x1344 +#define regGDS_GWS_RESET0_BASE_IDX 0 +#define regGDS_GWS_RESET1 0x1345 +#define regGDS_GWS_RESET1_BASE_IDX 0 +#define regGDS_GWS_RESOURCE_RESET 0x1346 +#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x1348 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 +#define regGDS_OA_RESET_MASK 0x1349 +#define regGDS_OA_RESET_MASK_BASE_IDX 0 +#define regGDS_OA_RESET 0x134a +#define regGDS_OA_RESET_BASE_IDX 0 +#define regGDS_ENHANCE 0x134b +#define regGDS_ENHANCE_BASE_IDX 0 +#define regGDS_OA_CGPG_RESTORE 0x134c +#define regGDS_OA_CGPG_RESTORE_BASE_IDX 0 +#define regGDS_CS_CTXSW_STATUS 0x134d +#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT0 0x134e +#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT1 0x134f +#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT2 0x1350 +#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT3 0x1351 +#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GFX_CTXSW_STATUS 0x1352 +#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT0 0x1353 +#define regGDS_VS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT1 0x1354 +#define regGDS_VS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT2 0x1355 +#define regGDS_VS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT3 0x1356 +#define regGDS_VS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT0 0x1357 +#define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT1 0x1358 +#define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT2 0x1359 +#define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT3 0x135a +#define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT0 0x135b +#define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT1 0x135c +#define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT2 0x135d +#define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT3 0x135e +#define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT0 0x135f +#define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT1 0x1360 +#define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT2 0x1361 +#define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT3 0x1362 +#define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT0 0x1363 +#define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT1 0x1364 +#define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT2 0x1365 +#define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT3 0x1366 +#define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT0 0x1367 +#define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT1 0x1368 +#define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT2 0x1369 +#define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT3 0x136a +#define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT0 0x136b +#define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT1 0x136c +#define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT2 0x136d +#define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT3 0x136e +#define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT0 0x136f +#define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT1 0x1370 +#define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT2 0x1371 +#define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT3 0x1372 +#define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT0 0x1373 +#define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT1 0x1374 +#define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT2 0x1375 +#define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT3 0x1376 +#define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT0 0x1377 +#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT1 0x1378 +#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT2 0x1379 +#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT3 0x137a +#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 + + +// addressBlock: gc_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0001 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0002 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE 0x0005 +#define regDB_HTILE_DATA_BASE_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE_HI 0x0006 +#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 +#define regDB_DEPTH_SIZE 0x0007 +#define regDB_DEPTH_SIZE_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0008 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0009 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_STENCIL_CLEAR 0x000a +#define regDB_STENCIL_CLEAR_BASE_IDX 1 +#define regDB_DEPTH_CLEAR 0x000b +#define regDB_DEPTH_CLEAR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x000c +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x000d +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regDB_Z_INFO 0x000e +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x000f +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0010 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x0011 +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x0012 +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x0013 +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x0014 +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x0015 +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x0016 +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x0017 +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_DFSM_CONTROL 0x0018 +#define regDB_DFSM_CONTROL_BASE_IDX 1 +#define regDB_Z_INFO2 0x001a +#define regDB_Z_INFO2_BASE_IDX 1 +#define regDB_STENCIL_INFO2 0x001b +#define regDB_STENCIL_INFO2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regCB_TARGET_MASK 0x008e +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x008f +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x00b4 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x00b5 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x00b6 +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x00b7 +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x00b8 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x00b9 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x00ba +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x00bb +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x00bc +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x00bd +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x00be +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x00bf +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x00c0 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x00c1 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x00c2 +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x00c3 +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x00c4 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x00c5 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x00c6 +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x00c7 +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x00c8 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x00c9 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x00ca +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x00cb +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x00cc +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x00cd +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x00ce +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x00cf +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x00d0 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x00d1 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x00d2 +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x00d3 +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regPA_SC_RIGHT_VERT_GRID 0x00e8 +#define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 +#define regPA_SC_LEFT_VERT_GRID 0x00e9 +#define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1 +#define regPA_SC_HORIZ_GRID 0x00ea +#define regPA_SC_HORIZ_GRID_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regCB_DCC_CONTROL 0x0109 +#define regCB_DCC_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x010b +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_STENCILREFMASK 0x010c +#define regDB_STENCILREFMASK_BASE_IDX 1 +#define regDB_STENCILREFMASK_BF 0x010d +#define regDB_STENCILREFMASK_BF_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0115 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0116 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0117 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x0118 +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x0119 +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011a +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011b +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x011c +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x011d +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x011e +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x011f +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0120 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0121 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0122 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0123 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x0124 +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x0125 +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x0126 +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x0127 +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0128 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0129 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x012a +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x012b +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x012c +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x012d +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x012e +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x012f +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x0130 +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x0131 +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x0132 +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x0133 +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0134 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0135 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0136 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0137 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0138 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0139 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x013a +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x013b +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x013c +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x013d +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x013e +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x013f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0140 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0141 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0142 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0143 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0144 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0145 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0146 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0147 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x0148 +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x0149 +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x014a +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x014b +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x014c +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x014d +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x014e +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x014f +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0150 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0151 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0152 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0153 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x0154 +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x0155 +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x0156 +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x0157 +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0158 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0159 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x015a +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x015b +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x015c +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x015d +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x015e +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x015f +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x0160 +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x0161 +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x0162 +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x0163 +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0164 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0165 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0166 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0167 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0168 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0169 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x016a +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x016b +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x016c +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x016d +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x016e +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x016f +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x0170 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x0171 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x0172 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x0173 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x0174 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x0175 +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x0176 +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x0177 +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x0178 +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x0179 +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x017a +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x017b +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x017c +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x017d +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x017e +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x017f +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x0180 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x0181 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x0182 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x0183 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x0184 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x0185 +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x0186 +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0191 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x0192 +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x0193 +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x0194 +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x0195 +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x0196 +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x0197 +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x0198 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x0199 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x019a +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x019b +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x019c +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x019d +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x019e +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x019f +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a0 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a1 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01a2 +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01a3 +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01a4 +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01a5 +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01a6 +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01a7 +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01a8 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01a9 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01aa +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01ab +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01ac +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01ad +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01ae +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01af +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b0 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_VS_OUT_CONFIG 0x01b1 +#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x01b3 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x01b4 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x01b5 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x01b6 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x01b8 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x01c3 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x01c4 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x01c5 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT 0x01d5 +#define regSX_PS_DOWNCONVERT_BASE_IDX 1 +#define regSX_BLEND_OPT_EPSILON 0x01d6 +#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define regSX_BLEND_OPT_CONTROL 0x01d7 +#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define regSX_MRT0_BLEND_OPT 0x01d8 +#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT1_BLEND_OPT 0x01d9 +#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT2_BLEND_OPT 0x01da +#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT3_BLEND_OPT 0x01db +#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT4_BLEND_OPT 0x01dc +#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT5_BLEND_OPT 0x01dd +#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT6_BLEND_OPT 0x01de +#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT7_BLEND_OPT 0x01df +#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regCB_MRT0_EPITCH 0x01e8 +#define regCB_MRT0_EPITCH_BASE_IDX 1 +#define regCB_MRT1_EPITCH 0x01e9 +#define regCB_MRT1_EPITCH_BASE_IDX 1 +#define regCB_MRT2_EPITCH 0x01ea +#define regCB_MRT2_EPITCH_BASE_IDX 1 +#define regCB_MRT3_EPITCH 0x01eb +#define regCB_MRT3_EPITCH_BASE_IDX 1 +#define regCB_MRT4_EPITCH 0x01ec +#define regCB_MRT4_EPITCH_BASE_IDX 1 +#define regCB_MRT5_EPITCH 0x01ed +#define regCB_MRT5_EPITCH_BASE_IDX 1 +#define regCB_MRT6_EPITCH 0x01ee +#define regCB_MRT6_EPITCH_BASE_IDX 1 +#define regCB_MRT7_EPITCH 0x01ef +#define regCB_MRT7_EPITCH_BASE_IDX 1 +#define regCS_COPY_STATE 0x01f3 +#define regCS_COPY_STATE_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_IMMED_DATA 0x01fd +#define regVGT_IMMED_DATA_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x0200 +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x0201 +#define regDB_EQAA_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0202 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x0203 +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0205 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0206 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0207 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_OBJPRIM_ID_CNTL 0x020d +#define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regVGT_OUTPUT_PATH_CNTL 0x0284 +#define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 +#define regVGT_HOS_CNTL 0x0285 +#define regVGT_HOS_CNTL_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_REUSE_DEPTH 0x0288 +#define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1 +#define regVGT_GROUP_PRIM_TYPE 0x0289 +#define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1 +#define regVGT_GROUP_FIRST_DECR 0x028a +#define regVGT_GROUP_FIRST_DECR_BASE_IDX 1 +#define regVGT_GROUP_DECR 0x028b +#define regVGT_GROUP_DECR_BASE_IDX 1 +#define regVGT_GROUP_VECT_0_CNTL 0x028c +#define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_1_CNTL 0x028d +#define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_0_FMT_CNTL 0x028e +#define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_1_FMT_CNTL 0x028f +#define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 +#define regVGT_GS_MODE 0x0290 +#define regVGT_GS_MODE_BASE_IDX 1 +#define regVGT_GS_ONCHIP_CNTL 0x0291 +#define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regVGT_ENHANCE 0x0294 +#define regVGT_ENHANCE_BASE_IDX 1 +#define regVGT_GS_PER_ES 0x0295 +#define regVGT_GS_PER_ES_BASE_IDX 1 +#define regVGT_ES_PER_GS 0x0296 +#define regVGT_ES_PER_GS_BASE_IDX 1 +#define regVGT_GS_PER_VS 0x0297 +#define regVGT_GS_PER_VS_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_1 0x0298 +#define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_2 0x0299 +#define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_3 0x029a +#define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x029b +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regIA_ENHANCE 0x029c +#define regIA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regWD_ENHANCE 0x02a0 +#define regWD_ENHANCE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x02a1 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x02a3 +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 +#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regVGT_INSTANCE_STEP_RATE_0 0x02a8 +#define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 +#define regVGT_INSTANCE_STEP_RATE_1 0x02a9 +#define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 +#define regIA_MULTI_VGT_PARAM_BC 0x02aa +#define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 +#define regVGT_ESGS_RING_ITEMSIZE 0x02ab +#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_GSVS_RING_ITEMSIZE 0x02ac +#define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02ad +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regVGT_VTX_CNT_EN 0x02ae +#define regVGT_VTX_CNT_EN_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regDB_PRELOAD_CONTROL 0x02b2 +#define regDB_PRELOAD_CONTROL_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 +#define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_0 0x02b5 +#define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 +#define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 +#define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_1 0x02b9 +#define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb +#define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_2 0x02bc +#define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_2 0x02bd +#define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf +#define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 +#define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_3 0x02c1 +#define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 +#define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02d5 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE 0x02d7 +#define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_1 0x02d8 +#define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_2 0x02d9 +#define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_3 0x02da +#define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02db +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x02dc +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regVGT_DISPATCH_DRAW_INDEX 0x02dd +#define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02e4 +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regVGT_STRMOUT_CONFIG 0x02e5 +#define regVGT_STRMOUT_CONFIG_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_CONFIG 0x02e6 +#define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 +#define regVGT_DMA_EVENT_INITIATOR 0x02e7 +#define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0310 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 +#define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 +#define regVGT_OUT_DEALLOC_CNTL 0x0317 +#define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0319 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x031a +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x031b +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x031c +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031d +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_DCC_CONTROL 0x031e +#define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_CMASK 0x031f +#define regCB_COLOR0_CMASK_BASE_IDX 1 +#define regCB_COLOR0_CMASK_BASE_EXT 0x0320 +#define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_FMASK 0x0321 +#define regCB_COLOR0_FMASK_BASE_IDX 1 +#define regCB_COLOR0_FMASK_BASE_EXT 0x0322 +#define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_CLEAR_WORD0 0x0323 +#define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR0_CLEAR_WORD1 0x0324 +#define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE 0x0325 +#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE_EXT 0x0326 +#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0327 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0328 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x0329 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x032a +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x032b +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x032c +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_DCC_CONTROL 0x032d +#define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_CMASK 0x032e +#define regCB_COLOR1_CMASK_BASE_IDX 1 +#define regCB_COLOR1_CMASK_BASE_EXT 0x032f +#define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_FMASK 0x0330 +#define regCB_COLOR1_FMASK_BASE_IDX 1 +#define regCB_COLOR1_FMASK_BASE_EXT 0x0331 +#define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_CLEAR_WORD0 0x0332 +#define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR1_CLEAR_WORD1 0x0333 +#define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE 0x0334 +#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE_EXT 0x0335 +#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x0336 +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0337 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x0338 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x0339 +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x033a +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x033b +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_DCC_CONTROL 0x033c +#define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_CMASK 0x033d +#define regCB_COLOR2_CMASK_BASE_IDX 1 +#define regCB_COLOR2_CMASK_BASE_EXT 0x033e +#define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_FMASK 0x033f +#define regCB_COLOR2_FMASK_BASE_IDX 1 +#define regCB_COLOR2_FMASK_BASE_EXT 0x0340 +#define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_CLEAR_WORD0 0x0341 +#define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR2_CLEAR_WORD1 0x0342 +#define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE 0x0343 +#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE_EXT 0x0344 +#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0345 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0346 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x0347 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0348 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x0349 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x034a +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_DCC_CONTROL 0x034b +#define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_CMASK 0x034c +#define regCB_COLOR3_CMASK_BASE_IDX 1 +#define regCB_COLOR3_CMASK_BASE_EXT 0x034d +#define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_FMASK 0x034e +#define regCB_COLOR3_FMASK_BASE_IDX 1 +#define regCB_COLOR3_FMASK_BASE_EXT 0x034f +#define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_CLEAR_WORD0 0x0350 +#define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR3_CLEAR_WORD1 0x0351 +#define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE 0x0352 +#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE_EXT 0x0353 +#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x0354 +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0355 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x0356 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x0357 +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x0358 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x0359 +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_DCC_CONTROL 0x035a +#define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_CMASK 0x035b +#define regCB_COLOR4_CMASK_BASE_IDX 1 +#define regCB_COLOR4_CMASK_BASE_EXT 0x035c +#define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_FMASK 0x035d +#define regCB_COLOR4_FMASK_BASE_IDX 1 +#define regCB_COLOR4_FMASK_BASE_EXT 0x035e +#define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_CLEAR_WORD0 0x035f +#define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR4_CLEAR_WORD1 0x0360 +#define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE 0x0361 +#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE_EXT 0x0362 +#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0363 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0364 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x0365 +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0366 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x0367 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0368 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_DCC_CONTROL 0x0369 +#define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_CMASK 0x036a +#define regCB_COLOR5_CMASK_BASE_IDX 1 +#define regCB_COLOR5_CMASK_BASE_EXT 0x036b +#define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_FMASK 0x036c +#define regCB_COLOR5_FMASK_BASE_IDX 1 +#define regCB_COLOR5_FMASK_BASE_EXT 0x036d +#define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_CLEAR_WORD0 0x036e +#define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR5_CLEAR_WORD1 0x036f +#define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE 0x0370 +#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE_EXT 0x0371 +#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x0372 +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0373 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x0374 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x0375 +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x0376 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0377 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_DCC_CONTROL 0x0378 +#define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_CMASK 0x0379 +#define regCB_COLOR6_CMASK_BASE_IDX 1 +#define regCB_COLOR6_CMASK_BASE_EXT 0x037a +#define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_FMASK 0x037b +#define regCB_COLOR6_FMASK_BASE_IDX 1 +#define regCB_COLOR6_FMASK_BASE_EXT 0x037c +#define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_CLEAR_WORD0 0x037d +#define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR6_CLEAR_WORD1 0x037e +#define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE 0x037f +#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE_EXT 0x0380 +#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0381 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0382 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x0383 +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0384 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x0385 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x0386 +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_DCC_CONTROL 0x0387 +#define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_CMASK 0x0388 +#define regCB_COLOR7_CMASK_BASE_IDX 1 +#define regCB_COLOR7_CMASK_BASE_EXT 0x0389 +#define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_FMASK 0x038a +#define regCB_COLOR7_FMASK_BASE_IDX 1 +#define regCB_COLOR7_FMASK_BASE_EXT 0x038b +#define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_CLEAR_WORD0 0x038c +#define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR7_CLEAR_WORD1 0x038d +#define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE 0x038e +#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE_EXT 0x038f +#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 + + +// addressBlock: gc_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_STREAM_OUT_ADDR_LO 0x2006 +#define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 +#define regCP_STREAM_OUT_ADDR_HI 0x2007 +#define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a +#define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b +#define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c +#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d +#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e +#define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f +#define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 +#define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 +#define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 +#define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 +#define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regCP_STREAM_OUT_CONTROL 0x203e +#define regCP_STREAM_OUT_CONTROL_BASE_IDX 1 +#define regCP_STRMOUT_CNTL 0x203f +#define regCP_STRMOUT_CNTL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regSCRATCH_UMSK 0x2050 +#define regSCRATCH_UMSK_BASE_IDX 1 +#define regSCRATCH_ADDR 0x2051 +#define regSCRATCH_ADDR_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_SEM_WAIT_TIMER 0x206f +#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_LO 0x2070 +#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_HI 0x2071 +#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_LO 0x2075 +#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_HI 0x2076 +#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_COHER_BASE_HI 0x2079 +#define regCP_COHER_BASE_HI_BASE_IDX 1 +#define regCP_COHER_START_DELAY 0x207b +#define regCP_COHER_START_DELAY_BASE_IDX 1 +#define regCP_COHER_CNTL 0x207c +#define regCP_COHER_CNTL_BASE_IDX 1 +#define regCP_COHER_SIZE 0x207d +#define regCP_COHER_SIZE_BASE_IDX 1 +#define regCP_COHER_BASE 0x207e +#define regCP_COHER_BASE_BASE_IDX 1 +#define regCP_COHER_STATUS 0x207f +#define regCP_COHER_STATUS_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_COHER_SIZE_HI 0x208c +#define regCP_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_CE_IB1_OFFSET 0x2098 +#define regCP_CE_IB1_OFFSET_BASE_IDX 1 +#define regCP_CE_IB2_OFFSET 0x2099 +#define regCP_CE_IB2_OFFSET_BASE_IDX 1 +#define regCP_CE_COUNTER 0x209a +#define regCP_CE_COUNTER_BASE_IDX 1 +#define regCP_CE_RB_OFFSET 0x209b +#define regCP_CE_RB_OFFSET_BASE_IDX 1 +#define regCP_CE_INIT_CMD_BUFSZ 0x20bd +#define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB1_CMD_BUFSZ 0x20be +#define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB2_CMD_BUFSZ 0x20bf +#define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_INIT_BASE_LO 0x20c3 +#define regCP_CE_INIT_BASE_LO_BASE_IDX 1 +#define regCP_CE_INIT_BASE_HI 0x20c4 +#define regCP_CE_INIT_BASE_HI_BASE_IDX 1 +#define regCP_CE_INIT_BUFSZ 0x20c5 +#define regCP_CE_INIT_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB1_BASE_LO 0x20c6 +#define regCP_CE_IB1_BASE_LO_BASE_IDX 1 +#define regCP_CE_IB1_BASE_HI 0x20c7 +#define regCP_CE_IB1_BASE_HI_BASE_IDX 1 +#define regCP_CE_IB1_BUFSZ 0x20c8 +#define regCP_CE_IB1_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB2_BASE_LO 0x20c9 +#define regCP_CE_IB2_BASE_LO_BASE_IDX 1 +#define regCP_CE_IB2_BASE_HI 0x20ca +#define regCP_CE_IB2_BASE_HI_BASE_IDX 1 +#define regCP_CE_IB2_BUFSZ 0x20cb +#define regCP_CE_IB2_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_CE_COMPLETION_STATUS 0x20ed +#define regCP_CE_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_CE_METADATA_BASE_ADDR 0x20f2 +#define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_CE_METADATA_BASE_ADDR_HI 0x20f3 +#define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR 0x20fb +#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR_HI 0x20fc +#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regVGT_GSVS_RING_SIZE 0x2241 +#define regVGT_GSVS_RING_SIZE_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 +#define regVGT_MAX_VTX_INDX 0x2248 +#define regVGT_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_MIN_VTX_INDX 0x2249 +#define regVGT_MIN_VTX_INDX_BASE_IDX 1 +#define regVGT_INDX_OFFSET 0x224a +#define regVGT_INDX_OFFSET_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_EN 0x224b +#define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2251 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regWD_POS_BUF_BASE 0x2252 +#define regWD_POS_BUF_BASE_BASE_IDX 1 +#define regWD_POS_BUF_BASE_HI 0x2253 +#define regWD_POS_BUF_BASE_HI_BASE_IDX 1 +#define regWD_CNTL_SB_BUF_BASE 0x2254 +#define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1 +#define regWD_CNTL_SB_BUF_BASE_HI 0x2255 +#define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 +#define regWD_INDEX_BUF_BASE 0x2256 +#define regWD_INDEX_BUF_BASE_BASE_IDX 1 +#define regWD_INDEX_BUF_BASE_HI 0x2257 +#define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1 +#define regIA_MULTI_VGT_PARAM 0x2258 +#define regIA_MULTI_VGT_PARAM_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x22b5 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BASE 0x2330 +#define regSQ_THREAD_TRACE_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_SIZE 0x2331 +#define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x2332 +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x2333 +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_PERF_MASK 0x2334 +#define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x2335 +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MODE 0x2336 +#define regSQ_THREAD_TRACE_MODE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BASE2 0x2337 +#define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 +#define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x2339 +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x233a +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HIWATER 0x233b +#define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CNTR 0x233c +#define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regSQC_WRITEBACK 0x2349 +#define regSQC_WRITEBACK_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regDB_ZPASS_COUNT_LOW 0x23fe +#define regDB_ZPASS_COUNT_LOW_BASE_IDX 1 +#define regDB_ZPASS_COUNT_HI 0x23ff +#define regDB_ZPASS_COUNT_HI_BASE_IDX 1 +#define regGDS_RD_ADDR 0x2400 +#define regGDS_RD_ADDR_BASE_IDX 1 +#define regGDS_RD_DATA 0x2401 +#define regGDS_RD_DATA_BASE_IDX 1 +#define regGDS_RD_BURST_ADDR 0x2402 +#define regGDS_RD_BURST_ADDR_BASE_IDX 1 +#define regGDS_RD_BURST_COUNT 0x2403 +#define regGDS_RD_BURST_COUNT_BASE_IDX 1 +#define regGDS_RD_BURST_DATA 0x2404 +#define regGDS_RD_BURST_DATA_BASE_IDX 1 +#define regGDS_WR_ADDR 0x2405 +#define regGDS_WR_ADDR_BASE_IDX 1 +#define regGDS_WR_DATA 0x2406 +#define regGDS_WR_DATA_BASE_IDX 1 +#define regGDS_WR_BURST_ADDR 0x2407 +#define regGDS_WR_BURST_ADDR_BASE_IDX 1 +#define regGDS_WR_BURST_DATA 0x2408 +#define regGDS_WR_BURST_DATA_BASE_IDX 1 +#define regGDS_WRITE_COMPLETE 0x2409 +#define regGDS_WRITE_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_CNTL 0x240a +#define regGDS_ATOM_CNTL_BASE_IDX 1 +#define regGDS_ATOM_COMPLETE 0x240b +#define regGDS_ATOM_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_BASE 0x240c +#define regGDS_ATOM_BASE_BASE_IDX 1 +#define regGDS_ATOM_SIZE 0x240d +#define regGDS_ATOM_SIZE_BASE_IDX 1 +#define regGDS_ATOM_OFFSET0 0x240e +#define regGDS_ATOM_OFFSET0_BASE_IDX 1 +#define regGDS_ATOM_OFFSET1 0x240f +#define regGDS_ATOM_OFFSET1_BASE_IDX 1 +#define regGDS_ATOM_DST 0x2410 +#define regGDS_ATOM_DST_BASE_IDX 1 +#define regGDS_ATOM_OP 0x2411 +#define regGDS_ATOM_OP_BASE_IDX 1 +#define regGDS_ATOM_SRC0 0x2412 +#define regGDS_ATOM_SRC0_BASE_IDX 1 +#define regGDS_ATOM_SRC0_U 0x2413 +#define regGDS_ATOM_SRC0_U_BASE_IDX 1 +#define regGDS_ATOM_SRC1 0x2414 +#define regGDS_ATOM_SRC1_BASE_IDX 1 +#define regGDS_ATOM_SRC1_U 0x2415 +#define regGDS_ATOM_SRC1_U_BASE_IDX 1 +#define regGDS_ATOM_READ0 0x2416 +#define regGDS_ATOM_READ0_BASE_IDX 1 +#define regGDS_ATOM_READ0_U 0x2417 +#define regGDS_ATOM_READ0_U_BASE_IDX 1 +#define regGDS_ATOM_READ1 0x2418 +#define regGDS_ATOM_READ1_BASE_IDX 1 +#define regGDS_ATOM_READ1_U 0x2419 +#define regGDS_ATOM_READ1_U_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNTL 0x241a +#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 +#define regGDS_GWS_RESOURCE 0x241b +#define regGDS_GWS_RESOURCE_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNT 0x241c +#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 +#define regGDS_OA_CNTL 0x241d +#define regGDS_OA_CNTL_BASE_IDX 1 +#define regGDS_OA_COUNTER 0x241e +#define regGDS_OA_COUNTER_BASE_IDX 1 +#define regGDS_OA_ADDRESS 0x241f +#define regGDS_OA_ADDRESS_BASE_IDX 1 +#define regGDS_OA_INCDEC 0x2420 +#define regGDS_OA_INCDEC_BASE_IDX 1 +#define regGDS_OA_RING_SIZE 0x2421 +#define regGDS_OA_RING_SIZE_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_WAVE_LIMIT_CNTL 0x2443 +#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0000 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0001 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0002 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0003 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0004 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0005 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0006 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0008 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x000c +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x000d +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_STATUS_SE2 0x000e +#define regGRBM_STATUS_SE2_BASE_IDX 0 +#define regGRBM_STATUS_SE3 0x000f +#define regGRBM_STATUS_SE3_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0016 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0017 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0018 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0019 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x001a +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x001b +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x001c +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x001d +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x001f +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0021 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_GFX_CNTL 0x0022 +#define regGRBM_GFX_CNTL_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0024 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0025 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS 0x0029 +#define regGRBM_CHICKEN_BITS_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x002a +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x002b +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_NOWHERE 0x003f +#define regGRBM_NOWHERE_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0040 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0041 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0042 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0043 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0044 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0045 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0046 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0047 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 + + +// addressBlock: gc_hypdec +// base address: 0x3e000 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_CE_UCODE_ADDR 0x5818 +#define regCP_CE_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_CE_UCODE_ADDR 0x5818 +#define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 +#define regCP_CE_UCODE_DATA 0x5819 +#define regCP_CE_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_CE_UCODE_DATA 0x5819 +#define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_ADDR 0x581c +#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_ADDR 0x581c +#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_DATA 0x581d +#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_DATA 0x581d +#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x583c +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x583d +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5a04 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_HYP_CAM_INDEX 0x5a04 +#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5a05 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA 0x5a05 +#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_0 0x5b25 +#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 +#define regRLC_RLCV_TIMER_CTRL 0x5b26 +#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 +#define regRLC_RLCV_TIMER_STAT 0x5b27 +#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_STAT 0x5b3f +#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_1 0x5b40 +#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_ADDR 0x5b42 +#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_DATA 0x5b43 +#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 +#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b45 +#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_CNTL 0x5b46 +#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_RESET 0x5b47 +#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5b48 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5b49 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c +#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e +#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_FORCE 0x5b4f +#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5b54 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5b55 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5b56 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5b57 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5b58 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5b59 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5b5a +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5b5b +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5b5c +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5b5d +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5b5e +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5b5f +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: gc_padec +// base address: 0x8800 +#define regVGT_VTX_VECT_EJECT_REG 0x022c +#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x022d +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x022e +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_LAST_COPY_STATE 0x0230 +#define regVGT_LAST_COPY_STATE_BASE_IDX 0 +#define regVGT_CACHE_INVALIDATION 0x0231 +#define regVGT_CACHE_INVALIDATION_BASE_IDX 0 +#define regVGT_STRMOUT_DELAY 0x0233 +#define regVGT_STRMOUT_DELAY_BASE_IDX 0 +#define regVGT_FIFO_DEPTHS 0x0234 +#define regVGT_FIFO_DEPTHS_BASE_IDX 0 +#define regVGT_GS_VERTEX_REUSE 0x0235 +#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0236 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_CNTL_STATUS 0x0237 +#define regIA_CNTL_STATUS_BASE_IDX 0 +#define regVGT_CNTL_STATUS 0x023c +#define regVGT_CNTL_STATUS_BASE_IDX 0 +#define regWD_CNTL_STATUS 0x023f +#define regWD_CNTL_STATUS_BASE_IDX 0 +#define regCC_GC_PRIM_CONFIG 0x0240 +#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 +#define regGC_USER_PRIM_CONFIG 0x0241 +#define regGC_USER_PRIM_CONFIG_BASE_IDX 0 +#define regWD_QOS 0x0242 +#define regWD_QOS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0243 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0244 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0246 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0247 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regVGT_SYS_CONFIG 0x0263 +#define regVGT_SYS_CONFIG_BASE_IDX 0 +#define regVGT_VS_MAX_WAVE_ID 0x0268 +#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x0269 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x026d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x026f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x0270 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regVGT_DMA_PRIMITIVE_TYPE 0x0271 +#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 +#define regVGT_DMA_CONTROL 0x0272 +#define regVGT_DMA_CONTROL_BASE_IDX 0 +#define regVGT_DMA_LS_HS_CONFIG 0x0273 +#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 +#define regWD_BUF_RESOURCE_1 0x0276 +#define regWD_BUF_RESOURCE_1_BASE_IDX 0 +#define regWD_BUF_RESOURCE_2 0x0277 +#define regWD_BUF_RESOURCE_2_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x0284 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x0285 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x0294 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x0295 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_0 0x02d1 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_1 0x02d2 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_2 0x02d3 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_3 0x02d4 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 +#define regPA_SC_ENHANCE_2 0x02dc +#define regPA_SC_ENHANCE_2_BASE_IDX 0 +#define regPA_SC_FIFO_SIZE 0x02f3 +#define regPA_SC_FIFO_SIZE_BASE_IDX 0 +#define regPA_SC_IF_FIFO_SIZE 0x02f5 +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 +#define regPA_UTCL1_CNTL1 0x02f9 +#define regPA_UTCL1_CNTL1_BASE_IDX 0 +#define regPA_UTCL1_CNTL2 0x02fa +#define regPA_UTCL1_CNTL2_BASE_IDX 0 +#define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb +#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 +#define regPA_SC_ENHANCE 0x02fc +#define regPA_SC_ENHANCE_BASE_IDX 0 +#define regPA_SC_ENHANCE_1 0x02fd +#define regPA_SC_ENHANCE_1_BASE_IDX 0 +#define regPA_SC_DSM_CNTL 0x02fe +#define regPA_SC_DSM_CNTL_BASE_IDX 0 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 + + +// addressBlock: gc_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 +#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 +#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 +#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 +#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 +#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_HI 0x304a +#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_LO 0x304b +#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_HI 0x304c +#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER0_LO 0x3080 +#define regWD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER0_HI 0x3081 +#define regWD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER1_LO 0x3082 +#define regWD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER1_HI 0x3083 +#define regWD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER2_LO 0x3084 +#define regWD_PERFCOUNTER2_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER2_HI 0x3085 +#define regWD_PERFCOUNTER2_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER3_LO 0x3086 +#define regWD_PERFCOUNTER3_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER3_HI 0x3087 +#define regWD_PERFCOUNTER3_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER0_LO 0x3088 +#define regIA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER0_HI 0x3089 +#define regIA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER1_LO 0x308a +#define regIA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER1_HI 0x308b +#define regIA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER2_LO 0x308c +#define regIA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER2_HI 0x308d +#define regIA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER3_LO 0x308e +#define regIA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER3_HI 0x308f +#define regIA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_LO 0x3090 +#define regVGT_PERFCOUNTER0_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_HI 0x3091 +#define regVGT_PERFCOUNTER0_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_LO 0x3092 +#define regVGT_PERFCOUNTER1_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_HI 0x3093 +#define regVGT_PERFCOUNTER1_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_LO 0x3094 +#define regVGT_PERFCOUNTER2_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_HI 0x3095 +#define regVGT_PERFCOUNTER2_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_LO 0x3096 +#define regVGT_PERFCOUNTER3_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_HI 0x3097 +#define regVGT_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_HI 0x31c1 +#define regSQ_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_HI 0x31c3 +#define regSQ_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_HI 0x31c5 +#define regSQ_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_HI 0x31c7 +#define regSQ_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_HI 0x31c9 +#define regSQ_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_HI 0x31cb +#define regSQ_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_HI 0x31cd +#define regSQ_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_HI 0x31cf +#define regSQ_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_LO 0x31d0 +#define regSQ_PERFCOUNTER8_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_HI 0x31d1 +#define regSQ_PERFCOUNTER8_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_LO 0x31d2 +#define regSQ_PERFCOUNTER9_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_HI 0x31d3 +#define regSQ_PERFCOUNTER9_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_LO 0x31d4 +#define regSQ_PERFCOUNTER10_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_HI 0x31d5 +#define regSQ_PERFCOUNTER10_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_LO 0x31d6 +#define regSQ_PERFCOUNTER11_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_HI 0x31d7 +#define regSQ_PERFCOUNTER11_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_LO 0x31d8 +#define regSQ_PERFCOUNTER12_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_HI 0x31d9 +#define regSQ_PERFCOUNTER12_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_LO 0x31da +#define regSQ_PERFCOUNTER13_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_HI 0x31db +#define regSQ_PERFCOUNTER13_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_LO 0x31dc +#define regSQ_PERFCOUNTER14_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_HI 0x31dd +#define regSQ_PERFCOUNTER14_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_LO 0x31de +#define regSQ_PERFCOUNTER15_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_HI 0x31df +#define regSQ_PERFCOUNTER15_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_LO 0x3280 +#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_HI 0x3281 +#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_LO 0x3282 +#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_HI 0x3283 +#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_LO 0x3284 +#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_HI 0x3285 +#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_LO 0x3286 +#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_HI 0x3287 +#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_LO 0x3380 +#define regTCC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_HI 0x3381 +#define regTCC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_LO 0x3382 +#define regTCC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_HI 0x3383 +#define regTCC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_LO 0x3384 +#define regTCC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_HI 0x3385 +#define regTCC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_LO 0x3386 +#define regTCC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_HI 0x3387 +#define regTCC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_LO 0x3390 +#define regTCA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_HI 0x3391 +#define regTCA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_LO 0x3392 +#define regTCA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_HI 0x3393 +#define regTCA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_LO 0x3394 +#define regTCA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_HI 0x3395 +#define regTCA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_LO 0x3396 +#define regTCA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_HI 0x3397 +#define regTCA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: gc_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 +#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 +#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 +#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 +#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER0_SELECT 0x3880 +#define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER1_SELECT 0x3881 +#define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER2_SELECT 0x3882 +#define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER3_SELECT 0x3883 +#define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER0_SELECT 0x3884 +#define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER1_SELECT 0x3885 +#define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER2_SELECT 0x3886 +#define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER3_SELECT 0x3887 +#define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER0_SELECT1 0x3888 +#define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_SELECT 0x388c +#define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_SELECT 0x388d +#define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_SELECT 0x388e +#define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_SELECT 0x388f +#define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_SELECT1 0x3890 +#define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_SELECT1 0x3891 +#define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER_SEID_MASK 0x3894 +#define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3905 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3984 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3985 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3986 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3987 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3988 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3989 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398a +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_MASK 0x39e1 +#define regSQ_PERFCOUNTER_MASK_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT 0x3a80 +#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT 0x3a81 +#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT 0x3a82 +#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT 0x3a83 +#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 +#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b45 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_SELECT 0x3b80 +#define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_SELECT1 0x3b81 +#define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_SELECT 0x3b82 +#define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_SELECT1 0x3b83 +#define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_SELECT 0x3b84 +#define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_SELECT 0x3b85 +#define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_SELECT 0x3b90 +#define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_SELECT1 0x3b91 +#define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_SELECT 0x3b92 +#define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_SELECT1 0x3b93 +#define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_SELECT 0x3b94 +#define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_SELECT 0x3b95 +#define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c85 +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c86 +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 +#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 +#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 +#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a +#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b +#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c +#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d +#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e +#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 +#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 +#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 +#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 +#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 +#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 +#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 +#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 +#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 +#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a +#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c9d +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c9e +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 +#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 +#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 0x3caf +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1_BASE_IDX 1 +#define regRLC_PERFMON_CLK_CNTL_UCODE 0x3cbe +#define regRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 +#define regRLC_PERFMON_CLK_CNTL 0x3cbf +#define regRLC_PERFMON_CLK_CNTL_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 + + +// addressBlock: gc_pwrdec +// base address: 0x3c000 +#define regCGTS_SM_CTRL_REG 0x5000 +#define regCGTS_SM_CTRL_REG_BASE_IDX 1 +#define regCGTS_RD_CTRL_REG 0x5001 +#define regCGTS_RD_CTRL_REG_BASE_IDX 1 +#define regCGTS_RD_REG 0x5002 +#define regCGTS_RD_REG_BASE_IDX 1 +#define regCGTS_TCC_DISABLE 0x5003 +#define regCGTS_TCC_DISABLE_BASE_IDX 1 +#define regCGTS_USER_TCC_DISABLE 0x5004 +#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 +#define regCGTS_TCC_DISABLE2 0x5005 +#define regCGTS_TCC_DISABLE2_BASE_IDX 1 +#define regCGTS_USER_TCC_DISABLE2 0x5006 +#define regCGTS_USER_TCC_DISABLE2_BASE_IDX 1 +#define regCGTS_CU0_SP0_CTRL_REG 0x5008 +#define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 +#define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_TA_SQC_CTRL_REG 0x500a +#define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_SP1_CTRL_REG 0x500b +#define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_SP0_CTRL_REG 0x500d +#define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_LDS_SQ_CTRL_REG 0x500e +#define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_TA_SQC_CTRL_REG 0x500f +#define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_SP1_CTRL_REG 0x5010 +#define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_SP0_CTRL_REG 0x5012 +#define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 +#define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_TA_SQC_CTRL_REG 0x5014 +#define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_SP1_CTRL_REG 0x5015 +#define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_SP0_CTRL_REG 0x5017 +#define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 +#define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_TA_SQC_CTRL_REG 0x5019 +#define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_SP1_CTRL_REG 0x501a +#define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_SP0_CTRL_REG 0x501c +#define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_LDS_SQ_CTRL_REG 0x501d +#define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_TA_SQC_CTRL_REG 0x501e +#define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_SP1_CTRL_REG 0x501f +#define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_SP0_CTRL_REG 0x5021 +#define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 +#define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_TA_SQC_CTRL_REG 0x5023 +#define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_SP1_CTRL_REG 0x5024 +#define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_SP0_CTRL_REG 0x5026 +#define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 +#define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_TA_SQC_CTRL_REG 0x5028 +#define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_SP1_CTRL_REG 0x5029 +#define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_SP0_CTRL_REG 0x502b +#define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_LDS_SQ_CTRL_REG 0x502c +#define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_TA_SQC_CTRL_REG 0x502d +#define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_SP1_CTRL_REG 0x502e +#define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_SP0_CTRL_REG 0x5030 +#define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 +#define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_TA_SQC_CTRL_REG 0x5032 +#define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_SP1_CTRL_REG 0x5033 +#define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_SP0_CTRL_REG 0x5035 +#define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 +#define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_TA_SQC_CTRL_REG 0x5037 +#define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_SP1_CTRL_REG 0x5038 +#define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_SP0_CTRL_REG 0x503a +#define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_LDS_SQ_CTRL_REG 0x503b +#define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_TA_SQC_CTRL_REG 0x503c +#define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_SP1_CTRL_REG 0x503d +#define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_SP0_CTRL_REG 0x503f +#define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 +#define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_TA_SQC_CTRL_REG 0x5041 +#define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_SP1_CTRL_REG 0x5042 +#define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_SP0_CTRL_REG 0x5044 +#define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 +#define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_TA_SQC_CTRL_REG 0x5046 +#define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_SP1_CTRL_REG 0x5047 +#define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_SP0_CTRL_REG 0x5049 +#define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_LDS_SQ_CTRL_REG 0x504a +#define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_TA_SQC_CTRL_REG 0x504b +#define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_SP1_CTRL_REG 0x504c +#define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_SP0_CTRL_REG 0x504e +#define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_LDS_SQ_CTRL_REG 0x504f +#define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_TA_SQC_CTRL_REG 0x5050 +#define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_SP1_CTRL_REG 0x5051 +#define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_SP0_CTRL_REG 0x5053 +#define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 +#define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_TA_SQC_CTRL_REG 0x5055 +#define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_SP1_CTRL_REG 0x5056 +#define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_TCPI_CTRL_REG 0x5058 +#define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_TCPI_CTRL_REG 0x5059 +#define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_TCPI_CTRL_REG 0x505a +#define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_TCPI_CTRL_REG 0x505b +#define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_TCPI_CTRL_REG 0x505c +#define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_TCPI_CTRL_REG 0x505d +#define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_TCPI_CTRL_REG 0x505e +#define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_TCPI_CTRL_REG 0x505f +#define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_TCPI_CTRL_REG 0x5060 +#define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_TCPI_CTRL_REG 0x5061 +#define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_TCPI_CTRL_REG 0x5062 +#define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_TCPI_CTRL_REG 0x5063 +#define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_TCPI_CTRL_REG 0x5064 +#define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_TCPI_CTRL_REG 0x5065 +#define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_TCPI_CTRL_REG 0x5066 +#define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_TCPI_CTRL_REG 0x5067 +#define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTT_SPI_PS_CLK_CTRL 0x507d +#define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SPIS_CLK_CTRL 0x507e +#define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SPI_CLK_CTRL 0x5080 +#define regCGTT_SPI_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PC_CLK_CTRL 0x5081 +#define regCGTT_PC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_BCI_CLK_CTRL 0x5082 +#define regCGTT_BCI_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL0 0x5089 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x508a +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x508b +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regSQ_POWER_THROTTLE 0x5091 +#define regSQ_POWER_THROTTLE_BASE_IDX 1 +#define regSQ_POWER_THROTTLE2 0x5092 +#define regSQ_POWER_THROTTLE2_BASE_IDX 1 +#define regCGTT_SX_CLK_CTRL0 0x5094 +#define regCGTT_SX_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SX_CLK_CTRL1 0x5095 +#define regCGTT_SX_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SX_CLK_CTRL2 0x5096 +#define regCGTT_SX_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SX_CLK_CTRL3 0x5097 +#define regCGTT_SX_CLK_CTRL3_BASE_IDX 1 +#define regCGTT_SX_CLK_CTRL4 0x5098 +#define regCGTT_SX_CLK_CTRL4_BASE_IDX 1 +#define regTD_CGTT_CTRL 0x509c +#define regTD_CGTT_CTRL_BASE_IDX 1 +#define regTA_CGTT_CTRL 0x509d +#define regTA_CGTT_CTRL_BASE_IDX 1 +#define regCGTT_TCI_CLK_CTRL 0x509f +#define regCGTT_TCI_CLK_CTRL_BASE_IDX 1 +#define regCGTT_GDS_CLK_CTRL 0x50a0 +#define regCGTT_GDS_CLK_CTRL_BASE_IDX 1 +#define regCGTT_TCP_TCR_CLK_CTRL 0x50a1 +#define regCGTT_TCP_TCR_CLK_CTRL_BASE_IDX 1 +#define regCGTT_TCI_TCR_CLK_CTRL 0x50a2 +#define regCGTT_TCI_TCR_CLK_CTRL_BASE_IDX 1 +#define regTCX_CGTT_SCLK_CTRL 0x50a3 +#define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regCB_CGTT_SCLK_CTRL 0x50a8 +#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL 0x50ac +#define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL2 0x50ad +#define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL3 0x50ae +#define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1 +#define regTCA_CGTT_SCLK_CTRL 0x50af +#define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPF_CLK_CTRL 0x50b1 +#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regRLC_GFX_RM_CNTL 0x50b6 +#define regRLC_GFX_RM_CNTL_BASE_IDX 1 +#define regRMI_CGTT_SCLK_CTRL 0x50c0 +#define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regSE_CAC_CGTT_CLK_CTRL 0x50d0 +#define regSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 +#define regGC_CAC_CGTT_CLK_CTRL 0x50d8 +#define regGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 +#define regGRBM_CGTT_CLK_CNTL 0x50e0 +#define regGRBM_CGTT_CLK_CNTL_BASE_IDX 1 + + +// addressBlock: gc_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x060c +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x060d +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x060e +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x060f +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x0614 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x0615 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_SUBTILE_CONTROL 0x0616 +#define regDB_SUBTILE_CONTROL_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x0617 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x0618 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x0619 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x061a +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_RING_CONTROL 0x061b +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x061c +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_RMI_CACHE_POLICY 0x061e +#define regDB_RMI_CACHE_POLICY_BASE_IDX 0 +#define regDB_DFSM_CONFIG 0x0630 +#define regDB_DFSM_CONFIG_BASE_IDX 0 +#define regDB_DFSM_WATERMARK 0x0631 +#define regDB_DFSM_WATERMARK_BASE_IDX 0 +#define regDB_DFSM_TILES_IN_FLIGHT 0x0632 +#define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 +#define regDB_DFSM_PRIMS_IN_FLIGHT 0x0633 +#define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 +#define regDB_DFSM_WATCHDOG 0x0634 +#define regDB_DFSM_WATCHDOG_BASE_IDX 0 +#define regDB_DFSM_FLUSH_ENABLE 0x0635 +#define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 +#define regDB_DFSM_FLUSH_AUX_EVENT 0x0636 +#define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 +#define regCC_RB_REDUNDANCY 0x063c +#define regCC_RB_REDUNDANCY_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x063d +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG 0x063e +#define regGB_ADDR_CONFIG_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x063f +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x0640 +#define regGB_GPU_ID_BASE_IDX 0 +#define regCC_RB_DAISY_CHAIN 0x0641 +#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x0642 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regGB_TILE_MODE0 0x0644 +#define regGB_TILE_MODE0_BASE_IDX 0 +#define regGB_TILE_MODE1 0x0645 +#define regGB_TILE_MODE1_BASE_IDX 0 +#define regGB_TILE_MODE2 0x0646 +#define regGB_TILE_MODE2_BASE_IDX 0 +#define regGB_TILE_MODE3 0x0647 +#define regGB_TILE_MODE3_BASE_IDX 0 +#define regGB_TILE_MODE4 0x0648 +#define regGB_TILE_MODE4_BASE_IDX 0 +#define regGB_TILE_MODE5 0x0649 +#define regGB_TILE_MODE5_BASE_IDX 0 +#define regGB_TILE_MODE6 0x064a +#define regGB_TILE_MODE6_BASE_IDX 0 +#define regGB_TILE_MODE7 0x064b +#define regGB_TILE_MODE7_BASE_IDX 0 +#define regGB_TILE_MODE8 0x064c +#define regGB_TILE_MODE8_BASE_IDX 0 +#define regGB_TILE_MODE9 0x064d +#define regGB_TILE_MODE9_BASE_IDX 0 +#define regGB_TILE_MODE10 0x064e +#define regGB_TILE_MODE10_BASE_IDX 0 +#define regGB_TILE_MODE11 0x064f +#define regGB_TILE_MODE11_BASE_IDX 0 +#define regGB_TILE_MODE12 0x0650 +#define regGB_TILE_MODE12_BASE_IDX 0 +#define regGB_TILE_MODE13 0x0651 +#define regGB_TILE_MODE13_BASE_IDX 0 +#define regGB_TILE_MODE14 0x0652 +#define regGB_TILE_MODE14_BASE_IDX 0 +#define regGB_TILE_MODE15 0x0653 +#define regGB_TILE_MODE15_BASE_IDX 0 +#define regGB_TILE_MODE16 0x0654 +#define regGB_TILE_MODE16_BASE_IDX 0 +#define regGB_TILE_MODE17 0x0655 +#define regGB_TILE_MODE17_BASE_IDX 0 +#define regGB_TILE_MODE18 0x0656 +#define regGB_TILE_MODE18_BASE_IDX 0 +#define regGB_TILE_MODE19 0x0657 +#define regGB_TILE_MODE19_BASE_IDX 0 +#define regGB_TILE_MODE20 0x0658 +#define regGB_TILE_MODE20_BASE_IDX 0 +#define regGB_TILE_MODE21 0x0659 +#define regGB_TILE_MODE21_BASE_IDX 0 +#define regGB_TILE_MODE22 0x065a +#define regGB_TILE_MODE22_BASE_IDX 0 +#define regGB_TILE_MODE23 0x065b +#define regGB_TILE_MODE23_BASE_IDX 0 +#define regGB_TILE_MODE24 0x065c +#define regGB_TILE_MODE24_BASE_IDX 0 +#define regGB_TILE_MODE25 0x065d +#define regGB_TILE_MODE25_BASE_IDX 0 +#define regGB_TILE_MODE26 0x065e +#define regGB_TILE_MODE26_BASE_IDX 0 +#define regGB_TILE_MODE27 0x065f +#define regGB_TILE_MODE27_BASE_IDX 0 +#define regGB_TILE_MODE28 0x0660 +#define regGB_TILE_MODE28_BASE_IDX 0 +#define regGB_TILE_MODE29 0x0661 +#define regGB_TILE_MODE29_BASE_IDX 0 +#define regGB_TILE_MODE30 0x0662 +#define regGB_TILE_MODE30_BASE_IDX 0 +#define regGB_TILE_MODE31 0x0663 +#define regGB_TILE_MODE31_BASE_IDX 0 +#define regGB_MACROTILE_MODE0 0x0664 +#define regGB_MACROTILE_MODE0_BASE_IDX 0 +#define regGB_MACROTILE_MODE1 0x0665 +#define regGB_MACROTILE_MODE1_BASE_IDX 0 +#define regGB_MACROTILE_MODE2 0x0666 +#define regGB_MACROTILE_MODE2_BASE_IDX 0 +#define regGB_MACROTILE_MODE3 0x0667 +#define regGB_MACROTILE_MODE3_BASE_IDX 0 +#define regGB_MACROTILE_MODE4 0x0668 +#define regGB_MACROTILE_MODE4_BASE_IDX 0 +#define regGB_MACROTILE_MODE5 0x0669 +#define regGB_MACROTILE_MODE5_BASE_IDX 0 +#define regGB_MACROTILE_MODE6 0x066a +#define regGB_MACROTILE_MODE6_BASE_IDX 0 +#define regGB_MACROTILE_MODE7 0x066b +#define regGB_MACROTILE_MODE7_BASE_IDX 0 +#define regGB_MACROTILE_MODE8 0x066c +#define regGB_MACROTILE_MODE8_BASE_IDX 0 +#define regGB_MACROTILE_MODE9 0x066d +#define regGB_MACROTILE_MODE9_BASE_IDX 0 +#define regGB_MACROTILE_MODE10 0x066e +#define regGB_MACROTILE_MODE10_BASE_IDX 0 +#define regGB_MACROTILE_MODE11 0x066f +#define regGB_MACROTILE_MODE11_BASE_IDX 0 +#define regGB_MACROTILE_MODE12 0x0670 +#define regGB_MACROTILE_MODE12_BASE_IDX 0 +#define regGB_MACROTILE_MODE13 0x0671 +#define regGB_MACROTILE_MODE13_BASE_IDX 0 +#define regGB_MACROTILE_MODE14 0x0672 +#define regGB_MACROTILE_MODE14_BASE_IDX 0 +#define regGB_MACROTILE_MODE15 0x0673 +#define regGB_MACROTILE_MODE15_BASE_IDX 0 +#define regCB_HW_CONTROL 0x0680 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x0681 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x0682 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x0683 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_RD 0x0686 +#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_WR 0x0687 +#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 +#define regCB_DCC_CONFIG 0x0688 +#define regCB_DCC_CONFIG_BASE_IDX 0 +#define regGC_USER_RB_REDUNDANCY 0x06de +#define regGC_USER_RB_REDUNDANCY_BASE_IDX 0 +#define regGC_USER_RB_BACKEND_DISABLE 0x06df +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 + + +// addressBlock: gc_rlcpdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_SAFE_MODE 0x4c05 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4c06 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4c08 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4c0a +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c11 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_LB_CNTR_MAX 0x4c12 +#define regRLC_LB_CNTR_MAX_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c13 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c15 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 +#define regRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 +#define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_LB_CNTL 0x4c19 +#define regRLC_LB_CNTL_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_LB_CNTR_INIT 0x4c1b +#define regRLC_LB_CNTR_INIT_BASE_IDX 1 +#define regRLC_LOAD_BALANCE_CNTR 0x4c1c +#define regRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4c40 +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_CU_STATUS 0x4c4e +#define regRLC_CU_STATUS_BASE_IDX 1 +#define regRLC_LB_INIT_CU_MASK 0x4c4f +#define regRLC_LB_INIT_CU_MASK_BASE_IDX 1 +#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 +#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 +#define regRLC_LB_PARAMS 0x4c51 +#define regRLC_LB_PARAMS_BASE_IDX 1 +#define regRLC_THREAD1_DELAY 0x4c52 +#define regRLC_THREAD1_DELAY_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_CU 0x4c54 +#define regRLC_MAX_PG_CU_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_PENDING 0x4c58 +#define regRLC_SERDES_RD_PENDING_BASE_IDX 1 +#define regRLC_SERDES_RD_MASTER_INDEX 0x4c59 +#define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d +#define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 +#define regRLC_SERDES_WR_CTRL 0x4c5f +#define regRLC_SERDES_WR_CTRL_BASE_IDX 1 +#define regRLC_SERDES_WR_DATA 0x4c60 +#define regRLC_SERDES_WR_DATA_BASE_IDX 1 +#define regRLC_SERDES_CU_MASTER_BUSY 0x4c61 +#define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 +#define regRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 +#define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x4c6c +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x4c6d +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x4c71 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x4c72 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x4c73 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_GPM_LOG_SIZE 0x4c77 +#define regRLC_GPM_LOG_SIZE_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_LOG_CONT 0x4c7b +#define regRLC_GPM_LOG_CONT_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH1 0x4c7f +#define regRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x4c83 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x4c84 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x4c85 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x4c86 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4c87 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_RLCV_COMMAND 0x4c89 +#define regRLC_SRM_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a +#define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4c9c +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x4ca2 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x4ca3 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x4ca4 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x4caa +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 +#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 +#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_2 0x4cb8 +#define regRLC_LB_THR_CONFIG_2_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_3 0x4cb9 +#define regRLC_LB_THR_CONFIG_3_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_4 0x4cba +#define regRLC_LB_THR_CONFIG_4_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_1 0x4cbf +#define regRLC_LB_THR_CONFIG_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 +#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 +#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 +#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x4cca +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNT 0x4ccb +#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 +#define regRLC_SPARE_INT 0x4ccc +#define regRLC_SPARE_INT_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_CNTL 0x4ccd +#define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_TRIG 0x4cce +#define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf +#define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 +#define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 +#define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 +#define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 +#define regRLC_DSM_TRIG 0x4cd3 +#define regRLC_DSM_TRIG_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_UTCL2_CNTL 0x4cd9 +#define regRLC_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_LBPW_CU_STAT 0x4cda +#define regRLC_LBPW_CU_STAT_BASE_IDX 1 +#define regRLC_DS_CNTL 0x4cdb +#define regRLC_DS_CNTL_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x4ce0 +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x4ce1 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4ce3 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4ce4 +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_CPG_STAT_INVAL 0x4d09 +#define regRLC_CPG_STAT_INVAL_BASE_IDX 1 +#define regRLC_EDC_CNT 0x4d40 +#define regRLC_EDC_CNT_BASE_IDX 1 +#define regRLC_EDC_CNT2 0x4d41 +#define regRLC_EDC_CNT2_BASE_IDX 1 +#define regRLC_DSM_CNTL 0x4d42 +#define regRLC_DSM_CNTL_BASE_IDX 1 +#define regRLC_DSM_CNTLA 0x4d43 +#define regRLC_DSM_CNTLA_BASE_IDX 1 +#define regRLC_DSM_CNTL2 0x4d44 +#define regRLC_DSM_CNTL2_BASE_IDX 1 +#define regRLC_DSM_CNTL2A 0x4d45 +#define regRLC_DSM_CNTL2A_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4f30 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 + + +// addressBlock: gc_rmi_rmidec +// base address: 0x9e00 +#define regRMI_GENERAL_CNTL 0x0780 +#define regRMI_GENERAL_CNTL_BASE_IDX 0 +#define regRMI_GENERAL_CNTL1 0x0781 +#define regRMI_GENERAL_CNTL1_BASE_IDX 0 +#define regRMI_GENERAL_STATUS 0x0782 +#define regRMI_GENERAL_STATUS_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS0 0x0783 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS1 0x0784 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS2 0x0785 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS3 0x0786 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 0 +#define regRMI_XBAR_CONFIG 0x0787 +#define regRMI_XBAR_CONFIG_BASE_IDX 0 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x0788 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x0789 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 +#define regRMI_DEMUX_CNTL 0x078a +#define regRMI_DEMUX_CNTL_BASE_IDX 0 +#define regRMI_UTCL1_CNTL1 0x078b +#define regRMI_UTCL1_CNTL1_BASE_IDX 0 +#define regRMI_UTCL1_CNTL2 0x078c +#define regRMI_UTCL1_CNTL2_BASE_IDX 0 +#define regRMI_UTC_UNIT_CONFIG 0x078d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 0 +#define regRMI_TCIW_FORMATTER0_CNTL 0x078e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 +#define regRMI_TCIW_FORMATTER1_CNTL 0x078f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 +#define regRMI_SCOREBOARD_CNTL 0x0790 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS0 0x0791 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS1 0x0792 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS2 0x0793 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 0 +#define regRMI_XBAR_ARBITER_CONFIG 0x0794 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x0795 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 +#define regRMI_CLOCK_CNTRL 0x0796 +#define regRMI_CLOCK_CNTRL_BASE_IDX 0 +#define regRMI_UTCL1_STATUS 0x0797 +#define regRMI_UTCL1_STATUS_BASE_IDX 0 +#define regRMI_SPARE 0x079e +#define regRMI_SPARE_BASE_IDX 0 +#define regRMI_SPARE_1 0x079f +#define regRMI_SPARE_1_BASE_IDX 0 +#define regRMI_SPARE_2 0x07a0 +#define regRMI_SPARE_2_BASE_IDX 0 + + +// addressBlock: gc_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_RSRC3_PS 0x0c07 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x0c08 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x0c09 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x0c0a +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x0c0b +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x0c0c +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x0c0d +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x0c0e +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x0c0f +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x0c10 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x0c11 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x0c12 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x0c13 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x0c14 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x0c15 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x0c16 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x0c17 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x0c18 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x0c19 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x0c1a +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x0c1b +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x0c1c +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x0c1d +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x0c1e +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x0c1f +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x0c20 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x0c21 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x0c22 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x0c23 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x0c24 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x0c25 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x0c26 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x0c27 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x0c28 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x0c29 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x0c2a +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x0c2b +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_VS 0x0c46 +#define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 +#define regSPI_SHADER_LATE_ALLOC_VS 0x0c47 +#define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_VS 0x0c48 +#define regSPI_SHADER_PGM_LO_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_VS 0x0c49 +#define regSPI_SHADER_PGM_HI_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_VS 0x0c4a +#define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_VS 0x0c4b +#define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_0 0x0c4c +#define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_1 0x0c4d +#define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_2 0x0c4e +#define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_3 0x0c4f +#define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_4 0x0c50 +#define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_5 0x0c51 +#define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_6 0x0c52 +#define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_7 0x0c53 +#define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_8 0x0c54 +#define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_9 0x0c55 +#define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_10 0x0c56 +#define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_11 0x0c57 +#define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_12 0x0c58 +#define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_13 0x0c59 +#define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_14 0x0c5a +#define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_15 0x0c5b +#define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_16 0x0c5c +#define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_17 0x0c5d +#define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_18 0x0c5e +#define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_19 0x0c5f +#define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_20 0x0c60 +#define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_21 0x0c61 +#define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_22 0x0c62 +#define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_23 0x0c63 +#define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_24 0x0c64 +#define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_25 0x0c65 +#define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_26 0x0c66 +#define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_27 0x0c67 +#define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_28 0x0c68 +#define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_29 0x0c69 +#define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_30 0x0c6a +#define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_31 0x0c6b +#define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c +#define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x0c81 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x0c84 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x0c85 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x0c87 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x0c88 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x0c89 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x0c8a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x0c8b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_0 0x0ccc +#define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_1 0x0ccd +#define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_2 0x0cce +#define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_3 0x0ccf +#define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_4 0x0cd0 +#define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_5 0x0cd1 +#define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_6 0x0cd2 +#define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_7 0x0cd3 +#define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_8 0x0cd4 +#define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_9 0x0cd5 +#define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_10 0x0cd6 +#define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_11 0x0cd7 +#define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_12 0x0cd8 +#define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_13 0x0cd9 +#define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_14 0x0cda +#define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_15 0x0cdb +#define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_16 0x0cdc +#define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_17 0x0cdd +#define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_18 0x0cde +#define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_19 0x0cdf +#define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_20 0x0ce0 +#define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_21 0x0ce1 +#define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_22 0x0ce2 +#define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_23 0x0ce3 +#define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_24 0x0ce4 +#define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_25 0x0ce5 +#define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_26 0x0ce6 +#define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_27 0x0ce7 +#define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_28 0x0ce8 +#define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_29 0x0ce9 +#define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_30 0x0cea +#define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_31 0x0ceb +#define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x0d01 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x0d04 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x0d05 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x0d07 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x0d08 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x0d09 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x0d0a +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x0d0b +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_0 0x0d0c +#define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_1 0x0d0d +#define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_2 0x0d0e +#define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_3 0x0d0f +#define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_4 0x0d10 +#define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_5 0x0d11 +#define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_6 0x0d12 +#define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_7 0x0d13 +#define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_8 0x0d14 +#define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_9 0x0d15 +#define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_10 0x0d16 +#define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_11 0x0d17 +#define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_12 0x0d18 +#define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_13 0x0d19 +#define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_14 0x0d1a +#define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_15 0x0d1b +#define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_16 0x0d1c +#define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_17 0x0d1d +#define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_18 0x0d1e +#define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_19 0x0d1f +#define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_20 0x0d20 +#define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_21 0x0d21 +#define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_22 0x0d22 +#define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_23 0x0d23 +#define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_24 0x0d24 +#define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_25 0x0d25 +#define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_26 0x0d26 +#define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_27 0x0d27 +#define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_28 0x0d28 +#define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_29 0x0d29 +#define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_30 0x0d2a +#define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_31 0x0d2b +#define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_0 0x0d4c +#define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_1 0x0d4d +#define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_2 0x0d4e +#define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_3 0x0d4f +#define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_4 0x0d50 +#define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_5 0x0d51 +#define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_6 0x0d52 +#define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_7 0x0d53 +#define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_8 0x0d54 +#define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_9 0x0d55 +#define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_10 0x0d56 +#define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_11 0x0d57 +#define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_12 0x0d58 +#define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_13 0x0d59 +#define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_14 0x0d5a +#define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_15 0x0d5b +#define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_16 0x0d5c +#define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_17 0x0d5d +#define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_18 0x0d5e +#define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_19 0x0d5f +#define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_20 0x0d60 +#define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_21 0x0d61 +#define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_22 0x0d62 +#define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_23 0x0d63 +#define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_24 0x0d64 +#define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_25 0x0d65 +#define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_26 0x0d66 +#define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_27 0x0d67 +#define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_28 0x0d68 +#define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_29 0x0d69 +#define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_30 0x0d6a +#define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_31 0x0d6b +#define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INITIATOR 0x0e00 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x0e01 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x0e02 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x0e03 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x0e04 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x0e05 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x0e06 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x0e07 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x0e08 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x0e09 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x0e0b +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x0e0c +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x0e0d +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x0e12 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x0e13 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x0e14 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x0e15 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x0e18 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x0e1b +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x0e1c +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x0e1d +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x0e1f +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x0e20 +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x0e21 +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x0e22 +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x0e25 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x0e26 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x0e27 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x0e28 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 +#define regCOMPUTE_RESTART_X2 0x0e29 +#define regCOMPUTE_RESTART_X2_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y2 0x0e2a +#define regCOMPUTE_RESTART_Y2_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z2 0x0e2b +#define regCOMPUTE_RESTART_Z2_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x0e2c +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x0e2d +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x0e40 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x0e41 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x0e42 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x0e43 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x0e44 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x0e45 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x0e46 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x0e47 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x0e48 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x0e49 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x0e4a +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x0e4b +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x0e4c +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x0e4d +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x0e4e +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x0e4f +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x0e7e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x0e7f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 + + +// addressBlock: gc_shsdec +// base address: 0x9000 +#define regSX_DEBUG_1 0x0419 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x043a +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_START_PHASE 0x043b +#define regSPI_START_PHASE_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x043c +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x0443 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x0444 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x0445 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x0452 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x04aa +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x04ab +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_1 0x04ac +#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x04ad +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x04ae +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x04af +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x04b0 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_6 0x04b1 +#define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_7 0x04b2 +#define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_8 0x04b3 +#define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_9 0x04b4 +#define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x04b5 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_1 0x04b6 +#define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x04b7 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_3 0x04b8 +#define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x04b9 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_5 0x04ba +#define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x04bb +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x04bc +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_8 0x04bd +#define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x04be +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_10 0x04bf +#define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x04c0 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_12 0x04c1 +#define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x04c2 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x04c3 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x04c4 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x04c5 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x04c6 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x04c7 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x04c8 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x04c9 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x04d4 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_CU_MASK 0x04d5 +#define regSPI_LB_CU_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x04d6 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 +#define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x04d8 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x04db +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x04e4 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 +#define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 +#define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 +#define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 + + +// addressBlock: gc_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x11c0 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x11c1 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x11c2 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x11c7 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x11c9 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x11ca +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x11cb +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x11cc +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x11cd +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x11ce +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x11cf +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x11d0 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_GDBG_WAVE_CNTL 0x11d1 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define regSPI_GDBG_TRAP_CONFIG 0x11d2 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x11d3 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_WAVE_CNTL3 0x11d5 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define regSPI_GDBG_TRAP_DATA0 0x11d8 +#define regSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define regSPI_GDBG_TRAP_DATA1 0x11d9 +#define regSPI_GDBG_TRAP_DATA1_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x11db +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_0 0x11dc +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_1 0x11dd +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_2 0x11de +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_3 0x11df +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_4 0x11e0 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_5 0x11e1 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_6 0x11e2 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_7 0x11e3 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_8 0x11e4 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_9 0x11e5 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_10 0x11f0 +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_11 0x11f1 +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_12 0x11f4 +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_13 0x11f5 +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_14 0x11f6 +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_15 0x11f7 +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x11fc +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 +#define regSPI_ARB_CNTL_0 0x11fd +#define regSPI_ARB_CNTL_0_BASE_IDX 0 + + +// addressBlock: gc_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x0300 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x0301 +#define regSQC_CONFIG_BASE_IDX 0 +#define regLDS_CONFIG 0x0302 +#define regLDS_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x0303 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQ_REG_CREDITS 0x0304 +#define regSQ_REG_CREDITS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x0305 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x0306 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x0307 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSQ_RUNTIME_CONFIG 0x0308 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL 0x0309 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 +#define regSH_MEM_BASES 0x030a +#define regSH_MEM_BASES_BASE_IDX 0 +#define regSQ_TIMEOUT_CONFIG 0x030b +#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS 0x030c +#define regSQ_TIMEOUT_STATUS_BASE_IDX 0 +#define regSH_MEM_CONFIG 0x030d +#define regSH_MEM_CONFIG_BASE_IDX 0 +#define regSP_MFMA_PORTD_RD_CONFIG 0x030e +#define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0 +#define regSH_CAC_CONFIG 0x030f +#define regSH_CAC_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL2 0x0310 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL3 0x0311 +#define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG 0x0312 +#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regGC_USER_SHADER_RATE_CONFIG 0x0313 +#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x0314 +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x0315 +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316 +#define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0 +#define regSQ_UTCL1_CNTL1 0x0317 +#define regSQ_UTCL1_CNTL1_BASE_IDX 0 +#define regSQ_UTCL1_CNTL2 0x0318 +#define regSQ_UTCL1_CNTL2_BASE_IDX 0 +#define regSQ_UTCL1_STATUS 0x0319 +#define regSQ_UTCL1_STATUS_BASE_IDX 0 +#define regSQ_FED_INTERRUPT_STATUS 0x031a +#define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0 +#define regSQ_CGTS_CONFIG 0x031b +#define regSQ_CGTS_CONFIG_BASE_IDX 0 +#define regSQ_SHADER_TBA_LO 0x031c +#define regSQ_SHADER_TBA_LO_BASE_IDX 0 +#define regSQ_SHADER_TBA_HI 0x031d +#define regSQ_SHADER_TBA_HI_BASE_IDX 0 +#define regSQ_SHADER_TMA_LO 0x031e +#define regSQ_SHADER_TMA_LO_BASE_IDX 0 +#define regSQ_SHADER_TMA_HI 0x031f +#define regSQ_SHADER_TMA_HI_BASE_IDX 0 +#define regSQC_DSM_CNTL 0x0320 +#define regSQC_DSM_CNTL_BASE_IDX 0 +#define regSQC_DSM_CNTLA 0x0321 +#define regSQC_DSM_CNTLA_BASE_IDX 0 +#define regSQC_DSM_CNTLB 0x0322 +#define regSQC_DSM_CNTLB_BASE_IDX 0 +#define regSQC_DSM_CNTL2 0x0325 +#define regSQC_DSM_CNTL2_BASE_IDX 0 +#define regSQC_DSM_CNTL2A 0x0326 +#define regSQC_DSM_CNTL2A_BASE_IDX 0 +#define regSQC_DSM_CNTL2B 0x0327 +#define regSQC_DSM_CNTL2B_BASE_IDX 0 +#define regSQC_DSM_CNTL2E 0x032a +#define regSQC_DSM_CNTL2E_BASE_IDX 0 +#define regSQC_EDC_FUE_CNTL 0x032b +#define regSQC_EDC_FUE_CNTL_BASE_IDX 0 +#define regSQC_EDC_CNT2 0x032c +#define regSQC_EDC_CNT2_BASE_IDX 0 +#define regSQC_EDC_CNT3 0x032d +#define regSQC_EDC_CNT3_BASE_IDX 0 +#define regSQC_EDC_PARITY_CNT3 0x032e +#define regSQC_EDC_PARITY_CNT3_BASE_IDX 0 +#define regSQ_DEBUG 0x0332 +#define regSQ_DEBUG_BASE_IDX 0 +#define regSQ_REG_TIMESTAMP 0x0374 +#define regSQ_REG_TIMESTAMP_BASE_IDX 0 +#define regSQ_CMD_TIMESTAMP 0x0375 +#define regSQ_CMD_TIMESTAMP_BASE_IDX 0 +#define regSQ_HOSTTRAP_STATUS 0x0376 +#define regSQ_HOSTTRAP_STATUS_BASE_IDX 0 +#define regSQ_IND_INDEX 0x0378 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x0379 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CONFIG1 0x037a +#define regSQ_CONFIG1_BASE_IDX 0 +#define regSQ_CMD 0x037b +#define regSQ_CMD_BASE_IDX 0 +#define regSQ_TIME_HI 0x037c +#define regSQ_TIME_HI_BASE_IDX 0 +#define regSQ_TIME_LO 0x037d +#define regSQ_TIME_LO_BASE_IDX 0 +#define regSQ_DS_0 0x037f +#define regSQ_DS_0_BASE_IDX 0 +#define regSQ_DS_1 0x037f +#define regSQ_DS_1_BASE_IDX 0 +#define regSQ_EXP_0 0x037f +#define regSQ_EXP_0_BASE_IDX 0 +#define regSQ_EXP_1 0x037f +#define regSQ_EXP_1_BASE_IDX 0 +#define regSQ_FLAT_0 0x037f +#define regSQ_FLAT_0_BASE_IDX 0 +#define regSQ_FLAT_1 0x037f +#define regSQ_FLAT_1_BASE_IDX 0 +#define regSQ_GLBL_0 0x037f +#define regSQ_GLBL_0_BASE_IDX 0 +#define regSQ_GLBL_1 0x037f +#define regSQ_GLBL_1_BASE_IDX 0 +#define regSQ_INST 0x037f +#define regSQ_INST_BASE_IDX 0 +#define regSQ_MIMG_0 0x037f +#define regSQ_MIMG_0_BASE_IDX 0 +#define regSQ_MIMG_1 0x037f +#define regSQ_MIMG_1_BASE_IDX 0 +#define regSQ_MTBUF_0 0x037f +#define regSQ_MTBUF_0_BASE_IDX 0 +#define regSQ_MTBUF_1 0x037f +#define regSQ_MTBUF_1_BASE_IDX 0 +#define regSQ_MUBUF_0 0x037f +#define regSQ_MUBUF_0_BASE_IDX 0 +#define regSQ_MUBUF_1 0x037f +#define regSQ_MUBUF_1_BASE_IDX 0 +#define regSQ_SCRATCH_0 0x037f +#define regSQ_SCRATCH_0_BASE_IDX 0 +#define regSQ_SCRATCH_1 0x037f +#define regSQ_SCRATCH_1_BASE_IDX 0 +#define regSQ_SMEM_0 0x037f +#define regSQ_SMEM_0_BASE_IDX 0 +#define regSQ_SMEM_1 0x037f +#define regSQ_SMEM_1_BASE_IDX 0 +#define regSQ_SOP1 0x037f +#define regSQ_SOP1_BASE_IDX 0 +#define regSQ_SOP2 0x037f +#define regSQ_SOP2_BASE_IDX 0 +#define regSQ_SOPC 0x037f +#define regSQ_SOPC_BASE_IDX 0 +#define regSQ_SOPK 0x037f +#define regSQ_SOPK_BASE_IDX 0 +#define regSQ_SOPP 0x037f +#define regSQ_SOPP_BASE_IDX 0 +#define regSQ_VINTRP 0x037f +#define regSQ_VINTRP_BASE_IDX 0 +#define regSQ_VOP1 0x037f +#define regSQ_VOP1_BASE_IDX 0 +#define regSQ_VOP2 0x037f +#define regSQ_VOP2_BASE_IDX 0 +#define regSQ_VOP3P_0 0x037f +#define regSQ_VOP3P_0_BASE_IDX 0 +#define regSQ_VOP3P_1 0x037f +#define regSQ_VOP3P_1_BASE_IDX 0 +#define regSQ_VOP3P_MFMA_0 0x037f +#define regSQ_VOP3P_MFMA_0_BASE_IDX 0 +#define regSQ_VOP3P_MFMA_1 0x037f +#define regSQ_VOP3P_MFMA_1_BASE_IDX 0 +#define regSQ_VOP3_0 0x037f +#define regSQ_VOP3_0_BASE_IDX 0 +#define regSQ_VOP3_0_SDST_ENC 0x037f +#define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0 +#define regSQ_VOP3_1 0x037f +#define regSQ_VOP3_1_BASE_IDX 0 +#define regSQ_VOPC 0x037f +#define regSQ_VOPC_BASE_IDX 0 +#define regSQ_VOP_DPP 0x037f +#define regSQ_VOP_DPP_BASE_IDX 0 +#define regSQ_VOP_SDWA 0x037f +#define regSQ_VOP_SDWA_BASE_IDX 0 +#define regSQ_VOP_SDWA_SDST_ENC 0x037f +#define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 +#define regSQ_LB_CTR_CTRL 0x0398 +#define regSQ_LB_CTR_CTRL_BASE_IDX 0 +#define regSQ_LB_DATA0 0x0399 +#define regSQ_LB_DATA0_BASE_IDX 0 +#define regSQ_LB_DATA1 0x039a +#define regSQ_LB_DATA1_BASE_IDX 0 +#define regSQ_LB_DATA2 0x039b +#define regSQ_LB_DATA2_BASE_IDX 0 +#define regSQ_LB_DATA3 0x039c +#define regSQ_LB_DATA3_BASE_IDX 0 +#define regSQ_LB_CTR_SEL 0x039d +#define regSQ_LB_CTR_SEL_BASE_IDX 0 +#define regSQ_LB_CTR0_CU 0x039e +#define regSQ_LB_CTR0_CU_BASE_IDX 0 +#define regSQ_LB_CTR1_CU 0x039f +#define regSQ_LB_CTR1_CU_BASE_IDX 0 +#define regSQ_LB_CTR2_CU 0x03a0 +#define regSQ_LB_CTR2_CU_BASE_IDX 0 +#define regSQ_LB_CTR3_CU 0x03a1 +#define regSQ_LB_CTR3_CU_BASE_IDX 0 +#define regSQC_EDC_CNT 0x03a2 +#define regSQC_EDC_CNT_BASE_IDX 0 +#define regSQ_EDC_SEC_CNT 0x03a3 +#define regSQ_EDC_SEC_CNT_BASE_IDX 0 +#define regSQ_EDC_DED_CNT 0x03a4 +#define regSQ_EDC_DED_CNT_BASE_IDX 0 +#define regSQ_EDC_INFO 0x03a5 +#define regSQ_EDC_INFO_BASE_IDX 0 +#define regSQ_EDC_CNT 0x03a6 +#define regSQ_EDC_CNT_BASE_IDX 0 +#define regSQ_EDC_FUE_CNTL 0x03a7 +#define regSQ_EDC_FUE_CNTL_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_CMN 0x03b0 +#define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0 +#define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 +#define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_MISC 0x03b0 +#define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_WAVE 0x03b0 +#define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 +#define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 +#define regSQ_WREXEC_EXEC_HI 0x03b1 +#define regSQ_WREXEC_EXEC_HI_BASE_IDX 0 +#define regSQ_WREXEC_EXEC_LO 0x03b1 +#define regSQ_WREXEC_EXEC_LO_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD0 0x03c0 +#define regSQ_BUF_RSRC_WORD0_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD1 0x03c1 +#define regSQ_BUF_RSRC_WORD1_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD2 0x03c2 +#define regSQ_BUF_RSRC_WORD2_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD3 0x03c3 +#define regSQ_BUF_RSRC_WORD3_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD0 0x03c4 +#define regSQ_IMG_RSRC_WORD0_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD1 0x03c5 +#define regSQ_IMG_RSRC_WORD1_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD2 0x03c6 +#define regSQ_IMG_RSRC_WORD2_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD3 0x03c7 +#define regSQ_IMG_RSRC_WORD3_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD4 0x03c8 +#define regSQ_IMG_RSRC_WORD4_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD5 0x03c9 +#define regSQ_IMG_RSRC_WORD5_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD6 0x03ca +#define regSQ_IMG_RSRC_WORD6_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD7 0x03cb +#define regSQ_IMG_RSRC_WORD7_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD0 0x03cc +#define regSQ_IMG_SAMP_WORD0_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD1 0x03cd +#define regSQ_IMG_SAMP_WORD1_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD2 0x03ce +#define regSQ_IMG_SAMP_WORD2_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD3 0x03cf +#define regSQ_IMG_SAMP_WORD3_BASE_IDX 0 +#define regSQ_FLAT_SCRATCH_WORD0 0x03d0 +#define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 +#define regSQ_FLAT_SCRATCH_WORD1 0x03d1 +#define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 +#define regSQ_M0_GPR_IDX_WORD 0x03d2 +#define regSQ_M0_GPR_IDX_WORD_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_CNTL1 0x03d3 +#define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_CNTL2 0x03d4 +#define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_CNTL1 0x03d5 +#define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_CNTL2 0x03d6 +#define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_STATUS 0x03d7 +#define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_STATUS 0x03d8 +#define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: gc_tcdec +// base address: 0xac00 +#define regTCP_INVALIDATE 0x0b00 +#define regTCP_INVALIDATE_BASE_IDX 0 +#define regTCP_STATUS 0x0b01 +#define regTCP_STATUS_BASE_IDX 0 +#define regTCP_CHAN_STEER_0 0x0b03 +#define regTCP_CHAN_STEER_0_BASE_IDX 0 +#define regTCP_CHAN_STEER_1 0x0b04 +#define regTCP_CHAN_STEER_1_BASE_IDX 0 +#define regTCP_ADDR_CONFIG 0x0b05 +#define regTCP_ADDR_CONFIG_BASE_IDX 0 +#define regTCP_CHAN_STEER_2 0x0b09 +#define regTCP_CHAN_STEER_2_BASE_IDX 0 +#define regTCP_CHAN_STEER_3 0x0b0a +#define regTCP_CHAN_STEER_3_BASE_IDX 0 +#define regTCP_CHAN_STEER_4 0x0b0b +#define regTCP_CHAN_STEER_4_BASE_IDX 0 +#define regTCP_CHAN_STEER_5 0x0b0c +#define regTCP_CHAN_STEER_5_BASE_IDX 0 +#define regTCP_EDC_CNT 0x0b17 +#define regTCP_EDC_CNT_BASE_IDX 0 +#define regTCP_EDC_CNT_NEW 0x0b18 +#define regTCP_EDC_CNT_NEW_BASE_IDX 0 +#define regTC_CFG_L1_LOAD_POLICY0 0x0b1a +#define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 +#define regTC_CFG_L1_LOAD_POLICY1 0x0b1b +#define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 +#define regTC_CFG_L1_STORE_POLICY 0x0b1c +#define regTC_CFG_L1_STORE_POLICY_BASE_IDX 0 +#define regTC_CFG_L2_LOAD_POLICY0 0x0b1d +#define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 +#define regTC_CFG_L2_LOAD_POLICY1 0x0b1e +#define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 +#define regTC_CFG_L2_STORE_POLICY0 0x0b1f +#define regTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 +#define regTC_CFG_L2_STORE_POLICY1 0x0b20 +#define regTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 +#define regTC_CFG_L2_ATOMIC_POLICY 0x0b21 +#define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 +#define regTC_CFG_L1_VOLATILE 0x0b22 +#define regTC_CFG_L1_VOLATILE_BASE_IDX 0 +#define regTC_CFG_L2_VOLATILE 0x0b23 +#define regTC_CFG_L2_VOLATILE_BASE_IDX 0 +#define regTCI_MISC 0x0b5c +#define regTCI_MISC_BASE_IDX 0 +#define regTCI_CNTL_3 0x0b5d +#define regTCI_CNTL_3_BASE_IDX 0 +#define regTCI_DSM_CNTL 0x0b5e +#define regTCI_DSM_CNTL_BASE_IDX 0 +#define regTCI_DSM_CNTL2 0x0b5f +#define regTCI_DSM_CNTL2_BASE_IDX 0 +#define regTCI_EDC_CNT 0x0b60 +#define regTCI_EDC_CNT_BASE_IDX 0 +#define regTCI_STATUS 0x0b61 +#define regTCI_STATUS_BASE_IDX 0 +#define regTCI_CNTL_1 0x0b62 +#define regTCI_CNTL_1_BASE_IDX 0 +#define regTCI_CNTL_2 0x0b63 +#define regTCI_CNTL_2_BASE_IDX 0 +#define regTCC_CTRL 0x0b80 +#define regTCC_CTRL_BASE_IDX 0 +#define regTCC_CTRL2 0x0b81 +#define regTCC_CTRL2_BASE_IDX 0 +#define regTCC_EDC_CNT 0x0b82 +#define regTCC_EDC_CNT_BASE_IDX 0 +#define regTCC_EDC_CNT2 0x0b83 +#define regTCC_EDC_CNT2_BASE_IDX 0 +#define regTCC_REDUNDANCY 0x0b84 +#define regTCC_REDUNDANCY_BASE_IDX 0 +#define regTCC_EXE_DISABLE 0x0b85 +#define regTCC_EXE_DISABLE_BASE_IDX 0 +#define regTCC_DSM_CNTL 0x0b86 +#define regTCC_DSM_CNTL_BASE_IDX 0 +#define regTCC_DSM_CNTLA 0x0b87 +#define regTCC_DSM_CNTLA_BASE_IDX 0 +#define regTCC_DSM_CNTL2 0x0b88 +#define regTCC_DSM_CNTL2_BASE_IDX 0 +#define regTCC_DSM_CNTL2A 0x0b89 +#define regTCC_DSM_CNTL2A_BASE_IDX 0 +#define regTCC_DSM_CNTL2B 0x0b8a +#define regTCC_DSM_CNTL2B_BASE_IDX 0 +#define regTCC_WBINVL2 0x0b8b +#define regTCC_WBINVL2_BASE_IDX 0 +#define regTCC_SOFT_RESET 0x0b8c +#define regTCC_SOFT_RESET_BASE_IDX 0 +#define regTCC_DSM_CNTL3 0x0b8e +#define regTCC_DSM_CNTL3_BASE_IDX 0 +#define regTCA_CTRL 0x0bc0 +#define regTCA_CTRL_BASE_IDX 0 +#define regTCA_BURST_MASK 0x0bc1 +#define regTCA_BURST_MASK_BASE_IDX 0 +#define regTCA_BURST_CTRL 0x0bc2 +#define regTCA_BURST_CTRL_BASE_IDX 0 +#define regTCA_DSM_CNTL 0x0bc3 +#define regTCA_DSM_CNTL_BASE_IDX 0 +#define regTCA_DSM_CNTL2 0x0bc4 +#define regTCA_DSM_CNTL2_BASE_IDX 0 +#define regTCA_EDC_CNT 0x0bc5 +#define regTCA_EDC_CNT_BASE_IDX 0 +#define regTCX_CTRL 0x0bc6 +#define regTCX_CTRL_BASE_IDX 0 +#define regTCX_DSM_CNTL 0x0bc7 +#define regTCX_DSM_CNTL_BASE_IDX 0 +#define regTCX_DSM_CNTL2 0x0bc8 +#define regTCX_DSM_CNTL2_BASE_IDX 0 +#define regTCX_EDC_CNT 0x0bc9 +#define regTCX_EDC_CNT_BASE_IDX 0 +#define regTCX_EDC_CNT2 0x0bca +#define regTCX_EDC_CNT2_BASE_IDX 0 + + +// addressBlock: gc_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x12a0 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x12a1 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x12a2 +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x12a3 +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x12a4 +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x12a5 +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x12a6 +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x12a7 +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x12a8 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x12a9 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x12aa +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x12ab +#define regTCP_WATCH3_CNTL_BASE_IDX 0 +#define regTCP_GATCL1_CNTL 0x12b0 +#define regTCP_GATCL1_CNTL_BASE_IDX 0 +#define regTCP_ATC_EDC_GATCL1_CNT 0x12b1 +#define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 +#define regTCP_GATCL1_DSM_CNTL 0x12b2 +#define regTCP_GATCL1_DSM_CNTL_BASE_IDX 0 +#define regTCP_DSM_CNTL 0x12b3 +#define regTCP_DSM_CNTL_BASE_IDX 0 +#define regTCP_UTCL1_CNTL1 0x12b5 +#define regTCP_UTCL1_CNTL1_BASE_IDX 0 +#define regTCP_UTCL1_CNTL2 0x12b6 +#define regTCP_UTCL1_CNTL2_BASE_IDX 0 +#define regTCP_UTCL1_STATUS 0x12b7 +#define regTCP_UTCL1_STATUS_BASE_IDX 0 +#define regTCP_DSM_CNTL2 0x12b8 +#define regTCP_DSM_CNTL2_BASE_IDX 0 +#define regTCP_PERFCOUNTER_FILTER 0x12b9 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 0 +#define regTCP_PERFCOUNTER_FILTER_EN 0x12ba +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 + + +// addressBlock: gc_tpdec +// base address: 0x9400 +#define regTD_STATUS 0x0526 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_EDC_CNT 0x052e +#define regTD_EDC_CNT_BASE_IDX 0 +#define regTD_DSM_CNTL 0x052f +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x0530 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x0533 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_CNTL 0x0541 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x0542 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_FEATURE_CNTL 0x0543 +#define regTA_FEATURE_CNTL_BASE_IDX 0 +#define regTA_STATUS 0x0548 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x0564 +#define regTA_SCRATCH_BASE_IDX 0 +#define regTA_DSM_CNTL 0x0584 +#define regTA_DSM_CNTL_BASE_IDX 0 +#define regTA_DSM_CNTL2 0x0585 +#define regTA_DSM_CNTL2_BASE_IDX 0 +#define regTA_EDC_CNT 0x0586 +#define regTA_EDC_CNT_BASE_IDX 0 + + +// addressBlock: gc_utcl2_atcl2dec +// base address: 0xa000 +#define regATC_L2_CNTL 0x0800 +#define regATC_L2_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL2 0x0801 +#define regATC_L2_CNTL2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA0 0x0804 +#define regATC_L2_CACHE_DATA0_BASE_IDX 0 +#define regATC_L2_CACHE_DATA1 0x0805 +#define regATC_L2_CACHE_DATA1_BASE_IDX 0 +#define regATC_L2_CACHE_DATA2 0x0806 +#define regATC_L2_CACHE_DATA2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA3 0x0807 +#define regATC_L2_CACHE_DATA3_BASE_IDX 0 +#define regATC_L2_CNTL3 0x0808 +#define regATC_L2_CNTL3_BASE_IDX 0 +#define regATC_L2_STATUS 0x0809 +#define regATC_L2_STATUS_BASE_IDX 0 +#define regATC_L2_STATUS2 0x080a +#define regATC_L2_STATUS2_BASE_IDX 0 +#define regATC_L2_MISC_CG 0x080b +#define regATC_L2_MISC_CG_BASE_IDX 0 +#define regATC_L2_MEM_POWER_LS 0x080c +#define regATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define regATC_L2_CGTT_CLK_CTRL 0x080d +#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_INDEX 0x080e +#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_INDEX 0x080f +#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_INDEX 0x0810 +#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_CNTL 0x0811 +#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_CNTL 0x0812 +#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_CNTL 0x0813 +#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL4 0x0814 +#define regATC_L2_CNTL4_BASE_IDX 0 +#define regATC_L2_MM_GROUP_RT_CLASSES 0x0815 +#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 + + +// addressBlock: gc_utcl2_atcl2pfcntldec +// base address: 0x37500 +#define regATC_L2_PERFCOUNTER0_CFG 0x3d40 +#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER1_CFG 0x3d41 +#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_atcl2pfcntrdec +// base address: 0x35400 +#define regATC_L2_PERFCOUNTER_LO 0x3500 +#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER_HI 0x3501 +#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_utcl2_l2tlbdec +// base address: 0xa640 +#define regL2TLB_TLB0_STATUS 0x0991 +#define regL2TLB_TLB0_STATUS_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0993 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0994 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0995 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0996 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 + + +// addressBlock: gc_utcl2_l2tlbpldec +// base address: 0x37570 +#define regL2TLB_PERFCOUNTER0_CFG 0x3d5c +#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER1_CFG 0x3d5d +#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER2_CFG 0x3d5e +#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER3_CFG 0x3d5f +#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x3d60 +#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_l2tlbprdec +// base address: 0x35460 +#define regL2TLB_PERFCOUNTER_LO 0x3518 +#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER_HI 0x3519 +#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vml2pfdec +// base address: 0xa100 +#define regVM_L2_CNTL 0x0840 +#define regVM_L2_CNTL_BASE_IDX 0 +#define regVM_L2_CNTL2 0x0841 +#define regVM_L2_CNTL2_BASE_IDX 0 +#define regVM_L2_CNTL3 0x0842 +#define regVM_L2_CNTL3_BASE_IDX 0 +#define regVM_L2_STATUS 0x0843 +#define regVM_L2_STATUS_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0844 +#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL 0x0847 +#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0848 +#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_STATUS 0x084b +#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regVM_L2_CNTL4 0x0857 +#define regVM_L2_CNTL4_BASE_IDX 0 +#define regVM_L2_MM_GROUP_RT_CLASSES 0x0858 +#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0859 +#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x085a +#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regVM_L2_CACHE_PARITY_CNTL 0x085b +#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regVM_L2_CGTT_CLK_CTRL 0x085e +#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regVM_L2_CGTT_BUSY_CTRL 0x085f +#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regVML2_MEM_ECC_INDEX 0x0861 +#define regVML2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_INDEX 0x0862 +#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 +#define regUTCL2_MEM_ECC_INDEX 0x0863 +#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_MEM_ECC_CNTL 0x0864 +#define regVML2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_CNTL 0x0865 +#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 +#define regUTCL2_MEM_ECC_CNTL 0x0866 +#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_MEM_ECC_STATUS 0x0867 +#define regVML2_MEM_ECC_STATUS_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_STATUS 0x0868 +#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_MEM_ECC_STATUS 0x0869 +#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_EDC_MODE 0x086a +#define regUTCL2_EDC_MODE_BASE_IDX 0 +#define regUTCL2_EDC_CONFIG 0x086b +#define regUTCL2_EDC_CONFIG_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vml2pldec +// base address: 0x37530 +#define regMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c +#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d +#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e +#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f +#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 +#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 +#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 +#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 +#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vml2prdec +// base address: 0x35420 +#define regMC_VM_L2_PERFCOUNTER_LO 0x3508 +#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER_HI 0x3509 +#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vml2vcdec +// base address: 0xa200 +#define regVM_CONTEXT0_CNTL 0x0880 +#define regVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regVM_CONTEXT1_CNTL 0x0881 +#define regVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regVM_CONTEXT2_CNTL 0x0882 +#define regVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regVM_CONTEXT3_CNTL 0x0883 +#define regVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regVM_CONTEXT4_CNTL 0x0884 +#define regVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regVM_CONTEXT5_CNTL 0x0885 +#define regVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regVM_CONTEXT6_CNTL 0x0886 +#define regVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regVM_CONTEXT7_CNTL 0x0887 +#define regVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regVM_CONTEXT8_CNTL 0x0888 +#define regVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regVM_CONTEXT9_CNTL 0x0889 +#define regVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regVM_CONTEXT10_CNTL 0x088a +#define regVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regVM_CONTEXT11_CNTL 0x088b +#define regVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regVM_CONTEXT12_CNTL 0x088c +#define regVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regVM_CONTEXT13_CNTL 0x088d +#define regVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regVM_CONTEXT14_CNTL 0x088e +#define regVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regVM_CONTEXT15_CNTL 0x088f +#define regVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regVM_CONTEXTS_DISABLE 0x0890 +#define regVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_SEM 0x0891 +#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_SEM 0x0892 +#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_SEM 0x0893 +#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_SEM 0x0894 +#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_SEM 0x0895 +#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_SEM 0x0896 +#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_SEM 0x0897 +#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_SEM 0x0898 +#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_SEM 0x0899 +#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_SEM 0x089a +#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_SEM 0x089b +#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_SEM 0x089c +#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_SEM 0x089d +#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_SEM 0x089e +#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_SEM 0x089f +#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_SEM 0x08a0 +#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_SEM 0x08a1 +#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_SEM 0x08a2 +#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_REQ 0x08a3 +#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_REQ 0x08a4 +#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_REQ 0x08a5 +#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_REQ 0x08a6 +#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_REQ 0x08a7 +#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_REQ 0x08a8 +#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_REQ 0x08a9 +#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_REQ 0x08aa +#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_REQ 0x08ab +#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_REQ 0x08ac +#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_REQ 0x08ad +#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_REQ 0x08ae +#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_REQ 0x08af +#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_REQ 0x08b0 +#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_REQ 0x08b1 +#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_REQ 0x08b2 +#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_REQ 0x08b3 +#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_REQ 0x08b4 +#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ACK 0x08b5 +#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ACK 0x08b6 +#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ACK 0x08b7 +#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ACK 0x08b8 +#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ACK 0x08b9 +#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ACK 0x08ba +#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ACK 0x08bb +#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ACK 0x08bc +#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ACK 0x08bd +#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ACK 0x08be +#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ACK 0x08bf +#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ACK 0x08c0 +#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ACK 0x08c1 +#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ACK 0x08c2 +#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ACK 0x08c3 +#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ACK 0x08c4 +#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ACK 0x08c5 +#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ACK 0x08c6 +#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vmsharedhvdec +// base address: 0x3ea00 +#define regMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 +#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 +#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 +#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 +#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 +#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 +#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 +#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 +#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 +#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 +#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a +#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b +#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c +#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d +#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e +#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f +#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_0 0x5a91 +#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_1 0x5a92 +#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_2 0x5a93 +#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_3 0x5a94 +#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_0 0x5a95 +#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_1 0x5a96 +#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_2 0x5a97 +#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_3 0x5a98 +#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_0 0x5a99 +#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_1 0x5a9a +#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_2 0x5a9b +#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_3 0x5a9c +#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_0 0x5a9d +#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_1 0x5a9e +#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_2 0x5a9f +#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_3 0x5aa0 +#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_0 0x5aa1 +#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_1 0x5aa2 +#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_2 0x5aa3 +#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_3 0x5aa4 +#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_0 0x5aa5 +#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_1 0x5aa6 +#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_2 0x5aa7 +#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_3 0x5aa8 +#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL 0x5aab +#define regVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_0 0x5aac +#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_1 0x5aad +#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_2 0x5aae +#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_3 0x5aaf +#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_4 0x5ab0 +#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_5 0x5ab1 +#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_6 0x5ab2 +#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_7 0x5ab3 +#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_8 0x5ab4 +#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_9 0x5ab5 +#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_10 0x5ab6 +#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_11 0x5ab7 +#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_12 0x5ab8 +#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_13 0x5ab9 +#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_14 0x5aba +#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_15 0x5abb +#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 +#define regMC_SHARED_ACTIVE_FCN_ID 0x5abc +#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define regMC_VM_XGMI_GPUIOV_ENABLE 0x5abd +#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vmsharedpfdec +// base address: 0xa590 +#define regMC_VM_FB_OFFSET 0x096b +#define regMC_VM_FB_OFFSET_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regMC_VM_STEERING 0x096e +#define regMC_VM_STEERING_BASE_IDX 0 +#define regMC_SHARED_VIRT_RESET_REQ 0x096f +#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define regMC_MEM_POWER_LS 0x0970 +#define regMC_MEM_POWER_LS_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_APT_CNTL 0x0973 +#define regMC_VM_APT_CNTL_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 +#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 +#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regUTCL2_CGTT_CLK_CTRL 0x0977 +#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_CNTL 0x0978 +#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_SIZE 0x0979 +#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_CNTL 0x097a +#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 +#define regMC_VM_HOST_MAPPING 0x097b +#define regMC_VM_HOST_MAPPING_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vmsharedvcdec +// base address: 0xa600 +#define regMC_VM_FB_LOCATION_BASE 0x0980 +#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regMC_VM_FB_LOCATION_TOP 0x0981 +#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regMC_VM_AGP_TOP 0x0982 +#define regMC_VM_AGP_TOP_BASE_IDX 0 +#define regMC_VM_AGP_BOT 0x0983 +#define regMC_VM_AGP_BOT_BASE_IDX 0 +#define regMC_VM_AGP_BASE 0x0984 +#define regMC_VM_AGP_BASE_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB_CNTL 0x0987 +#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: gccacind +// base address: 0x0 +#define ixGC_CAC_CNTL 0x0000 +#define ixGC_CAC_OVR_SEL 0x0001 +#define ixGC_CAC_OVR_VAL 0x0002 +#define ixGC_CAC_WEIGHT_BCI_0 0x0003 +#define ixGC_CAC_WEIGHT_CB_0 0x0004 +#define ixGC_CAC_WEIGHT_CB_1 0x0005 +#define ixGC_CAC_WEIGHT_CP_0 0x0008 +#define ixGC_CAC_WEIGHT_CP_1 0x0009 +#define ixGC_CAC_WEIGHT_DB_0 0x000a +#define ixGC_CAC_WEIGHT_DB_1 0x000b +#define ixGC_CAC_WEIGHT_GDS_0 0x000e +#define ixGC_CAC_WEIGHT_GDS_1 0x000f +#define ixGC_CAC_WEIGHT_IA_0 0x0010 +#define ixGC_CAC_WEIGHT_LDS_0 0x0011 +#define ixGC_CAC_WEIGHT_LDS_1 0x0012 +#define ixGC_CAC_WEIGHT_PA_0 0x0013 +#define ixGC_CAC_WEIGHT_PC_0 0x0014 +#define ixGC_CAC_WEIGHT_SC_0 0x0015 +#define ixGC_CAC_WEIGHT_SPI_0 0x0016 +#define ixGC_CAC_WEIGHT_SPI_1 0x0017 +#define ixGC_CAC_WEIGHT_SPI_2 0x0018 +#define ixGC_CAC_WEIGHT_SQ_0 0x001a +#define ixGC_CAC_WEIGHT_SQ_1 0x001b +#define ixGC_CAC_WEIGHT_SQ_2 0x001c +#define ixGC_CAC_WEIGHT_SQ_3 0x001d +#define ixGC_CAC_WEIGHT_SQ_4 0x001e +#define ixGC_CAC_WEIGHT_SX_0 0x001f +#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 +#define ixGC_CAC_WEIGHT_TA_0 0x0021 +#define ixGC_CAC_WEIGHT_TCC_0 0x0022 +#define ixGC_CAC_WEIGHT_TCC_1 0x0023 +#define ixGC_CAC_WEIGHT_TCC_2 0x0024 +#define ixGC_CAC_WEIGHT_TCP_0 0x0025 +#define ixGC_CAC_WEIGHT_TCP_1 0x0026 +#define ixGC_CAC_WEIGHT_TCP_2 0x0027 +#define ixGC_CAC_WEIGHT_TD_0 0x0028 +#define ixGC_CAC_WEIGHT_TD_1 0x0029 +#define ixGC_CAC_WEIGHT_TD_2 0x002a +#define ixGC_CAC_WEIGHT_VGT_0 0x002b +#define ixGC_CAC_WEIGHT_VGT_1 0x002c +#define ixGC_CAC_WEIGHT_WD_0 0x002d +#define ixGC_CAC_WEIGHT_CU_0 0x0032 +#define ixGC_CAC_ACC_BCI0 0x0042 +#define ixGC_CAC_ACC_CB0 0x0043 +#define ixGC_CAC_ACC_CB1 0x0044 +#define ixGC_CAC_ACC_CB2 0x0045 +#define ixGC_CAC_ACC_CB3 0x0046 +#define ixGC_CAC_ACC_CP0 0x004b +#define ixGC_CAC_ACC_CP1 0x004c +#define ixGC_CAC_ACC_CP2 0x004d +#define ixGC_CAC_ACC_DB0 0x004e +#define ixGC_CAC_ACC_DB1 0x004f +#define ixGC_CAC_ACC_DB2 0x0050 +#define ixGC_CAC_ACC_DB3 0x0051 +#define ixGC_CAC_ACC_GDS0 0x0056 +#define ixGC_CAC_ACC_GDS1 0x0057 +#define ixGC_CAC_ACC_GDS2 0x0058 +#define ixGC_CAC_ACC_GDS3 0x0059 +#define ixGC_CAC_ACC_IA0 0x005a +#define ixGC_CAC_ACC_LDS0 0x005b +#define ixGC_CAC_ACC_LDS1 0x005c +#define ixGC_CAC_ACC_LDS2 0x005d +#define ixGC_CAC_ACC_LDS3 0x005e +#define ixGC_CAC_ACC_PA0 0x005f +#define ixGC_CAC_ACC_PA1 0x0060 +#define ixGC_CAC_ACC_PC0 0x0061 +#define ixGC_CAC_ACC_SC0 0x0062 +#define ixGC_CAC_ACC_SPI0 0x0063 +#define ixGC_CAC_ACC_SPI1 0x0064 +#define ixGC_CAC_ACC_SPI2 0x0065 +#define ixGC_CAC_ACC_SPI3 0x0066 +#define ixGC_CAC_ACC_SPI4 0x0067 +#define ixGC_CAC_ACC_SPI5 0x0068 +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f +#define ixGC_CAC_ACC_EA0 0x0070 +#define ixGC_CAC_ACC_EA1 0x0071 +#define ixGC_CAC_ACC_EA2 0x0072 +#define ixGC_CAC_ACC_EA3 0x0073 +#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 +#define ixGC_CAC_OVRD_EA 0x0075 +#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 +#define ixGC_CAC_WEIGHT_EA_0 0x0077 +#define ixGC_CAC_WEIGHT_EA_1 0x0078 +#define ixGC_CAC_WEIGHT_RMI_0 0x0079 +#define ixGC_CAC_ACC_RMI0 0x007a +#define ixGC_CAC_OVRD_RMI 0x007b +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c +#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d +#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e +#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f +#define ixGC_CAC_ACC_EA4 0x0080 +#define ixGC_CAC_ACC_EA5 0x0081 +#define ixGC_CAC_WEIGHT_EA_2 0x0082 +#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 +#define ixGC_CAC_ACC_SQ0_UPPER 0x008a +#define ixGC_CAC_ACC_SQ1_LOWER 0x008b +#define ixGC_CAC_ACC_SQ1_UPPER 0x008c +#define ixGC_CAC_ACC_SQ2_LOWER 0x008d +#define ixGC_CAC_ACC_SQ2_UPPER 0x008e +#define ixGC_CAC_ACC_SQ3_LOWER 0x008f +#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 +#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 +#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 +#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 +#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 +#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 +#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 +#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 +#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 +#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 +#define ixGC_CAC_ACC_SQ8_UPPER 0x009a +#define ixGC_CAC_ACC_SX0 0x009b +#define ixGC_CAC_ACC_SXRB0 0x009c +#define ixGC_CAC_ACC_SXRB1 0x009d +#define ixGC_CAC_ACC_TA0 0x009e +#define ixGC_CAC_ACC_TCC0 0x009f +#define ixGC_CAC_ACC_TCC1 0x00a0 +#define ixGC_CAC_ACC_TCC2 0x00a1 +#define ixGC_CAC_ACC_TCC3 0x00a2 +#define ixGC_CAC_ACC_TCC4 0x00a3 +#define ixGC_CAC_ACC_TCP0 0x00a4 +#define ixGC_CAC_ACC_TCP1 0x00a5 +#define ixGC_CAC_ACC_TCP2 0x00a6 +#define ixGC_CAC_ACC_TCP3 0x00a7 +#define ixGC_CAC_ACC_TCP4 0x00a8 +#define ixGC_CAC_ACC_TD0 0x00a9 +#define ixGC_CAC_ACC_TD1 0x00aa +#define ixGC_CAC_ACC_TD2 0x00ab +#define ixGC_CAC_ACC_TD3 0x00ac +#define ixGC_CAC_ACC_TD4 0x00ad +#define ixGC_CAC_ACC_TD5 0x00ae +#define ixGC_CAC_ACC_VGT0 0x00af +#define ixGC_CAC_ACC_VGT1 0x00b0 +#define ixGC_CAC_ACC_VGT2 0x00b1 +#define ixGC_CAC_ACC_WD0 0x00b2 +#define ixGC_CAC_ACC_CU0 0x00ba +#define ixGC_CAC_ACC_CU1 0x00bb +#define ixGC_CAC_ACC_CU2 0x00bc +#define ixGC_CAC_ACC_CU3 0x00bd +#define ixGC_CAC_ACC_CU4 0x00be +#define ixGC_CAC_ACC_CU5 0x00bf +#define ixGC_CAC_ACC_CU6 0x00c0 +#define ixGC_CAC_ACC_CU7 0x00c1 +#define ixGC_CAC_ACC_CU8 0x00c2 +#define ixGC_CAC_ACC_CU9 0x00c3 +#define ixGC_CAC_ACC_CU10 0x00c4 +#define ixGC_CAC_ACC_CU11 0x00c5 +#define ixGC_CAC_ACC_CU12 0x00c6 +#define ixGC_CAC_ACC_CU13 0x00c7 +#define ixGC_CAC_OVRD_BCI 0x00da +#define ixGC_CAC_OVRD_CB 0x00db +#define ixGC_CAC_OVRD_CP 0x00dd +#define ixGC_CAC_OVRD_DB 0x00de +#define ixGC_CAC_OVRD_GDS 0x00e0 +#define ixGC_CAC_OVRD_IA 0x00e1 +#define ixGC_CAC_OVRD_LDS 0x00e2 +#define ixGC_CAC_OVRD_PA 0x00e3 +#define ixGC_CAC_OVRD_PC 0x00e4 +#define ixGC_CAC_OVRD_SC 0x00e5 +#define ixGC_CAC_OVRD_SPI 0x00e6 +#define ixGC_CAC_OVRD_CU 0x00e7 +#define ixGC_CAC_OVRD_SQ 0x00e8 +#define ixGC_CAC_OVRD_SX 0x00e9 +#define ixGC_CAC_OVRD_SXRB 0x00ea +#define ixGC_CAC_OVRD_TA 0x00eb +#define ixGC_CAC_OVRD_TCC 0x00ec +#define ixGC_CAC_OVRD_TCP 0x00ed +#define ixGC_CAC_OVRD_TD 0x00ee +#define ixGC_CAC_OVRD_VGT 0x00ef +#define ixGC_CAC_OVRD_WD 0x00f0 +#define ixGC_CAC_ACC_BCI1 0x00ff +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 +#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 +#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a +#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b +#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c +#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d +#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e +#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f +#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 +#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 +#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 +#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 +#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 +#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 +#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 +#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 +#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 +#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 +#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d +#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e +#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f +#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 +#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 +#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 +#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 +#define ixEDC_STALL_PATTERN_1_2 0x0130 +#define ixEDC_STALL_PATTERN_3_4 0x0131 +#define ixEDC_STALL_PATTERN_5_6 0x0132 +#define ixEDC_STALL_PATTERN_7 0x0133 +#define ixPCC_STALL_PATTERN_1_2 0x0134 +#define ixPCC_STALL_PATTERN_3_4 0x0135 +#define ixPCC_STALL_PATTERN_5_6 0x0136 +#define ixPCC_STALL_PATTERN_7 0x0137 +#define ixPCC_THROT_REINCR_FIRST_PATN_1_8 0x0138 +#define ixPCC_THROT_REINCR_FIRST_PATN_9_16 0x0139 +#define ixPCC_THROT_REINCR_FIRST_PATN_17_20 0x0140 +#define ixPCC_THROT_DECR_FIRST_PATN_1_4 0x0141 +#define ixPCC_THROT_DECR_FIRST_PATN_5_7 0x0142 +#define ixPWRBRK_STALL_PATTERN_CTRL 0x0143 +#define ixPWRBRK_STALL_PATTERN_1_2 0x0144 +#define ixPWRBRK_STALL_PATTERN_3_4 0x0145 +#define ixPWRBRK_STALL_PATTERN_5_6 0x0146 +#define ixPWRBRK_STALL_PATTERN_7 0x0147 +#define ixPCC_PWRBRK_HYSTERESIS_CTRL 0x0148 +#define ixFIXED_PATTERN_PERF_COUNTER_CTRL 0x015f +#define ixFIXED_PATTERN_PERF_COUNTER_1 0x0160 +#define ixFIXED_PATTERN_PERF_COUNTER_2 0x0161 +#define ixFIXED_PATTERN_PERF_COUNTER_3 0x0162 +#define ixFIXED_PATTERN_PERF_COUNTER_4 0x0163 +#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0164 +#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0165 +#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0166 +#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0167 +#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0168 +#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0169 + + +// addressBlock: secacind +// base address: 0x0 +#define ixSE_CAC_CNTL 0x0000 +#define ixSE_CAC_OVR_SEL 0x0001 +#define ixSE_CAC_OVR_VAL 0x0002 + + +// addressBlock: sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_VALID_AND_IDLE 0x000a +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_INST_DW0 0x001a +#define ixSQ_WAVE_INST_DW1 0x001b +#define ixSQ_WAVE_IB_DBG0 0x001c +#define ixSQ_WAVE_IB_DBG1 0x001d +#define ixSQ_WAVE_FLUSH_IB 0x001e +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027c +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f +#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..bc4d2997cb51e084ded0c9a75a3f85d5f6500968 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h @@ -0,0 +1,32949 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_9_4_2_SH_MASK_HEADER +#define _gc_9_4_2_SH_MASK_HEADER + + +// addressBlock: didtind +//DIDT_SQ_CTRL0 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b +#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L +#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L +//DIDT_SQ_CTRL2 +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +//DIDT_SQ_STALL_CTRL +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +//DIDT_SQ_TUNING_CTRL +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_SQ_STALL_AUTO_RELEASE_CTRL +#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_SQ_CTRL3 +#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_SQ_STALL_PATTERN_1_2 +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_SQ_STALL_PATTERN_3_4 +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_SQ_STALL_PATTERN_5_6 +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_SQ_STALL_PATTERN_7 +#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_SQ_MPD_SCALE_FACTOR +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L +#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L +//DIDT_SQ_THROTTLE_CNTL0 +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL +#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L +//DIDT_SQ_THROTTLE_CNTL1 +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L +#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L +//DIDT_SQ_THROTTLE_CNTL_STATUS +#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 +#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L +//DIDT_SQ_WEIGHT0_3 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_SQ_WEIGHT4_7 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_SQ_WEIGHT8_11 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_SQ_EDC_CTRL +#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 +#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L +//DIDT_SQ_THROTTLE_CTRL +#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 +#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 +#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 +#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L +#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L +#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L +//DIDT_SQ_EDC_STALL_PATTERN_1_2 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_SQ_EDC_STALL_PATTERN_3_4 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_SQ_EDC_STALL_PATTERN_5_6 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_SQ_EDC_STALL_PATTERN_7 +#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_SQ_EDC_STATUS +#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_SQ_EDC_STALL_DELAY_1 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x8 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x18 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000FFL +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000FF00L +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00FF0000L +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xFF000000L +//DIDT_SQ_EDC_STALL_DELAY_2 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x8 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x18 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000FFL +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000FF00L +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00FF0000L +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xFF000000L +//DIDT_SQ_EDC_STALL_DELAY_3 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x8 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x18 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000FFL +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000FF00L +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00FF0000L +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xFF000000L +//DIDT_SQ_EDC_STALL_DELAY_4 +#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x8 +#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000FFL +#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000FF00L +//DIDT_SQ_EDC_OVERFLOW +#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_SQ_EDC_ROLLING_POWER_DELTA +#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_DB_CTRL0 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b +#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c +#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L +#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L +//DIDT_DB_CTRL2 +#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +//DIDT_DB_STALL_CTRL +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +//DIDT_DB_TUNING_CTRL +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_DB_STALL_AUTO_RELEASE_CTRL +#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_DB_CTRL3 +#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_DB_STALL_PATTERN_1_2 +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_DB_STALL_PATTERN_3_4 +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_DB_STALL_PATTERN_5_6 +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_DB_STALL_PATTERN_7 +#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_DB_MPD_SCALE_FACTOR +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L +#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L +//DIDT_DB_THROTTLE_CNTL0 +#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 +#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 +#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 +#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd +#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L +#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L +#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL +#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L +//DIDT_DB_THROTTLE_CNTL1 +#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 +#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 +#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa +#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf +#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL +#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L +#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L +#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L +//DIDT_DB_THROTTLE_CNTL_STATUS +#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 +#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L +//DIDT_DB_WEIGHT0_3 +#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_DB_WEIGHT4_7 +#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_DB_WEIGHT8_11 +#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_DB_EDC_CTRL +#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 +#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L +//DIDT_DB_THROTTLE_CTRL +#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 +#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 +#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 +#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L +#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L +#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L +//DIDT_DB_EDC_STALL_PATTERN_1_2 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_DB_EDC_STALL_PATTERN_3_4 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_DB_EDC_STALL_PATTERN_5_6 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_DB_EDC_STALL_PATTERN_7 +#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_DB_EDC_STATUS +#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_DB_EDC_STALL_DELAY_1 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x6 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xc +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x12 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003FL +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000FC0L +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003F000L +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00FC0000L +//DIDT_DB_EDC_OVERFLOW +#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_DB_EDC_ROLLING_POWER_DELTA +#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_TD_CTRL0 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b +#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c +#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L +#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L +//DIDT_TD_CTRL2 +#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +//DIDT_TD_STALL_CTRL +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +//DIDT_TD_TUNING_CTRL +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_TD_STALL_AUTO_RELEASE_CTRL +#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_TD_CTRL3 +#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_TD_STALL_PATTERN_1_2 +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_TD_STALL_PATTERN_3_4 +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_TD_STALL_PATTERN_5_6 +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_TD_STALL_PATTERN_7 +#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_TD_MPD_SCALE_FACTOR +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L +#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L +//DIDT_TD_THROTTLE_CNTL0 +#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 +#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 +#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 +#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd +#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L +#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L +#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL +#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L +//DIDT_TD_THROTTLE_CNTL1 +#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 +#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 +#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa +#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf +#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL +#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L +#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L +#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L +//DIDT_TD_THROTTLE_CNTL_STATUS +#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 +#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L +//DIDT_TD_WEIGHT0_3 +#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_TD_WEIGHT4_7 +#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_TD_WEIGHT8_11 +#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_TD_EDC_CTRL +#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 +#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L +//DIDT_TD_THROTTLE_CTRL +#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 +#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 +#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 +#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L +#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L +#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L +//DIDT_TD_EDC_STALL_PATTERN_1_2 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_TD_EDC_STALL_PATTERN_3_4 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_TD_EDC_STALL_PATTERN_5_6 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_TD_EDC_STALL_PATTERN_7 +#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_TD_EDC_STATUS +#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_TD_EDC_STALL_DELAY_1 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x8 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x18 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000FFL +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000FF00L +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00FF0000L +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xFF000000L +//DIDT_TD_EDC_STALL_DELAY_2 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x8 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x18 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000FFL +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000FF00L +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00FF0000L +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xFF000000L +//DIDT_TD_EDC_STALL_DELAY_3 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x8 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x18 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000FFL +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000FF00L +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00FF0000L +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xFF000000L +//DIDT_TD_EDC_STALL_DELAY_4 +#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x8 +#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000FFL +#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000FF00L +//DIDT_TD_EDC_OVERFLOW +#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_TD_EDC_ROLLING_POWER_DELTA +#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_TCP_CTRL0 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b +#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L +#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L +//DIDT_TCP_CTRL2 +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +//DIDT_TCP_STALL_CTRL +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +//DIDT_TCP_TUNING_CTRL +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_TCP_STALL_AUTO_RELEASE_CTRL +#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_TCP_CTRL3 +#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_TCP_STALL_PATTERN_1_2 +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_TCP_STALL_PATTERN_3_4 +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_TCP_STALL_PATTERN_5_6 +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_TCP_STALL_PATTERN_7 +#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_TCP_MPD_SCALE_FACTOR +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L +#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L +//DIDT_TCP_THROTTLE_CNTL0 +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL +#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L +//DIDT_TCP_THROTTLE_CNTL1 +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L +#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L +//DIDT_TCP_THROTTLE_CNTL_STATUS +#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 +#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L +//DIDT_TCP_WEIGHT0_3 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_TCP_WEIGHT4_7 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_TCP_WEIGHT8_11 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_TCP_EDC_CTRL +#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 +#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L +//DIDT_TCP_THROTTLE_CTRL +#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 +#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 +#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 +#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L +#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L +#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L +//DIDT_TCP_EDC_STALL_PATTERN_1_2 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_TCP_EDC_STALL_PATTERN_3_4 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_TCP_EDC_STALL_PATTERN_5_6 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_TCP_EDC_STALL_PATTERN_7 +#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_TCP_EDC_STATUS +#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_TCP_EDC_STALL_DELAY_1 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x8 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x18 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000FFL +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000FF00L +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00FF0000L +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xFF000000L +//DIDT_TCP_EDC_STALL_DELAY_2 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x8 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x18 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000FFL +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000FF00L +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00FF0000L +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xFF000000L +//DIDT_TCP_EDC_STALL_DELAY_3 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x8 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x18 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000FFL +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000FF00L +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00FF0000L +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xFF000000L +//DIDT_TCP_EDC_STALL_DELAY_4 +#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x8 +#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000FFL +#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000FF00L +//DIDT_TCP_EDC_OVERFLOW +#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_TCP_EDC_ROLLING_POWER_DELTA +#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_SQ_STALL_EVENT_COUNTER +#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DB_STALL_EVENT_COUNTER +#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TD_STALL_EVENT_COUNTER +#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TCP_STALL_EVENT_COUNTER +#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DBR_STALL_EVENT_COUNTER +#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_SQ_EDC_PCC_PERF_COUNTER +#define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 +#define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TD_EDC_PCC_PERF_COUNTER +#define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 +#define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TCP_EDC_PCC_PERF_COUNTER +#define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 +#define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DB_EDC_PCC_PERF_COUNTER +#define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 +#define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DBR_EDC_PCC_PERF_COUNTER +#define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 +#define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_SQ_CTRL1 +#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_SQ_EDC_THRESHOLD +#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_DB_CTRL1 +#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_DB_EDC_THRESHOLD +#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_TD_CTRL1 +#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_TD_EDC_THRESHOLD +#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_TCP_CTRL1 +#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_TCP_EDC_THRESHOLD +#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL + + +// addressBlock: gc_cpdec +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_CPC_PRIV_VIOLATION_ADDR +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MEC_ME2_HEADER_DUMP +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_CE_COMPARE_COUNT +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_DE_COUNT +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_CE_COUNT +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_LAST_INVAL_COUNT +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL +//CP_DE_DE_COUNT +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +//CP_STAT +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_CE_HEADER_DUMP +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CE_INSTR_PNTR +#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC1_INSTR_PNTR +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC2_INSTR_PNTR +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_ROQ_THRESHOLDS +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L +//CP_MEQ_STQ_THRESHOLD +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL +//CP_RB2_RPTR +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB1_RPTR +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_CEQ1_AVAIL +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L +//CP_CEQ2_AVAIL +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL +//CP_CE_ROQ_RB_STAT +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_CE_ROQ_IB1_STAT +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_CE_ROQ_IB2_STAT +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +//CP_PRIV_VIOLATION_ADDR +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL + + +// addressBlock: gc_cppdec +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 +#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +//CP_GFX_ERROR +#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 +#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f +#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L +#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//CP_INT_CNTL +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE1_PRIORITY +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING1_PRIORITY +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE2_PRIORITY +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING2_PRIORITY +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_ME0_PIPE1_VMID +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR_HI +#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB2_WPTR +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CP_RB1_BASE +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB1_CNTL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB1_RPTR_ADDR +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB1_RPTR_ADDR_HI +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB2_BASE +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB2_CNTL +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB2_RPTR_ADDR +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB2_RPTR_ADDR_HI +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING1 +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING2 +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING1 +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING2 +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_ME_F32_INTERRUPT +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L +//CP_PFP_F32_INTERRUPT +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L +//CP_CE_F32_INTERRUPT +#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x1 +#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x2 +#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x3 +#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L +#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L +#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L +//CP_MEC1_F32_INTERRUPT +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INTERRUPT +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +//CP_MEM_SLP_CNTL +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//CP_ECC_DMA_FIRST_OCCURRENCE +#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE_MASK 0x00007000L +#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING1 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING2 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE0_INT_CNTL +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE1_INT_CNTL +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE2_INT_CNTL +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE3_INT_CNTL +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE0_INT_STATUS +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE1_INT_STATUS +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE2_INT_STATUS +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE3_INT_STATUS +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT 0x2 +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK 0x00000004L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE_PRIORITY_CNTS +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME2_PIPE0_PRIORITY +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE1_PRIORITY +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE2_PRIORITY +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE3_PRIORITY +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_CE_PRGRM_CNTR_START +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_MEC2_PRGRM_CNTR_START +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_CE_INTR_ROUTINE_START +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_MEC2_INTR_ROUTINE_START +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_RB1_BASE_HI +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT 0x6 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK 0x00000040L +//CP_MEC1_F32_INT_DIS +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INT_DIS +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L + + +// addressBlock: gc_cppdec2 +//CP_RB_DOORBELL_CONTROL_SCH_0 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_1 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_3 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_4 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_5 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_6 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_7 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CPF_EDC_TAG_CNT +#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 +#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 +#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L +#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL +//CPF_EDC_ROQ_CNT +#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0 +#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2 +#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4 +#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6 +#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L +#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL +#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L +#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L +//CPG_EDC_TAG_CNT +#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 +#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 +#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L +#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL +//CPG_EDC_DMA_CNT +#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0 +#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2 +#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4 +#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6 +#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L +#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL +#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L +#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L +//CPC_EDC_SCRATCH_CNT +#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0 +#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2 +#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L +#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL +//CPC_EDC_UCODE_CNT +#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0 +#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2 +#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L +#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL +//DC_EDC_STATE_CNT +#define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0 +#define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2 +#define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L +#define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL +//DC_EDC_CSINVOC_CNT +#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0 +#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2 +#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4 +#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6 +#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L +#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL +#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L +#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L +//DC_EDC_RESTORE_CNT +#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0 +#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2 +#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4 +#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6 +#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L +#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL +#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L +#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L +//CP_CPF_DSM_CNTL +#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//CP_CPG_DSM_CNTL +#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//CP_CPC_DSM_CNTL +#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT 0xc +#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT 0xf +#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//CP_CPF_DSM_CNTL2 +#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK 0x00000100L +//CP_CPG_DSM_CNTL2 +#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK 0x00000100L +//CP_CPC_DSM_CNTL2 +#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT 0xb +#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT 0xc +#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT 0xe +#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT 0xf +#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT 0x11 +#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT 0x14 +#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT 0x17 +#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT 0x1a +#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK 0x00000100L +#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK 0x00000800L +#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK 0x00004000L +#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK 0x00020000L +#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK 0x00100000L +#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK 0x00800000L +#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK 0x04000000L +//CP_CPF_DSM_CNTL2A +#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT 0x0 +#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK 0x0000003FL +//CP_CPG_DSM_CNTL2A +#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT 0x0 +#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK 0x0000003FL +//CP_CPC_DSM_CNTL2A +#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT 0x0 +#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK 0x0000003FL +//CP_EDC_FUE_CNTL +#define CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT 0x0 +#define CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT 0x1 +#define CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT 0x2 +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT 0x3 +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT 0x4 +#define CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT 0x5 +#define CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT 0x6 +#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT 0x7 +#define CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT 0x10 +#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT 0x11 +#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT 0x12 +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT 0x13 +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT 0x14 +#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT 0x15 +#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT 0x16 +#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT 0x17 +#define CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK 0x00000001L +#define CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK 0x00000002L +#define CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK 0x00000004L +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK 0x00000008L +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK 0x00000010L +#define CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK 0x00000020L +#define CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK 0x00000040L +#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK 0x00000080L +#define CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK 0x00010000L +#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK 0x00020000L +#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK 0x00040000L +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK 0x00080000L +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK 0x00100000L +#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK 0x00200000L +#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK 0x00400000L +#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK 0x00800000L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 +#define CP_SD_CNTL__WD_EN__SHIFT 0x5 +#define CP_SD_CNTL__IA_EN__SHIFT 0x6 +#define CP_SD_CNTL__PA_EN__SHIFT 0x7 +#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L +#define CP_SD_CNTL__WD_EN_MASK 0x00000020L +#define CP_SD_CNTL__IA_EN_MASK 0x00000040L +#define CP_SD_CNTL__PA_EN_MASK 0x00000080L +#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: gc_cpphqddec +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_SEMA_CMD +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL +#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x07FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x07FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL + + + + +// addressBlock: gc_didtdec +//DIDT_IND_INDEX +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL +//DIDT_IND_DATA +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL +//DIDT_INDEX_AUTO_INCR_EN +#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 +#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L + + +// addressBlock: gc_ea_gceadec +//GCEA_DRAM_RD_CLI2GRP_MAP0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_CLI2GRP_MAP1 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP1 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_GRP2VC_MAP +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_WR_GRP2VC_MAP +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_RD_LAZY +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_WR_LAZY +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_RD_CAM_CNTL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_WR_CAM_CNTL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_PAGE_BURST +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_AGE +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_WR_PRI_AGE +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_RD_PRI_QUEUING +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_QUEUING +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_FIXED +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_FIXED +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_URGENCY +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_WR_PRI_URGENCY +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_RD_PRI_QUANT_PRI1 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI2 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI3 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI1 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI2 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI3 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_ADDRNORM_BASE_ADDR0 +#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR0 +#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_BASE_ADDR1 +#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR1 +#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_OFFSET_ADDR1 +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//GCEA_ADDRNORM_BASE_ADDR2 +#define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR2 +#define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_BASE_ADDR3 +#define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR3 +#define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_OFFSET_ADDR3 +#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//GCEA_ADDRNORM_MEGABASE_ADDR0 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_MEGALIMIT_ADDR0 +#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_MEGABASE_ADDR1 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_MEGALIMIT_ADDR1 +#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORMDRAM_HOLE_CNTL +#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//GCEA_ADDRNORMGMI_HOLE_CNTL +#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG +#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//GCEA_ADDRDEC_BANK_CFG +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//GCEA_ADDRDEC_MISC_CFG +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//GCEA_ADDRDECDRAM_HARVEST_ENABLE +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//GCEA_ADDRDECGMI_HARVEST_ENABLE +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//GCEA_ADDRDEC0_BASE_ADDR_CS0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS2 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS3 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_CS01 +#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_CS23 +#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_CFG_CS01 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC0_ADDR_CFG_CS23 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC0_ADDR_SEL_CS01 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC0_ADDR_SEL_CS23 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC0_ADDR_SEL2_CS01 +#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC0_ADDR_SEL2_CS23 +#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC0_COL_SEL_LO_CS01 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_LO_CS23 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_HI_CS01 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_HI_CS23 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC0_RM_SEL_CS01 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_CS23 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_SECCS01 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_SECCS23 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_BASE_ADDR_CS0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS2 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS3 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_CS01 +#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_CS23 +#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_CFG_CS01 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC1_ADDR_CFG_CS23 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC1_ADDR_SEL_CS01 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC1_ADDR_SEL_CS23 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC1_ADDR_SEL2_CS01 +#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC1_ADDR_SEL2_CS23 +#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC1_COL_SEL_LO_CS01 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_LO_CS23 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_HI_CS01 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_HI_CS23 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC1_RM_SEL_CS01 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_CS23 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_SECCS01 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_SECCS23 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC2_BASE_ADDR_CS0 +#define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_CS1 +#define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_CS2 +#define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_CS3 +#define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_SECCS0 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_SECCS1 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_SECCS2 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_BASE_ADDR_SECCS3 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_ADDR_MASK_CS01 +#define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_ADDR_MASK_CS23 +#define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_ADDR_MASK_SECCS01 +#define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_ADDR_MASK_SECCS23 +#define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC2_ADDR_CFG_CS01 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC2_ADDR_CFG_CS23 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//GCEA_ADDRDEC2_ADDR_SEL_CS01 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC2_ADDR_SEL_CS23 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC2_ADDR_SEL2_CS01 +#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC2_ADDR_SEL2_CS23 +#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//GCEA_ADDRDEC2_COL_SEL_LO_CS01 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC2_COL_SEL_LO_CS23 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC2_COL_SEL_HI_CS01 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC2_COL_SEL_HI_CS23 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC2_RM_SEL_CS01 +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC2_RM_SEL_CS23 +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC2_RM_SEL_SECCS01 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC2_RM_SEL_SECCS23 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRNORMDRAM_GLOBAL_CNTL +//GCEA_ADDRNORMGMI_GLOBAL_CNTL +//GCEA_ADDRNORM_MEGACONTROL_ADDR0 +#define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//GCEA_ADDRNORM_MEGACONTROL_ADDR1 +#define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//GCEA_ADDRNORMDRAM_MASKING +#define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//GCEA_ADDRNORMGMI_MASKING +#define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//GCEA_IO_RD_CLI2GRP_MAP0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_CLI2GRP_MAP1 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP1 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_COMBINE_FLUSH +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//GCEA_IO_WR_COMBINE_FLUSH +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//GCEA_IO_GROUP_BURST +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_IO_RD_PRI_AGE +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_WR_PRI_AGE +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_RD_PRI_QUEUING +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_QUEUING +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_FIXED +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_FIXED +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_URGENCY +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_WR_PRI_URGENCY +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_RD_PRI_URGENCY_MASKING +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_WR_PRI_URGENCY_MASKING +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_RD_PRI_QUANT_PRI1 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI2 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI3 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI1 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI2 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI3 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_MISC +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//GCEA_LATENCY_SAMPLING +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//GCEA_PERFCOUNTER_LO +#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER_HI +#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCEA_PERFCOUNTER0_CFG +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER1_CFG +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L + + +// addressBlock: gc_ea_gceadec2 +//GCEA_PERFCOUNTER_RSLT_CNTL +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCEA_EDC_CNT +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//GCEA_EDC_CNT2 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//GCEA_DSM_CNTL +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//GCEA_DSM_CNTLA +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//GCEA_DSM_CNTLB +//GCEA_DSM_CNTL2 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//GCEA_DSM_CNTL2A +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//GCEA_DSM_CNTL2B +//GCEA_TCC_XBR_CREDITS +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L +//GCEA_TCC_XBR_MAXBURST +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 +#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 +#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL +#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L +#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L +//GCEA_PROBE_CNTL +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L +//GCEA_PROBE_MAP +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf +#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L +#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L +//GCEA_ERR_STATUS +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +//GCEA_MISC2 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd +#define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe +#define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L +#define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L +#define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L +//GCEA_DRAM_BANK_ARB +#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0 +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1 +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x9 +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xf +#define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX__SHIFT 0x10 +#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000001FEL +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00007E00L +#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00008000L +#define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX_MASK 0x00010000L +//GCEA_ADDRDEC_SELECT +#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//GCEA_EDC_CNT3 +#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0x1e +#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK 0x30000000L +#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0xC0000000L + +// addressBlock: gc_ea_pwrdec +//GCEA_CGTT_CLK_CTRL +#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L + + +// addressBlock: gc_gccacdec +//GC_CAC_CTRL_1 +#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 +#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL +#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L +//GC_CAC_CTRL_2 +#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2 +#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3 +#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L +#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L +//GC_CAC_INDEX_AUTO_INCR_EN +#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x0 +#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000001L +//GC_CAC_AGGR_LOWER +#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 +#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_UPPER +#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 +#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL +//GC_EDC_PERF_COUNTER +#define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 +#define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PCC_PERF_COUNTER +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_CAC_SOFT_CTRL +#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 +#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L +//GC_DIDT_CTRL0 +#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 +#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 +#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L +#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L +//GC_DIDT_CTRL1 +#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 +#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 +#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//GC_DIDT_CTRL2 +#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +//GC_DIDT_WEIGHT +#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 +#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 +#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 +#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 +#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL +#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L +#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L +#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L +//GC_THROTTLE_CTRL1 +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN__SHIFT 0xd +#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE__SHIFT 0xe +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x11 +#define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN__SHIFT 0x13 +#define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN__SHIFT 0x14 +#define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE__SHIFT 0x15 +#define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL__SHIFT 0x16 +#define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN__SHIFT 0x17 +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x18 +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN_MASK 0x00002000L +#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE_MASK 0x0001C000L +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x00060000L +#define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN_MASK 0x00080000L +#define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN_MASK 0x00100000L +#define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE_MASK 0x00200000L +#define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL_MASK 0x00400000L +#define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN_MASK 0x00800000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x07000000L +//GC_EDC_CTRL +#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 +#define GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT 0xb +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xc +#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x10 +#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0x14 +#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0x1e +#define GC_EDC_CTRL__PCC_DITHER_MODE__SHIFT 0x1f +#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L +#define GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000800L +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x0000F000L +#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x000F0000L +#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK 0x3FF00000L +#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x40000000L +#define GC_EDC_CTRL__PCC_DITHER_MODE_MASK 0x80000000L +//GC_EDC_THRESHOLD +#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//GC_EDC_STATUS +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 +#define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX__SHIFT 0x3 +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L +#define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX_MASK 0x000001F8L +//GC_EDC_OVERFLOW +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//GC_EDC_ROLLING_POWER_DELTA +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//GC_EDC_CTRL1 +#define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL__SHIFT 0x0 +#define GC_EDC_CTRL1__THROTTLE_SRC0_MASK__SHIFT 0x4 +#define GC_EDC_CTRL1__THROTTLE_SRC1_MASK__SHIFT 0x5 +#define GC_EDC_CTRL1__THROTTLE_SRC2_MASK__SHIFT 0x6 +#define GC_EDC_CTRL1__THROTTLE_SRC3_MASK__SHIFT 0x7 +#define GC_EDC_CTRL1__THROTTLE_SRC4_MASK__SHIFT 0x8 +#define GC_EDC_CTRL1__THROTTLE_SRC5_MASK__SHIFT 0x9 +#define GC_EDC_CTRL1__THROTTLE_SRC6_MASK__SHIFT 0xa +#define GC_EDC_CTRL1__THROTTLE_SRC7_MASK__SHIFT 0xb +#define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL_MASK 0x0000000FL +#define GC_EDC_CTRL1__THROTTLE_SRC0_MASK_MASK 0x00000010L +#define GC_EDC_CTRL1__THROTTLE_SRC1_MASK_MASK 0x00000020L +#define GC_EDC_CTRL1__THROTTLE_SRC2_MASK_MASK 0x00000040L +#define GC_EDC_CTRL1__THROTTLE_SRC3_MASK_MASK 0x00000080L +#define GC_EDC_CTRL1__THROTTLE_SRC4_MASK_MASK 0x00000100L +#define GC_EDC_CTRL1__THROTTLE_SRC5_MASK_MASK 0x00000200L +#define GC_EDC_CTRL1__THROTTLE_SRC6_MASK_MASK 0x00000400L +#define GC_EDC_CTRL1__THROTTLE_SRC7_MASK_MASK 0x00000800L +//GC_THROTTLE_CTRL2 +#define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP_MASK 0x000003E0L +//PWRBRK_PERF_COUNTER +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_THROTTLE_CTRL +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 +#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x2 +#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x3 +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x4 +#define GC_THROTTLE_CTRL__NON_DITHER__SHIFT 0x5 +#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x7 +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0x8 +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0x9 +#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa +#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT 0x14 +#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT 0x19 +#define GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT 0x1e +#define GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT 0x1f +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L +#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000004L +#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000008L +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000010L +#define GC_THROTTLE_CTRL__NON_DITHER_MASK 0x00000020L +#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000080L +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000100L +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000200L +#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK 0x000FFC00L +#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK 0x01F00000L +#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK 0x3E000000L +#define GC_THROTTLE_CTRL__INST_THROT_INCR_MASK 0x40000000L +#define GC_THROTTLE_CTRL__INST_THROT_DECR_MASK 0x80000000L +//GC_CAC_IND_INDEX +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//GC_CAC_IND_DATA +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL +//SE_CAC_IND_INDEX +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//SE_CAC_IND_DATA +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL + + + + +// addressBlock: gc_gdsdec +//GDS_CONFIG +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT 0x9 +#define GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT 0xb +#define GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT 0xd +#define GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT 0xf +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L +#define GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK 0x00000600L +#define GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK 0x00001800L +#define GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK 0x00006000L +#define GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK 0x00018000L +//GDS_CNTL_STATUS +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe +#define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xf +#define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0x10 +#define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0x11 +#define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x12 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L +#define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00008000L +#define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00010000L +#define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00020000L +#define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00040000L +//GDS_ENHANCE2 +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT 0x10 +#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT 0x11 +#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT 0x12 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x13 +#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK 0x00010000L +#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK 0x00020000L +#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK 0x00040000L +#define GDS_ENHANCE2__UNUSED_MASK 0xFFF80000L +//GDS_PROTECTION_FAULT +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_VM_PROTECTION_FAULT +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L +#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_EDC_CNT +#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 +#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 +#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L +#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L +//GDS_EDC_GRBM_CNT +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 +#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 +#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L +#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL +#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L +//GDS_EDC_OA_DED +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L +//GDS_DSM_CNTL +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//GDS_EDC_OA_PHY_CNT +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L +//GDS_EDC_OA_PIPE_CNT +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe +#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L +#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_DSM_CNTL2 +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L +//GDS_WD_GDS_CSB +#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 +#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd +#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL +#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L + + +// addressBlock: gc_gdspdec +//GDS_VMID0_BASE +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID0_SIZE +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID1_BASE +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID1_SIZE +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID2_BASE +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID2_SIZE +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID3_BASE +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID3_SIZE +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID4_BASE +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID4_SIZE +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID5_BASE +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID5_SIZE +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID6_BASE +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID6_SIZE +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID7_BASE +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID7_SIZE +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID8_BASE +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID8_SIZE +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID9_BASE +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID9_SIZE +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID10_BASE +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID10_SIZE +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID11_BASE +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID11_SIZE +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID12_BASE +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID12_SIZE +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID13_BASE +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID13_SIZE +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID14_BASE +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID14_SIZE +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID15_BASE +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID15_SIZE +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_GWS_VMID0 +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID1 +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID2 +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID3 +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID4 +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID5 +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID6 +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID7 +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID8 +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID9 +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID10 +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID11 +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID12 +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID13 +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID14 +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID15 +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L +//GDS_OA_VMID0 +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID1 +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID2 +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID3 +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID4 +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID5 +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID6 +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID7 +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID8 +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID9 +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID10 +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID11 +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID12 +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID13 +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID14 +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID15 +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L +//GDS_GWS_RESET0 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L +//GDS_GWS_RESET1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L +//GDS_GWS_RESOURCE_RESET +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GDS_OA_RESET_MASK +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L +//GDS_OA_RESET +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_OA_RESET__RESET_MASK 0x00000001L +#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L +//GDS_ENHANCE +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 +#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 +#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17 +#define GDS_ENHANCE__UNUSED__SHIFT 0x18 +#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L +#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L +#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L +#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L +#define GDS_ENHANCE__UNUSED_MASK 0xFF000000L +//GDS_OA_CGPG_RESTORE +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L +//GDS_CS_CTXSW_STATUS +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_CS_CTXSW_CNT0 +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT1 +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT2 +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT3 +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GFX_CTXSW_STATUS +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_VS_CTXSW_CNT0 +#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT1 +#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT2 +#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT3 +#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT0 +#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT1 +#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT2 +#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT3 +#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT0 +#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT1 +#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT2 +#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT3 +#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT0 +#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT1 +#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT2 +#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT3 +#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT0 +#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT1 +#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT2 +#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT3 +#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT0 +#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT1 +#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT2 +#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT3 +#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT0 +#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT1 +#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT2 +#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT3 +#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT0 +#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT1 +#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT2 +#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT3 +#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT0 +#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT1 +#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT2 +#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT3 +#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT0 +#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT1 +#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT2 +#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT3 +#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L + + +// addressBlock: gc_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +//DB_HTILE_DATA_BASE +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_HTILE_DATA_BASE_HI +#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DEPTH_SIZE +#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL +#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_STENCIL_CLEAR +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL +//DB_DEPTH_CLEAR +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_Z_INFO__MAXMIP__SHIFT 0x10 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DFSM_CONTROL +#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 +#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L +//DB_Z_INFO2 +#define DB_Z_INFO2__EPITCH__SHIFT 0x0 +#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL +//DB_STENCIL_INFO2 +#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 +#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//PA_SC_RIGHT_VERT_GRID +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_LEFT_VERT_GRID +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_HORIZ_GRID +#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 +#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 +#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 +#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 +#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL +#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L +#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L +#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//CB_DCC_CONTROL +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd +#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L +#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_STENCILREFMASK +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L +//DB_STENCILREFMASK_BF +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_PROG_NEAR_CLIP_Z +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_VS_OUT_CONFIG +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//SX_PS_DOWNCONVERT +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL +#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L +#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L +#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L +#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L +#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L +#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L +//SX_BLEND_OPT_EPSILON +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L +//SX_BLEND_OPT_CONTROL +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L +//SX_MRT0_BLEND_OPT +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT1_BLEND_OPT +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT2_BLEND_OPT +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT3_BLEND_OPT +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT4_BLEND_OPT +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT5_BLEND_OPT +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT6_BLEND_OPT +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT7_BLEND_OPT +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_MRT0_EPITCH +#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT1_EPITCH +#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT2_EPITCH +#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT3_EPITCH +#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT4_EPITCH +#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT5_EPITCH +#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT6_EPITCH +#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT7_EPITCH +#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL +//CS_COPY_STATE +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +//DB_EQAA +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +//PA_CL_OBJPRIM_ID_CNTL +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_STEREO_CNTL +#define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0 +#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 +#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 +#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 +#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa +#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd +#define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L +#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL +#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L +#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L +#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L +#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +//VGT_OUTPUT_PATH_CNTL +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L +//VGT_HOS_CNTL +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_REUSE_DEPTH +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL +//VGT_GROUP_PRIM_TYPE +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L +//VGT_GROUP_FIRST_DECR +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL +//VGT_GROUP_DECR +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL +//VGT_GROUP_VECT_0_CNTL +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_1_CNTL +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_0_FMT_CNTL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GROUP_VECT_1_FMT_CNTL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GS_MODE +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe +#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf +#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_MODE__MODE_MASK 0x00000007L +#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L +#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L +#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L +#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L +#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L +#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L +#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L +#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L +//VGT_GS_ONCHIP_CNTL +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_GS_PER_ES +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL +//VGT_ES_PER_GS +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL +//VGT_GS_PER_VS +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL +//VGT_GSVS_RING_OFFSET_1 +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_2 +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_3 +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L +//IA_ENHANCE +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +//WD_ENHANCE +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_GS_MAX_PRIMS_PER_SUBGROUP +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L +//VGT_INSTANCE_STEP_RATE_0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL +//VGT_INSTANCE_STEP_RATE_1 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL +//IA_MULTI_VGT_PARAM_BC +//VGT_ESGS_RING_ITEMSIZE +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GSVS_RING_ITEMSIZE +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//VGT_VTX_CNT_EN +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 +#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L +#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +//DB_PRELOAD_CONTROL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L +//VGT_STRMOUT_BUFFER_SIZE_0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_1 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_1 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_1 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_2 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_2 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_2 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_3 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_3 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_3 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L +//VGT_GS_VERT_ITEMSIZE +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_1 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_2 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_3 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//VGT_DISPATCH_DRAW_INDEX +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL +//VGT_STRMOUT_CONFIG +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L +//VGT_STRMOUT_BUFFER_CONFIG +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L +//VGT_DMA_EVENT_INITIATOR +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +//VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL +//VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR0_DCC_CONTROL +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR0_CMASK +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_CMASK_BASE_EXT +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_FMASK +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_FMASK_BASE_EXT +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_CLEAR_WORD0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR0_CLEAR_WORD1 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE_EXT +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR1_DCC_CONTROL +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR1_CMASK +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_CMASK_BASE_EXT +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_FMASK +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_FMASK_BASE_EXT +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_CLEAR_WORD0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR1_CLEAR_WORD1 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE_EXT +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR2_DCC_CONTROL +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR2_CMASK +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_CMASK_BASE_EXT +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_FMASK +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_FMASK_BASE_EXT +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_CLEAR_WORD0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR2_CLEAR_WORD1 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE_EXT +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR3_DCC_CONTROL +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR3_CMASK +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_CMASK_BASE_EXT +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_FMASK +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_FMASK_BASE_EXT +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_CLEAR_WORD0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR3_CLEAR_WORD1 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE_EXT +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR4_DCC_CONTROL +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR4_CMASK +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_CMASK_BASE_EXT +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_FMASK +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_FMASK_BASE_EXT +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_CLEAR_WORD0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR4_CLEAR_WORD1 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE_EXT +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR5_DCC_CONTROL +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR5_CMASK +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_CMASK_BASE_EXT +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_FMASK +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_FMASK_BASE_EXT +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_CLEAR_WORD0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR5_CLEAR_WORD1 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE_EXT +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR6_DCC_CONTROL +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR6_CMASK +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_CMASK_BASE_EXT +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_FMASK +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_FMASK_BASE_EXT +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_CLEAR_WORD0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR6_CLEAR_WORD1 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE_EXT +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR7_DCC_CONTROL +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR7_CMASK +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_CMASK_BASE_EXT +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_FMASK +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_FMASK_BASE_EXT +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_CLEAR_WORD0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR7_CLEAR_WORD1 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE_EXT +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL + + +// addressBlock: gc_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_STREAM_OUT_ADDR_LO +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL +//CP_STREAM_OUT_ADDR_HI +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_LO +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_HI +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_LO +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_HI +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_LO +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_HI +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_LO +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_HI +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_LO +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_HI +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_LO +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_HI +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_LO +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_HI +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_LO +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_HI +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STREAM_OUT_CONTROL +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STRMOUT_CNTL +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//SCRATCH_UMSK +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L +//SCRATCH_ADDR +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_LO +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_HI +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_LO +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_HI +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_LO +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_LO +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_HI +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_HI +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_LO +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_LO +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_HI +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_HI +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_SEM_WAIT_TIMER +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL +//CP_SIG_SEM_ADDR_LO +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_SIG_SEM_ADDR_HI +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_WAIT_SEM_ADDR_LO +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_WAIT_SEM_ADDR_HI +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_COHER_BASE_HI +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_COHER_START_DELAY +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL +//CP_COHER_CNTL +#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 +#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e +#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L +#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L +//CP_COHER_SIZE +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_COHER_BASE +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_COHER_STATUS +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_COHER_STATUS__MEID_MASK 0x03000000L +#define CP_COHER_STATUS__STATUS_MASK 0x80000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_COHER_SIZE_HI +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_CE_IB1_OFFSET +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_CE_IB2_OFFSET +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_CE_COUNTER +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_RB_OFFSET +#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_CE_INIT_CMD_BUFSZ +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL +//CP_CE_IB1_CMD_BUFSZ +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_IB2_CMD_BUFSZ +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_INIT_BASE_LO +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L +//CP_CE_INIT_BASE_HI +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL +//CP_CE_INIT_BUFSZ +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL +//CP_CE_IB1_BASE_LO +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB1_BASE_HI +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB1_BUFSZ +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_CE_IB2_BASE_LO +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB2_BASE_HI +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB2_BUFSZ +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_CE_COMPLETION_STATUS +#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_CE_METADATA_BASE_ADDR +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_CE_METADATA_BASE_ADDR_HI +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_GDS_BKUP_ADDR +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_GDS_BKUP_ADDR_HI +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//VGT_GSVS_RING_SIZE +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//VGT_MULTI_PRIM_IB_RESET_EN +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_POS_BUF_BASE +#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 +#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_POS_BUF_BASE_HI +#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_CNTL_SB_BUF_BASE +#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_CNTL_SB_BUF_BASE_HI +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_INDEX_BUF_BASE +#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 +#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_INDEX_BUF_BASE_HI +#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//IA_MULTI_VGT_PARAM +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_STATE_STEREO_X +#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 +#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BASE +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_SIZE +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L +//SQ_THREAD_TRACE_PERF_MASK +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L +//SQ_THREAD_TRACE_MODE +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L +//SQ_THREAD_TRACE_BASE2 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL +//SQ_THREAD_TRACE_TOKEN_MASK2 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L +//SQ_THREAD_TRACE_HIWATER +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L +//SQ_THREAD_TRACE_CNTR +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__WRITEBACK__SHIFT 0x3 +#define SQC_CACHES__VOL__SHIFT 0x4 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__WRITEBACK_MASK 0x00000008L +#define SQC_CACHES__VOL_MASK 0x00000010L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//SQC_WRITEBACK +#define SQC_WRITEBACK__DWB__SHIFT 0x0 +#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 +#define SQC_WRITEBACK__DWB_MASK 0x00000001L +#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_ZPASS_COUNT_LOW +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_ZPASS_COUNT_HI +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL +//GDS_RD_ADDR +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_DATA +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL +//GDS_RD_BURST_ADDR +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_BURST_COUNT +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL +//GDS_RD_BURST_DATA +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL +//GDS_WR_ADDR +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_DATA +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WR_BURST_ADDR +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_BURST_DATA +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WRITE_COMPLETE +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL +//GDS_ATOM_CNTL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L +//GDS_ATOM_COMPLETE +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL +//GDS_ATOM_BASE +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL +#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_SIZE +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL +#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_OFFSET0 +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_OFFSET1 +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_DST +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL +//GDS_ATOM_OP +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OP__OP_MASK 0x000000FFL +#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_SRC0 +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC0_U +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1 +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1_U +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0 +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0_U +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1 +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1_U +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL +//GDS_GWS_RESOURCE_CNTL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L +//GDS_GWS_RESOURCE +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xe +#define GDS_GWS_RESOURCE__DED__SHIFT 0xf +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x11 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e +#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00003FFEL +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00004000L +#define GDS_GWS_RESOURCE__DED_MASK 0x00008000L +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00010000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFE0000L +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L +#define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L +//GDS_GWS_RESOURCE_CNT +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_OA_CNTL +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL +#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L +//GDS_OA_COUNTER +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL +//GDS_OA_ADDRESS +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL +#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L +//GDS_OA_INCDEC +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L +//GDS_OA_RING_SIZE +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L +//SPI_WAVE_LIMIT_CNTL +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 +#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L +#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L + + +// addressBlock: gc_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L +#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L +#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L +#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__TA_BUSY_SE4__SHIFT 0x3 +#define GRBM_STATUS_SE0__SX_BUSY_SE4__SHIFT 0x4 +#define GRBM_STATUS_SE0__SPI_BUSY_SE4__SHIFT 0x5 +#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__TA_BUSY_SE4_MASK 0x00000008L +#define GRBM_STATUS_SE0__SX_BUSY_SE4_MASK 0x00000010L +#define GRBM_STATUS_SE0__SPI_BUSY_SE4_MASK 0x00000020L +#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__TA_BUSY_SE5__SHIFT 0x3 +#define GRBM_STATUS_SE1__SX_BUSY_SE5__SHIFT 0x4 +#define GRBM_STATUS_SE1__SPI_BUSY_SE5__SHIFT 0x5 +#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__TA_BUSY_SE5_MASK 0x00000008L +#define GRBM_STATUS_SE1__SX_BUSY_SE5_MASK 0x00000010L +#define GRBM_STATUS_SE1__SPI_BUSY_SE5_MASK 0x00000020L +#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_STATUS_SE2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__TA_BUSY_SE6__SHIFT 0x3 +#define GRBM_STATUS_SE2__SX_BUSY_SE6__SHIFT 0x4 +#define GRBM_STATUS_SE2__SPI_BUSY_SE6__SHIFT 0x5 +#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__TA_BUSY_SE6_MASK 0x00000008L +#define GRBM_STATUS_SE2__SX_BUSY_SE6_MASK 0x00000010L +#define GRBM_STATUS_SE2__SPI_BUSY_SE6_MASK 0x00000020L +#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE3 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__TA_BUSY_SE7__SHIFT 0x3 +#define GRBM_STATUS_SE3__SX_BUSY_SE7__SHIFT 0x4 +#define GRBM_STATUS_SE3__SPI_BUSY_SE7__SHIFT 0x5 +#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__TA_BUSY_SE7_MASK 0x00000008L +#define GRBM_STATUS_SE3__SX_BUSY_SE7_MASK 0x00000010L +#define GRBM_STATUS_SE3__SPI_BUSY_SE7_MASK 0x00000020L +#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_CHICKEN_BITS +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L +//GRBM_FENCE_RANGE0 +#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L +//GRBM_FENCE_RANGE1 +#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//VIOLATION_DATA_ASYNC_VF_PROG +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L + + +// addressBlock: gc_hypdec +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_CE_UCODE_ADDR +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_HYP_CE_UCODE_ADDR +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_CE_UCODE_DATA +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_CE_UCODE_DATA +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC2_UCODE_ADDR +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME2_UCODE_ADDR +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC2_UCODE_DATA +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME2_UCODE_DATA +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_HYP_CAM_INDEX +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_HYP_CAM_DATA +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_0 +#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_CTRL +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCV_TIMER_STAT +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L +//RLC_HYP_SEMAPHORE_0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_1 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 +#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 +#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7 +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 +#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT 0x9 +#define RLC_CLK_CNTL__RESERVED_11_10__SHIFT 0xa +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc +#define RLC_CLK_CNTL__RESERVED_1__SHIFT 0xe +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x13 +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL +#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L +#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L +#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L +#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L +#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK 0x00000200L +#define RLC_CLK_CNTL__RESERVED_11_10_MASK 0x00000C00L +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L +#define RLC_CLK_CNTL__RESERVED_1_MASK 0x0003C000L +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_ACTIVE_FCN_ID +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_STAT +#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_1 +#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_UCODE_ADDR +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_GPU_IOV_UCODE_DATA +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCRATCH_ADDR +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPU_IOV_SCRATCH_DATA +#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_F32_CNTL +#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_F32_RESET +#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 +#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L +#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_VIRT_RESET_REQ +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_DISABLE +#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_FORCE +#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPU_IOV_SDMA2_STATUS +#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA3_STATUS +#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA4_STATUS +#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA5_STATUS +#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA6_STATUS +#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA7_STATUS +#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA2_BUSY_STATUS +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_BUSY_STATUS +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_BUSY_STATUS +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_BUSY_STATUS +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_BUSY_STATUS +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_BUSY_STATUS +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: gc_padec +//VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L +//VGT_CACHE_INVALIDATION +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L +//VGT_STRMOUT_DELAY +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L +//VGT_FIFO_DEPTHS +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L +//VGT_GS_VERTEX_REUSE +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_CNTL_STATUS +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L +//VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L +//WD_CNTL_STATUS +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L +//CC_GC_PRIM_CONFIG +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//GC_USER_PRIM_CONFIG +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//WD_QOS +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x00000001L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//VGT_SYS_CONFIG +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +//VGT_VS_MAX_WAVE_ID +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//VGT_DMA_PRIMITIVE_TYPE +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_DMA_CONTROL +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 +#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L +#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L +#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L +//VGT_DMA_LS_HS_CONFIG +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +//WD_BUF_RESOURCE_1 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L +//WD_BUF_RESOURCE_2 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL +#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 +#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 +#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L +#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L +#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_ENHANCE_2 +#define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0 +#define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1 +#define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2 +#define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3 +#define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4 +#define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7 +#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8 +#define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L +#define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L +#define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L +#define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L +#define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L +#define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L +#define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_UTCL1_CNTL1 +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//PA_UTCL1_CNTL2 +#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 +#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd +#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b +#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL +#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L +#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L +//PA_SIDEBAND_REQUEST_DELAYS +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e +#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L +#define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L + + +// addressBlock: gc_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_LO +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_HI +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_LO +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_HI +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_LO +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_HI +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_LO +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_HI +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_LO +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_HI +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_LO +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_HI +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_LO +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_HI +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_LO +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_HI +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_LO +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_HI +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_LO +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_HI +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_LO +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_HI +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_LO +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_HI +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_LO +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_LO +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_LO +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_LO +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_HI +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_HI +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_HI +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_HI +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_LO +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_HI +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_LO +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_HI +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_LO +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_HI +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_LO +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_HI +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_LO +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_HI +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_LO +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_HI +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_LO +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_HI +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_LO +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_HI +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_LO +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_HI +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_LO +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_HI +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_LO +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_HI +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_LO +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_HI +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_LO +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_HI +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_LO +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_HI +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_LO +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_HI +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_LO +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_HI +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_LO +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_HI +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_LO +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_HI +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_LO +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_HI +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_LO +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_HI +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_SE0_PERFCOUNTER_SELECT +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x17 +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x18 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x19 +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4_MASK 0x00800000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4_MASK 0x01000000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4_MASK 0x02000000L +//GRBM_SE1_PERFCOUNTER_SELECT +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x17 +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x18 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x19 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5_MASK 0x00800000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5_MASK 0x01000000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5_MASK 0x02000000L +//GRBM_SE2_PERFCOUNTER_SELECT +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x17 +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x18 +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x19 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6_MASK 0x00800000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6_MASK 0x01000000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6_MASK 0x02000000L +//GRBM_SE3_PERFCOUNTER_SELECT +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x17 +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x18 +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x19 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7_MASK 0x00800000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7_MASK 0x01000000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7_MASK 0x02000000L +//WD_PERFCOUNTER0_SELECT +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER1_SELECT +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER2_SELECT +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER3_SELECT +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER1_SELECT +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER2_SELECT +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER3_SELECT +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT1 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT1 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT1 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER_SEID_MASK +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L +#define SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK 0xFFFF0000L +//SQ_PERFCOUNTER_MASK +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER1_SELECT +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER2_SELECT +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER3_SELECT +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT1 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT1 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT1 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER2_SELECT +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER3_SELECT +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT1 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT1 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER2_SELECT +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER3_SELECT +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_DB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_IA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TD_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SX_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL +//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SAMPLE_DELAY_MAX +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8 +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1__SHIFT 0x7 +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE__SHIFT 0xc +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE__SHIFT 0x11 +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE__SHIFT 0x16 +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE__SHIFT 0x1b +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1_MASK 0x0000007FL +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1_MASK 0x00000F80L +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE_MASK 0x0001F000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE_MASK 0x003E0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE_MASK 0x07C00000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE_MASK 0xF8000000L +//RLC_PERFMON_CLK_CNTL_UCODE +#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_PERFMON_CLK_CNTL +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L + + +// addressBlock: gc_pwrdec +//CGTS_SM_CTRL_REG +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L +//CGTS_RD_CTRL_REG +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L +//CGTS_RD_REG +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL +//CGTS_TCC_DISABLE +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_USER_TCC_DISABLE +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_TCC_DISABLE2 +#define CGTS_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10 +#define CGTS_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_USER_TCC_DISABLE2 +#define CGTS_USER_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_CU0_SP0_CTRL_REG +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_LDS_SQ_CTRL_REG +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TA_SQC_CTRL_REG +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_SP1_CTRL_REG +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_SP0_CTRL_REG +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_LDS_SQ_CTRL_REG +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_TA_SQC_CTRL_REG +#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU1_SP1_CTRL_REG +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_SP0_CTRL_REG +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_LDS_SQ_CTRL_REG +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_TA_SQC_CTRL_REG +#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_SP1_CTRL_REG +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_SP0_CTRL_REG +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_LDS_SQ_CTRL_REG +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_TA_SQC_CTRL_REG +#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU3_SP1_CTRL_REG +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_SP0_CTRL_REG +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_LDS_SQ_CTRL_REG +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_TA_SQC_CTRL_REG +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_SP1_CTRL_REG +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_SP0_CTRL_REG +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_LDS_SQ_CTRL_REG +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_TA_SQC_CTRL_REG +#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU5_SP1_CTRL_REG +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP0_CTRL_REG +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_LDS_SQ_CTRL_REG +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_TA_SQC_CTRL_REG +#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP1_CTRL_REG +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_SP0_CTRL_REG +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_LDS_SQ_CTRL_REG +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_TA_SQC_CTRL_REG +#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU7_SP1_CTRL_REG +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_SP0_CTRL_REG +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_LDS_SQ_CTRL_REG +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_TA_SQC_CTRL_REG +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_SP1_CTRL_REG +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_SP0_CTRL_REG +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_LDS_SQ_CTRL_REG +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_TA_SQC_CTRL_REG +#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU9_SP1_CTRL_REG +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_SP0_CTRL_REG +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_LDS_SQ_CTRL_REG +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_TA_SQC_CTRL_REG +#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_SP1_CTRL_REG +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_SP0_CTRL_REG +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_LDS_SQ_CTRL_REG +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_TA_SQC_CTRL_REG +#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU11_SP1_CTRL_REG +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP0_CTRL_REG +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_LDS_SQ_CTRL_REG +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_TA_SQC_CTRL_REG +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP1_CTRL_REG +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_SP0_CTRL_REG +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_LDS_SQ_CTRL_REG +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_TA_SQC_CTRL_REG +#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU13_SP1_CTRL_REG +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_SP0_CTRL_REG +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_LDS_SQ_CTRL_REG +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_TA_SQC_CTRL_REG +#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_SP1_CTRL_REG +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_SP0_CTRL_REG +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_LDS_SQ_CTRL_REG +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_TA_SQC_CTRL_REG +#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU15_SP1_CTRL_REG +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TCPI_CTRL_REG +#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU1_TCPI_CTRL_REG +#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU2_TCPI_CTRL_REG +#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU3_TCPI_CTRL_REG +#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU4_TCPI_CTRL_REG +#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU5_TCPI_CTRL_REG +#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU6_TCPI_CTRL_REG +#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU7_TCPI_CTRL_REG +#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU8_TCPI_CTRL_REG +#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU9_TCPI_CTRL_REG +#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU10_TCPI_CTRL_REG +#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU11_TCPI_CTRL_REG +#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU12_TCPI_CTRL_REG +#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU13_TCPI_CTRL_REG +#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU14_TCPI_CTRL_REG +#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU15_TCPI_CTRL_REG +#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTT_SPI_PS_CLK_CTRL +#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 +#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SPIS_CLK_CTRL +#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 +#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 +#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a +#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L +#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L +#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L +#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SPI_CLK_CTRL +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PC_CLK_CTRL +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_BCI_CLK_CTRL +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SC_CLK_CTRL2 +#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_POWER_THROTTLE +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L +//SQ_POWER_THROTTLE2 +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L +//CGTT_SX_CLK_CTRL0 +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL1 +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL2 +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL3 +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL4 +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L +//TD_CGTT_CTRL +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TA_CGTT_CTRL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCI_CLK_CTRL +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCI_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_GDS_CLK_CTRL +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCP_TCR_CLK_CTRL +#define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCP_TCR_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCP_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCI_TCR_CLK_CTRL +#define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_TCR_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCI_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCX_CGTT_SCLK_CTRL +#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L +//CB_CGTT_SCLK_CTRL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCC_CGTT_SCLK_CTRL +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCC_CGTT_SCLK_CTRL2 +#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +//TCC_CGTT_SCLK_CTRL3 +#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT 0xc +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT 0xd +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT 0xe +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT 0xf +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT 0x10 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT 0x11 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT 0x12 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT 0x13 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT 0x14 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT 0x15 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT 0x17 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK 0x00001000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK 0x00002000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK 0x00004000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK 0x00008000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK 0x00010000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK 0x00020000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK 0x00040000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK 0x00080000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK 0x00100000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK 0x00200000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK 0x00800000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +//TCA_CGTT_SCLK_CTRL +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPF_CLK_CTRL +#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//RLC_GFX_RM_CNTL +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 +#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L +#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RMI_CGTT_SCLK_CTRL +#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SE_CAC_CGTT_CLK_CTRL +#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG__SHIFT 0x1d +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG_MASK 0x20000000L +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//GC_CAC_CGTT_CLK_CTRL +#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//GRBM_CGTT_CLK_CNTL +#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L + + +// addressBlock: gc_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +//DB_DEBUG2 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__RESERVED__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a +#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L +#define DB_DEBUG2__RESERVED_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L +#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe +#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 +#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e +#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L +#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0x3FF80000L +#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L +#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L +//DB_SUBTILE_CONTROL +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_RMI_CACHE_POLICY +#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 +#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 +#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 +#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 +#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 +#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb +#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 +#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 +#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 +#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 +#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 +#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 +#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a +#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b +#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L +#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L +#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L +#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L +#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L +#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L +#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L +#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L +#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L +#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L +#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L +#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L +#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L +#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L +//DB_DFSM_CONFIG +#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 +#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 +#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 +#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L +#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L +#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L +//DB_DFSM_WATERMARK +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L +//DB_DFSM_TILES_IN_FLIGHT +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_PRIMS_IN_FLIGHT +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_WATCHDOG +#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 +#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL +//DB_DFSM_FLUSH_ENABLE +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L +//DB_DFSM_FLUSH_AUX_EVENT +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L +//CC_RB_REDUNDANCY +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L +//GB_ADDR_CONFIG +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//CC_RB_DAISY_CHAIN +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L +//GB_TILE_MODE0 +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE1 +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE2 +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE3 +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE4 +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE5 +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE6 +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE7 +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE8 +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE9 +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE10 +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE11 +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE12 +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE13 +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE14 +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE15 +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE16 +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE17 +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE18 +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE19 +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE20 +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE21 +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE22 +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE23 +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE24 +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE25 +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE26 +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE27 +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE28 +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE29 +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE30 +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE31 +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L +//GB_MACROTILE_MODE0 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE1 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE2 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE4 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE5 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE6 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE7 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE8 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE9 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE10 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE11 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE12 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE13 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE14 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE15 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L +//CB_HW_CONTROL +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L +#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L +//CB_HW_MEM_ARBITER_RD +#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_HW_MEM_ARBITER_WR +#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_DCC_CONFIG +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L +//GC_USER_RB_REDUNDANCY +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L + + +// addressBlock: gc_rlcpdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__RESERVED__SHIFT 0x4 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RESERVED__SHIFT 0x8 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L +//RLC_LB_CNTR_MAX +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK_1 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L +//RLC_SERDES_NONCU_MASTER_BUSY_1 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_LB_CNTL +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L +#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L +//RLC_LB_CNTR_INIT +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL +//RLC_LOAD_BALANCE_CNTR +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_CLK_COUNT_GFXCLK_LSB +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_MSB +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_LSB +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_MSB +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_CTRL +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L +//RLC_CLK_COUNT_STAT +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 +#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 +#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L +#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L +#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 +#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L +#define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT 0x9 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10__SHIFT 0xa +#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK 0x00000200L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10_MASK 0x0000FC00L +#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_CU_STATUS +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL +//RLC_LB_INIT_CU_MASK +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_ALWAYS_ACTIVE_CU_MASK +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_PARAMS +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_THREAD1_DELAY +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L +#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L +//RLC_PG_ALWAYS_ON_CU_MASK +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_CU +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL +#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SERDES_RD_PENDING +#define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0 +#define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L +//RLC_SERDES_RD_MASTER_INDEX +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_CU_MASTER_MASK +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L +//RLC_SERDES_WR_CTRL +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf +#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L +#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L +#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L +//RLC_SERDES_WR_DATA +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_CU_MASTER_BUSY +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL +//RLC_SERDES_NONCU_MASTER_BUSY +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_LOG_SIZE +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL +#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_LOG_CONT +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH1 +#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L +#define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L +#define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_RLCV_COMMAND +#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 +#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL +#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L +#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L +#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_RLCV_COMMAND_STATUS +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 +#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L +#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_1 +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_2 +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L +//RLC_LB_THR_CONFIG_2 +#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_3 +#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_4 +#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_LB_THR_CONFIG_1 +#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH1_ERROR_1 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH1_ERROR_2 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH2_ERROR_1 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH2_ERROR_2 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNT +#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL +//RLC_SPARE_INT +#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_PREWALKER_UTCL1_CNTL +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L +//RLC_PREWALKER_UTCL1_TRIG +#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 +#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f +#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L +#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L +#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L +//RLC_PREWALKER_UTCL1_ADDR_LSB +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_ADDR_MSB +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL +//RLC_PREWALKER_UTCL1_SIZE_LSB +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_SIZE_MSB +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L +//RLC_DSM_TRIG +#define RLC_DSM_TRIG__START__SHIFT 0x0 +#define RLC_DSM_TRIG__START_MASK 0x00000001L +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_UTCL2_CNTL +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_LBPW_CU_STAT +#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 +#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 +#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL +#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L +//RLC_DS_CNTL +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 +#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 +#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L +#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L +#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L +//RLC_GPM_INT_STAT_TH0 +#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 +#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_13 +#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_14 +#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_15 +#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_SPARE_INT_1 +#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_SPARE_INT_1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_SEMAPHORE_2 +#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_3 +#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPU_CLOCK_COUNT_LSB_1 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_1 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_CLOCK_COUNT_LSB_2 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_2 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_2 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_CPG_STAT_INVAL +#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0 +#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L +//RLC_EDC_CNT +#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT 0x0 +#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT 0x2 +#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 +#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 +#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT 0x8 +#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT 0xa +#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc +#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT 0xe +#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT 0x10 +#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT 0x12 +#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 +#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 +#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT 0x18 +#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT 0x1a +#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT 0x1c +#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT 0x1e +#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK 0x00000003L +#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK 0x0000000CL +#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L +#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L +#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK 0x00000300L +#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK 0x00000C00L +#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L +#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L +#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK 0x00030000L +#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK 0x000C0000L +#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L +#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L +#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK 0x03000000L +#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK 0x0C000000L +#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK 0x30000000L +#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK 0xC0000000L +//RLC_EDC_CNT2 +#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT 0x0 +#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT 0x2 +#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 +#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 +#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT 0x8 +#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT 0xa +#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc +#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT 0xe +#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT 0x10 +#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT 0x12 +#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 +#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 +#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT 0x18 +#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT 0x1a +#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT 0x1c +#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT 0x1e +#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK 0x00000003L +#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK 0x0000000CL +#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L +#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L +#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK 0x00000300L +#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK 0x00000C00L +#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L +#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L +#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK 0x00030000L +#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK 0x000C0000L +#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L +#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L +#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK 0x03000000L +#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK 0x0C000000L +#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK 0x30000000L +#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK 0xC0000000L +//RLC_DSM_CNTL +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +//RLC_DSM_CNTLA +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf +#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +//RLC_DSM_CNTL2 +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define RLC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define RLC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//RLC_DSM_CNTL2A +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: gc_rmi_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//RMI_UTC_UNIT_CONFIG +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_SPARE +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 +#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 +#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L +#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L +#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 +#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 +#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 +#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 +#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 +#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 +#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 +#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 +#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L +#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L +#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L +#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L +#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L +#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L +#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L +#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L +#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L +#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L + + +// addressBlock: gc_shdec +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_VS +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_LATE_ALLOC_VS +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL +//SPI_SHADER_PGM_LO_VS +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_VS +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_VS +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_VS +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_VS_0 +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_1 +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_2 +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_3 +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_4 +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_5 +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_6 +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_7 +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_8 +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_9 +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_10 +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_11 +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_12 +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_13 +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_14 +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_15 +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_16 +#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_17 +#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_18 +#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_19 +#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_20 +#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_21 +#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_22 +#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_23 +#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_24 +#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_25 +#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_26 +#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_27 +#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_28 +#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_29 +#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_30 +#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_31 +#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC2_GS_VS +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_ES_0 +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_1 +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_2 +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_3 +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_4 +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_5 +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_6 +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_7 +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_8 +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_9 +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_10 +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_11 +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_12 +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_13 +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_14 +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_15 +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_16 +#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_17 +#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_18 +#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_19 +#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_20 +#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_21 +#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_22 +#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_23 +#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_24 +#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_25 +#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_26 +#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_27 +#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_28 +#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_29 +#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_30 +#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_31 +#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_LS_0 +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_1 +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_2 +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_3 +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_4 +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_5 +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_6 +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_7 +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_8 +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_9 +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_10 +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_11 +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_12 +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_13 +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_14 +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_15 +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_16 +#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_17 +#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_18 +#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_19 +#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_20 +#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_21 +#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_22 +#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_23 +#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_24 +#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_25 +#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_26 +#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_27 +#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_28 +#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_29 +#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_30 +#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_31 +#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_1 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_2 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_3 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_4 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_5 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_6 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_7 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_8 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_9 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_10 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_11 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_12 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_13 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_14 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_15 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_16 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_17 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_18 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_19 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_20 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_21 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_22 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_23 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_24 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_25 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_26 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_27 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_28 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_29 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_30 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_31 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1__SHIFT 0x2 +#define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0__SHIFT 0x11 +#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1__SHIFT 0x12 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L +#define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1_MASK 0x0000000CL +#define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID_MASK 0x00000010L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0_MASK 0x00020000L +#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1_MASK 0x00040000L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE4 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE5 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE6 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE7 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_RESTART_X2 +#define COMPUTE_RESTART_X2__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X2__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y2 +#define COMPUTE_RESTART_Y2__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y2__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z2 +#define COMPUTE_RESTART_Z2__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z2__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_SHADER_CHKSUM +#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//COMPUTE_PGM_RSRC3 +#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT 0x0 +#define COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT 0x10 +#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC3__TG_SPLIT_MASK 0x00010000L +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_END +#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_shsdec +//SX_DEBUG_1 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L +#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_START_PHASE +#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 +#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 +#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 +#define SPI_START_PHASE__SPI_TD_GAP__SHIFT 0x6 +#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L +#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL +#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L +#define SPI_START_PHASE__SPI_TD_GAP_MASK 0x000003C0L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SPI_DSM_CNTL__UNUSED__SHIFT 0xf +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT 0xa +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT 0xc +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT 0xd +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT 0xf +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT 0x13 +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT 0x15 +#define SPI_DSM_CNTL2__UNUSED__SHIFT 0x16 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK 0x00000C00L +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK 0x00001000L +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK 0x00006000L +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK 0x00008000L +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK 0x00180000L +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK 0x00200000L +#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFC00000L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2 +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4 +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6 +#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8 +#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa +#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10 +#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12 +#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L +#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L +#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L +#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L +#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L +#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_1 +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_6 +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_7 +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_8 +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_9 +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_1 +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_3 +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_5 +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_8 +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_10 +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_12 +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_CU_MASK +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_CU_MASK +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_4 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_5 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_6 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_7 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x01FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_HSGS +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_VSPS +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_CS +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L + + +// addressBlock: gc_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x01L +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L +//SPI_GDBG_PER_VMID_CNTL +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x0001L +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x0006L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x0008L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x1FF0L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x2000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_GDBG_TRAP_DATA0 +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL +//SPI_GDBG_TRAP_DATA1 +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L + + +// addressBlock: gc_sqdec +//SQ_CONFIG +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0 +#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT 0x1 +#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT 0x2 +#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT 0x3 +#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x4 +#define SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT 0x5 +#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT 0x6 +#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L +#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK 0x00000002L +#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK 0x00000004L +#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK 0x00000008L +#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000010L +#define SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK 0x00000020L +#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK 0x00000040L +#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 +#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 +#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1d +#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT 0x1e +#define SQC_CONFIG__MEM_LS_DISABLE__SHIFT 0x1f +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L +#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x1F000000L +#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x20000000L +#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK 0x40000000L +#define SQC_CONFIG__MEM_LS_DISABLE_MASK 0x80000000L +//LDS_CONFIG +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 +#define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT 0x1 +#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2 +#define LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT 0x3 +#define LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT 0x4 +#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT 0x5 +#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT 0x6 +#define LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT 0x7 +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L +#define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK 0x00000002L +#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L +#define LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK 0x00000008L +#define LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK 0x00000010L +#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK 0x00000020L +#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK 0x00000040L +#define LDS_CONFIG__DISABLE_PHASE_FGCG_MASK 0x00000080L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L +//SQ_REG_CREDITS +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L +//SQ_DEBUG_STS_GLOBAL +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000FFF0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0FFF0000L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SQ_TIMEOUT_CONFIG +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0 +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6 +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L +//SQ_TIMEOUT_STATUS +#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 +#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc +#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L +#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L +#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L +//SP_MFMA_PORTD_RD_CONFIG +#define SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT 0x0 +#define SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT 0x1 +#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT 0x4 +#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT 0x9 +#define SP_MFMA_PORTD_RD_CONFIG__SET_MASK 0x00000001L +#define SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK 0x0000000EL +#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK 0x000001F0L +#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK 0x1FFFFE00L +//SH_CAC_CONFIG +#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x0 +#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x1 +#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT 0x2 +#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT 0x3 +#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT 0x4 +#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT 0x5 +#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT 0x6 +#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT 0x8 +#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT 0x9 +#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT 0x10 +#define SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT 0x14 +#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000001L +#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000002L +#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK 0x00000004L +#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK 0x00000008L +#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK 0x00000010L +#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK 0x00000020L +#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK 0x00000040L +#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK 0x00000100L +#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK 0x00000200L +#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK 0x000F0000L +#define SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK 0x0FF00000L +//SQ_DEBUG_STS_GLOBAL2 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000FFL +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000FF00L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00FF0000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xFF000000L +//SQ_DEBUG_STS_GLOBAL3 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000FL +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000003F0L +//CC_GC_SHADER_RATE_CONFIG +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//GC_USER_SHADER_RATE_CONFIG +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_DEBUG_PERFCOUNT_TRAP +#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT 0x0 +#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT 0x1 +#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT 0x4 +#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK 0x00000001L +#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK 0x0000000EL +#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK 0x0FFFFFF0L +//SQ_UTCL1_CNTL1 +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 +#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L +#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQ_UTCL1_CNTL2 +#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c +#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L +//SQ_UTCL1_STATUS +#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 +#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L +#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L +//SQ_FED_INTERRUPT_STATUS +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT 0x0 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT 0x2 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT 0x4 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT 0x8 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT 0xc +#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT 0x11 +#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT 0x12 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK 0x00000001L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK 0x0000000CL +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK 0x000000F0L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK 0x00000F00L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK 0x0000F000L +#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK 0x00020000L +#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK 0x00040000L +//SQ_CGTS_CONFIG +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT 0x0 +#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT 0x4 +#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT 0x8 +#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT 0xc +#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT 0x10 +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT 0x12 +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK 0x0000000FL +#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK 0x000000F0L +#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK 0x00000F00L +#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK 0x0000F000L +#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK 0x00030000L +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK 0x000C0000L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL +//SQC_DSM_CNTL +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTLA +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTLB +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTL2 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//SQC_DSM_CNTL2A +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_DSM_CNTL2B +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_DSM_CNTL2E +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +//SQC_EDC_FUE_CNTL +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQC_EDC_CNT2 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK 0x00C00000L +//SQC_EDC_CNT3 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK 0x000C0000L +//SQC_EDC_PARITY_CNT3 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18 +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +//SQ_REG_TIMESTAMP +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_CMD_TIMESTAMP +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL +#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L +#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L +#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L +#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CONFIG1 +#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT 0x0 +#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT 0x1 +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT 0x2 +#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT 0x3 +#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT 0x4 +#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT 0x5 +#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT 0x6 +#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT 0xc +#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT 0xd +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT 0xe +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT 0xf +#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT 0x18 +#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT 0x19 +#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT 0x1a +#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT 0x1b +#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT 0x1c +#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT 0x1d +#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT 0x1e +#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT 0x1f +#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK 0x00000001L +#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK 0x00000002L +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK 0x00000004L +#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK 0x00000008L +#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK 0x00000010L +#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK 0x00000020L +#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK 0x00000040L +#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK 0x00001000L +#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK 0x00002000L +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK 0x00004000L +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK 0x00008000L +#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK 0x01000000L +#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK 0x02000000L +#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK 0x04000000L +#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK 0x08000000L +#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK 0x10000000L +#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK 0x20000000L +#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK 0x40000000L +#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK 0x80000000L +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x00000007L +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x000F0000L +#define SQ_CMD__SIMD_ID_MASK 0x00300000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L +//SQ_TIME_HI +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL +//SQ_TIME_LO +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL +//SQ_DS_0 +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS__SHIFT 0x10 +#define SQ_DS_0__OP__SHIFT 0x11 +#define SQ_DS_0__ACC__SHIFT 0x19 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_DS_0__OFFSET0_MASK 0x000000FFL +#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L +#define SQ_DS_0__GDS_MASK 0x00010000L +#define SQ_DS_0__OP_MASK 0x01FE0000L +#define SQ_DS_0__ACC_MASK 0x02000000L +#define SQ_DS_0__ENCODING_MASK 0xFC000000L +//SQ_DS_1 +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0x000000FFL +#define SQ_DS_1__DATA0_MASK 0x0000FF00L +#define SQ_DS_1__DATA1_MASK 0x00FF0000L +#define SQ_DS_1__VDST_MASK 0xFF000000L +//SQ_EXP_0 +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_EXP_0__EN_MASK 0x0000000FL +#define SQ_EXP_0__TGT_MASK 0x000003F0L +#define SQ_EXP_0__COMPR_MASK 0x00000400L +#define SQ_EXP_0__DONE_MASK 0x00000800L +#define SQ_EXP_0__VM_MASK 0x00001000L +#define SQ_EXP_0__ENCODING_MASK 0xFC000000L +//SQ_EXP_1 +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0x000000FFL +#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L +#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L +#define SQ_EXP_1__VSRC3_MASK 0xFF000000L +//SQ_FLAT_0 +#define SQ_FLAT_0__OFFSET__SHIFT 0x0 +#define SQ_FLAT_0__LDS__SHIFT 0xd +#define SQ_FLAT_0__SEG__SHIFT 0xe +#define SQ_FLAT_0__GLC__SHIFT 0x10 +#define SQ_FLAT_0__SLC__SHIFT 0x11 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__SCC__SHIFT 0x19 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL +#define SQ_FLAT_0__LDS_MASK 0x00002000L +#define SQ_FLAT_0__SEG_MASK 0x0000C000L +#define SQ_FLAT_0__GLC_MASK 0x00010000L +#define SQ_FLAT_0__SLC_MASK 0x00020000L +#define SQ_FLAT_0__OP_MASK 0x01FC0000L +#define SQ_FLAT_0__SCC_MASK 0x02000000L +#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L +//SQ_FLAT_1 +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__SADDR__SHIFT 0x10 +#define SQ_FLAT_1__ACC__SHIFT 0x17 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_FLAT_1__ADDR_MASK 0x000000FFL +#define SQ_FLAT_1__DATA_MASK 0x0000FF00L +#define SQ_FLAT_1__SADDR_MASK 0x007F0000L +#define SQ_FLAT_1__ACC_MASK 0x00800000L +#define SQ_FLAT_1__VDST_MASK 0xFF000000L +//SQ_GLBL_0 +#define SQ_GLBL_0__OFFSET__SHIFT 0x0 +#define SQ_GLBL_0__LDS__SHIFT 0xd +#define SQ_GLBL_0__SEG__SHIFT 0xe +#define SQ_GLBL_0__GLC__SHIFT 0x10 +#define SQ_GLBL_0__SLC__SHIFT 0x11 +#define SQ_GLBL_0__OP__SHIFT 0x12 +#define SQ_GLBL_0__SCC__SHIFT 0x19 +#define SQ_GLBL_0__ENCODING__SHIFT 0x1a +#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL +#define SQ_GLBL_0__LDS_MASK 0x00002000L +#define SQ_GLBL_0__SEG_MASK 0x0000C000L +#define SQ_GLBL_0__GLC_MASK 0x00010000L +#define SQ_GLBL_0__SLC_MASK 0x00020000L +#define SQ_GLBL_0__OP_MASK 0x01FC0000L +#define SQ_GLBL_0__SCC_MASK 0x02000000L +#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L +//SQ_GLBL_1 +#define SQ_GLBL_1__ADDR__SHIFT 0x0 +#define SQ_GLBL_1__DATA__SHIFT 0x8 +#define SQ_GLBL_1__SADDR__SHIFT 0x10 +#define SQ_GLBL_1__ACC__SHIFT 0x17 +#define SQ_GLBL_1__VDST__SHIFT 0x18 +#define SQ_GLBL_1__ADDR_MASK 0x000000FFL +#define SQ_GLBL_1__DATA_MASK 0x0000FF00L +#define SQ_GLBL_1__SADDR_MASK 0x007F0000L +#define SQ_GLBL_1__ACC_MASK 0x00800000L +#define SQ_GLBL_1__VDST_MASK 0xFF000000L +//SQ_INST +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL +//SQ_MIMG_0 +#define SQ_MIMG_0__OPM__SHIFT 0x0 +#define SQ_MIMG_0__SCC__SHIFT 0x7 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__GLC__SHIFT 0xd +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__A16__SHIFT 0xf +#define SQ_MIMG_0__ACC__SHIFT 0x10 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__SLC__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_MIMG_0__OPM_MASK 0x00000001L +#define SQ_MIMG_0__SCC_MASK 0x00000080L +#define SQ_MIMG_0__DMASK_MASK 0x00000F00L +#define SQ_MIMG_0__UNORM_MASK 0x00001000L +#define SQ_MIMG_0__GLC_MASK 0x00002000L +#define SQ_MIMG_0__DA_MASK 0x00004000L +#define SQ_MIMG_0__A16_MASK 0x00008000L +#define SQ_MIMG_0__ACC_MASK 0x00010000L +#define SQ_MIMG_0__LWE_MASK 0x00020000L +#define SQ_MIMG_0__OP_MASK 0x01FC0000L +#define SQ_MIMG_0__SLC_MASK 0x02000000L +#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L +//SQ_MIMG_1 +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_MIMG_1__D16__SHIFT 0x1f +#define SQ_MIMG_1__VADDR_MASK 0x000000FFL +#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L +#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L +#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L +#define SQ_MIMG_1__D16_MASK 0x80000000L +//SQ_MTBUF_0 +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__GLC__SHIFT 0xe +#define SQ_MTBUF_0__OP__SHIFT 0xf +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MTBUF_0__GLC_MASK 0x00004000L +#define SQ_MTBUF_0__OP_MASK 0x00078000L +#define SQ_MTBUF_0__DFMT_MASK 0x00780000L +#define SQ_MTBUF_0__NFMT_MASK 0x03800000L +#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MTBUF_1 +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SCC__SHIFT 0x15 +#define SQ_MTBUF_1__SLC__SHIFT 0x16 +#define SQ_MTBUF_1__ACC__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MTBUF_1__SCC_MASK 0x00200000L +#define SQ_MTBUF_1__SLC_MASK 0x00400000L +#define SQ_MTBUF_1__ACC_MASK 0x00800000L +#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_MUBUF_0 +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__GLC__SHIFT 0xe +#define SQ_MUBUF_0__SCC__SHIFT 0xf +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__SLC__SHIFT 0x11 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MUBUF_0__GLC_MASK 0x00004000L +#define SQ_MUBUF_0__SCC_MASK 0x00008000L +#define SQ_MUBUF_0__LDS_MASK 0x00010000L +#define SQ_MUBUF_0__SLC_MASK 0x00020000L +#define SQ_MUBUF_0__OP_MASK 0x01FC0000L +#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MUBUF_1 +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__ACC__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MUBUF_1__ACC_MASK 0x00800000L +#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_SCRATCH_0 +#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 +#define SQ_SCRATCH_0__LDS__SHIFT 0xd +#define SQ_SCRATCH_0__SEG__SHIFT 0xe +#define SQ_SCRATCH_0__GLC__SHIFT 0x10 +#define SQ_SCRATCH_0__SLC__SHIFT 0x11 +#define SQ_SCRATCH_0__OP__SHIFT 0x12 +#define SQ_SCRATCH_0__SCC__SHIFT 0x19 +#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a +#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL +#define SQ_SCRATCH_0__LDS_MASK 0x00002000L +#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L +#define SQ_SCRATCH_0__GLC_MASK 0x00010000L +#define SQ_SCRATCH_0__SLC_MASK 0x00020000L +#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L +#define SQ_SCRATCH_0__SCC_MASK 0x02000000L +#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L +//SQ_SCRATCH_1 +#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 +#define SQ_SCRATCH_1__DATA__SHIFT 0x8 +#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 +#define SQ_SCRATCH_1__ACC__SHIFT 0x17 +#define SQ_SCRATCH_1__VDST__SHIFT 0x18 +#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL +#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L +#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L +#define SQ_SCRATCH_1__ACC_MASK 0x00800000L +#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L +//SQ_SMEM_0 +#define SQ_SMEM_0__SBASE__SHIFT 0x0 +#define SQ_SMEM_0__SDATA__SHIFT 0x6 +#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe +#define SQ_SMEM_0__NV__SHIFT 0xf +#define SQ_SMEM_0__GLC__SHIFT 0x10 +#define SQ_SMEM_0__IMM__SHIFT 0x11 +#define SQ_SMEM_0__OP__SHIFT 0x12 +#define SQ_SMEM_0__ENCODING__SHIFT 0x1a +#define SQ_SMEM_0__SBASE_MASK 0x0000003FL +#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L +#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L +#define SQ_SMEM_0__NV_MASK 0x00008000L +#define SQ_SMEM_0__GLC_MASK 0x00010000L +#define SQ_SMEM_0__IMM_MASK 0x00020000L +#define SQ_SMEM_0__OP_MASK 0x03FC0000L +#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L +//SQ_SMEM_1 +#define SQ_SMEM_1__OFFSET__SHIFT 0x0 +#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 +#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL +#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L +//SQ_SOP1 +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOP1__SSRC0_MASK 0x000000FFL +#define SQ_SOP1__OP_MASK 0x0000FF00L +#define SQ_SOP1__SDST_MASK 0x007F0000L +#define SQ_SOP1__ENCODING_MASK 0xFF800000L +//SQ_SOP2 +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_SOP2__SSRC0_MASK 0x000000FFL +#define SQ_SOP2__SSRC1_MASK 0x0000FF00L +#define SQ_SOP2__SDST_MASK 0x007F0000L +#define SQ_SOP2__OP_MASK 0x3F800000L +#define SQ_SOP2__ENCODING_MASK 0xC0000000L +//SQ_SOPC +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0x000000FFL +#define SQ_SOPC__SSRC1_MASK 0x0000FF00L +#define SQ_SOPC__OP_MASK 0x007F0000L +#define SQ_SOPC__ENCODING_MASK 0xFF800000L +//SQ_SOPK +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPK__SDST_MASK 0x007F0000L +#define SQ_SOPK__OP_MASK 0x0F800000L +#define SQ_SOPK__ENCODING_MASK 0xF0000000L +//SQ_SOPP +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPP__OP_MASK 0x007F0000L +#define SQ_SOPP__ENCODING_MASK 0xFF800000L +//SQ_VINTRP +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define SQ_VINTRP__VSRC_MASK 0x000000FFL +#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L +#define SQ_VINTRP__ATTR_MASK 0x0000FC00L +#define SQ_VINTRP__OP_MASK 0x00030000L +#define SQ_VINTRP__VDST_MASK 0x03FC0000L +#define SQ_VINTRP__ENCODING_MASK 0xFC000000L +//SQ_VOP1 +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_VOP1__SRC0_MASK 0x000001FFL +#define SQ_VOP1__OP_MASK 0x0001FE00L +#define SQ_VOP1__VDST_MASK 0x01FE0000L +#define SQ_VOP1__ENCODING_MASK 0xFE000000L +//SQ_VOP2 +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_VOP2__SRC0_MASK 0x000001FFL +#define SQ_VOP2__VSRC1_MASK 0x0001FE00L +#define SQ_VOP2__VDST_MASK 0x01FE0000L +#define SQ_VOP2__OP_MASK 0x7E000000L +#define SQ_VOP2__ENCODING_MASK 0x80000000L +//SQ_VOP3P_0 +#define SQ_VOP3P_0__VDST__SHIFT 0x0 +#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 +#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe +#define SQ_VOP3P_0__CLAMP__SHIFT 0xf +#define SQ_VOP3P_0__OP__SHIFT 0x10 +#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 +#define SQ_VOP3P_0__VDST_MASK 0x000000FFL +#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L +#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L +#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L +#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3P_0__OP_MASK 0x007F0000L +#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L +//SQ_VOP3P_1 +#define SQ_VOP3P_1__SRC0__SHIFT 0x0 +#define SQ_VOP3P_1__SRC1__SHIFT 0x9 +#define SQ_VOP3P_1__SRC2__SHIFT 0x12 +#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b +#define SQ_VOP3P_1__NEG__SHIFT 0x1d +#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L +#define SQ_VOP3P_1__NEG_MASK 0xE0000000L +//SQ_VOP3P_MFMA_0 +#define SQ_VOP3P_MFMA_0__VDST__SHIFT 0x0 +#define SQ_VOP3P_MFMA_0__CBSZ__SHIFT 0x8 +#define SQ_VOP3P_MFMA_0__ABID__SHIFT 0xb +#define SQ_VOP3P_MFMA_0__ACC_CD__SHIFT 0xf +#define SQ_VOP3P_MFMA_0__OP__SHIFT 0x10 +#define SQ_VOP3P_MFMA_0__ENCODING__SHIFT 0x17 +#define SQ_VOP3P_MFMA_0__VDST_MASK 0x000000FFL +#define SQ_VOP3P_MFMA_0__CBSZ_MASK 0x00000700L +#define SQ_VOP3P_MFMA_0__ABID_MASK 0x00007800L +#define SQ_VOP3P_MFMA_0__ACC_CD_MASK 0x00008000L +#define SQ_VOP3P_MFMA_0__OP_MASK 0x007F0000L +#define SQ_VOP3P_MFMA_0__ENCODING_MASK 0xFF800000L +//SQ_VOP3P_MFMA_1 +#define SQ_VOP3P_MFMA_1__SRC0__SHIFT 0x0 +#define SQ_VOP3P_MFMA_1__SRC1__SHIFT 0x9 +#define SQ_VOP3P_MFMA_1__SRC2__SHIFT 0x12 +#define SQ_VOP3P_MFMA_1__ACC__SHIFT 0x1b +#define SQ_VOP3P_MFMA_1__BLGP__SHIFT 0x1d +#define SQ_VOP3P_MFMA_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3P_MFMA_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3P_MFMA_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3P_MFMA_1__ACC_MASK 0x18000000L +#define SQ_VOP3P_MFMA_1__BLGP_MASK 0xE0000000L +//SQ_VOP3_0 +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3_0__CLAMP__SHIFT 0xf +#define SQ_VOP3_0__OP__SHIFT 0x10 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0__VDST_MASK 0x000000FFL +#define SQ_VOP3_0__ABS_MASK 0x00000700L +#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L +#define SQ_VOP3_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0__OP_MASK 0x03FF0000L +#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L +//SQ_VOP3_0_SDST_ENC +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L +//SQ_VOP3_1 +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_VOP3_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3_1__OMOD_MASK 0x18000000L +#define SQ_VOP3_1__NEG_MASK 0xE0000000L +//SQ_VOPC +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VOPC__SRC0_MASK 0x000001FFL +#define SQ_VOPC__VSRC1_MASK 0x0001FE00L +#define SQ_VOPC__OP_MASK 0x01FE0000L +#define SQ_VOPC__ENCODING_MASK 0xFE000000L +//SQ_VOP_DPP +#define SQ_VOP_DPP__SRC0__SHIFT 0x0 +#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 +#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 +#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 +#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 +#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 +#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c +#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL +#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L +#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L +#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L +#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L +#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L +#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L +//SQ_VOP_SDWA +#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 +#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb +#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd +#define SQ_VOP_SDWA__OMOD__SHIFT 0xe +#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA__S0__SHIFT 0x17 +#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA__S1__SHIFT 0x1f +#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L +#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L +#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L +#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L +#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA__S0_MASK 0x00800000L +#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA__S1_MASK 0x80000000L +//SQ_VOP_SDWA_SDST_ENC +#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f +#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L +//SQ_LB_CTR_CTRL +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +//SQ_LB_DATA0 +#define SQ_LB_DATA0__DATA__SHIFT 0x0 +#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA1 +#define SQ_LB_DATA1__DATA__SHIFT 0x0 +#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA2 +#define SQ_LB_DATA2__DATA__SHIFT 0x0 +#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA3 +#define SQ_LB_DATA3__DATA__SHIFT 0x0 +#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL +//SQ_LB_CTR_SEL +#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 +#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 +#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 +#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc +#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL +#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L +#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L +#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L +//SQ_LB_CTR0_CU +#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR1_CU +#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR2_CU +#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR3_CU +#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L +//SQC_EDC_CNT +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L +//SQ_EDC_SEC_CNT +#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL +#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L +#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L +//SQ_EDC_DED_CNT +#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL +#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L +#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L +//SQ_EDC_INFO +#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 +#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 +#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL +#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L +#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L +#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L +//SQ_EDC_CNT +#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 +#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 +#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 +#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 +#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 +#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa +#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc +#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe +#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 +#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 +#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 +#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 +#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 +#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a +#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L +#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL +#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L +#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L +#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L +#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L +#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L +#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L +#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L +#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L +#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L +#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L +#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L +#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L +//SQ_EDC_FUE_CNTL +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_CMN +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L +//SQ_THREAD_TRACE_WORD_EVENT +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L +//SQ_THREAD_TRACE_WORD_INST +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L +//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_ISSUE +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L +//SQ_THREAD_TRACE_WORD_MISC +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L +//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L +//SQ_THREAD_TRACE_WORD_REG_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_WAVE +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L +//SQ_THREAD_TRACE_WORD_WAVE_START +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L +//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL +//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL +//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L +//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL +//SQ_WREXEC_EXEC_HI +#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a +#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b +#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c +#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f +#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L +#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L +#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L +#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L +//SQ_WREXEC_EXEC_LO +#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD1 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L +//SQ_BUF_RSRC_WORD2 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L +#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L +//SQ_IMG_RSRC_WORD0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_RSRC_WORD1 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L +#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L +#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L +//SQ_IMG_RSRC_WORD2 +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L +//SQ_IMG_RSRC_WORD3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L +#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD4 +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L +//SQ_IMG_RSRC_WORD5 +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 +#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L +#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L +#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD6 +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD7 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_SAMP_WORD0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L +//SQ_IMG_SAMP_WORD1 +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L +//SQ_IMG_SAMP_WORD2 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L +//SQ_IMG_SAMP_WORD3 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L +//SQ_FLAT_SCRATCH_WORD0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL +//SQ_FLAT_SCRATCH_WORD1 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL +//SQ_M0_GPR_IDX_WORD +#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe +#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf +#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L +#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L +//SQC_ICACHE_UTCL1_CNTL1 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_ICACHE_UTCL1_CNTL2 +#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_DCACHE_UTCL1_CNTL1 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_DCACHE_UTCL1_CNTL2 +#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_ICACHE_UTCL1_STATUS +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//SQC_DCACHE_UTCL1_STATUS +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L + + +// addressBlock: gc_tcdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_STATUS__VM_BUSY__SHIFT 0x8 +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L +#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L +#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L +#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L +#define TCP_STATUS__READ_BUSY_MASK 0x00000040L +#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L +#define TCP_STATUS__VM_BUSY_MASK 0x00000100L +//TCP_CHAN_STEER_0 +#define TCP_CHAN_STEER_0__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_0__CHAN1__SHIFT 0x5 +#define TCP_CHAN_STEER_0__CHAN2__SHIFT 0xa +#define TCP_CHAN_STEER_0__CHAN3__SHIFT 0xf +#define TCP_CHAN_STEER_0__CHAN4__SHIFT 0x14 +#define TCP_CHAN_STEER_0__CHAN5__SHIFT 0x19 +#define TCP_CHAN_STEER_0__CHAN0_MASK 0x0000001FL +#define TCP_CHAN_STEER_0__CHAN1_MASK 0x000003E0L +#define TCP_CHAN_STEER_0__CHAN2_MASK 0x00007C00L +#define TCP_CHAN_STEER_0__CHAN3_MASK 0x000F8000L +#define TCP_CHAN_STEER_0__CHAN4_MASK 0x01F00000L +#define TCP_CHAN_STEER_0__CHAN5_MASK 0x3E000000L +//TCP_CHAN_STEER_1 +#define TCP_CHAN_STEER_1__CHAN6__SHIFT 0x0 +#define TCP_CHAN_STEER_1__CHAN7__SHIFT 0x5 +#define TCP_CHAN_STEER_1__CHAN8__SHIFT 0xa +#define TCP_CHAN_STEER_1__CHAN9__SHIFT 0xf +#define TCP_CHAN_STEER_1__CHANA__SHIFT 0x14 +#define TCP_CHAN_STEER_1__CHAN6_MASK 0x0000001FL +#define TCP_CHAN_STEER_1__CHAN7_MASK 0x000003E0L +#define TCP_CHAN_STEER_1__CHAN8_MASK 0x00007C00L +#define TCP_CHAN_STEER_1__CHAN9_MASK 0x000F8000L +#define TCP_CHAN_STEER_1__CHANA_MASK 0x01F00000L +//TCP_ADDR_CONFIG +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x5 +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x7 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0xa +#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb +#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc +#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000001FL +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000060L +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x00000380L +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000400L +#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L +#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L +#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L +//TCP_CHAN_STEER_2 +#define TCP_CHAN_STEER_2__CHANC__SHIFT 0x0 +#define TCP_CHAN_STEER_2__CHAND__SHIFT 0x5 +#define TCP_CHAN_STEER_2__CHANE__SHIFT 0xa +#define TCP_CHAN_STEER_2__CHANF__SHIFT 0xf +#define TCP_CHAN_STEER_2__CHAN10__SHIFT 0x14 +#define TCP_CHAN_STEER_2__CHAN11__SHIFT 0x19 +#define TCP_CHAN_STEER_2__CHANC_MASK 0x0000001FL +#define TCP_CHAN_STEER_2__CHAND_MASK 0x000003E0L +#define TCP_CHAN_STEER_2__CHANE_MASK 0x00007C00L +#define TCP_CHAN_STEER_2__CHANF_MASK 0x000F8000L +#define TCP_CHAN_STEER_2__CHAN10_MASK 0x01F00000L +#define TCP_CHAN_STEER_2__CHAN11_MASK 0x3E000000L +//TCP_CHAN_STEER_3 +#define TCP_CHAN_STEER_3__CHAN12__SHIFT 0x0 +#define TCP_CHAN_STEER_3__CHAN13__SHIFT 0x5 +#define TCP_CHAN_STEER_3__CHAN14__SHIFT 0xa +#define TCP_CHAN_STEER_3__CHAN15__SHIFT 0xf +#define TCP_CHAN_STEER_3__CHAN16__SHIFT 0x14 +#define TCP_CHAN_STEER_3__CHAN17__SHIFT 0x19 +#define TCP_CHAN_STEER_3__CHAN12_MASK 0x0000001FL +#define TCP_CHAN_STEER_3__CHAN13_MASK 0x000003E0L +#define TCP_CHAN_STEER_3__CHAN14_MASK 0x00007C00L +#define TCP_CHAN_STEER_3__CHAN15_MASK 0x000F8000L +#define TCP_CHAN_STEER_3__CHAN16_MASK 0x01F00000L +#define TCP_CHAN_STEER_3__CHAN17_MASK 0x3E000000L +//TCP_CHAN_STEER_4 +#define TCP_CHAN_STEER_4__CHAN18__SHIFT 0x0 +#define TCP_CHAN_STEER_4__CHAN19__SHIFT 0x5 +#define TCP_CHAN_STEER_4__CHAN1A__SHIFT 0xa +#define TCP_CHAN_STEER_4__CHAN1B__SHIFT 0xf +#define TCP_CHAN_STEER_4__CHAN1C__SHIFT 0x14 +#define TCP_CHAN_STEER_4__CHAN1D__SHIFT 0x19 +#define TCP_CHAN_STEER_4__CHAN18_MASK 0x0000001FL +#define TCP_CHAN_STEER_4__CHAN19_MASK 0x000003E0L +#define TCP_CHAN_STEER_4__CHAN1A_MASK 0x00007C00L +#define TCP_CHAN_STEER_4__CHAN1B_MASK 0x000F8000L +#define TCP_CHAN_STEER_4__CHAN1C_MASK 0x01F00000L +#define TCP_CHAN_STEER_4__CHAN1D_MASK 0x3E000000L +//TCP_CHAN_STEER_5 +#define TCP_CHAN_STEER_5__CHAN1E__SHIFT 0x0 +#define TCP_CHAN_STEER_5__CHAN1F__SHIFT 0x5 +#define TCP_CHAN_STEER_5__CHAN1E_MASK 0x0000001FL +#define TCP_CHAN_STEER_5__CHAN1F_MASK 0x000003E0L +//TCP_EDC_CNT +#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL +#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L +#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L +//TCP_EDC_CNT_NEW +#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2 +#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4 +#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6 +#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT 0xa +#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xc +#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xe +#define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT__SHIFT 0x12 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x14 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x16 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x18 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x1a +#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L +#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL +#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L +#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L +#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK 0x00000300L +#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK 0x00000C00L +#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00003000L +#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x0000C000L +#define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT_MASK 0x00030000L +#define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT_MASK 0x000C0000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00300000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x00C00000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x03000000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x0C000000L +//TC_CFG_L1_LOAD_POLICY0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_LOAD_POLICY1 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L1_STORE_POLICY +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L +//TC_CFG_L2_LOAD_POLICY0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_LOAD_POLICY1 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY1 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_ATOMIC_POLICY +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_VOLATILE +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL +//TC_CFG_L2_VOLATILE +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL +//TCI_MISC +#define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0 +#define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1 +#define TCI_MISC__FGCG_REPEATER_DISABLE_MASK 0x00000001L +#define TCI_MISC__LEGACY_MGCG_DISABLE_MASK 0x00000002L +//TCI_CNTL_3 +#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT 0x0 +#define TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT 0x2 +#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT 0x4 +#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT 0x7 +#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK 0x00000003L +#define TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK 0x0000000CL +#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK 0x00000070L +#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK 0x00000080L +//TCI_DSM_CNTL +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +//TCI_DSM_CNTL2 +#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT 0x1a +#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK 0xFC000000L +//TCI_EDC_CNT +#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT 0x0 +#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT 0x2 +#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK 0x00000003L +#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK 0x0000000CL +//TCI_STATUS +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L +//TCI_CNTL_1 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L +//TCI_CNTL_2 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL +//TCC_CTRL +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT 0x16 +#define TCC_CTRL__EXECUTE_CLK_MODE__SHIFT 0x17 +#define TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT 0x19 +#define TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT 0x1a +#define TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT 0x1b +#define TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT 0x1c +#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L +#define TCC_CTRL__RATE_MASK 0x0000000CL +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L +#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK 0x00400000L +#define TCC_CTRL__EXECUTE_CLK_MODE_MASK 0x01800000L +#define TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK 0x02000000L +#define TCC_CTRL__SRC_FIFO_CLK_MODE_MASK 0x04000000L +#define TCC_CTRL__MC_WRITE_CLK_MODE_MASK 0x08000000L +#define TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK 0x10000000L +//TCC_CTRL2 +#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 +#define TCC_CTRL2__INF_NAN_CLAMP__SHIFT 0x10 +#define TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT 0x11 +#define TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT 0x12 +#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT 0x17 +#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT 0x18 +#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT 0x19 +#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT 0x1a +#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT 0x1b +#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT 0x1c +#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x1d +#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL +#define TCC_CTRL2__INF_NAN_CLAMP_MASK 0x00010000L +#define TCC_CTRL2__PROBE_FILTER_CTRL_MASK 0x00020000L +#define TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK 0x007C0000L +#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK 0x00800000L +#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK 0x01000000L +#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK 0x02000000L +#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK 0x04000000L +#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK 0x08000000L +#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK 0x10000000L +#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x20000000L +//TCC_EDC_CNT +#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 +#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 +#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 +#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 +#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa +#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc +#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe +#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 +#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 +#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14 +#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT 0x16 +#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT 0x18 +#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT 0x1a +#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L +#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL +#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L +#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L +#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L +#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L +#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L +#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L +#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L +#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L +#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK 0x00300000L +#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK 0x00C00000L +#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK 0x03000000L +#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK 0x0C000000L +//TCC_EDC_CNT2 +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT 0x2 +#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT 0x4 +#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT 0x6 +#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT 0x8 +#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT 0xa +#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT 0xc +#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT 0xe +#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT 0x10 +#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT 0x12 +#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14 +#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT 0x16 +#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT 0x18 +#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT 0x1a +#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT 0x1c +#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT 0x1e +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK 0x00000003L +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK 0x0000000CL +#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK 0x00000030L +#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK 0x000000C0L +#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK 0x00000300L +#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK 0x00000C00L +#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK 0x00003000L +#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK 0x0000C000L +#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK 0x00030000L +#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK 0x000C0000L +#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK 0x00300000L +#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK 0x00C00000L +#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK 0x03000000L +#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK 0x0C000000L +#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK 0x30000000L +#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK 0xC0000000L +//TCC_REDUNDANCY +#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 +#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 +#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L +#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L +//TCC_EXE_DISABLE +#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 +#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L +//TCC_DSM_CNTL +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTLA +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTL2 +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCC_DSM_CNTL2A +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT 0x1b +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT 0x1d +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x04000000L +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK 0x18000000L +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK 0x20000000L +//TCC_DSM_CNTL2B +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT 0x12 +#define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD__SHIFT 0x18 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK 0x00FC0000L +#define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD_MASK 0x1F000000L +//TCC_WBINVL2 +#define TCC_WBINVL2__DONE__SHIFT 0x4 +#define TCC_WBINVL2__DONE_MASK 0x00000010L +//TCC_SOFT_RESET +#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 +#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L +//TCC_DSM_CNTL3 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK 0x00800000L +//TCA_CTRL +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 +#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 +#define TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT 0x8 +#define TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT 0x9 +#define TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT 0xa +#define TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT 0xb +#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT 0xc +#define TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT 0xd +#define TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT 0x10 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL +#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L +#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L +#define TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK 0x00000100L +#define TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK 0x00000200L +#define TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK 0x00000400L +#define TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK 0x00000800L +#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK 0x00001000L +#define TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK 0x0000E000L +#define TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK 0x00070000L +//TCA_BURST_MASK +#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 +#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL +//TCA_BURST_CTRL +#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 +#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 +#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 +#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 +#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 +#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa +#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb +#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc +#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd +#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L +#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L +#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L +#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L +#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L +#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L +#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L +#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L +#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L +//TCA_DSM_CNTL +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +//TCA_DSM_CNTL2 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCA_EDC_CNT +#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT 0x0 +#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT 0x2 +#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT 0x4 +#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT 0x6 +#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK 0x00000003L +#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK 0x0000000CL +#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK 0x00000030L +#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK 0x000000C0L +//TCX_CTRL +#define TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT 0x0 +#define TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT 0x1 +#define TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT 0x2 +#define TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK 0x00000001L +#define TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK 0x00000002L +#define TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK 0x00000004L +//TCX_DSM_CNTL +#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT 0x2 +#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT 0x4 +#define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT 0x8 +#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT 0xa +#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL__SHIFT 0xe +#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT 0x10 +#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT 0x14 +#define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL__SHIFT 0x16 +#define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT 0x1a +#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT 0x1c +#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x1e +#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK 0x0000000CL +#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK 0x00000030L +#define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK 0x00000300L +#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK 0x00000C00L +#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL_MASK 0x0000C000L +#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK 0x00030000L +#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK 0x00300000L +#define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL_MASK 0x00C00000L +#define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK 0x0C000000L +#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK 0x30000000L +#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK 0x40000000L +//TCX_DSM_CNTL2 +#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCX_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCX_EDC_CNT +#define TCX_EDC_CNT__GROUP0_SEC_COUNT__SHIFT 0x0 +#define TCX_EDC_CNT__GROUP0_DED_COUNT__SHIFT 0x2 +#define TCX_EDC_CNT__GROUP1_SEC_COUNT__SHIFT 0x4 +#define TCX_EDC_CNT__GROUP1_DED_COUNT__SHIFT 0x6 +#define TCX_EDC_CNT__GROUP2_SEC_COUNT__SHIFT 0x8 +#define TCX_EDC_CNT__GROUP2_DED_COUNT__SHIFT 0xa +#define TCX_EDC_CNT__GROUP3_SEC_COUNT__SHIFT 0xc +#define TCX_EDC_CNT__GROUP3_DED_COUNT__SHIFT 0xe +#define TCX_EDC_CNT__GROUP4_SEC_COUNT__SHIFT 0x10 +#define TCX_EDC_CNT__GROUP4_DED_COUNT__SHIFT 0x12 +#define TCX_EDC_CNT__GROUP5_SED_COUNT__SHIFT 0x14 +#define TCX_EDC_CNT__GROUP6_SED_COUNT__SHIFT 0x16 +#define TCX_EDC_CNT__GROUP7_SED_COUNT__SHIFT 0x18 +#define TCX_EDC_CNT__GROUP8_SED_COUNT__SHIFT 0x1a +#define TCX_EDC_CNT__GROUP9_SED_COUNT__SHIFT 0x1c +#define TCX_EDC_CNT__GROUP10_SED_COUNT__SHIFT 0x1e +#define TCX_EDC_CNT__GROUP0_SEC_COUNT_MASK 0x00000003L +#define TCX_EDC_CNT__GROUP0_DED_COUNT_MASK 0x0000000CL +#define TCX_EDC_CNT__GROUP1_SEC_COUNT_MASK 0x00000030L +#define TCX_EDC_CNT__GROUP1_DED_COUNT_MASK 0x000000C0L +#define TCX_EDC_CNT__GROUP2_SEC_COUNT_MASK 0x00000300L +#define TCX_EDC_CNT__GROUP2_DED_COUNT_MASK 0x00000C00L +#define TCX_EDC_CNT__GROUP3_SEC_COUNT_MASK 0x00003000L +#define TCX_EDC_CNT__GROUP3_DED_COUNT_MASK 0x0000C000L +#define TCX_EDC_CNT__GROUP4_SEC_COUNT_MASK 0x00030000L +#define TCX_EDC_CNT__GROUP4_DED_COUNT_MASK 0x000C0000L +#define TCX_EDC_CNT__GROUP5_SED_COUNT_MASK 0x00300000L +#define TCX_EDC_CNT__GROUP6_SED_COUNT_MASK 0x00C00000L +#define TCX_EDC_CNT__GROUP7_SED_COUNT_MASK 0x03000000L +#define TCX_EDC_CNT__GROUP8_SED_COUNT_MASK 0x0C000000L +#define TCX_EDC_CNT__GROUP9_SED_COUNT_MASK 0x30000000L +#define TCX_EDC_CNT__GROUP10_SED_COUNT_MASK 0xC0000000L +//TCX_EDC_CNT2 +#define TCX_EDC_CNT2__GROUP11_SED_COUNT__SHIFT 0x0 +#define TCX_EDC_CNT2__GROUP12_SED_COUNT__SHIFT 0x2 +#define TCX_EDC_CNT2__GROUP13_SED_COUNT__SHIFT 0x4 +#define TCX_EDC_CNT2__GROUP14_SED_COUNT__SHIFT 0x6 +#define TCX_EDC_CNT2__GROUP11_SED_COUNT_MASK 0x00000003L +#define TCX_EDC_CNT2__GROUP12_SED_COUNT_MASK 0x0000000CL +#define TCX_EDC_CNT2__GROUP13_SED_COUNT_MASK 0x00000030L +#define TCX_EDC_CNT2__GROUP14_SED_COUNT_MASK 0x000000C0L + + +// addressBlock: gc_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L +//TCP_GATCL1_CNTL +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_ATC_EDC_GATCL1_CNT +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL +//TCP_GATCL1_DSM_CNTL +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L +//TCP_DSM_CNTL +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +//TCP_UTCL1_CNTL1 +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT 0x10 +#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK 0x00010000L +#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_UTCL1_CNTL2 +#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//TCP_UTCL1_STATUS +#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//TCP_DSM_CNTL2 +#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT 0x1a +#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK 0xFC000000L +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 +#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L +#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L +#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L + + +// addressBlock: gc_tpdec +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_EDC_CNT +#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0 +#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2 +#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4 +#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6 +#define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT 0x8 +#define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT 0xa +#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L +#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL +#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L +#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L +#define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK 0x00000300L +#define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK 0x00000C00L +//TD_DSM_CNTL +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//TD_DSM_CNTL2 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_CNTL +#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 +#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL +#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L +#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 +#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc +#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd +#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe +#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c +#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d +#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L +#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L +#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L +#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L +#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L +#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L +#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L +//TA_FEATURE_CNTL +#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT 0x4 +#define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH__SHIFT 0xa +#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT 0xb +#define TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT 0xc +#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT 0xd +#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK 0x00000030L +#define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH_MASK 0x00000400L +#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK 0x00000800L +#define TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK 0x00001000L +#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK 0x00002000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_DSM_CNTL +#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc +#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//TA_DSM_CNTL2 +#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xb +#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT 0x1a +#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L +//TA_EDC_CNT +#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 +#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 +#define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT__SHIFT 0x4 +#define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT__SHIFT 0x6 +#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 +#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa +#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc +#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe +#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 +#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 +#define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT__SHIFT 0x14 +#define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT__SHIFT 0x16 +#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L +#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL +#define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT_MASK 0x00000030L +#define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT_MASK 0x000000C0L +#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L +#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L +#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L +#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L +#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L +#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L +#define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT_MASK 0x00300000L +#define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT_MASK 0x00C00000L + + +// addressBlock: gc_utcl2_atcl2dec +//ATC_L2_CNTL +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L +//ATC_L2_CNTL2 +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//ATC_L2_CACHE_DATA0 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATC_L2_CACHE_DATA1 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA2 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA3 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CNTL3 +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//ATC_L2_STATUS +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__BUSY_MASK 0x00000001L +//ATC_L2_STATUS2 +#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 +#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc +#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12 +#define ATC_L2_STATUS2__UCE__SHIFT 0x13 +#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL +#define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L +#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L +#define ATC_L2_STATUS2__UCE_MASK 0x00080000L +//ATC_L2_MISC_CG +#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATC_L2_MEM_POWER_LS +#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATC_L2_CGTT_CLK_CTRL +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//ATC_L2_CACHE_4K_DSM_INDEX +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_32K_DSM_INDEX +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_2M_DSM_INDEX +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_4K_DSM_CNTL +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_32K_DSM_CNTL +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_2M_DSM_CNTL +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CNTL4 +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//ATC_L2_MM_GROUP_RT_CLASSES +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL + + +// addressBlock: gc_utcl2_atcl2pfcntldec +//ATC_L2_PERFCOUNTER0_CFG +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER1_CFG +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_utcl2_atcl2pfcntrdec +//ATC_L2_PERFCOUNTER_LO +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_L2_PERFCOUNTER_HI +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_utcl2_l2tlbdec +//L2TLB_TLB0_STATUS +#define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L + + +// addressBlock: gc_utcl2_l2tlbpldec +//L2TLB_PERFCOUNTER0_CFG +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER1_CFG +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER2_CFG +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER3_CFG +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER_RSLT_CNTL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_utcl2_l2tlbprdec +//L2TLB_PERFCOUNTER_LO +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//L2TLB_PERFCOUNTER_HI +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_utcl2_vml2pfdec +//VM_L2_CNTL +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VM_L2_CNTL2 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_CNTL3 +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_STATUS +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VM_DUMMY_PAGE_FAULT_CNTL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_CNTL +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VM_L2_PROTECTION_FAULT_CNTL2 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_STATUS +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L +//VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VM_L2_CNTL4 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +//VM_L2_MM_GROUP_RT_CLASSES +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VM_L2_BANK_SELECT_RESERVED_CID +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_BANK_SELECT_RESERVED_CID2 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_CACHE_PARITY_CNTL +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VM_L2_CGTT_CLK_CTRL +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//VM_L2_CGTT_BUSY_CTRL +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L +//VML2_MEM_ECC_INDEX +#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_WALKER_MEM_ECC_INDEX +#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//UTCL2_MEM_ECC_INDEX +#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_MEM_ECC_CNTL +#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_WALKER_MEM_ECC_CNTL +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//UTCL2_MEM_ECC_CNTL +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_MEM_ECC_STATUS +#define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//VML2_WALKER_MEM_ECC_STATUS +#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_MEM_ECC_STATUS +#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_EDC_MODE +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 +#define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d +#define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L +#define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L +#define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L +//UTCL2_EDC_CONFIG +#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L + + +// addressBlock: gc_utcl2_vml2pldec +//MC_VM_L2_PERFCOUNTER0_CFG +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER1_CFG +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER2_CFG +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER3_CFG +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER4_CFG +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER5_CFG +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER6_CFG +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER7_CFG +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_utcl2_vml2prdec +//MC_VM_L2_PERFCOUNTER_LO +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_L2_PERFCOUNTER_HI +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_utcl2_vml2vcdec +//VM_CONTEXT0_CNTL +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT1_CNTL +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT2_CNTL +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT3_CNTL +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT4_CNTL +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT5_CNTL +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT6_CNTL +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT7_CNTL +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT8_CNTL +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT9_CNTL +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT10_CNTL +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT11_CNTL +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT12_CNTL +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT13_CNTL +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT14_CNTL +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT15_CNTL +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXTS_DISABLE +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_INVALIDATE_ENG0_SEM +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG1_SEM +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG2_SEM +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG3_SEM +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG4_SEM +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG5_SEM +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG6_SEM +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG7_SEM +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG8_SEM +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG9_SEM +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG10_SEM +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG11_SEM +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG12_SEM +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG13_SEM +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG14_SEM +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG15_SEM +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG16_SEM +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG17_SEM +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG0_REQ +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG1_REQ +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG2_REQ +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG3_REQ +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG4_REQ +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG5_REQ +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG6_REQ +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG7_REQ +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG8_REQ +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG9_REQ +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG10_REQ +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG11_REQ +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG12_REQ +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG13_REQ +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG14_REQ +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG15_REQ +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG16_REQ +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG17_REQ +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG0_ACK +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG1_ACK +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG2_ACK +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG3_ACK +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG4_ACK +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG5_ACK +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG6_ACK +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG7_ACK +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG8_ACK +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG9_ACK +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG10_ACK +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG11_ACK +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG12_ACK +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG13_ACK +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG14_ACK +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG15_ACK +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG16_ACK +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG17_ACK +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: gc_utcl2_vmsharedhvdec +//MC_VM_FB_SIZE_OFFSET_VF0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF1 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF2 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF3 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF4 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF5 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF6 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF7 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF8 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF9 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF11 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF12 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF13 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF14 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF15 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_MARC_BASE_LO_0 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_1 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_2 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_3 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_HI_0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_1 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_2 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_3 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_LO_0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_2 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_3 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_HI_0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_1 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_2 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_3 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_LO_0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_1 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_2 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_3 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_HI_0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_1 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_2 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_3 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VM_PCIE_ATS_CNTL +#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_0 +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_1 +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_2 +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_3 +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_4 +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_5 +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_6 +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_7 +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_8 +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_9 +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_10 +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_11 +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_12 +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_13 +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_14 +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_15 +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//MC_SHARED_ACTIVE_FCN_ID +#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MC_VM_XGMI_GPUIOV_ENABLE +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L + + +// addressBlock: gc_utcl2_vmsharedpfdec +//MC_VM_FB_OFFSET +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MC_VM_STEERING +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MC_SHARED_VIRT_RESET_REQ +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MC_MEM_POWER_LS +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_APT_CNTL +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 +#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L +#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L +//MC_VM_LOCAL_HBM_ADDRESS_START +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_END +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//UTCL2_CGTT_CLK_CTRL +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//MC_VM_XGMI_LFB_CNTL +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//MC_VM_XGMI_LFB_SIZE +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//MC_VM_CACHEABLE_DRAM_CNTL +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L +//MC_VM_HOST_MAPPING +#define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L + + +// addressBlock: gc_utcl2_vmsharedvcdec +//MC_VM_FB_LOCATION_BASE +#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MC_VM_FB_LOCATION_TOP +#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_TOP +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_BOT +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MC_VM_AGP_BASE +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_MX_L1_TLB_CNTL +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: gccacind +//GC_CAC_CNTL +#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 +#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 +#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 +#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 +#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L +#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL +#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L +#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L +//GC_CAC_OVR_SEL +#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 +#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL +#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 +#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_BCI_0 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CB_0 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CB_1 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_1 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_DB_0 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_DB_1 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_1 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_IA_0 +#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_LDS_0 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_LDS_1 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PA_0 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PC_0 +#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SC_0 +#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SPI_0 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SPI_1 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SPI_2 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_0 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_1 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_2 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_3 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_4 +#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SX_0 +#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SXRB_0 +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_TA_0 +#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_TCC_0 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCC_1 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCC_2 +#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_TCP_0 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCP_1 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCP_2 +#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_TD_0 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TD_1 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TD_2 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_VGT_0 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_VGT_1 +#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_WD_0 +#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_CU_0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL +//GC_CAC_ACC_BCI0 +#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB0 +#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB1 +#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB2 +#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB3 +#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP1 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP2 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB0 +#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB1 +#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB2 +#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB3 +#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS1 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS2 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS3 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_IA0 +#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS0 +#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS1 +#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS2 +#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS3 +#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PA0 +#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PA1 +#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PC0 +#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SC0 +#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI0 +#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI1 +#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI2 +#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI3 +#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI4 +#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI5 +#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_UTCL2_ATCL2_0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L +//GC_CAC_ACC_EA0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA1 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA2 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA3 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL20 +#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_EA +#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_UTCL2_ATCL2 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_WEIGHT_EA_0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_EA_1 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_RMI_0 +#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL +//GC_CAC_ACC_RMI0 +#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_RMI +#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_WEIGHT_UTCL2_ATCL2_1 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L +//GC_CAC_ACC_UTCL2_ATCL21 +#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL22 +#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL23 +#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA4 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA5 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_EA_2 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L +//GC_CAC_ACC_SQ0_LOWER +#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ0_UPPER +#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ1_LOWER +#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ1_UPPER +#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ2_LOWER +#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ2_UPPER +#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ3_LOWER +#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ3_UPPER +#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ4_LOWER +#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ4_UPPER +#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ5_LOWER +#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ5_UPPER +#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ6_LOWER +#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ6_UPPER +#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ7_LOWER +#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ7_UPPER +#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SQ8_LOWER +#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ8_UPPER +#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +//GC_CAC_ACC_SX0 +#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SXRB0 +#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SXRB1 +#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TA0 +#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC0 +#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC1 +#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC2 +#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC3 +#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC4 +#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP0 +#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP1 +#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP2 +#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP3 +#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP4 +#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD0 +#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD1 +#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD2 +#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD3 +#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD4 +#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD5 +#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT0 +#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT1 +#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT2 +#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_WD0 +#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU0 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU1 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU2 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU3 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU4 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU5 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU6 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU7 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU8 +#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU9 +#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU10 +#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU11 +#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU12 +#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU13 +#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_BCI +#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 +#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L +#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL +//GC_CAC_OVRD_CB +#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_CP +#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 +#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L +#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L +//GC_CAC_OVRD_DB +#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_GDS +#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_IA +#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_LDS +#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_PA +#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 +#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L +#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL +//GC_CAC_OVRD_PC +#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SC +#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SPI +#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_CU +#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SQ +#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 +#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL +#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L +//GC_CAC_OVRD_SX +#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SXRB +#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_TA +#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_TCC +#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_OVRD_TCP +#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_OVRD_TD +#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_VGT +#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 +#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L +#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L +//GC_CAC_OVRD_WD +#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_ACC_BCI1 +#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_UTCL2_ATCL2_2 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_UTCL2_ROUTER_0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_1 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_2 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_3 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_4 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_1 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_2 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL +//GC_CAC_ACC_UTCL2_ATCL24 +#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER1 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER2 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER3 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER4 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER5 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER6 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER7 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER8 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER9 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML20 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML21 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML22 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML23 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML24 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_UTCL2_ROUTER +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L +//GC_CAC_OVRD_UTCL2_VML2 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_WEIGHT_UTCL2_WALKER_0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_1 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_2 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL +//GC_CAC_ACC_UTCL2_WALKER0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER1 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER2 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER3 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER4 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_UTCL2_WALKER +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L +//EDC_STALL_PATTERN_1_2 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_3_4 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_5_6 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_7 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_STALL_PATTERN_1_2 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_3_4 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_5_6 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_7 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_THROT_REINCR_FIRST_PATN_1_8 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT 0x0 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT 0x4 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT 0x8 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT 0xc +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT 0x10 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT 0x14 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT 0x18 +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT 0x1c +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK 0x00000007L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK 0x00000070L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK 0x00000700L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK 0x00007000L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK 0x00070000L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK 0x00700000L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK 0x07000000L +#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK 0x70000000L +//PCC_THROT_REINCR_FIRST_PATN_9_16 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT 0x0 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT 0x4 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT 0x8 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT 0xc +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT 0x10 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT 0x14 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT 0x18 +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT 0x1c +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK 0x00000007L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK 0x00000070L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK 0x00000700L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK 0x00007000L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK 0x00070000L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK 0x00700000L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK 0x07000000L +#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK 0x70000000L +//PCC_THROT_REINCR_FIRST_PATN_17_20 +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT 0x0 +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT 0x4 +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT 0x8 +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT 0xc +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK 0x00000007L +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK 0x00000070L +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK 0x00000700L +#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK 0x00007000L +//PCC_THROT_DECR_FIRST_PATN_1_4 +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT 0x0 +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT 0x8 +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT 0x10 +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT 0x18 +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK 0x0000001FL +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK 0x00001F00L +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK 0x001F0000L +#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK 0x1F000000L +//PCC_THROT_DECR_FIRST_PATN_5_7 +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT 0x0 +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT 0x8 +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT 0x10 +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK 0x0000001FL +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK 0x00001F00L +#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK 0x001F0000L +//PWRBRK_STALL_PATTERN_CTRL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +//PWRBRK_STALL_PATTERN_1_2 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_3_4 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_5_6 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_7 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_PWRBRK_HYSTERESIS_CTRL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x0 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x000000FFL +//FIXED_PATTERN_PERF_COUNTER_CTRL +#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x1 +#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00000001L +#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x0000003EL +//FIXED_PATTERN_PERF_COUNTER_1 +#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_2 +#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_3 +#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_4 +#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_5 +#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_6 +#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_7 +#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_8 +#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_9 +#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL +//FIXED_PATTERN_PERF_COUNTER_10 +#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 +#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL + + + + +// addressBlock: secacind +//SE_CAC_CNTL +#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 +#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 +#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 +#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 +#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L +#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL +#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L +#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L +//SE_CAC_OVR_SEL +#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 +#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL +//SE_CAC_OVR_VAL +#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 +#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL + + +// addressBlock: sqind +//SQ_DEBUG_STS_LOCAL +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L +//SQ_DEBUG_CTRL_LOCAL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT 0x8 +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT 0x9 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK 0x00000100L +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK 0x00000200L +//SQ_WAVE_VALID_AND_IDLE +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0xFFFFFFFFL +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 +#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a +#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L +#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L +#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L +#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +//SQ_WAVE_TRAPSTS +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb +#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L +#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L +#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L +#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x0000E000L +#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L +#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x6 +#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT 0xc +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x12 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00000FC0L +#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK 0x0003F000L +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FC0000L +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf +#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 +#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L +#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L +#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L +#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL +//SQ_WAVE_INST_DW0 +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL +//SQ_WAVE_INST_DW1 +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL +//SQ_WAVE_IB_DBG0 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 +#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 +#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 +#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb +#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L +#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L +#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L +#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L +#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL +//SQ_INTERRUPT_WORD_AUTO_CTXID +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_AUTO_HI +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_AUTO_LO +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L +//SQ_INTERRUPT_WORD_CMN_CTXID +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_CMN_HI +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_CTXID +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_WAVE_HI +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_LO +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..adb7a21e2a103276a645aa14ee4e6341332e7d71 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h @@ -0,0 +1,5125 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_1_7_OFFSET_HEADER +#define _mmhub_1_7_OFFSET_HEADER + + + +// addressBlock: mmhub_dagb_dagbdec0 +// base address: 0x68000 +#define regDAGB0_RDCLI0 0x0000 +#define regDAGB0_RDCLI0_BASE_IDX 0 +#define regDAGB0_RDCLI1 0x0001 +#define regDAGB0_RDCLI1_BASE_IDX 0 +#define regDAGB0_RDCLI2 0x0002 +#define regDAGB0_RDCLI2_BASE_IDX 0 +#define regDAGB0_RDCLI3 0x0003 +#define regDAGB0_RDCLI3_BASE_IDX 0 +#define regDAGB0_RDCLI4 0x0004 +#define regDAGB0_RDCLI4_BASE_IDX 0 +#define regDAGB0_RDCLI5 0x0005 +#define regDAGB0_RDCLI5_BASE_IDX 0 +#define regDAGB0_RDCLI6 0x0006 +#define regDAGB0_RDCLI6_BASE_IDX 0 +#define regDAGB0_RDCLI7 0x0007 +#define regDAGB0_RDCLI7_BASE_IDX 0 +#define regDAGB0_RDCLI8 0x0008 +#define regDAGB0_RDCLI8_BASE_IDX 0 +#define regDAGB0_RDCLI9 0x0009 +#define regDAGB0_RDCLI9_BASE_IDX 0 +#define regDAGB0_RDCLI10 0x000a +#define regDAGB0_RDCLI10_BASE_IDX 0 +#define regDAGB0_RDCLI11 0x000b +#define regDAGB0_RDCLI11_BASE_IDX 0 +#define regDAGB0_RDCLI12 0x000c +#define regDAGB0_RDCLI12_BASE_IDX 0 +#define regDAGB0_RDCLI13 0x000d +#define regDAGB0_RDCLI13_BASE_IDX 0 +#define regDAGB0_RDCLI14 0x000e +#define regDAGB0_RDCLI14_BASE_IDX 0 +#define regDAGB0_RDCLI15 0x000f +#define regDAGB0_RDCLI15_BASE_IDX 0 +#define regDAGB0_RD_CNTL 0x0010 +#define regDAGB0_RD_CNTL_BASE_IDX 0 +#define regDAGB0_RD_GMI_CNTL 0x0011 +#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB 0x0012 +#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 +#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 +#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015 +#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 +#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_RD_VC0_CNTL 0x001c +#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC1_CNTL 0x001d +#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC2_CNTL 0x001e +#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC3_CNTL 0x001f +#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC4_CNTL 0x0020 +#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC5_CNTL 0x0021 +#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC6_CNTL 0x0022 +#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC7_CNTL 0x0023 +#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB0_RD_CNTL_MISC 0x0024 +#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_RD_TLB_CREDIT 0x0025 +#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026 +#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027 +#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK_PENDING 0x0028 +#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GO_PENDING 0x0029 +#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a +#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_TLB_PENDING 0x002b +#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OARB_PENDING 0x002c +#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OSD_PENDING 0x002d +#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI0 0x002e +#define regDAGB0_WRCLI0_BASE_IDX 0 +#define regDAGB0_WRCLI1 0x002f +#define regDAGB0_WRCLI1_BASE_IDX 0 +#define regDAGB0_WRCLI2 0x0030 +#define regDAGB0_WRCLI2_BASE_IDX 0 +#define regDAGB0_WRCLI3 0x0031 +#define regDAGB0_WRCLI3_BASE_IDX 0 +#define regDAGB0_WRCLI4 0x0032 +#define regDAGB0_WRCLI4_BASE_IDX 0 +#define regDAGB0_WRCLI5 0x0033 +#define regDAGB0_WRCLI5_BASE_IDX 0 +#define regDAGB0_WRCLI6 0x0034 +#define regDAGB0_WRCLI6_BASE_IDX 0 +#define regDAGB0_WRCLI7 0x0035 +#define regDAGB0_WRCLI7_BASE_IDX 0 +#define regDAGB0_WRCLI8 0x0036 +#define regDAGB0_WRCLI8_BASE_IDX 0 +#define regDAGB0_WRCLI9 0x0037 +#define regDAGB0_WRCLI9_BASE_IDX 0 +#define regDAGB0_WRCLI10 0x0038 +#define regDAGB0_WRCLI10_BASE_IDX 0 +#define regDAGB0_WRCLI11 0x0039 +#define regDAGB0_WRCLI11_BASE_IDX 0 +#define regDAGB0_WRCLI12 0x003a +#define regDAGB0_WRCLI12_BASE_IDX 0 +#define regDAGB0_WRCLI13 0x003b +#define regDAGB0_WRCLI13_BASE_IDX 0 +#define regDAGB0_WRCLI14 0x003c +#define regDAGB0_WRCLI14_BASE_IDX 0 +#define regDAGB0_WRCLI15 0x003d +#define regDAGB0_WRCLI15_BASE_IDX 0 +#define regDAGB0_WR_CNTL 0x003e +#define regDAGB0_WR_CNTL_BASE_IDX 0 +#define regDAGB0_WR_GMI_CNTL 0x003f +#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB 0x0040 +#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041 +#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042 +#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB0_WR_CGTT_CLK_CTRL 0x0043 +#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045 +#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB 0x004a +#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_VC0_CNTL 0x004f +#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC1_CNTL 0x0050 +#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC2_CNTL 0x0051 +#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC3_CNTL 0x0052 +#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC4_CNTL 0x0053 +#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC5_CNTL 0x0054 +#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC6_CNTL 0x0055 +#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC7_CNTL 0x0056 +#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB0_WR_CNTL_MISC 0x0057 +#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_WR_TLB_CREDIT 0x0058 +#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_DATA_CREDIT 0x0059 +#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_MISC_CREDIT 0x005a +#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b +#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c +#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK_PENDING 0x0060 +#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GO_PENDING 0x0061 +#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062 +#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_TLB_PENDING 0x0063 +#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OARB_PENDING 0x0064 +#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OSD_PENDING 0x0065 +#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067 +#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB0_DAGB_DLY 0x0068 +#define regDAGB0_DAGB_DLY_BASE_IDX 0 +#define regDAGB0_CNTL_MISC 0x0069 +#define regDAGB0_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_CNTL_MISC2 0x006a +#define regDAGB0_CNTL_MISC2_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CNTL 0x006b +#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CLEAR 0x006c +#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS0 0x006d +#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS1 0x006e +#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS2 0x006f +#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS3 0x0070 +#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB0_FIFO_EMPTY 0x0071 +#define regDAGB0_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB0_FIFO_FULL 0x0072 +#define regDAGB0_FIFO_FULL_BASE_IDX 0 +#define regDAGB0_WR_CREDITS_FULL 0x0073 +#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_RD_CREDITS_FULL 0x0074 +#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_LO 0x0075 +#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_HI 0x0076 +#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER0_CFG 0x0077 +#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER1_CFG 0x0078 +#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER2_CFG 0x0079 +#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a +#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB0_L1TLB_REG_RW 0x007b +#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB0_RESERVE1 0x007c +#define regDAGB0_RESERVE1_BASE_IDX 0 +#define regDAGB0_RESERVE2 0x007d +#define regDAGB0_RESERVE2_BASE_IDX 0 +#define regDAGB0_RESERVE3 0x007e +#define regDAGB0_RESERVE3_BASE_IDX 0 +#define regDAGB0_RESERVE4 0x007f +#define regDAGB0_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_dagb_dagbdec1 +// base address: 0x68200 +#define regDAGB1_RDCLI0 0x0080 +#define regDAGB1_RDCLI0_BASE_IDX 0 +#define regDAGB1_RDCLI1 0x0081 +#define regDAGB1_RDCLI1_BASE_IDX 0 +#define regDAGB1_RDCLI2 0x0082 +#define regDAGB1_RDCLI2_BASE_IDX 0 +#define regDAGB1_RDCLI3 0x0083 +#define regDAGB1_RDCLI3_BASE_IDX 0 +#define regDAGB1_RDCLI4 0x0084 +#define regDAGB1_RDCLI4_BASE_IDX 0 +#define regDAGB1_RDCLI5 0x0085 +#define regDAGB1_RDCLI5_BASE_IDX 0 +#define regDAGB1_RDCLI6 0x0086 +#define regDAGB1_RDCLI6_BASE_IDX 0 +#define regDAGB1_RDCLI7 0x0087 +#define regDAGB1_RDCLI7_BASE_IDX 0 +#define regDAGB1_RDCLI8 0x0088 +#define regDAGB1_RDCLI8_BASE_IDX 0 +#define regDAGB1_RDCLI9 0x0089 +#define regDAGB1_RDCLI9_BASE_IDX 0 +#define regDAGB1_RDCLI10 0x008a +#define regDAGB1_RDCLI10_BASE_IDX 0 +#define regDAGB1_RDCLI11 0x008b +#define regDAGB1_RDCLI11_BASE_IDX 0 +#define regDAGB1_RDCLI12 0x008c +#define regDAGB1_RDCLI12_BASE_IDX 0 +#define regDAGB1_RDCLI13 0x008d +#define regDAGB1_RDCLI13_BASE_IDX 0 +#define regDAGB1_RDCLI14 0x008e +#define regDAGB1_RDCLI14_BASE_IDX 0 +#define regDAGB1_RDCLI15 0x008f +#define regDAGB1_RDCLI15_BASE_IDX 0 +#define regDAGB1_RD_CNTL 0x0090 +#define regDAGB1_RD_CNTL_BASE_IDX 0 +#define regDAGB1_RD_GMI_CNTL 0x0091 +#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB 0x0092 +#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 +#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 +#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095 +#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 +#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB1_RD_VC0_CNTL 0x009c +#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC1_CNTL 0x009d +#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC2_CNTL 0x009e +#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC3_CNTL 0x009f +#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC4_CNTL 0x00a0 +#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC5_CNTL 0x00a1 +#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC6_CNTL 0x00a2 +#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC7_CNTL 0x00a3 +#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB1_RD_CNTL_MISC 0x00a4 +#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_RD_TLB_CREDIT 0x00a5 +#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6 +#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK_PENDING 0x00a8 +#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GO_PENDING 0x00a9 +#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa +#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_TLB_PENDING 0x00ab +#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OARB_PENDING 0x00ac +#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OSD_PENDING 0x00ad +#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI0 0x00ae +#define regDAGB1_WRCLI0_BASE_IDX 0 +#define regDAGB1_WRCLI1 0x00af +#define regDAGB1_WRCLI1_BASE_IDX 0 +#define regDAGB1_WRCLI2 0x00b0 +#define regDAGB1_WRCLI2_BASE_IDX 0 +#define regDAGB1_WRCLI3 0x00b1 +#define regDAGB1_WRCLI3_BASE_IDX 0 +#define regDAGB1_WRCLI4 0x00b2 +#define regDAGB1_WRCLI4_BASE_IDX 0 +#define regDAGB1_WRCLI5 0x00b3 +#define regDAGB1_WRCLI5_BASE_IDX 0 +#define regDAGB1_WRCLI6 0x00b4 +#define regDAGB1_WRCLI6_BASE_IDX 0 +#define regDAGB1_WRCLI7 0x00b5 +#define regDAGB1_WRCLI7_BASE_IDX 0 +#define regDAGB1_WRCLI8 0x00b6 +#define regDAGB1_WRCLI8_BASE_IDX 0 +#define regDAGB1_WRCLI9 0x00b7 +#define regDAGB1_WRCLI9_BASE_IDX 0 +#define regDAGB1_WRCLI10 0x00b8 +#define regDAGB1_WRCLI10_BASE_IDX 0 +#define regDAGB1_WRCLI11 0x00b9 +#define regDAGB1_WRCLI11_BASE_IDX 0 +#define regDAGB1_WRCLI12 0x00ba +#define regDAGB1_WRCLI12_BASE_IDX 0 +#define regDAGB1_WRCLI13 0x00bb +#define regDAGB1_WRCLI13_BASE_IDX 0 +#define regDAGB1_WRCLI14 0x00bc +#define regDAGB1_WRCLI14_BASE_IDX 0 +#define regDAGB1_WRCLI15 0x00bd +#define regDAGB1_WRCLI15_BASE_IDX 0 +#define regDAGB1_WR_CNTL 0x00be +#define regDAGB1_WR_CNTL_BASE_IDX 0 +#define regDAGB1_WR_GMI_CNTL 0x00bf +#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB1_WR_ADDR_DAGB 0x00c0 +#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1 +#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2 +#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3 +#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4 +#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5 +#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8 +#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c9 +#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB1_WR_DATA_DAGB 0x00ca +#define regDAGB1_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cb +#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00cc +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cd +#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00ce +#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB1_WR_VC0_CNTL 0x00cf +#define regDAGB1_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC1_CNTL 0x00d0 +#define regDAGB1_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC2_CNTL 0x00d1 +#define regDAGB1_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC3_CNTL 0x00d2 +#define regDAGB1_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC4_CNTL 0x00d3 +#define regDAGB1_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC5_CNTL 0x00d4 +#define regDAGB1_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC6_CNTL 0x00d5 +#define regDAGB1_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB1_WR_VC7_CNTL 0x00d6 +#define regDAGB1_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB1_WR_CNTL_MISC 0x00d7 +#define regDAGB1_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_WR_TLB_CREDIT 0x00d8 +#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB1_WR_DATA_CREDIT 0x00d9 +#define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB1_WR_MISC_CREDIT 0x00da +#define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00db +#define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00dc +#define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00dd +#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00de +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00df +#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB1_WRCLI_ASK_PENDING 0x00e0 +#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_GO_PENDING 0x00e1 +#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e2 +#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_TLB_PENDING 0x00e3 +#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_OARB_PENDING 0x00e4 +#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_OSD_PENDING 0x00e5 +#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e6 +#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e7 +#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB1_DAGB_DLY 0x00e8 +#define regDAGB1_DAGB_DLY_BASE_IDX 0 +#define regDAGB1_CNTL_MISC 0x00e9 +#define regDAGB1_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_CNTL_MISC2 0x00ea +#define regDAGB1_CNTL_MISC2_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_CNTL 0x00eb +#define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_CLEAR 0x00ec +#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_STATUS0 0x00ed +#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_STATUS1 0x00ee +#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_STATUS2 0x00ef +#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB1_FATAL_ERROR_STATUS3 0x00f0 +#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB1_FIFO_EMPTY 0x00f1 +#define regDAGB1_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB1_FIFO_FULL 0x00f2 +#define regDAGB1_FIFO_FULL_BASE_IDX 0 +#define regDAGB1_WR_CREDITS_FULL 0x00f3 +#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB1_RD_CREDITS_FULL 0x00f4 +#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_LO 0x00f5 +#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_HI 0x00f6 +#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER0_CFG 0x00f7 +#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER1_CFG 0x00f8 +#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER2_CFG 0x00f9 +#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fa +#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB1_L1TLB_REG_RW 0x00fb +#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB1_RESERVE1 0x00fc +#define regDAGB1_RESERVE1_BASE_IDX 0 +#define regDAGB1_RESERVE2 0x00fd +#define regDAGB1_RESERVE2_BASE_IDX 0 +#define regDAGB1_RESERVE3 0x00fe +#define regDAGB1_RESERVE3_BASE_IDX 0 +#define regDAGB1_RESERVE4 0x00ff +#define regDAGB1_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_dagb_dagbdec2 +// base address: 0x68400 +#define regDAGB2_RDCLI0 0x0100 +#define regDAGB2_RDCLI0_BASE_IDX 0 +#define regDAGB2_RDCLI1 0x0101 +#define regDAGB2_RDCLI1_BASE_IDX 0 +#define regDAGB2_RDCLI2 0x0102 +#define regDAGB2_RDCLI2_BASE_IDX 0 +#define regDAGB2_RDCLI3 0x0103 +#define regDAGB2_RDCLI3_BASE_IDX 0 +#define regDAGB2_RDCLI4 0x0104 +#define regDAGB2_RDCLI4_BASE_IDX 0 +#define regDAGB2_RDCLI5 0x0105 +#define regDAGB2_RDCLI5_BASE_IDX 0 +#define regDAGB2_RDCLI6 0x0106 +#define regDAGB2_RDCLI6_BASE_IDX 0 +#define regDAGB2_RDCLI7 0x0107 +#define regDAGB2_RDCLI7_BASE_IDX 0 +#define regDAGB2_RDCLI8 0x0108 +#define regDAGB2_RDCLI8_BASE_IDX 0 +#define regDAGB2_RDCLI9 0x0109 +#define regDAGB2_RDCLI9_BASE_IDX 0 +#define regDAGB2_RDCLI10 0x010a +#define regDAGB2_RDCLI10_BASE_IDX 0 +#define regDAGB2_RDCLI11 0x010b +#define regDAGB2_RDCLI11_BASE_IDX 0 +#define regDAGB2_RDCLI12 0x010c +#define regDAGB2_RDCLI12_BASE_IDX 0 +#define regDAGB2_RDCLI13 0x010d +#define regDAGB2_RDCLI13_BASE_IDX 0 +#define regDAGB2_RDCLI14 0x010e +#define regDAGB2_RDCLI14_BASE_IDX 0 +#define regDAGB2_RDCLI15 0x010f +#define regDAGB2_RDCLI15_BASE_IDX 0 +#define regDAGB2_RD_CNTL 0x0110 +#define regDAGB2_RD_CNTL_BASE_IDX 0 +#define regDAGB2_RD_GMI_CNTL 0x0111 +#define regDAGB2_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB2_RD_ADDR_DAGB 0x0112 +#define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 +#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 +#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB2_RD_CGTT_CLK_CTRL 0x0115 +#define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 +#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 +#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 +#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 +#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a +#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b +#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB2_RD_VC0_CNTL 0x011c +#define regDAGB2_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC1_CNTL 0x011d +#define regDAGB2_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC2_CNTL 0x011e +#define regDAGB2_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC3_CNTL 0x011f +#define regDAGB2_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC4_CNTL 0x0120 +#define regDAGB2_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC5_CNTL 0x0121 +#define regDAGB2_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC6_CNTL 0x0122 +#define regDAGB2_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB2_RD_VC7_CNTL 0x0123 +#define regDAGB2_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB2_RD_CNTL_MISC 0x0124 +#define regDAGB2_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB2_RD_TLB_CREDIT 0x0125 +#define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126 +#define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127 +#define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB2_RDCLI_ASK_PENDING 0x0128 +#define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB2_RDCLI_GO_PENDING 0x0129 +#define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a +#define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB2_RDCLI_TLB_PENDING 0x012b +#define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB2_RDCLI_OARB_PENDING 0x012c +#define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB2_RDCLI_OSD_PENDING 0x012d +#define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI0 0x012e +#define regDAGB2_WRCLI0_BASE_IDX 0 +#define regDAGB2_WRCLI1 0x012f +#define regDAGB2_WRCLI1_BASE_IDX 0 +#define regDAGB2_WRCLI2 0x0130 +#define regDAGB2_WRCLI2_BASE_IDX 0 +#define regDAGB2_WRCLI3 0x0131 +#define regDAGB2_WRCLI3_BASE_IDX 0 +#define regDAGB2_WRCLI4 0x0132 +#define regDAGB2_WRCLI4_BASE_IDX 0 +#define regDAGB2_WRCLI5 0x0133 +#define regDAGB2_WRCLI5_BASE_IDX 0 +#define regDAGB2_WRCLI6 0x0134 +#define regDAGB2_WRCLI6_BASE_IDX 0 +#define regDAGB2_WRCLI7 0x0135 +#define regDAGB2_WRCLI7_BASE_IDX 0 +#define regDAGB2_WRCLI8 0x0136 +#define regDAGB2_WRCLI8_BASE_IDX 0 +#define regDAGB2_WRCLI9 0x0137 +#define regDAGB2_WRCLI9_BASE_IDX 0 +#define regDAGB2_WRCLI10 0x0138 +#define regDAGB2_WRCLI10_BASE_IDX 0 +#define regDAGB2_WRCLI11 0x0139 +#define regDAGB2_WRCLI11_BASE_IDX 0 +#define regDAGB2_WRCLI12 0x013a +#define regDAGB2_WRCLI12_BASE_IDX 0 +#define regDAGB2_WRCLI13 0x013b +#define regDAGB2_WRCLI13_BASE_IDX 0 +#define regDAGB2_WRCLI14 0x013c +#define regDAGB2_WRCLI14_BASE_IDX 0 +#define regDAGB2_WRCLI15 0x013d +#define regDAGB2_WRCLI15_BASE_IDX 0 +#define regDAGB2_WR_CNTL 0x013e +#define regDAGB2_WR_CNTL_BASE_IDX 0 +#define regDAGB2_WR_GMI_CNTL 0x013f +#define regDAGB2_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB2_WR_ADDR_DAGB 0x0140 +#define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0141 +#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0142 +#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB2_WR_CGTT_CLK_CTRL 0x0143 +#define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0144 +#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0145 +#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0146 +#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0147 +#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0148 +#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0149 +#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB2_WR_DATA_DAGB 0x014a +#define regDAGB2_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014b +#define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014c +#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014d +#define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014e +#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB2_WR_VC0_CNTL 0x014f +#define regDAGB2_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC1_CNTL 0x0150 +#define regDAGB2_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC2_CNTL 0x0151 +#define regDAGB2_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC3_CNTL 0x0152 +#define regDAGB2_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC4_CNTL 0x0153 +#define regDAGB2_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC5_CNTL 0x0154 +#define regDAGB2_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC6_CNTL 0x0155 +#define regDAGB2_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB2_WR_VC7_CNTL 0x0156 +#define regDAGB2_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB2_WR_CNTL_MISC 0x0157 +#define regDAGB2_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB2_WR_TLB_CREDIT 0x0158 +#define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB2_WR_DATA_CREDIT 0x0159 +#define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB2_WR_MISC_CREDIT 0x015a +#define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015b +#define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015c +#define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015d +#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015e +#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015f +#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB2_WRCLI_ASK_PENDING 0x0160 +#define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_GO_PENDING 0x0161 +#define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_GBLSEND_PENDING 0x0162 +#define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_TLB_PENDING 0x0163 +#define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_OARB_PENDING 0x0164 +#define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_OSD_PENDING 0x0165 +#define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0166 +#define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0167 +#define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB2_DAGB_DLY 0x0168 +#define regDAGB2_DAGB_DLY_BASE_IDX 0 +#define regDAGB2_CNTL_MISC 0x0169 +#define regDAGB2_CNTL_MISC_BASE_IDX 0 +#define regDAGB2_CNTL_MISC2 0x016a +#define regDAGB2_CNTL_MISC2_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_CNTL 0x016b +#define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_CLEAR 0x016c +#define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_STATUS0 0x016d +#define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_STATUS1 0x016e +#define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_STATUS2 0x016f +#define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB2_FATAL_ERROR_STATUS3 0x0170 +#define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB2_FIFO_EMPTY 0x0171 +#define regDAGB2_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB2_FIFO_FULL 0x0172 +#define regDAGB2_FIFO_FULL_BASE_IDX 0 +#define regDAGB2_WR_CREDITS_FULL 0x0173 +#define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB2_RD_CREDITS_FULL 0x0174 +#define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER_LO 0x0175 +#define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER_HI 0x0176 +#define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER0_CFG 0x0177 +#define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER1_CFG 0x0178 +#define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER2_CFG 0x0179 +#define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017a +#define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB2_L1TLB_REG_RW 0x017b +#define regDAGB2_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB2_RESERVE1 0x017c +#define regDAGB2_RESERVE1_BASE_IDX 0 +#define regDAGB2_RESERVE2 0x017d +#define regDAGB2_RESERVE2_BASE_IDX 0 +#define regDAGB2_RESERVE3 0x017e +#define regDAGB2_RESERVE3_BASE_IDX 0 +#define regDAGB2_RESERVE4 0x017f +#define regDAGB2_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_dagb_dagbdec3 +// base address: 0x68600 +#define regDAGB3_RDCLI0 0x0180 +#define regDAGB3_RDCLI0_BASE_IDX 0 +#define regDAGB3_RDCLI1 0x0181 +#define regDAGB3_RDCLI1_BASE_IDX 0 +#define regDAGB3_RDCLI2 0x0182 +#define regDAGB3_RDCLI2_BASE_IDX 0 +#define regDAGB3_RDCLI3 0x0183 +#define regDAGB3_RDCLI3_BASE_IDX 0 +#define regDAGB3_RDCLI4 0x0184 +#define regDAGB3_RDCLI4_BASE_IDX 0 +#define regDAGB3_RDCLI5 0x0185 +#define regDAGB3_RDCLI5_BASE_IDX 0 +#define regDAGB3_RDCLI6 0x0186 +#define regDAGB3_RDCLI6_BASE_IDX 0 +#define regDAGB3_RDCLI7 0x0187 +#define regDAGB3_RDCLI7_BASE_IDX 0 +#define regDAGB3_RDCLI8 0x0188 +#define regDAGB3_RDCLI8_BASE_IDX 0 +#define regDAGB3_RDCLI9 0x0189 +#define regDAGB3_RDCLI9_BASE_IDX 0 +#define regDAGB3_RDCLI10 0x018a +#define regDAGB3_RDCLI10_BASE_IDX 0 +#define regDAGB3_RDCLI11 0x018b +#define regDAGB3_RDCLI11_BASE_IDX 0 +#define regDAGB3_RDCLI12 0x018c +#define regDAGB3_RDCLI12_BASE_IDX 0 +#define regDAGB3_RDCLI13 0x018d +#define regDAGB3_RDCLI13_BASE_IDX 0 +#define regDAGB3_RDCLI14 0x018e +#define regDAGB3_RDCLI14_BASE_IDX 0 +#define regDAGB3_RDCLI15 0x018f +#define regDAGB3_RDCLI15_BASE_IDX 0 +#define regDAGB3_RD_CNTL 0x0190 +#define regDAGB3_RD_CNTL_BASE_IDX 0 +#define regDAGB3_RD_GMI_CNTL 0x0191 +#define regDAGB3_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB3_RD_ADDR_DAGB 0x0192 +#define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 +#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 +#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB3_RD_CGTT_CLK_CTRL 0x0195 +#define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 +#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 +#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 +#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 +#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a +#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b +#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB3_RD_VC0_CNTL 0x019c +#define regDAGB3_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC1_CNTL 0x019d +#define regDAGB3_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC2_CNTL 0x019e +#define regDAGB3_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC3_CNTL 0x019f +#define regDAGB3_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC4_CNTL 0x01a0 +#define regDAGB3_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC5_CNTL 0x01a1 +#define regDAGB3_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC6_CNTL 0x01a2 +#define regDAGB3_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB3_RD_VC7_CNTL 0x01a3 +#define regDAGB3_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB3_RD_CNTL_MISC 0x01a4 +#define regDAGB3_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB3_RD_TLB_CREDIT 0x01a5 +#define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6 +#define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7 +#define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB3_RDCLI_ASK_PENDING 0x01a8 +#define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB3_RDCLI_GO_PENDING 0x01a9 +#define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa +#define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB3_RDCLI_TLB_PENDING 0x01ab +#define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB3_RDCLI_OARB_PENDING 0x01ac +#define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB3_RDCLI_OSD_PENDING 0x01ad +#define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI0 0x01ae +#define regDAGB3_WRCLI0_BASE_IDX 0 +#define regDAGB3_WRCLI1 0x01af +#define regDAGB3_WRCLI1_BASE_IDX 0 +#define regDAGB3_WRCLI2 0x01b0 +#define regDAGB3_WRCLI2_BASE_IDX 0 +#define regDAGB3_WRCLI3 0x01b1 +#define regDAGB3_WRCLI3_BASE_IDX 0 +#define regDAGB3_WRCLI4 0x01b2 +#define regDAGB3_WRCLI4_BASE_IDX 0 +#define regDAGB3_WRCLI5 0x01b3 +#define regDAGB3_WRCLI5_BASE_IDX 0 +#define regDAGB3_WRCLI6 0x01b4 +#define regDAGB3_WRCLI6_BASE_IDX 0 +#define regDAGB3_WRCLI7 0x01b5 +#define regDAGB3_WRCLI7_BASE_IDX 0 +#define regDAGB3_WRCLI8 0x01b6 +#define regDAGB3_WRCLI8_BASE_IDX 0 +#define regDAGB3_WRCLI9 0x01b7 +#define regDAGB3_WRCLI9_BASE_IDX 0 +#define regDAGB3_WRCLI10 0x01b8 +#define regDAGB3_WRCLI10_BASE_IDX 0 +#define regDAGB3_WRCLI11 0x01b9 +#define regDAGB3_WRCLI11_BASE_IDX 0 +#define regDAGB3_WRCLI12 0x01ba +#define regDAGB3_WRCLI12_BASE_IDX 0 +#define regDAGB3_WRCLI13 0x01bb +#define regDAGB3_WRCLI13_BASE_IDX 0 +#define regDAGB3_WRCLI14 0x01bc +#define regDAGB3_WRCLI14_BASE_IDX 0 +#define regDAGB3_WRCLI15 0x01bd +#define regDAGB3_WRCLI15_BASE_IDX 0 +#define regDAGB3_WR_CNTL 0x01be +#define regDAGB3_WR_CNTL_BASE_IDX 0 +#define regDAGB3_WR_GMI_CNTL 0x01bf +#define regDAGB3_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB3_WR_ADDR_DAGB 0x01c0 +#define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c1 +#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c2 +#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB3_WR_CGTT_CLK_CTRL 0x01c3 +#define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c4 +#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c5 +#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c6 +#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c7 +#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c8 +#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c9 +#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB3_WR_DATA_DAGB 0x01ca +#define regDAGB3_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cb +#define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01cc +#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cd +#define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01ce +#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB3_WR_VC0_CNTL 0x01cf +#define regDAGB3_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC1_CNTL 0x01d0 +#define regDAGB3_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC2_CNTL 0x01d1 +#define regDAGB3_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC3_CNTL 0x01d2 +#define regDAGB3_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC4_CNTL 0x01d3 +#define regDAGB3_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC5_CNTL 0x01d4 +#define regDAGB3_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC6_CNTL 0x01d5 +#define regDAGB3_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB3_WR_VC7_CNTL 0x01d6 +#define regDAGB3_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB3_WR_CNTL_MISC 0x01d7 +#define regDAGB3_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB3_WR_TLB_CREDIT 0x01d8 +#define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB3_WR_DATA_CREDIT 0x01d9 +#define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB3_WR_MISC_CREDIT 0x01da +#define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01db +#define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01dc +#define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01dd +#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01de +#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01df +#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB3_WRCLI_ASK_PENDING 0x01e0 +#define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_GO_PENDING 0x01e1 +#define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e2 +#define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_TLB_PENDING 0x01e3 +#define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_OARB_PENDING 0x01e4 +#define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_OSD_PENDING 0x01e5 +#define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e6 +#define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e7 +#define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB3_DAGB_DLY 0x01e8 +#define regDAGB3_DAGB_DLY_BASE_IDX 0 +#define regDAGB3_CNTL_MISC 0x01e9 +#define regDAGB3_CNTL_MISC_BASE_IDX 0 +#define regDAGB3_CNTL_MISC2 0x01ea +#define regDAGB3_CNTL_MISC2_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_CNTL 0x01eb +#define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_CLEAR 0x01ec +#define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_STATUS0 0x01ed +#define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_STATUS1 0x01ee +#define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_STATUS2 0x01ef +#define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB3_FATAL_ERROR_STATUS3 0x01f0 +#define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB3_FIFO_EMPTY 0x01f1 +#define regDAGB3_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB3_FIFO_FULL 0x01f2 +#define regDAGB3_FIFO_FULL_BASE_IDX 0 +#define regDAGB3_WR_CREDITS_FULL 0x01f3 +#define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB3_RD_CREDITS_FULL 0x01f4 +#define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER_LO 0x01f5 +#define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER_HI 0x01f6 +#define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER0_CFG 0x01f7 +#define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER1_CFG 0x01f8 +#define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER2_CFG 0x01f9 +#define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fa +#define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB3_L1TLB_REG_RW 0x01fb +#define regDAGB3_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB3_RESERVE1 0x01fc +#define regDAGB3_RESERVE1_BASE_IDX 0 +#define regDAGB3_RESERVE2 0x01fd +#define regDAGB3_RESERVE2_BASE_IDX 0 +#define regDAGB3_RESERVE3 0x01fe +#define regDAGB3_RESERVE3_BASE_IDX 0 +#define regDAGB3_RESERVE4 0x01ff +#define regDAGB3_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_dagb_dagbdec4 +// base address: 0x68800 +#define regDAGB4_RDCLI0 0x0200 +#define regDAGB4_RDCLI0_BASE_IDX 0 +#define regDAGB4_RDCLI1 0x0201 +#define regDAGB4_RDCLI1_BASE_IDX 0 +#define regDAGB4_RDCLI2 0x0202 +#define regDAGB4_RDCLI2_BASE_IDX 0 +#define regDAGB4_RDCLI3 0x0203 +#define regDAGB4_RDCLI3_BASE_IDX 0 +#define regDAGB4_RDCLI4 0x0204 +#define regDAGB4_RDCLI4_BASE_IDX 0 +#define regDAGB4_RDCLI5 0x0205 +#define regDAGB4_RDCLI5_BASE_IDX 0 +#define regDAGB4_RDCLI6 0x0206 +#define regDAGB4_RDCLI6_BASE_IDX 0 +#define regDAGB4_RDCLI7 0x0207 +#define regDAGB4_RDCLI7_BASE_IDX 0 +#define regDAGB4_RDCLI8 0x0208 +#define regDAGB4_RDCLI8_BASE_IDX 0 +#define regDAGB4_RDCLI9 0x0209 +#define regDAGB4_RDCLI9_BASE_IDX 0 +#define regDAGB4_RDCLI10 0x020a +#define regDAGB4_RDCLI10_BASE_IDX 0 +#define regDAGB4_RDCLI11 0x020b +#define regDAGB4_RDCLI11_BASE_IDX 0 +#define regDAGB4_RDCLI12 0x020c +#define regDAGB4_RDCLI12_BASE_IDX 0 +#define regDAGB4_RDCLI13 0x020d +#define regDAGB4_RDCLI13_BASE_IDX 0 +#define regDAGB4_RDCLI14 0x020e +#define regDAGB4_RDCLI14_BASE_IDX 0 +#define regDAGB4_RDCLI15 0x020f +#define regDAGB4_RDCLI15_BASE_IDX 0 +#define regDAGB4_RD_CNTL 0x0210 +#define regDAGB4_RD_CNTL_BASE_IDX 0 +#define regDAGB4_RD_GMI_CNTL 0x0211 +#define regDAGB4_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB4_RD_ADDR_DAGB 0x0212 +#define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 +#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 +#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB4_RD_CGTT_CLK_CTRL 0x0215 +#define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 +#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 +#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 +#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 +#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a +#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b +#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB4_RD_VC0_CNTL 0x021c +#define regDAGB4_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC1_CNTL 0x021d +#define regDAGB4_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC2_CNTL 0x021e +#define regDAGB4_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC3_CNTL 0x021f +#define regDAGB4_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC4_CNTL 0x0220 +#define regDAGB4_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC5_CNTL 0x0221 +#define regDAGB4_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC6_CNTL 0x0222 +#define regDAGB4_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB4_RD_VC7_CNTL 0x0223 +#define regDAGB4_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB4_RD_CNTL_MISC 0x0224 +#define regDAGB4_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB4_RD_TLB_CREDIT 0x0225 +#define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226 +#define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227 +#define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB4_RDCLI_ASK_PENDING 0x0228 +#define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB4_RDCLI_GO_PENDING 0x0229 +#define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a +#define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB4_RDCLI_TLB_PENDING 0x022b +#define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB4_RDCLI_OARB_PENDING 0x022c +#define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB4_RDCLI_OSD_PENDING 0x022d +#define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI0 0x022e +#define regDAGB4_WRCLI0_BASE_IDX 0 +#define regDAGB4_WRCLI1 0x022f +#define regDAGB4_WRCLI1_BASE_IDX 0 +#define regDAGB4_WRCLI2 0x0230 +#define regDAGB4_WRCLI2_BASE_IDX 0 +#define regDAGB4_WRCLI3 0x0231 +#define regDAGB4_WRCLI3_BASE_IDX 0 +#define regDAGB4_WRCLI4 0x0232 +#define regDAGB4_WRCLI4_BASE_IDX 0 +#define regDAGB4_WRCLI5 0x0233 +#define regDAGB4_WRCLI5_BASE_IDX 0 +#define regDAGB4_WRCLI6 0x0234 +#define regDAGB4_WRCLI6_BASE_IDX 0 +#define regDAGB4_WRCLI7 0x0235 +#define regDAGB4_WRCLI7_BASE_IDX 0 +#define regDAGB4_WRCLI8 0x0236 +#define regDAGB4_WRCLI8_BASE_IDX 0 +#define regDAGB4_WRCLI9 0x0237 +#define regDAGB4_WRCLI9_BASE_IDX 0 +#define regDAGB4_WRCLI10 0x0238 +#define regDAGB4_WRCLI10_BASE_IDX 0 +#define regDAGB4_WRCLI11 0x0239 +#define regDAGB4_WRCLI11_BASE_IDX 0 +#define regDAGB4_WRCLI12 0x023a +#define regDAGB4_WRCLI12_BASE_IDX 0 +#define regDAGB4_WRCLI13 0x023b +#define regDAGB4_WRCLI13_BASE_IDX 0 +#define regDAGB4_WRCLI14 0x023c +#define regDAGB4_WRCLI14_BASE_IDX 0 +#define regDAGB4_WRCLI15 0x023d +#define regDAGB4_WRCLI15_BASE_IDX 0 +#define regDAGB4_WR_CNTL 0x023e +#define regDAGB4_WR_CNTL_BASE_IDX 0 +#define regDAGB4_WR_GMI_CNTL 0x023f +#define regDAGB4_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB4_WR_ADDR_DAGB 0x0240 +#define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0241 +#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0242 +#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB4_WR_CGTT_CLK_CTRL 0x0243 +#define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0244 +#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0245 +#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0246 +#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0247 +#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0248 +#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0249 +#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB4_WR_DATA_DAGB 0x024a +#define regDAGB4_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024b +#define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024c +#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024d +#define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024e +#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB4_WR_VC0_CNTL 0x024f +#define regDAGB4_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC1_CNTL 0x0250 +#define regDAGB4_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC2_CNTL 0x0251 +#define regDAGB4_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC3_CNTL 0x0252 +#define regDAGB4_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC4_CNTL 0x0253 +#define regDAGB4_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC5_CNTL 0x0254 +#define regDAGB4_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC6_CNTL 0x0255 +#define regDAGB4_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB4_WR_VC7_CNTL 0x0256 +#define regDAGB4_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB4_WR_CNTL_MISC 0x0257 +#define regDAGB4_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB4_WR_TLB_CREDIT 0x0258 +#define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB4_WR_DATA_CREDIT 0x0259 +#define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB4_WR_MISC_CREDIT 0x025a +#define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025b +#define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025c +#define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025d +#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025e +#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025f +#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB4_WRCLI_ASK_PENDING 0x0260 +#define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_GO_PENDING 0x0261 +#define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_GBLSEND_PENDING 0x0262 +#define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_TLB_PENDING 0x0263 +#define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_OARB_PENDING 0x0264 +#define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_OSD_PENDING 0x0265 +#define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0266 +#define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0267 +#define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB4_DAGB_DLY 0x0268 +#define regDAGB4_DAGB_DLY_BASE_IDX 0 +#define regDAGB4_CNTL_MISC 0x0269 +#define regDAGB4_CNTL_MISC_BASE_IDX 0 +#define regDAGB4_CNTL_MISC2 0x026a +#define regDAGB4_CNTL_MISC2_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_CNTL 0x026b +#define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_CLEAR 0x026c +#define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_STATUS0 0x026d +#define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_STATUS1 0x026e +#define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_STATUS2 0x026f +#define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB4_FATAL_ERROR_STATUS3 0x0270 +#define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB4_FIFO_EMPTY 0x0271 +#define regDAGB4_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB4_FIFO_FULL 0x0272 +#define regDAGB4_FIFO_FULL_BASE_IDX 0 +#define regDAGB4_WR_CREDITS_FULL 0x0273 +#define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB4_RD_CREDITS_FULL 0x0274 +#define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER_LO 0x0275 +#define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER_HI 0x0276 +#define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER0_CFG 0x0277 +#define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER1_CFG 0x0278 +#define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER2_CFG 0x0279 +#define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027a +#define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB4_L1TLB_REG_RW 0x027b +#define regDAGB4_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB4_RESERVE1 0x027c +#define regDAGB4_RESERVE1_BASE_IDX 0 +#define regDAGB4_RESERVE2 0x027d +#define regDAGB4_RESERVE2_BASE_IDX 0 +#define regDAGB4_RESERVE3 0x027e +#define regDAGB4_RESERVE3_BASE_IDX 0 +#define regDAGB4_RESERVE4 0x027f +#define regDAGB4_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_dagb_dagbdec5 +// base address: 0x68a00 +#define regDAGB5_RDCLI0 0x0280 +#define regDAGB5_RDCLI0_BASE_IDX 0 +#define regDAGB5_RDCLI1 0x0281 +#define regDAGB5_RDCLI1_BASE_IDX 0 +#define regDAGB5_RDCLI2 0x0282 +#define regDAGB5_RDCLI2_BASE_IDX 0 +#define regDAGB5_RDCLI3 0x0283 +#define regDAGB5_RDCLI3_BASE_IDX 0 +#define regDAGB5_RDCLI4 0x0284 +#define regDAGB5_RDCLI4_BASE_IDX 0 +#define regDAGB5_RDCLI5 0x0285 +#define regDAGB5_RDCLI5_BASE_IDX 0 +#define regDAGB5_RDCLI6 0x0286 +#define regDAGB5_RDCLI6_BASE_IDX 0 +#define regDAGB5_RDCLI7 0x0287 +#define regDAGB5_RDCLI7_BASE_IDX 0 +#define regDAGB5_RDCLI8 0x0288 +#define regDAGB5_RDCLI8_BASE_IDX 0 +#define regDAGB5_RDCLI9 0x0289 +#define regDAGB5_RDCLI9_BASE_IDX 0 +#define regDAGB5_RDCLI10 0x028a +#define regDAGB5_RDCLI10_BASE_IDX 0 +#define regDAGB5_RDCLI11 0x028b +#define regDAGB5_RDCLI11_BASE_IDX 0 +#define regDAGB5_RDCLI12 0x028c +#define regDAGB5_RDCLI12_BASE_IDX 0 +#define regDAGB5_RDCLI13 0x028d +#define regDAGB5_RDCLI13_BASE_IDX 0 +#define regDAGB5_RDCLI14 0x028e +#define regDAGB5_RDCLI14_BASE_IDX 0 +#define regDAGB5_RDCLI15 0x028f +#define regDAGB5_RDCLI15_BASE_IDX 0 +#define regDAGB5_RD_CNTL 0x0290 +#define regDAGB5_RD_CNTL_BASE_IDX 0 +#define regDAGB5_RD_GMI_CNTL 0x0291 +#define regDAGB5_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB5_RD_ADDR_DAGB 0x0292 +#define regDAGB5_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x0293 +#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x0294 +#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB5_RD_CGTT_CLK_CTRL 0x0295 +#define regDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x0296 +#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x0297 +#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x0298 +#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x0299 +#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x029a +#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x029b +#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB5_RD_VC0_CNTL 0x029c +#define regDAGB5_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC1_CNTL 0x029d +#define regDAGB5_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC2_CNTL 0x029e +#define regDAGB5_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC3_CNTL 0x029f +#define regDAGB5_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC4_CNTL 0x02a0 +#define regDAGB5_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC5_CNTL 0x02a1 +#define regDAGB5_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC6_CNTL 0x02a2 +#define regDAGB5_RD_VC6_CNTL_BASE_IDX 0 +#define regDAGB5_RD_VC7_CNTL 0x02a3 +#define regDAGB5_RD_VC7_CNTL_BASE_IDX 0 +#define regDAGB5_RD_CNTL_MISC 0x02a4 +#define regDAGB5_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB5_RD_TLB_CREDIT 0x02a5 +#define regDAGB5_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB5_RD_RDRET_CREDIT_CNTL 0x02a6 +#define regDAGB5_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB5_RD_RDRET_CREDIT_CNTL2 0x02a7 +#define regDAGB5_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB5_RDCLI_ASK_PENDING 0x02a8 +#define regDAGB5_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB5_RDCLI_GO_PENDING 0x02a9 +#define regDAGB5_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB5_RDCLI_GBLSEND_PENDING 0x02aa +#define regDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB5_RDCLI_TLB_PENDING 0x02ab +#define regDAGB5_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB5_RDCLI_OARB_PENDING 0x02ac +#define regDAGB5_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB5_RDCLI_OSD_PENDING 0x02ad +#define regDAGB5_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI0 0x02ae +#define regDAGB5_WRCLI0_BASE_IDX 0 +#define regDAGB5_WRCLI1 0x02af +#define regDAGB5_WRCLI1_BASE_IDX 0 +#define regDAGB5_WRCLI2 0x02b0 +#define regDAGB5_WRCLI2_BASE_IDX 0 +#define regDAGB5_WRCLI3 0x02b1 +#define regDAGB5_WRCLI3_BASE_IDX 0 +#define regDAGB5_WRCLI4 0x02b2 +#define regDAGB5_WRCLI4_BASE_IDX 0 +#define regDAGB5_WRCLI5 0x02b3 +#define regDAGB5_WRCLI5_BASE_IDX 0 +#define regDAGB5_WRCLI6 0x02b4 +#define regDAGB5_WRCLI6_BASE_IDX 0 +#define regDAGB5_WRCLI7 0x02b5 +#define regDAGB5_WRCLI7_BASE_IDX 0 +#define regDAGB5_WRCLI8 0x02b6 +#define regDAGB5_WRCLI8_BASE_IDX 0 +#define regDAGB5_WRCLI9 0x02b7 +#define regDAGB5_WRCLI9_BASE_IDX 0 +#define regDAGB5_WRCLI10 0x02b8 +#define regDAGB5_WRCLI10_BASE_IDX 0 +#define regDAGB5_WRCLI11 0x02b9 +#define regDAGB5_WRCLI11_BASE_IDX 0 +#define regDAGB5_WRCLI12 0x02ba +#define regDAGB5_WRCLI12_BASE_IDX 0 +#define regDAGB5_WRCLI13 0x02bb +#define regDAGB5_WRCLI13_BASE_IDX 0 +#define regDAGB5_WRCLI14 0x02bc +#define regDAGB5_WRCLI14_BASE_IDX 0 +#define regDAGB5_WRCLI15 0x02bd +#define regDAGB5_WRCLI15_BASE_IDX 0 +#define regDAGB5_WR_CNTL 0x02be +#define regDAGB5_WR_CNTL_BASE_IDX 0 +#define regDAGB5_WR_GMI_CNTL 0x02bf +#define regDAGB5_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB5_WR_ADDR_DAGB 0x02c0 +#define regDAGB5_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x02c1 +#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x02c2 +#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define regDAGB5_WR_CGTT_CLK_CTRL 0x02c3 +#define regDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x02c4 +#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x02c5 +#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x02c6 +#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x02c7 +#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x02c8 +#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x02c9 +#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB5_WR_DATA_DAGB 0x02ca +#define regDAGB5_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB5_WR_DATA_DAGB_MAX_BURST0 0x02cb +#define regDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x02cc +#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB5_WR_DATA_DAGB_MAX_BURST1 0x02cd +#define regDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x02ce +#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB5_WR_VC0_CNTL 0x02cf +#define regDAGB5_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC1_CNTL 0x02d0 +#define regDAGB5_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC2_CNTL 0x02d1 +#define regDAGB5_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC3_CNTL 0x02d2 +#define regDAGB5_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC4_CNTL 0x02d3 +#define regDAGB5_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC5_CNTL 0x02d4 +#define regDAGB5_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC6_CNTL 0x02d5 +#define regDAGB5_WR_VC6_CNTL_BASE_IDX 0 +#define regDAGB5_WR_VC7_CNTL 0x02d6 +#define regDAGB5_WR_VC7_CNTL_BASE_IDX 0 +#define regDAGB5_WR_CNTL_MISC 0x02d7 +#define regDAGB5_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB5_WR_TLB_CREDIT 0x02d8 +#define regDAGB5_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB5_WR_DATA_CREDIT 0x02d9 +#define regDAGB5_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB5_WR_MISC_CREDIT 0x02da +#define regDAGB5_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB5_WR_OSD_CREDIT_CNTL1 0x02db +#define regDAGB5_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB5_WR_OSD_CREDIT_CNTL2 0x02dc +#define regDAGB5_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x02dd +#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x02de +#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02df +#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB5_WRCLI_ASK_PENDING 0x02e0 +#define regDAGB5_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_GO_PENDING 0x02e1 +#define regDAGB5_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_GBLSEND_PENDING 0x02e2 +#define regDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_TLB_PENDING 0x02e3 +#define regDAGB5_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_OARB_PENDING 0x02e4 +#define regDAGB5_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_OSD_PENDING 0x02e5 +#define regDAGB5_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_DBUS_ASK_PENDING 0x02e6 +#define regDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB5_WRCLI_DBUS_GO_PENDING 0x02e7 +#define regDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB5_DAGB_DLY 0x02e8 +#define regDAGB5_DAGB_DLY_BASE_IDX 0 +#define regDAGB5_CNTL_MISC 0x02e9 +#define regDAGB5_CNTL_MISC_BASE_IDX 0 +#define regDAGB5_CNTL_MISC2 0x02ea +#define regDAGB5_CNTL_MISC2_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_CNTL 0x02eb +#define regDAGB5_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_CLEAR 0x02ec +#define regDAGB5_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_STATUS0 0x02ed +#define regDAGB5_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_STATUS1 0x02ee +#define regDAGB5_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_STATUS2 0x02ef +#define regDAGB5_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB5_FATAL_ERROR_STATUS3 0x02f0 +#define regDAGB5_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB5_FIFO_EMPTY 0x02f1 +#define regDAGB5_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB5_FIFO_FULL 0x02f2 +#define regDAGB5_FIFO_FULL_BASE_IDX 0 +#define regDAGB5_WR_CREDITS_FULL 0x02f3 +#define regDAGB5_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB5_RD_CREDITS_FULL 0x02f4 +#define regDAGB5_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER_LO 0x02f5 +#define regDAGB5_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER_HI 0x02f6 +#define regDAGB5_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER0_CFG 0x02f7 +#define regDAGB5_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER1_CFG 0x02f8 +#define regDAGB5_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER2_CFG 0x02f9 +#define regDAGB5_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB5_PERFCOUNTER_RSLT_CNTL 0x02fa +#define regDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB5_L1TLB_REG_RW 0x02fb +#define regDAGB5_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB5_RESERVE1 0x02fc +#define regDAGB5_RESERVE1_BASE_IDX 0 +#define regDAGB5_RESERVE2 0x02fd +#define regDAGB5_RESERVE2_BASE_IDX 0 +#define regDAGB5_RESERVE3 0x02fe +#define regDAGB5_RESERVE3_BASE_IDX 0 +#define regDAGB5_RESERVE4 0x02ff +#define regDAGB5_RESERVE4_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec0 +// base address: 0x68c00 +#define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300 +#define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301 +#define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302 +#define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303 +#define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304 +#define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305 +#define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA0_DRAM_RD_LAZY 0x0306 +#define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA0_DRAM_WR_LAZY 0x0307 +#define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA0_DRAM_RD_CAM_CNTL 0x0308 +#define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA0_DRAM_WR_CAM_CNTL 0x0309 +#define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA0_DRAM_PAGE_BURST 0x030a +#define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_AGE 0x030b +#define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_AGE 0x030c +#define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d +#define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e +#define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_FIXED 0x030f +#define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_FIXED 0x0310 +#define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311 +#define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312 +#define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315 +#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318 +#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319 +#define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a +#define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b +#define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c +#define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d +#define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e +#define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA0_GMI_RD_LAZY 0x031f +#define regMMEA0_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA0_GMI_WR_LAZY 0x0320 +#define regMMEA0_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA0_GMI_RD_CAM_CNTL 0x0321 +#define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA0_GMI_WR_CAM_CNTL 0x0322 +#define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA0_GMI_PAGE_BURST 0x0323 +#define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_AGE 0x0324 +#define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_AGE 0x0325 +#define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_QUEUING 0x0326 +#define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_QUEUING 0x0327 +#define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_FIXED 0x0328 +#define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_FIXED 0x0329 +#define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_URGENCY 0x032a +#define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_URGENCY 0x032b +#define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c +#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d +#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e +#define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f +#define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330 +#define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333 +#define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_ADDRNORM_BASE_ADDR0 0x0334 +#define regMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA0_ADDRNORM_LIMIT_ADDR0 0x0335 +#define regMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA0_ADDRNORM_BASE_ADDR1 0x0336 +#define regMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORM_LIMIT_ADDR1 0x0337 +#define regMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORM_OFFSET_ADDR1 0x0338 +#define regMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORM_BASE_ADDR2 0x0339 +#define regMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA0_ADDRNORM_LIMIT_ADDR2 0x033a +#define regMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA0_ADDRNORM_BASE_ADDR3 0x033b +#define regMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA0_ADDRNORM_LIMIT_ADDR3 0x033c +#define regMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA0_ADDRNORM_OFFSET_ADDR3 0x033d +#define regMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGABASE_ADDR0 0x033e +#define regMMEA0_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0x033f +#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGABASE_ADDR1 0x0340 +#define regMMEA0_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0x0341 +#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0343 +#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA0_ADDRNORMGMI_HOLE_CNTL 0x0344 +#define regMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0345 +#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0346 +#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA0_ADDRDEC_BANK_CFG 0x0347 +#define regMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA0_ADDRDEC_MISC_CFG 0x0348 +#define regMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0353 +#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x035e +#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x035f +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0360 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0361 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0362 +#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0363 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0364 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0365 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0366 +#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0367 +#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0368 +#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0369 +#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x036a +#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x036b +#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x036c +#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x036d +#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x036e +#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x036f +#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0370 +#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0371 +#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0372 +#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0373 +#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0374 +#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_RM_SEL_CS01 0x0375 +#define regMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_RM_SEL_CS23 0x0376 +#define regMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0377 +#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0378 +#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0379 +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x037a +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x037b +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x037c +#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x037d +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x037e +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x037f +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0380 +#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0381 +#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0382 +#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0383 +#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0384 +#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0385 +#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0386 +#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0387 +#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0388 +#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0389 +#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x038a +#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x038b +#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x038c +#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x038d +#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x038e +#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_RM_SEL_CS01 0x038f +#define regMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_RM_SEL_CS23 0x0390 +#define regMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0391 +#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0392 +#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0393 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0394 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0395 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0396 +#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0397 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0398 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0399 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x039a +#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x039b +#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x039c +#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x039d +#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x039e +#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x039f +#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x03a0 +#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x03a1 +#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x03a2 +#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x03a3 +#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x03a4 +#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x03a5 +#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x03a6 +#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x03a7 +#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x03a8 +#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_RM_SEL_CS01 0x03a9 +#define regMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_RM_SEL_CS23 0x03aa +#define regMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x03ab +#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x03ac +#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x03ad +#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x03ae +#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0x03d1 +#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0x03d2 +#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA0_ADDRNORMDRAM_MASKING 0x03d3 +#define regMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA0_ADDRNORMGMI_MASKING 0x03d4 +#define regMMEA0_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5 +#define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6 +#define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7 +#define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8 +#define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9 +#define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da +#define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA0_IO_GROUP_BURST 0x03db +#define regMMEA0_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_AGE 0x03dc +#define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_AGE 0x03dd +#define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_QUEUING 0x03de +#define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_QUEUING 0x03df +#define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_FIXED 0x03e0 +#define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_FIXED 0x03e1 +#define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_URGENCY 0x03e2 +#define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_URGENCY 0x03e3 +#define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4 +#define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5 +#define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6 +#define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7 +#define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8 +#define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9 +#define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea +#define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb +#define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA0_SDP_ARB_DRAM 0x03ec +#define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA0_SDP_ARB_GMI 0x03ed +#define regMMEA0_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA0_SDP_ARB_FINAL 0x03ee +#define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA0_SDP_DRAM_PRIORITY 0x03ef +#define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA0_SDP_GMI_PRIORITY 0x03f0 +#define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA0_SDP_IO_PRIORITY 0x03f1 +#define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA0_SDP_CREDITS 0x03f2 +#define regMMEA0_SDP_CREDITS_BASE_IDX 0 +#define regMMEA0_SDP_TAG_RESERVE0 0x03f3 +#define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA0_SDP_TAG_RESERVE1 0x03f4 +#define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA0_SDP_VCC_RESERVE0 0x03f5 +#define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA0_SDP_VCC_RESERVE1 0x03f6 +#define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA0_SDP_VCD_RESERVE0 0x03f7 +#define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA0_SDP_VCD_RESERVE1 0x03f8 +#define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA0_SDP_REQ_CNTL 0x03f9 +#define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA0_MISC 0x03fa +#define regMMEA0_MISC_BASE_IDX 0 +#define regMMEA0_LATENCY_SAMPLING 0x03fb +#define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA0_PERFCOUNTER_LO 0x03fc +#define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA0_PERFCOUNTER_HI 0x03fd +#define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA0_PERFCOUNTER0_CFG 0x03fe +#define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA0_PERFCOUNTER1_CFG 0x03ff +#define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400 +#define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA0_EDC_CNT 0x0406 +#define regMMEA0_EDC_CNT_BASE_IDX 0 +#define regMMEA0_EDC_CNT2 0x0407 +#define regMMEA0_EDC_CNT2_BASE_IDX 0 +#define regMMEA0_DSM_CNTL 0x0408 +#define regMMEA0_DSM_CNTL_BASE_IDX 0 +#define regMMEA0_DSM_CNTLA 0x0409 +#define regMMEA0_DSM_CNTLA_BASE_IDX 0 +#define regMMEA0_DSM_CNTLB 0x040a +#define regMMEA0_DSM_CNTLB_BASE_IDX 0 +#define regMMEA0_DSM_CNTL2 0x040b +#define regMMEA0_DSM_CNTL2_BASE_IDX 0 +#define regMMEA0_DSM_CNTL2A 0x040c +#define regMMEA0_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA0_DSM_CNTL2B 0x040d +#define regMMEA0_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA0_CGTT_CLK_CTRL 0x040f +#define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA0_EDC_MODE 0x0410 +#define regMMEA0_EDC_MODE_BASE_IDX 0 +#define regMMEA0_ERR_STATUS 0x0411 +#define regMMEA0_ERR_STATUS_BASE_IDX 0 +#define regMMEA0_MISC2 0x0412 +#define regMMEA0_MISC2_BASE_IDX 0 +#define regMMEA0_ADDRDEC_SELECT 0x0413 +#define regMMEA0_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA0_EDC_CNT3 0x0414 +#define regMMEA0_EDC_CNT3_BASE_IDX 0 +#define regMMEA0_MISC_AON 0x0415 +#define regMMEA0_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec1 +// base address: 0x69100 +#define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440 +#define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441 +#define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442 +#define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443 +#define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444 +#define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445 +#define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA1_DRAM_RD_LAZY 0x0446 +#define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA1_DRAM_WR_LAZY 0x0447 +#define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA1_DRAM_RD_CAM_CNTL 0x0448 +#define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA1_DRAM_WR_CAM_CNTL 0x0449 +#define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA1_DRAM_PAGE_BURST 0x044a +#define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_AGE 0x044b +#define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_AGE 0x044c +#define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d +#define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e +#define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_FIXED 0x044f +#define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_FIXED 0x0450 +#define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451 +#define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452 +#define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455 +#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458 +#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459 +#define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a +#define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b +#define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c +#define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d +#define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e +#define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA1_GMI_RD_LAZY 0x045f +#define regMMEA1_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA1_GMI_WR_LAZY 0x0460 +#define regMMEA1_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA1_GMI_RD_CAM_CNTL 0x0461 +#define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA1_GMI_WR_CAM_CNTL 0x0462 +#define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA1_GMI_PAGE_BURST 0x0463 +#define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_AGE 0x0464 +#define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_AGE 0x0465 +#define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_QUEUING 0x0466 +#define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_QUEUING 0x0467 +#define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_FIXED 0x0468 +#define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_FIXED 0x0469 +#define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_URGENCY 0x046a +#define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_URGENCY 0x046b +#define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c +#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d +#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e +#define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f +#define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470 +#define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473 +#define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_ADDRNORM_BASE_ADDR0 0x0474 +#define regMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA1_ADDRNORM_LIMIT_ADDR0 0x0475 +#define regMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA1_ADDRNORM_BASE_ADDR1 0x0476 +#define regMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORM_LIMIT_ADDR1 0x0477 +#define regMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORM_OFFSET_ADDR1 0x0478 +#define regMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORM_BASE_ADDR2 0x0479 +#define regMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA1_ADDRNORM_LIMIT_ADDR2 0x047a +#define regMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA1_ADDRNORM_BASE_ADDR3 0x047b +#define regMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA1_ADDRNORM_LIMIT_ADDR3 0x047c +#define regMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA1_ADDRNORM_OFFSET_ADDR3 0x047d +#define regMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGABASE_ADDR0 0x047e +#define regMMEA1_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0x047f +#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGABASE_ADDR1 0x0480 +#define regMMEA1_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0x0481 +#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0483 +#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0484 +#define regMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0485 +#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0486 +#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA1_ADDRDEC_BANK_CFG 0x0487 +#define regMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA1_ADDRDEC_MISC_CFG 0x0488 +#define regMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0493 +#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x049e +#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x049f +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x04a0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x04a1 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x04a2 +#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x04a3 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x04a4 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x04a5 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x04a6 +#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x04a7 +#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x04a8 +#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x04a9 +#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x04aa +#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x04ab +#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x04ac +#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x04ad +#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x04ae +#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x04af +#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x04b0 +#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x04b1 +#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x04b2 +#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x04b3 +#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x04b4 +#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_RM_SEL_CS01 0x04b5 +#define regMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_RM_SEL_CS23 0x04b6 +#define regMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x04b7 +#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x04b8 +#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x04b9 +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x04ba +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x04bb +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x04bc +#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x04bd +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x04be +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x04bf +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x04c0 +#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x04c1 +#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x04c2 +#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x04c3 +#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x04c4 +#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x04c5 +#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x04c6 +#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x04c7 +#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x04c8 +#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x04c9 +#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x04ca +#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x04cb +#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x04cc +#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x04cd +#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x04ce +#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_RM_SEL_CS01 0x04cf +#define regMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_RM_SEL_CS23 0x04d0 +#define regMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x04d1 +#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x04d2 +#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x04d3 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x04d4 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x04d5 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x04d6 +#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x04d7 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x04d8 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x04d9 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x04da +#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x04db +#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x04dc +#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x04dd +#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x04de +#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x04df +#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x04e0 +#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x04e1 +#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x04e2 +#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x04e3 +#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x04e4 +#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x04e5 +#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x04e6 +#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x04e7 +#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x04e8 +#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_RM_SEL_CS01 0x04e9 +#define regMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_RM_SEL_CS23 0x04ea +#define regMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x04eb +#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x04ec +#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x04ed +#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x04ee +#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0x0511 +#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0x0512 +#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA1_ADDRNORMDRAM_MASKING 0x0513 +#define regMMEA1_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA1_ADDRNORMGMI_MASKING 0x0514 +#define regMMEA1_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515 +#define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516 +#define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517 +#define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518 +#define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519 +#define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a +#define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA1_IO_GROUP_BURST 0x051b +#define regMMEA1_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_AGE 0x051c +#define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_AGE 0x051d +#define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_QUEUING 0x051e +#define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_QUEUING 0x051f +#define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_FIXED 0x0520 +#define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_FIXED 0x0521 +#define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_URGENCY 0x0522 +#define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_URGENCY 0x0523 +#define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524 +#define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525 +#define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526 +#define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527 +#define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528 +#define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529 +#define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a +#define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b +#define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA1_SDP_ARB_DRAM 0x052c +#define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA1_SDP_ARB_GMI 0x052d +#define regMMEA1_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA1_SDP_ARB_FINAL 0x052e +#define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA1_SDP_DRAM_PRIORITY 0x052f +#define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA1_SDP_GMI_PRIORITY 0x0530 +#define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA1_SDP_IO_PRIORITY 0x0531 +#define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA1_SDP_CREDITS 0x0532 +#define regMMEA1_SDP_CREDITS_BASE_IDX 0 +#define regMMEA1_SDP_TAG_RESERVE0 0x0533 +#define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA1_SDP_TAG_RESERVE1 0x0534 +#define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA1_SDP_VCC_RESERVE0 0x0535 +#define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA1_SDP_VCC_RESERVE1 0x0536 +#define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA1_SDP_VCD_RESERVE0 0x0537 +#define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA1_SDP_VCD_RESERVE1 0x0538 +#define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA1_SDP_REQ_CNTL 0x0539 +#define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA1_MISC 0x053a +#define regMMEA1_MISC_BASE_IDX 0 +#define regMMEA1_LATENCY_SAMPLING 0x053b +#define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA1_PERFCOUNTER_LO 0x053c +#define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA1_PERFCOUNTER_HI 0x053d +#define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA1_PERFCOUNTER0_CFG 0x053e +#define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA1_PERFCOUNTER1_CFG 0x053f +#define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540 +#define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA1_EDC_CNT 0x0546 +#define regMMEA1_EDC_CNT_BASE_IDX 0 +#define regMMEA1_EDC_CNT2 0x0547 +#define regMMEA1_EDC_CNT2_BASE_IDX 0 +#define regMMEA1_DSM_CNTL 0x0548 +#define regMMEA1_DSM_CNTL_BASE_IDX 0 +#define regMMEA1_DSM_CNTLA 0x0549 +#define regMMEA1_DSM_CNTLA_BASE_IDX 0 +#define regMMEA1_DSM_CNTLB 0x054a +#define regMMEA1_DSM_CNTLB_BASE_IDX 0 +#define regMMEA1_DSM_CNTL2 0x054b +#define regMMEA1_DSM_CNTL2_BASE_IDX 0 +#define regMMEA1_DSM_CNTL2A 0x054c +#define regMMEA1_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA1_DSM_CNTL2B 0x054d +#define regMMEA1_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA1_CGTT_CLK_CTRL 0x054f +#define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA1_EDC_MODE 0x0550 +#define regMMEA1_EDC_MODE_BASE_IDX 0 +#define regMMEA1_ERR_STATUS 0x0551 +#define regMMEA1_ERR_STATUS_BASE_IDX 0 +#define regMMEA1_MISC2 0x0552 +#define regMMEA1_MISC2_BASE_IDX 0 +#define regMMEA1_ADDRDEC_SELECT 0x0553 +#define regMMEA1_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA1_EDC_CNT3 0x0554 +#define regMMEA1_EDC_CNT3_BASE_IDX 0 +#define regMMEA1_MISC_AON 0x0555 +#define regMMEA1_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec2 +// base address: 0x69600 +#define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580 +#define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581 +#define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582 +#define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583 +#define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584 +#define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585 +#define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA2_DRAM_RD_LAZY 0x0586 +#define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA2_DRAM_WR_LAZY 0x0587 +#define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA2_DRAM_RD_CAM_CNTL 0x0588 +#define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA2_DRAM_WR_CAM_CNTL 0x0589 +#define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA2_DRAM_PAGE_BURST 0x058a +#define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_AGE 0x058b +#define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_AGE 0x058c +#define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d +#define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e +#define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_FIXED 0x058f +#define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_FIXED 0x0590 +#define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591 +#define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592 +#define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595 +#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598 +#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599 +#define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a +#define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b +#define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c +#define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d +#define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e +#define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA2_GMI_RD_LAZY 0x059f +#define regMMEA2_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA2_GMI_WR_LAZY 0x05a0 +#define regMMEA2_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA2_GMI_RD_CAM_CNTL 0x05a1 +#define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA2_GMI_WR_CAM_CNTL 0x05a2 +#define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA2_GMI_PAGE_BURST 0x05a3 +#define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_AGE 0x05a4 +#define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_AGE 0x05a5 +#define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6 +#define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7 +#define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_FIXED 0x05a8 +#define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_FIXED 0x05a9 +#define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa +#define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab +#define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac +#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad +#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae +#define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af +#define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0 +#define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3 +#define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_ADDRNORM_BASE_ADDR0 0x05b4 +#define regMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA2_ADDRNORM_LIMIT_ADDR0 0x05b5 +#define regMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA2_ADDRNORM_BASE_ADDR1 0x05b6 +#define regMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORM_LIMIT_ADDR1 0x05b7 +#define regMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORM_OFFSET_ADDR1 0x05b8 +#define regMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORM_BASE_ADDR2 0x05b9 +#define regMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA2_ADDRNORM_LIMIT_ADDR2 0x05ba +#define regMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA2_ADDRNORM_BASE_ADDR3 0x05bb +#define regMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA2_ADDRNORM_LIMIT_ADDR3 0x05bc +#define regMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA2_ADDRNORM_OFFSET_ADDR3 0x05bd +#define regMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGABASE_ADDR0 0x05be +#define regMMEA2_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0 0x05bf +#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGABASE_ADDR1 0x05c0 +#define regMMEA2_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1 0x05c1 +#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x05c3 +#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA2_ADDRNORMGMI_HOLE_CNTL 0x05c4 +#define regMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x05c5 +#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x05c6 +#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA2_ADDRDEC_BANK_CFG 0x05c7 +#define regMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA2_ADDRDEC_MISC_CFG 0x05c8 +#define regMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x05d3 +#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x05de +#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x05df +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x05e0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x05e1 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x05e2 +#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x05e3 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x05e4 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x05e5 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x05e6 +#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x05e7 +#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x05e8 +#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x05e9 +#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x05ea +#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x05eb +#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x05ec +#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x05ed +#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x05ee +#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x05ef +#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x05f0 +#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x05f1 +#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x05f2 +#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x05f3 +#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x05f4 +#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_RM_SEL_CS01 0x05f5 +#define regMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_RM_SEL_CS23 0x05f6 +#define regMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x05f7 +#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x05f8 +#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x05f9 +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x05fa +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x05fb +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x05fc +#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x05fd +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x05fe +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x05ff +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0600 +#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0601 +#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0602 +#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0603 +#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0604 +#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0605 +#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0606 +#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0607 +#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0608 +#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0609 +#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x060a +#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x060b +#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x060c +#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x060d +#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x060e +#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_RM_SEL_CS01 0x060f +#define regMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_RM_SEL_CS23 0x0610 +#define regMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0611 +#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0612 +#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0613 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0614 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0615 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0616 +#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0617 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0618 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0619 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x061a +#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x061b +#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x061c +#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x061d +#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x061e +#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x061f +#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x0620 +#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x0621 +#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x0622 +#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x0623 +#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x0624 +#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x0625 +#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x0626 +#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x0627 +#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x0628 +#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_RM_SEL_CS01 0x0629 +#define regMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_RM_SEL_CS23 0x062a +#define regMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x062b +#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x062c +#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x062d +#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x062e +#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0 0x0651 +#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1 0x0652 +#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA2_ADDRNORMDRAM_MASKING 0x0653 +#define regMMEA2_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA2_ADDRNORMGMI_MASKING 0x0654 +#define regMMEA2_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA2_IO_RD_CLI2GRP_MAP0 0x0655 +#define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_IO_RD_CLI2GRP_MAP1 0x0656 +#define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_IO_WR_CLI2GRP_MAP0 0x0657 +#define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA2_IO_WR_CLI2GRP_MAP1 0x0658 +#define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA2_IO_RD_COMBINE_FLUSH 0x0659 +#define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA2_IO_WR_COMBINE_FLUSH 0x065a +#define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA2_IO_GROUP_BURST 0x065b +#define regMMEA2_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_AGE 0x065c +#define regMMEA2_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_AGE 0x065d +#define regMMEA2_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_QUEUING 0x065e +#define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_QUEUING 0x065f +#define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_FIXED 0x0660 +#define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_FIXED 0x0661 +#define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_URGENCY 0x0662 +#define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_URGENCY 0x0663 +#define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_URGENCY_MASKING 0x0664 +#define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_URGENCY_MASKING 0x0665 +#define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_QUANT_PRI1 0x0666 +#define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_QUANT_PRI2 0x0667 +#define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_IO_RD_PRI_QUANT_PRI3 0x0668 +#define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_QUANT_PRI1 0x0669 +#define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_QUANT_PRI2 0x066a +#define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA2_IO_WR_PRI_QUANT_PRI3 0x066b +#define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA2_SDP_ARB_DRAM 0x066c +#define regMMEA2_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA2_SDP_ARB_GMI 0x066d +#define regMMEA2_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA2_SDP_ARB_FINAL 0x066e +#define regMMEA2_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA2_SDP_DRAM_PRIORITY 0x066f +#define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA2_SDP_GMI_PRIORITY 0x0670 +#define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA2_SDP_IO_PRIORITY 0x0671 +#define regMMEA2_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA2_SDP_CREDITS 0x0672 +#define regMMEA2_SDP_CREDITS_BASE_IDX 0 +#define regMMEA2_SDP_TAG_RESERVE0 0x0673 +#define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA2_SDP_TAG_RESERVE1 0x0674 +#define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA2_SDP_VCC_RESERVE0 0x0675 +#define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA2_SDP_VCC_RESERVE1 0x0676 +#define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA2_SDP_VCD_RESERVE0 0x0677 +#define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA2_SDP_VCD_RESERVE1 0x0678 +#define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA2_SDP_REQ_CNTL 0x0679 +#define regMMEA2_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA2_MISC 0x067a +#define regMMEA2_MISC_BASE_IDX 0 +#define regMMEA2_LATENCY_SAMPLING 0x067b +#define regMMEA2_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA2_PERFCOUNTER_LO 0x067c +#define regMMEA2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA2_PERFCOUNTER_HI 0x067d +#define regMMEA2_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA2_PERFCOUNTER0_CFG 0x067e +#define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA2_PERFCOUNTER1_CFG 0x067f +#define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680 +#define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA2_EDC_CNT 0x0686 +#define regMMEA2_EDC_CNT_BASE_IDX 0 +#define regMMEA2_EDC_CNT2 0x0687 +#define regMMEA2_EDC_CNT2_BASE_IDX 0 +#define regMMEA2_DSM_CNTL 0x0688 +#define regMMEA2_DSM_CNTL_BASE_IDX 0 +#define regMMEA2_DSM_CNTLA 0x0689 +#define regMMEA2_DSM_CNTLA_BASE_IDX 0 +#define regMMEA2_DSM_CNTLB 0x068a +#define regMMEA2_DSM_CNTLB_BASE_IDX 0 +#define regMMEA2_DSM_CNTL2 0x068b +#define regMMEA2_DSM_CNTL2_BASE_IDX 0 +#define regMMEA2_DSM_CNTL2A 0x068c +#define regMMEA2_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA2_DSM_CNTL2B 0x068d +#define regMMEA2_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA2_CGTT_CLK_CTRL 0x068f +#define regMMEA2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA2_EDC_MODE 0x0690 +#define regMMEA2_EDC_MODE_BASE_IDX 0 +#define regMMEA2_ERR_STATUS 0x0691 +#define regMMEA2_ERR_STATUS_BASE_IDX 0 +#define regMMEA2_MISC2 0x0692 +#define regMMEA2_MISC2_BASE_IDX 0 +#define regMMEA2_ADDRDEC_SELECT 0x0693 +#define regMMEA2_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA2_EDC_CNT3 0x0694 +#define regMMEA2_EDC_CNT3_BASE_IDX 0 +#define regMMEA2_MISC_AON 0x0695 +#define regMMEA2_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec3 +// base address: 0x69b00 +#define regMMEA3_DRAM_RD_CLI2GRP_MAP0 0x06c0 +#define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_DRAM_RD_CLI2GRP_MAP1 0x06c1 +#define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_DRAM_WR_CLI2GRP_MAP0 0x06c2 +#define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_DRAM_WR_CLI2GRP_MAP1 0x06c3 +#define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_DRAM_RD_GRP2VC_MAP 0x06c4 +#define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA3_DRAM_WR_GRP2VC_MAP 0x06c5 +#define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA3_DRAM_RD_LAZY 0x06c6 +#define regMMEA3_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA3_DRAM_WR_LAZY 0x06c7 +#define regMMEA3_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA3_DRAM_RD_CAM_CNTL 0x06c8 +#define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA3_DRAM_WR_CAM_CNTL 0x06c9 +#define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA3_DRAM_PAGE_BURST 0x06ca +#define regMMEA3_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_AGE 0x06cb +#define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_AGE 0x06cc +#define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_QUEUING 0x06cd +#define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_QUEUING 0x06ce +#define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_FIXED 0x06cf +#define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_FIXED 0x06d0 +#define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_URGENCY 0x06d1 +#define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_URGENCY 0x06d2 +#define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x06d3 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x06d4 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x06d5 +#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x06d6 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x06d7 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x06d8 +#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_GMI_RD_CLI2GRP_MAP0 0x06d9 +#define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_GMI_RD_CLI2GRP_MAP1 0x06da +#define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_GMI_WR_CLI2GRP_MAP0 0x06db +#define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_GMI_WR_CLI2GRP_MAP1 0x06dc +#define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_GMI_RD_GRP2VC_MAP 0x06dd +#define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA3_GMI_WR_GRP2VC_MAP 0x06de +#define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA3_GMI_RD_LAZY 0x06df +#define regMMEA3_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA3_GMI_WR_LAZY 0x06e0 +#define regMMEA3_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA3_GMI_RD_CAM_CNTL 0x06e1 +#define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA3_GMI_WR_CAM_CNTL 0x06e2 +#define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA3_GMI_PAGE_BURST 0x06e3 +#define regMMEA3_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_AGE 0x06e4 +#define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_AGE 0x06e5 +#define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_QUEUING 0x06e6 +#define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_QUEUING 0x06e7 +#define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_FIXED 0x06e8 +#define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_FIXED 0x06e9 +#define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_URGENCY 0x06ea +#define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_URGENCY 0x06eb +#define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x06ec +#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x06ed +#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_QUANT_PRI1 0x06ee +#define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_QUANT_PRI2 0x06ef +#define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_GMI_RD_PRI_QUANT_PRI3 0x06f0 +#define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI1 0x06f1 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI2 0x06f2 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI3 0x06f3 +#define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_ADDRNORM_BASE_ADDR0 0x06f4 +#define regMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA3_ADDRNORM_LIMIT_ADDR0 0x06f5 +#define regMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA3_ADDRNORM_BASE_ADDR1 0x06f6 +#define regMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORM_LIMIT_ADDR1 0x06f7 +#define regMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORM_OFFSET_ADDR1 0x06f8 +#define regMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORM_BASE_ADDR2 0x06f9 +#define regMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA3_ADDRNORM_LIMIT_ADDR2 0x06fa +#define regMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA3_ADDRNORM_BASE_ADDR3 0x06fb +#define regMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA3_ADDRNORM_LIMIT_ADDR3 0x06fc +#define regMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA3_ADDRNORM_OFFSET_ADDR3 0x06fd +#define regMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGABASE_ADDR0 0x06fe +#define regMMEA3_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0 0x06ff +#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGABASE_ADDR1 0x0700 +#define regMMEA3_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1 0x0701 +#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0703 +#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0704 +#define regMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0705 +#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0706 +#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA3_ADDRDEC_BANK_CFG 0x0707 +#define regMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA3_ADDRDEC_MISC_CFG 0x0708 +#define regMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0713 +#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x071e +#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x071f +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x0720 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x0721 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x0722 +#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x0723 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x0724 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x0725 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x0726 +#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x0727 +#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x0728 +#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x0729 +#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x072a +#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x072b +#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x072c +#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x072d +#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x072e +#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x072f +#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x0730 +#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x0731 +#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x0732 +#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x0733 +#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x0734 +#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_RM_SEL_CS01 0x0735 +#define regMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_RM_SEL_CS23 0x0736 +#define regMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x0737 +#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x0738 +#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x0739 +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x073a +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x073b +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x073c +#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x073d +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x073e +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x073f +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x0740 +#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x0741 +#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x0742 +#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x0743 +#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x0744 +#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x0745 +#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x0746 +#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x0747 +#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x0748 +#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x0749 +#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x074a +#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x074b +#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x074c +#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x074d +#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x074e +#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_RM_SEL_CS01 0x074f +#define regMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_RM_SEL_CS23 0x0750 +#define regMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x0751 +#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x0752 +#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x0753 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x0754 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x0755 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x0756 +#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x0757 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x0758 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x0759 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x075a +#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x075b +#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x075c +#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x075d +#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x075e +#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x075f +#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x0760 +#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x0761 +#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x0762 +#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x0763 +#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x0764 +#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x0765 +#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x0766 +#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x0767 +#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x0768 +#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_RM_SEL_CS01 0x0769 +#define regMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_RM_SEL_CS23 0x076a +#define regMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x076b +#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x076c +#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x076d +#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x076e +#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0 0x0791 +#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1 0x0792 +#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA3_ADDRNORMDRAM_MASKING 0x0793 +#define regMMEA3_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA3_ADDRNORMGMI_MASKING 0x0794 +#define regMMEA3_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA3_IO_RD_CLI2GRP_MAP0 0x0795 +#define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_IO_RD_CLI2GRP_MAP1 0x0796 +#define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_IO_WR_CLI2GRP_MAP0 0x0797 +#define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA3_IO_WR_CLI2GRP_MAP1 0x0798 +#define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA3_IO_RD_COMBINE_FLUSH 0x0799 +#define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA3_IO_WR_COMBINE_FLUSH 0x079a +#define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA3_IO_GROUP_BURST 0x079b +#define regMMEA3_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_AGE 0x079c +#define regMMEA3_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_AGE 0x079d +#define regMMEA3_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_QUEUING 0x079e +#define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_QUEUING 0x079f +#define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_FIXED 0x07a0 +#define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_FIXED 0x07a1 +#define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_URGENCY 0x07a2 +#define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_URGENCY 0x07a3 +#define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_URGENCY_MASKING 0x07a4 +#define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_URGENCY_MASKING 0x07a5 +#define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_QUANT_PRI1 0x07a6 +#define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_QUANT_PRI2 0x07a7 +#define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_IO_RD_PRI_QUANT_PRI3 0x07a8 +#define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_QUANT_PRI1 0x07a9 +#define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_QUANT_PRI2 0x07aa +#define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA3_IO_WR_PRI_QUANT_PRI3 0x07ab +#define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA3_SDP_ARB_DRAM 0x07ac +#define regMMEA3_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA3_SDP_ARB_GMI 0x07ad +#define regMMEA3_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA3_SDP_ARB_FINAL 0x07ae +#define regMMEA3_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA3_SDP_DRAM_PRIORITY 0x07af +#define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA3_SDP_GMI_PRIORITY 0x07b0 +#define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA3_SDP_IO_PRIORITY 0x07b1 +#define regMMEA3_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA3_SDP_CREDITS 0x07b2 +#define regMMEA3_SDP_CREDITS_BASE_IDX 0 +#define regMMEA3_SDP_TAG_RESERVE0 0x07b3 +#define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA3_SDP_TAG_RESERVE1 0x07b4 +#define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA3_SDP_VCC_RESERVE0 0x07b5 +#define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA3_SDP_VCC_RESERVE1 0x07b6 +#define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA3_SDP_VCD_RESERVE0 0x07b7 +#define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA3_SDP_VCD_RESERVE1 0x07b8 +#define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA3_SDP_REQ_CNTL 0x07b9 +#define regMMEA3_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA3_MISC 0x07ba +#define regMMEA3_MISC_BASE_IDX 0 +#define regMMEA3_LATENCY_SAMPLING 0x07bb +#define regMMEA3_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA3_PERFCOUNTER_LO 0x07bc +#define regMMEA3_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA3_PERFCOUNTER_HI 0x07bd +#define regMMEA3_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA3_PERFCOUNTER0_CFG 0x07be +#define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA3_PERFCOUNTER1_CFG 0x07bf +#define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0 +#define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA3_EDC_CNT 0x07c6 +#define regMMEA3_EDC_CNT_BASE_IDX 0 +#define regMMEA3_EDC_CNT2 0x07c7 +#define regMMEA3_EDC_CNT2_BASE_IDX 0 +#define regMMEA3_DSM_CNTL 0x07c8 +#define regMMEA3_DSM_CNTL_BASE_IDX 0 +#define regMMEA3_DSM_CNTLA 0x07c9 +#define regMMEA3_DSM_CNTLA_BASE_IDX 0 +#define regMMEA3_DSM_CNTLB 0x07ca +#define regMMEA3_DSM_CNTLB_BASE_IDX 0 +#define regMMEA3_DSM_CNTL2 0x07cb +#define regMMEA3_DSM_CNTL2_BASE_IDX 0 +#define regMMEA3_DSM_CNTL2A 0x07cc +#define regMMEA3_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA3_DSM_CNTL2B 0x07cd +#define regMMEA3_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA3_CGTT_CLK_CTRL 0x07cf +#define regMMEA3_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA3_EDC_MODE 0x07d0 +#define regMMEA3_EDC_MODE_BASE_IDX 0 +#define regMMEA3_ERR_STATUS 0x07d1 +#define regMMEA3_ERR_STATUS_BASE_IDX 0 +#define regMMEA3_MISC2 0x07d2 +#define regMMEA3_MISC2_BASE_IDX 0 +#define regMMEA3_ADDRDEC_SELECT 0x07d3 +#define regMMEA3_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA3_EDC_CNT3 0x07d4 +#define regMMEA3_EDC_CNT3_BASE_IDX 0 +#define regMMEA3_MISC_AON 0x07d5 +#define regMMEA3_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec4 +// base address: 0x6a000 +#define regMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0800 +#define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0801 +#define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0802 +#define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0803 +#define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_DRAM_RD_GRP2VC_MAP 0x0804 +#define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA4_DRAM_WR_GRP2VC_MAP 0x0805 +#define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA4_DRAM_RD_LAZY 0x0806 +#define regMMEA4_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA4_DRAM_WR_LAZY 0x0807 +#define regMMEA4_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA4_DRAM_RD_CAM_CNTL 0x0808 +#define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA4_DRAM_WR_CAM_CNTL 0x0809 +#define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA4_DRAM_PAGE_BURST 0x080a +#define regMMEA4_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_AGE 0x080b +#define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_AGE 0x080c +#define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_QUEUING 0x080d +#define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_QUEUING 0x080e +#define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_FIXED 0x080f +#define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_FIXED 0x0810 +#define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_URGENCY 0x0811 +#define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_URGENCY 0x0812 +#define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0813 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0814 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0815 +#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0816 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0817 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0818 +#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_GMI_RD_CLI2GRP_MAP0 0x0819 +#define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_GMI_RD_CLI2GRP_MAP1 0x081a +#define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_GMI_WR_CLI2GRP_MAP0 0x081b +#define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_GMI_WR_CLI2GRP_MAP1 0x081c +#define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_GMI_RD_GRP2VC_MAP 0x081d +#define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA4_GMI_WR_GRP2VC_MAP 0x081e +#define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA4_GMI_RD_LAZY 0x081f +#define regMMEA4_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA4_GMI_WR_LAZY 0x0820 +#define regMMEA4_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA4_GMI_RD_CAM_CNTL 0x0821 +#define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA4_GMI_WR_CAM_CNTL 0x0822 +#define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA4_GMI_PAGE_BURST 0x0823 +#define regMMEA4_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_AGE 0x0824 +#define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_AGE 0x0825 +#define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_QUEUING 0x0826 +#define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_QUEUING 0x0827 +#define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_FIXED 0x0828 +#define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_FIXED 0x0829 +#define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_URGENCY 0x082a +#define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_URGENCY 0x082b +#define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x082c +#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x082d +#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_QUANT_PRI1 0x082e +#define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_QUANT_PRI2 0x082f +#define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_GMI_RD_PRI_QUANT_PRI3 0x0830 +#define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI1 0x0831 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI2 0x0832 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI3 0x0833 +#define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_ADDRNORM_BASE_ADDR0 0x0834 +#define regMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA4_ADDRNORM_LIMIT_ADDR0 0x0835 +#define regMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA4_ADDRNORM_BASE_ADDR1 0x0836 +#define regMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORM_LIMIT_ADDR1 0x0837 +#define regMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORM_OFFSET_ADDR1 0x0838 +#define regMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORM_BASE_ADDR2 0x0839 +#define regMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA4_ADDRNORM_LIMIT_ADDR2 0x083a +#define regMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA4_ADDRNORM_BASE_ADDR3 0x083b +#define regMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA4_ADDRNORM_LIMIT_ADDR3 0x083c +#define regMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA4_ADDRNORM_OFFSET_ADDR3 0x083d +#define regMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGABASE_ADDR0 0x083e +#define regMMEA4_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0 0x083f +#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGABASE_ADDR1 0x0840 +#define regMMEA4_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1 0x0841 +#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x0843 +#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA4_ADDRNORMGMI_HOLE_CNTL 0x0844 +#define regMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0845 +#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0846 +#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA4_ADDRDEC_BANK_CFG 0x0847 +#define regMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA4_ADDRDEC_MISC_CFG 0x0848 +#define regMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x0853 +#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x085e +#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x085f +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x0860 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x0861 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x0862 +#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x0863 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x0864 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x0865 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x0866 +#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x0867 +#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x0868 +#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x0869 +#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x086a +#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x086b +#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x086c +#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x086d +#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x086e +#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x086f +#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x0870 +#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x0871 +#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x0872 +#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x0873 +#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x0874 +#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_RM_SEL_CS01 0x0875 +#define regMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_RM_SEL_CS23 0x0876 +#define regMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x0877 +#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x0878 +#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x0879 +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x087a +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x087b +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x087c +#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x087d +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x087e +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x087f +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0880 +#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0881 +#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0882 +#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0883 +#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0884 +#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0885 +#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0886 +#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0887 +#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0888 +#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0889 +#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x088a +#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x088b +#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x088c +#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x088d +#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x088e +#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_RM_SEL_CS01 0x088f +#define regMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_RM_SEL_CS23 0x0890 +#define regMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0891 +#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0892 +#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0893 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0894 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0895 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0896 +#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0897 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0898 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0899 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x089a +#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x089b +#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x089c +#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x089d +#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x089e +#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x089f +#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x08a0 +#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x08a1 +#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x08a2 +#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x08a3 +#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x08a4 +#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x08a5 +#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x08a6 +#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x08a7 +#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x08a8 +#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_RM_SEL_CS01 0x08a9 +#define regMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_RM_SEL_CS23 0x08aa +#define regMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x08ab +#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x08ac +#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x08ad +#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x08ae +#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0 0x08d1 +#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1 0x08d2 +#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA4_ADDRNORMDRAM_MASKING 0x08d3 +#define regMMEA4_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA4_ADDRNORMGMI_MASKING 0x08d4 +#define regMMEA4_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA4_IO_RD_CLI2GRP_MAP0 0x08d5 +#define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_IO_RD_CLI2GRP_MAP1 0x08d6 +#define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_IO_WR_CLI2GRP_MAP0 0x08d7 +#define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA4_IO_WR_CLI2GRP_MAP1 0x08d8 +#define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA4_IO_RD_COMBINE_FLUSH 0x08d9 +#define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA4_IO_WR_COMBINE_FLUSH 0x08da +#define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA4_IO_GROUP_BURST 0x08db +#define regMMEA4_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_AGE 0x08dc +#define regMMEA4_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_AGE 0x08dd +#define regMMEA4_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_QUEUING 0x08de +#define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_QUEUING 0x08df +#define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_FIXED 0x08e0 +#define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_FIXED 0x08e1 +#define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_URGENCY 0x08e2 +#define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_URGENCY 0x08e3 +#define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_URGENCY_MASKING 0x08e4 +#define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_URGENCY_MASKING 0x08e5 +#define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_QUANT_PRI1 0x08e6 +#define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_QUANT_PRI2 0x08e7 +#define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_IO_RD_PRI_QUANT_PRI3 0x08e8 +#define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_QUANT_PRI1 0x08e9 +#define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_QUANT_PRI2 0x08ea +#define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA4_IO_WR_PRI_QUANT_PRI3 0x08eb +#define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA4_SDP_ARB_DRAM 0x08ec +#define regMMEA4_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA4_SDP_ARB_GMI 0x08ed +#define regMMEA4_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA4_SDP_ARB_FINAL 0x08ee +#define regMMEA4_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA4_SDP_DRAM_PRIORITY 0x08ef +#define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA4_SDP_GMI_PRIORITY 0x08f0 +#define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA4_SDP_IO_PRIORITY 0x08f1 +#define regMMEA4_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA4_SDP_CREDITS 0x08f2 +#define regMMEA4_SDP_CREDITS_BASE_IDX 0 +#define regMMEA4_SDP_TAG_RESERVE0 0x08f3 +#define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA4_SDP_TAG_RESERVE1 0x08f4 +#define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA4_SDP_VCC_RESERVE0 0x08f5 +#define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA4_SDP_VCC_RESERVE1 0x08f6 +#define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA4_SDP_VCD_RESERVE0 0x08f7 +#define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA4_SDP_VCD_RESERVE1 0x08f8 +#define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA4_SDP_REQ_CNTL 0x08f9 +#define regMMEA4_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA4_MISC 0x08fa +#define regMMEA4_MISC_BASE_IDX 0 +#define regMMEA4_LATENCY_SAMPLING 0x08fb +#define regMMEA4_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA4_PERFCOUNTER_LO 0x08fc +#define regMMEA4_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA4_PERFCOUNTER_HI 0x08fd +#define regMMEA4_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA4_PERFCOUNTER0_CFG 0x08fe +#define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA4_PERFCOUNTER1_CFG 0x08ff +#define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900 +#define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA4_EDC_CNT 0x0906 +#define regMMEA4_EDC_CNT_BASE_IDX 0 +#define regMMEA4_EDC_CNT2 0x0907 +#define regMMEA4_EDC_CNT2_BASE_IDX 0 +#define regMMEA4_DSM_CNTL 0x0908 +#define regMMEA4_DSM_CNTL_BASE_IDX 0 +#define regMMEA4_DSM_CNTLA 0x0909 +#define regMMEA4_DSM_CNTLA_BASE_IDX 0 +#define regMMEA4_DSM_CNTLB 0x090a +#define regMMEA4_DSM_CNTLB_BASE_IDX 0 +#define regMMEA4_DSM_CNTL2 0x090b +#define regMMEA4_DSM_CNTL2_BASE_IDX 0 +#define regMMEA4_DSM_CNTL2A 0x090c +#define regMMEA4_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA4_DSM_CNTL2B 0x090d +#define regMMEA4_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA4_CGTT_CLK_CTRL 0x090f +#define regMMEA4_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA4_EDC_MODE 0x0910 +#define regMMEA4_EDC_MODE_BASE_IDX 0 +#define regMMEA4_ERR_STATUS 0x0911 +#define regMMEA4_ERR_STATUS_BASE_IDX 0 +#define regMMEA4_MISC2 0x0912 +#define regMMEA4_MISC2_BASE_IDX 0 +#define regMMEA4_ADDRDEC_SELECT 0x0913 +#define regMMEA4_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA4_EDC_CNT3 0x0914 +#define regMMEA4_EDC_CNT3_BASE_IDX 0 +#define regMMEA4_MISC_AON 0x0915 +#define regMMEA4_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec5 +// base address: 0x6a500 +#define regMMEA5_DRAM_RD_CLI2GRP_MAP0 0x0940 +#define regMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_DRAM_RD_CLI2GRP_MAP1 0x0941 +#define regMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_DRAM_WR_CLI2GRP_MAP0 0x0942 +#define regMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_DRAM_WR_CLI2GRP_MAP1 0x0943 +#define regMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_DRAM_RD_GRP2VC_MAP 0x0944 +#define regMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA5_DRAM_WR_GRP2VC_MAP 0x0945 +#define regMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA5_DRAM_RD_LAZY 0x0946 +#define regMMEA5_DRAM_RD_LAZY_BASE_IDX 0 +#define regMMEA5_DRAM_WR_LAZY 0x0947 +#define regMMEA5_DRAM_WR_LAZY_BASE_IDX 0 +#define regMMEA5_DRAM_RD_CAM_CNTL 0x0948 +#define regMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA5_DRAM_WR_CAM_CNTL 0x0949 +#define regMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA5_DRAM_PAGE_BURST 0x094a +#define regMMEA5_DRAM_PAGE_BURST_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_AGE 0x094b +#define regMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_AGE 0x094c +#define regMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_QUEUING 0x094d +#define regMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_QUEUING 0x094e +#define regMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_FIXED 0x094f +#define regMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_FIXED 0x0950 +#define regMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_URGENCY 0x0951 +#define regMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_URGENCY 0x0952 +#define regMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x0953 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x0954 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x0955 +#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x0956 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x0957 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x0958 +#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_GMI_RD_CLI2GRP_MAP0 0x0959 +#define regMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_GMI_RD_CLI2GRP_MAP1 0x095a +#define regMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_GMI_WR_CLI2GRP_MAP0 0x095b +#define regMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_GMI_WR_CLI2GRP_MAP1 0x095c +#define regMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_GMI_RD_GRP2VC_MAP 0x095d +#define regMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA5_GMI_WR_GRP2VC_MAP 0x095e +#define regMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 0 +#define regMMEA5_GMI_RD_LAZY 0x095f +#define regMMEA5_GMI_RD_LAZY_BASE_IDX 0 +#define regMMEA5_GMI_WR_LAZY 0x0960 +#define regMMEA5_GMI_WR_LAZY_BASE_IDX 0 +#define regMMEA5_GMI_RD_CAM_CNTL 0x0961 +#define regMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 0 +#define regMMEA5_GMI_WR_CAM_CNTL 0x0962 +#define regMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 0 +#define regMMEA5_GMI_PAGE_BURST 0x0963 +#define regMMEA5_GMI_PAGE_BURST_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_AGE 0x0964 +#define regMMEA5_GMI_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_AGE 0x0965 +#define regMMEA5_GMI_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_QUEUING 0x0966 +#define regMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_QUEUING 0x0967 +#define regMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_FIXED 0x0968 +#define regMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_FIXED 0x0969 +#define regMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_URGENCY 0x096a +#define regMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_URGENCY 0x096b +#define regMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x096c +#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x096d +#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_QUANT_PRI1 0x096e +#define regMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_QUANT_PRI2 0x096f +#define regMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_GMI_RD_PRI_QUANT_PRI3 0x0970 +#define regMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI1 0x0971 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI2 0x0972 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI3 0x0973 +#define regMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_ADDRNORM_BASE_ADDR0 0x0974 +#define regMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define regMMEA5_ADDRNORM_LIMIT_ADDR0 0x0975 +#define regMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define regMMEA5_ADDRNORM_BASE_ADDR1 0x0976 +#define regMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORM_LIMIT_ADDR1 0x0977 +#define regMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORM_OFFSET_ADDR1 0x0978 +#define regMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORM_BASE_ADDR2 0x0979 +#define regMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 0 +#define regMMEA5_ADDRNORM_LIMIT_ADDR2 0x097a +#define regMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 +#define regMMEA5_ADDRNORM_BASE_ADDR3 0x097b +#define regMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 0 +#define regMMEA5_ADDRNORM_LIMIT_ADDR3 0x097c +#define regMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 +#define regMMEA5_ADDRNORM_OFFSET_ADDR3 0x097d +#define regMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGABASE_ADDR0 0x097e +#define regMMEA5_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0 0x097f +#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGABASE_ADDR1 0x0980 +#define regMMEA5_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1 0x0981 +#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x0983 +#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 +#define regMMEA5_ADDRNORMGMI_HOLE_CNTL 0x0984 +#define regMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 +#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0985 +#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0986 +#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 +#define regMMEA5_ADDRDEC_BANK_CFG 0x0987 +#define regMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define regMMEA5_ADDRDEC_MISC_CFG 0x0988 +#define regMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x0993 +#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x099e +#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x099f +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x09a0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x09a1 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x09a2 +#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x09a3 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x09a4 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x09a5 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x09a6 +#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x09a7 +#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x09a8 +#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x09a9 +#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x09aa +#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x09ab +#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x09ac +#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x09ad +#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x09ae +#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x09af +#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x09b0 +#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x09b1 +#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x09b2 +#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x09b3 +#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x09b4 +#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_RM_SEL_CS01 0x09b5 +#define regMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_RM_SEL_CS23 0x09b6 +#define regMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x09b7 +#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x09b8 +#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x09b9 +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x09ba +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x09bb +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x09bc +#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x09bd +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x09be +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x09bf +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x09c0 +#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x09c1 +#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x09c2 +#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x09c3 +#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x09c4 +#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x09c5 +#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x09c6 +#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x09c7 +#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x09c8 +#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x09c9 +#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x09ca +#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x09cb +#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x09cc +#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x09cd +#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x09ce +#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_RM_SEL_CS01 0x09cf +#define regMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_RM_SEL_CS23 0x09d0 +#define regMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x09d1 +#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x09d2 +#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x09d3 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x09d4 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x09d5 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x09d6 +#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x09d7 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x09d8 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x09d9 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x09da +#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x09db +#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x09dc +#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x09dd +#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x09de +#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x09df +#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x09e0 +#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x09e1 +#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x09e2 +#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x09e3 +#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x09e4 +#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x09e5 +#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x09e6 +#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x09e7 +#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x09e8 +#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_RM_SEL_CS01 0x09e9 +#define regMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_RM_SEL_CS23 0x09ea +#define regMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x09eb +#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 +#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x09ec +#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 +#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x09ed +#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x09ee +#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0 0x0a11 +#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 +#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1 0x0a12 +#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 +#define regMMEA5_ADDRNORMDRAM_MASKING 0x0a13 +#define regMMEA5_ADDRNORMDRAM_MASKING_BASE_IDX 0 +#define regMMEA5_ADDRNORMGMI_MASKING 0x0a14 +#define regMMEA5_ADDRNORMGMI_MASKING_BASE_IDX 0 +#define regMMEA5_IO_RD_CLI2GRP_MAP0 0x0a15 +#define regMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_IO_RD_CLI2GRP_MAP1 0x0a16 +#define regMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_IO_WR_CLI2GRP_MAP0 0x0a17 +#define regMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regMMEA5_IO_WR_CLI2GRP_MAP1 0x0a18 +#define regMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regMMEA5_IO_RD_COMBINE_FLUSH 0x0a19 +#define regMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA5_IO_WR_COMBINE_FLUSH 0x0a1a +#define regMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regMMEA5_IO_GROUP_BURST 0x0a1b +#define regMMEA5_IO_GROUP_BURST_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_AGE 0x0a1c +#define regMMEA5_IO_RD_PRI_AGE_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_AGE 0x0a1d +#define regMMEA5_IO_WR_PRI_AGE_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_QUEUING 0x0a1e +#define regMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_QUEUING 0x0a1f +#define regMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_FIXED 0x0a20 +#define regMMEA5_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_FIXED 0x0a21 +#define regMMEA5_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_URGENCY 0x0a22 +#define regMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_URGENCY 0x0a23 +#define regMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_URGENCY_MASKING 0x0a24 +#define regMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_URGENCY_MASKING 0x0a25 +#define regMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_QUANT_PRI1 0x0a26 +#define regMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_QUANT_PRI2 0x0a27 +#define regMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_IO_RD_PRI_QUANT_PRI3 0x0a28 +#define regMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_QUANT_PRI1 0x0a29 +#define regMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_QUANT_PRI2 0x0a2a +#define regMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regMMEA5_IO_WR_PRI_QUANT_PRI3 0x0a2b +#define regMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regMMEA5_SDP_ARB_DRAM 0x0a2c +#define regMMEA5_SDP_ARB_DRAM_BASE_IDX 0 +#define regMMEA5_SDP_ARB_GMI 0x0a2d +#define regMMEA5_SDP_ARB_GMI_BASE_IDX 0 +#define regMMEA5_SDP_ARB_FINAL 0x0a2e +#define regMMEA5_SDP_ARB_FINAL_BASE_IDX 0 +#define regMMEA5_SDP_DRAM_PRIORITY 0x0a2f +#define regMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regMMEA5_SDP_GMI_PRIORITY 0x0a30 +#define regMMEA5_SDP_GMI_PRIORITY_BASE_IDX 0 +#define regMMEA5_SDP_IO_PRIORITY 0x0a31 +#define regMMEA5_SDP_IO_PRIORITY_BASE_IDX 0 +#define regMMEA5_SDP_CREDITS 0x0a32 +#define regMMEA5_SDP_CREDITS_BASE_IDX 0 +#define regMMEA5_SDP_TAG_RESERVE0 0x0a33 +#define regMMEA5_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regMMEA5_SDP_TAG_RESERVE1 0x0a34 +#define regMMEA5_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regMMEA5_SDP_VCC_RESERVE0 0x0a35 +#define regMMEA5_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regMMEA5_SDP_VCC_RESERVE1 0x0a36 +#define regMMEA5_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regMMEA5_SDP_VCD_RESERVE0 0x0a37 +#define regMMEA5_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regMMEA5_SDP_VCD_RESERVE1 0x0a38 +#define regMMEA5_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regMMEA5_SDP_REQ_CNTL 0x0a39 +#define regMMEA5_SDP_REQ_CNTL_BASE_IDX 0 +#define regMMEA5_MISC 0x0a3a +#define regMMEA5_MISC_BASE_IDX 0 +#define regMMEA5_LATENCY_SAMPLING 0x0a3b +#define regMMEA5_LATENCY_SAMPLING_BASE_IDX 0 +#define regMMEA5_PERFCOUNTER_LO 0x0a3c +#define regMMEA5_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMEA5_PERFCOUNTER_HI 0x0a3d +#define regMMEA5_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMEA5_PERFCOUNTER0_CFG 0x0a3e +#define regMMEA5_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMEA5_PERFCOUNTER1_CFG 0x0a3f +#define regMMEA5_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMEA5_PERFCOUNTER_RSLT_CNTL 0x0a40 +#define regMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA5_EDC_CNT 0x0a46 +#define regMMEA5_EDC_CNT_BASE_IDX 0 +#define regMMEA5_EDC_CNT2 0x0a47 +#define regMMEA5_EDC_CNT2_BASE_IDX 0 +#define regMMEA5_DSM_CNTL 0x0a48 +#define regMMEA5_DSM_CNTL_BASE_IDX 0 +#define regMMEA5_DSM_CNTLA 0x0a49 +#define regMMEA5_DSM_CNTLA_BASE_IDX 0 +#define regMMEA5_DSM_CNTLB 0x0a4a +#define regMMEA5_DSM_CNTLB_BASE_IDX 0 +#define regMMEA5_DSM_CNTL2 0x0a4b +#define regMMEA5_DSM_CNTL2_BASE_IDX 0 +#define regMMEA5_DSM_CNTL2A 0x0a4c +#define regMMEA5_DSM_CNTL2A_BASE_IDX 0 +#define regMMEA5_DSM_CNTL2B 0x0a4d +#define regMMEA5_DSM_CNTL2B_BASE_IDX 0 +#define regMMEA5_CGTT_CLK_CTRL 0x0a4f +#define regMMEA5_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMEA5_EDC_MODE 0x0a50 +#define regMMEA5_EDC_MODE_BASE_IDX 0 +#define regMMEA5_ERR_STATUS 0x0a51 +#define regMMEA5_ERR_STATUS_BASE_IDX 0 +#define regMMEA5_MISC2 0x0a52 +#define regMMEA5_MISC2_BASE_IDX 0 +#define regMMEA5_ADDRDEC_SELECT 0x0a53 +#define regMMEA5_ADDRDEC_SELECT_BASE_IDX 0 +#define regMMEA5_EDC_CNT3 0x0a54 +#define regMMEA5_EDC_CNT3_BASE_IDX 0 +#define regMMEA5_MISC_AON 0x0a55 +#define regMMEA5_MISC_AON_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1dec +// base address: 0x6ac00 +#define regMC_VM_MX_L1_TLB0_STATUS 0x0b08 +#define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB1_STATUS 0x0b09 +#define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB2_STATUS 0x0b0a +#define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB3_STATUS 0x0b0b +#define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB4_STATUS 0x0b0c +#define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB5_STATUS 0x0b0d +#define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB6_STATUS 0x0b0e +#define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB7_STATUS 0x0b0f +#define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1pldec +// base address: 0x6ac80 +#define regMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0b20 +#define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0b21 +#define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0b22 +#define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0b23 +#define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0b24 +#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1prdec +// base address: 0x6acc0 +#define regMC_VM_MX_L1_PERFCOUNTER_LO 0x0b30 +#define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 +#define regMC_VM_MX_L1_PERFCOUNTER_HI 0x0b31 +#define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_pctldec0 +// base address: 0x6aa00 +#define regPCTL0_CTRL 0x0a80 +#define regPCTL0_CTRL_BASE_IDX 0 +#define regPCTL0_MMHUB_DEEPSLEEP_IB 0x0a81 +#define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x0a82 +#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 +#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0a83 +#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 +#define regPCTL0_PG_IGNORE_DEEPSLEEP 0x0a84 +#define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 +#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x0a85 +#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL0_SLICE0_CFG_DAGB_BUSY 0x0a86 +#define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE0_CFG_DS_ALLOW 0x0a87 +#define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x0a88 +#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_SLICE1_CFG_DAGB_BUSY 0x0a89 +#define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE1_CFG_DS_ALLOW 0x0a8a +#define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x0a8b +#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_SLICE2_CFG_DAGB_BUSY 0x0a8c +#define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE2_CFG_DS_ALLOW 0x0a8d +#define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x0a8e +#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_SLICE3_CFG_DAGB_BUSY 0x0a8f +#define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE3_CFG_DS_ALLOW 0x0a90 +#define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x0a91 +#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_SLICE4_CFG_DAGB_BUSY 0x0a92 +#define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE4_CFG_DS_ALLOW 0x0a93 +#define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x0a94 +#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_SLICE5_CFG_DAGB_BUSY 0x0a95 +#define regPCTL0_SLICE5_CFG_DAGB_BUSY_BASE_IDX 0 +#define regPCTL0_SLICE5_CFG_DS_ALLOW 0x0a96 +#define regPCTL0_SLICE5_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB 0x0a97 +#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL0_UTCL2_MISC 0x0a98 +#define regPCTL0_UTCL2_MISC_BASE_IDX 0 +#define regPCTL0_SLICE0_MISC 0x0a99 +#define regPCTL0_SLICE0_MISC_BASE_IDX 0 +#define regPCTL0_SLICE1_MISC 0x0a9a +#define regPCTL0_SLICE1_MISC_BASE_IDX 0 +#define regPCTL0_SLICE2_MISC 0x0a9b +#define regPCTL0_SLICE2_MISC_BASE_IDX 0 +#define regPCTL0_SLICE3_MISC 0x0a9c +#define regPCTL0_SLICE3_MISC_BASE_IDX 0 +#define regPCTL0_SLICE4_MISC 0x0a9d +#define regPCTL0_SLICE4_MISC_BASE_IDX 0 +#define regPCTL0_SLICE5_MISC 0x0a9e +#define regPCTL0_SLICE5_MISC_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2dec +// base address: 0x6ad00 +#define regATC_L2_CNTL 0x0b40 +#define regATC_L2_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL2 0x0b41 +#define regATC_L2_CNTL2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA0 0x0b44 +#define regATC_L2_CACHE_DATA0_BASE_IDX 0 +#define regATC_L2_CACHE_DATA1 0x0b45 +#define regATC_L2_CACHE_DATA1_BASE_IDX 0 +#define regATC_L2_CACHE_DATA2 0x0b46 +#define regATC_L2_CACHE_DATA2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA3 0x0b47 +#define regATC_L2_CACHE_DATA3_BASE_IDX 0 +#define regATC_L2_CNTL3 0x0b48 +#define regATC_L2_CNTL3_BASE_IDX 0 +#define regATC_L2_STATUS 0x0b49 +#define regATC_L2_STATUS_BASE_IDX 0 +#define regATC_L2_STATUS2 0x0b4a +#define regATC_L2_STATUS2_BASE_IDX 0 +#define regATC_L2_MISC_CG 0x0b4b +#define regATC_L2_MISC_CG_BASE_IDX 0 +#define regATC_L2_MEM_POWER_LS 0x0b4c +#define regATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define regATC_L2_CGTT_CLK_CTRL 0x0b4d +#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_INDEX 0x0b4e +#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_INDEX 0x0b4f +#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_INDEX 0x0b50 +#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_CNTL 0x0b51 +#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_CNTL 0x0b52 +#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_CNTL 0x0b53 +#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL4 0x0b54 +#define regATC_L2_CNTL4_BASE_IDX 0 +#define regATC_L2_MM_GROUP_RT_CLASSES 0x0b55 +#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +// base address: 0x6b4d0 +#define regATC_L2_PERFCOUNTER0_CFG 0x0d34 +#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regATC_L2_PERFCOUNTER1_CFG 0x0d35 +#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x0d36 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +// base address: 0x6b4c0 +#define regATC_L2_PERFCOUNTER_LO 0x0d30 +#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define regATC_L2_PERFCOUNTER_HI 0x0d31 +#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_l2tlbdec +// base address: 0x6b580 +#define regL2TLB_TLB0_STATUS 0x0d61 +#define regL2TLB_TLB0_STATUS_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0d63 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0d64 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0d65 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0d66 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_l2tlbpldec +// base address: 0x6b5a0 +#define regL2TLB_PERFCOUNTER0_CFG 0x0d68 +#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regL2TLB_PERFCOUNTER1_CFG 0x0d69 +#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regL2TLB_PERFCOUNTER2_CFG 0x0d6a +#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regL2TLB_PERFCOUNTER3_CFG 0x0d6b +#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x0d6c +#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_l2tlbprdec +// base address: 0x6b5c0 +#define regL2TLB_PERFCOUNTER_LO 0x0d70 +#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 0 +#define regL2TLB_PERFCOUNTER_HI 0x0d71 +#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2pfdec +// base address: 0x6ae00 +#define regVM_L2_CNTL 0x0b80 +#define regVM_L2_CNTL_BASE_IDX 0 +#define regVM_L2_CNTL2 0x0b81 +#define regVM_L2_CNTL2_BASE_IDX 0 +#define regVM_L2_CNTL3 0x0b82 +#define regVM_L2_CNTL3_BASE_IDX 0 +#define regVM_L2_STATUS 0x0b83 +#define regVM_L2_STATUS_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0b84 +#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0b85 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0b86 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL 0x0b87 +#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0b88 +#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0b89 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0b8a +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_STATUS 0x0b8b +#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0b8c +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0b8d +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0b8e +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0b8f +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0b91 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0b92 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0b93 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0b94 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0b95 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0b96 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regVM_L2_CNTL4 0x0b97 +#define regVM_L2_CNTL4_BASE_IDX 0 +#define regVM_L2_MM_GROUP_RT_CLASSES 0x0b98 +#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0b99 +#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x0b9a +#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regVM_L2_CACHE_PARITY_CNTL 0x0b9b +#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regVM_L2_CGTT_CLK_CTRL 0x0b9e +#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regVM_L2_CGTT_BUSY_CTRL 0x0b9f +#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regVML2_MEM_ECC_INDEX 0x0ba1 +#define regVML2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_INDEX 0x0ba2 +#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 +#define regUTCL2_MEM_ECC_INDEX 0x0ba3 +#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_MEM_ECC_CNTL 0x0ba4 +#define regVML2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_CNTL 0x0ba5 +#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 +#define regUTCL2_MEM_ECC_CNTL 0x0ba6 +#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_MEM_ECC_STATUS 0x0ba7 +#define regVML2_MEM_ECC_STATUS_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_STATUS 0x0ba8 +#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_MEM_ECC_STATUS 0x0ba9 +#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_EDC_MODE 0x0baa +#define regUTCL2_EDC_MODE_BASE_IDX 0 +#define regUTCL2_EDC_CONFIG 0x0bab +#define regUTCL2_EDC_CONFIG_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2pldec +// base address: 0x6b500 +#define regMC_VM_L2_PERFCOUNTER0_CFG 0x0d40 +#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER1_CFG 0x0d41 +#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER2_CFG 0x0d42 +#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER3_CFG 0x0d43 +#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER4_CFG 0x0d44 +#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER5_CFG 0x0d45 +#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER6_CFG 0x0d46 +#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER7_CFG 0x0d47 +#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0d48 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2prdec +// base address: 0x6b540 +#define regMC_VM_L2_PERFCOUNTER_LO 0x0d50 +#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMC_VM_L2_PERFCOUNTER_HI 0x0d51 +#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2vcdec +// base address: 0x6af00 +#define regVM_CONTEXT0_CNTL 0x0bc0 +#define regVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regVM_CONTEXT1_CNTL 0x0bc1 +#define regVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regVM_CONTEXT2_CNTL 0x0bc2 +#define regVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regVM_CONTEXT3_CNTL 0x0bc3 +#define regVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regVM_CONTEXT4_CNTL 0x0bc4 +#define regVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regVM_CONTEXT5_CNTL 0x0bc5 +#define regVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regVM_CONTEXT6_CNTL 0x0bc6 +#define regVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regVM_CONTEXT7_CNTL 0x0bc7 +#define regVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regVM_CONTEXT8_CNTL 0x0bc8 +#define regVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regVM_CONTEXT9_CNTL 0x0bc9 +#define regVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regVM_CONTEXT10_CNTL 0x0bca +#define regVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regVM_CONTEXT11_CNTL 0x0bcb +#define regVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regVM_CONTEXT12_CNTL 0x0bcc +#define regVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regVM_CONTEXT13_CNTL 0x0bcd +#define regVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regVM_CONTEXT14_CNTL 0x0bce +#define regVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regVM_CONTEXT15_CNTL 0x0bcf +#define regVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regVM_CONTEXTS_DISABLE 0x0bd0 +#define regVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_SEM 0x0bd1 +#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_SEM 0x0bd2 +#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_SEM 0x0bd3 +#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_SEM 0x0bd4 +#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_SEM 0x0bd5 +#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_SEM 0x0bd6 +#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_SEM 0x0bd7 +#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_SEM 0x0bd8 +#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_SEM 0x0bd9 +#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_SEM 0x0bda +#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_SEM 0x0bdb +#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_SEM 0x0bdc +#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_SEM 0x0bdd +#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_SEM 0x0bde +#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_SEM 0x0bdf +#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_SEM 0x0be0 +#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_SEM 0x0be1 +#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_SEM 0x0be2 +#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_REQ 0x0be3 +#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_REQ 0x0be4 +#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_REQ 0x0be5 +#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_REQ 0x0be6 +#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_REQ 0x0be7 +#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_REQ 0x0be8 +#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_REQ 0x0be9 +#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_REQ 0x0bea +#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_REQ 0x0beb +#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_REQ 0x0bec +#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_REQ 0x0bed +#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_REQ 0x0bee +#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_REQ 0x0bef +#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_REQ 0x0bf0 +#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_REQ 0x0bf1 +#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_REQ 0x0bf2 +#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_REQ 0x0bf3 +#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_REQ 0x0bf4 +#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ACK 0x0bf5 +#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ACK 0x0bf6 +#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ACK 0x0bf7 +#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ACK 0x0bf8 +#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ACK 0x0bf9 +#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ACK 0x0bfa +#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ACK 0x0bfb +#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ACK 0x0bfc +#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ACK 0x0bfd +#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ACK 0x0bfe +#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ACK 0x0bff +#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ACK 0x0c00 +#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ACK 0x0c01 +#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ACK 0x0c02 +#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ACK 0x0c03 +#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ACK 0x0c04 +#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ACK 0x0c05 +#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ACK 0x0c06 +#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0c07 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0c08 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0c09 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0c0a +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0c0b +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0c0c +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0c0d +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0c0e +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0c0f +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0c10 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0c11 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0c12 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0c13 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0c14 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0c15 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0c16 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0c17 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0c18 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0c19 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0c1a +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0c1b +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0c1c +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0c1d +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0c1e +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0c1f +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0c20 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0c21 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0c22 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0c23 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0c24 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0c25 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0c26 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0c27 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0c28 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0c29 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0c2a +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0c2b +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0c2c +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0c2d +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0c2e +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0c2f +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0c30 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0c31 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0c32 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0c33 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0c34 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0c35 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0c36 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0c37 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0c38 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0c39 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0c3a +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0c3b +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0c3c +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0c3d +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0c3e +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0c3f +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0c40 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0c41 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0c42 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0c43 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0c44 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0c45 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0c46 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0c47 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0c48 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0c49 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0c4a +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0c4b +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0c4c +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0c4d +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0c4e +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0c4f +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0c50 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0c51 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0c52 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0c53 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0c54 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0c55 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0c56 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0c57 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0c58 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0c59 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0c5a +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0c5b +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0c5c +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0c5d +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0c5e +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0c5f +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0c60 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0c61 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0c62 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0c63 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0c64 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0c65 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0c66 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0c67 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0c68 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0c69 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0c6a +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0c6b +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0c6c +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0c6d +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0c6e +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0c6f +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0c70 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0c71 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0c72 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0c73 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0c74 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0c75 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0c76 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0c77 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0c78 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0c79 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0c7a +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0c7b +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0c7c +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0c7d +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0c7e +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0c7f +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0c80 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0c81 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0c82 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0c83 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0c84 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0c85 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0c86 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0c87 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0c88 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0c89 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0c8a +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +// base address: 0x6b380 +#define regMC_VM_FB_SIZE_OFFSET_VF0 0x0ce0 +#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF1 0x0ce1 +#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF2 0x0ce2 +#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF3 0x0ce3 +#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF4 0x0ce4 +#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF5 0x0ce5 +#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF6 0x0ce6 +#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF7 0x0ce7 +#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF8 0x0ce8 +#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF9 0x0ce9 +#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF10 0x0cea +#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF11 0x0ceb +#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF12 0x0cec +#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF13 0x0ced +#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF14 0x0cee +#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 +#define regMC_VM_FB_SIZE_OFFSET_VF15 0x0cef +#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 +#define regMC_VM_MARC_BASE_LO_0 0x0cf1 +#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 0 +#define regMC_VM_MARC_BASE_LO_1 0x0cf2 +#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 0 +#define regMC_VM_MARC_BASE_LO_2 0x0cf3 +#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 0 +#define regMC_VM_MARC_BASE_LO_3 0x0cf4 +#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 0 +#define regMC_VM_MARC_BASE_HI_0 0x0cf5 +#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 0 +#define regMC_VM_MARC_BASE_HI_1 0x0cf6 +#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 0 +#define regMC_VM_MARC_BASE_HI_2 0x0cf7 +#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 0 +#define regMC_VM_MARC_BASE_HI_3 0x0cf8 +#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_LO_0 0x0cf9 +#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_LO_1 0x0cfa +#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_LO_2 0x0cfb +#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_LO_3 0x0cfc +#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_HI_0 0x0cfd +#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_HI_1 0x0cfe +#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_HI_2 0x0cff +#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 +#define regMC_VM_MARC_RELOC_HI_3 0x0d00 +#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 +#define regMC_VM_MARC_LEN_LO_0 0x0d01 +#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 0 +#define regMC_VM_MARC_LEN_LO_1 0x0d02 +#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 0 +#define regMC_VM_MARC_LEN_LO_2 0x0d03 +#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 0 +#define regMC_VM_MARC_LEN_LO_3 0x0d04 +#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 0 +#define regMC_VM_MARC_LEN_HI_0 0x0d05 +#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 0 +#define regMC_VM_MARC_LEN_HI_1 0x0d06 +#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 0 +#define regMC_VM_MARC_LEN_HI_2 0x0d07 +#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 0 +#define regMC_VM_MARC_LEN_HI_3 0x0d08 +#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL 0x0d0b +#define regVM_PCIE_ATS_CNTL_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_0 0x0d0c +#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_1 0x0d0d +#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_2 0x0d0e +#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_3 0x0d0f +#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_4 0x0d10 +#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_5 0x0d11 +#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_6 0x0d12 +#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_7 0x0d13 +#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_8 0x0d14 +#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_9 0x0d15 +#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_10 0x0d16 +#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_11 0x0d17 +#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_12 0x0d18 +#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_13 0x0d19 +#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_14 0x0d1a +#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 +#define regVM_PCIE_ATS_CNTL_VF_15 0x0d1b +#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 +#define regMC_SHARED_ACTIVE_FCN_ID 0x0d1c +#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define regMC_VM_XGMI_GPUIOV_ENABLE 0x0d1d +#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +// base address: 0x6b290 +#define regMC_VM_FB_OFFSET 0x0cab +#define regMC_VM_FB_OFFSET_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0cac +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0cad +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regMC_VM_STEERING 0x0cae +#define regMC_VM_STEERING_BASE_IDX 0 +#define regMC_SHARED_VIRT_RESET_REQ 0x0caf +#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define regMC_MEM_POWER_LS 0x0cb0 +#define regMC_MEM_POWER_LS_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0cb1 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0cb2 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_APT_CNTL 0x0cb3 +#define regMC_VM_APT_CNTL_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0cb4 +#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0cb5 +#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0cb6 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regUTCL2_CGTT_CLK_CTRL 0x0cb7 +#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_CNTL 0x0cb8 +#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_SIZE 0x0cb9 +#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_CNTL 0x0cba +#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 +#define regMC_VM_HOST_MAPPING 0x0cbb +#define regMC_VM_HOST_MAPPING_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +// base address: 0x6b300 +#define regMC_VM_FB_LOCATION_BASE 0x0cc0 +#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regMC_VM_FB_LOCATION_TOP 0x0cc1 +#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regMC_VM_AGP_TOP 0x0cc2 +#define regMC_VM_AGP_TOP_BASE_IDX 0 +#define regMC_VM_AGP_BOT 0x0cc3 +#define regMC_VM_AGP_BOT_BASE_IDX 0 +#define regMC_VM_AGP_BASE 0x0cc4 +#define regMC_VM_AGP_BASE_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0cc5 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0cc6 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB_CNTL 0x0cc7 +#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..c1185f36c0808282e365e5c355c0b55cdfe9f768 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h @@ -0,0 +1,32178 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_1_7_SH_MASK_HEADER +#define _mmhub_1_7_SH_MASK_HEADER + + +// addressBlock: mmhub_dagb_dagbdec0 +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB0_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC6_CNTL +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC7_CNTL +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RD_RDRET_CREDIT_CNTL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB0_RD_RDRET_CREDIT_CNTL2 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB0_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC6_CNTL +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC7_CNTL +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB0_WR_OSD_CREDIT_CNTL1 +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB0_WR_OSD_CREDIT_CNTL2 +#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB0_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB0_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB0_FATAL_ERROR_CNTL +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB0_FATAL_ERROR_CLEAR +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB0_FATAL_ERROR_STATUS0 +#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB0_FATAL_ERROR_STATUS1 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB0_FATAL_ERROR_STATUS2 +#define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB0_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB0_FATAL_ERROR_STATUS3 +#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_L1TLB_REG_RW +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec1 +//DAGB1_RDCLI0 +#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI1 +#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI2 +#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI3 +#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI4 +#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI5 +#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI6 +#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI7 +#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI8 +#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI9 +#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI10 +#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI11 +#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI12 +#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI13 +#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI14 +#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI15 +#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_RD_CNTL +#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB1_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB1_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB1_RD_GMI_CNTL +#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB1_RD_ADDR_DAGB +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB1_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB1_RD_CGTT_CLK_CTRL +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_VC0_CNTL +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC1_CNTL +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC2_CNTL +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC3_CNTL +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC4_CNTL +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC5_CNTL +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC6_CNTL +#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC7_CNTL +#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_CNTL_MISC +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB1_RD_TLB_CREDIT +#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_RD_RDRET_CREDIT_CNTL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB1_RD_RDRET_CREDIT_CNTL2 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB1_RDCLI_ASK_PENDING +#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GO_PENDING +#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GBLSEND_PENDING +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_TLB_PENDING +#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OARB_PENDING +#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OSD_PENDING +#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI0 +#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI1 +#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI2 +#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI3 +#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI4 +#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI5 +#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI6 +#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI7 +#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI8 +#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI9 +#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI10 +#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI11 +#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI12 +#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI13 +#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI14 +#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI15 +#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_WR_CNTL +#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB1_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB1_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB1_WR_GMI_CNTL +#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB1_WR_ADDR_DAGB +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB1_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB1_WR_CGTT_CLK_CTRL +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB1_WR_DATA_DAGB_MAX_BURST0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_MAX_BURST1 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_VC0_CNTL +#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC1_CNTL +#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC2_CNTL +#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC3_CNTL +#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC4_CNTL +#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC5_CNTL +#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC6_CNTL +#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC7_CNTL +#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_CNTL_MISC +#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB1_WR_TLB_CREDIT +#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_WR_DATA_CREDIT +#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB1_WR_MISC_CREDIT +#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB1_WR_OSD_CREDIT_CNTL1 +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB1_WR_OSD_CREDIT_CNTL2 +#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_ASK_PENDING +#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_GO_PENDING +#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_GBLSEND_PENDING +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_TLB_PENDING +#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_OARB_PENDING +#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_OSD_PENDING +#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_DBUS_ASK_PENDING +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_DBUS_GO_PENDING +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_DAGB_DLY +#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB1_CNTL_MISC +#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB1_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB1_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB1_FATAL_ERROR_CNTL +#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB1_FATAL_ERROR_CLEAR +#define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB1_FATAL_ERROR_STATUS0 +#define DAGB1_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB1_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB1_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB1_FATAL_ERROR_STATUS1 +#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB1_FATAL_ERROR_STATUS2 +#define DAGB1_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB1_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB1_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB1_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB1_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB1_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB1_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB1_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB1_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB1_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB1_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB1_FATAL_ERROR_STATUS3 +#define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB1_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB1_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB1_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB1_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB1_FIFO_EMPTY +#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB1_FIFO_FULL +#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB1_WR_CREDITS_FULL +#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB1_RD_CREDITS_FULL +#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB1_PERFCOUNTER_LO +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB1_PERFCOUNTER_HI +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB1_PERFCOUNTER0_CFG +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER1_CFG +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER2_CFG +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER_RSLT_CNTL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB1_L1TLB_REG_RW +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB1_RESERVE1 +#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE2 +#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE3 +#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE4 +#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec2 +//DAGB2_RDCLI0 +#define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI1 +#define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI2 +#define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI3 +#define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI4 +#define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI5 +#define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI6 +#define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI7 +#define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI8 +#define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI9 +#define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI10 +#define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI11 +#define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI12 +#define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI13 +#define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI14 +#define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI15 +#define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB2_RD_CNTL +#define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB2_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB2_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB2_RD_GMI_CNTL +#define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB2_RD_ADDR_DAGB +#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB2_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB2_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB2_RD_CGTT_CLK_CTRL +#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_RD_VC0_CNTL +#define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC1_CNTL +#define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC2_CNTL +#define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC3_CNTL +#define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC4_CNTL +#define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC5_CNTL +#define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC6_CNTL +#define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC7_CNTL +#define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_CNTL_MISC +#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB2_RD_TLB_CREDIT +#define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB2_RD_RDRET_CREDIT_CNTL +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB2_RD_RDRET_CREDIT_CNTL2 +#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB2_RDCLI_ASK_PENDING +#define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_GO_PENDING +#define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_GBLSEND_PENDING +#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_TLB_PENDING +#define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_OARB_PENDING +#define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_OSD_PENDING +#define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI0 +#define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI1 +#define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI2 +#define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI3 +#define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI4 +#define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI5 +#define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI6 +#define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI7 +#define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI8 +#define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI9 +#define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI10 +#define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI11 +#define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI12 +#define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI13 +#define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI14 +#define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI15 +#define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB2_WR_CNTL +#define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB2_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB2_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB2_WR_GMI_CNTL +#define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB2_WR_ADDR_DAGB +#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB2_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB2_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB2_WR_CGTT_CLK_CTRL +#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB +#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB2_WR_DATA_DAGB_MAX_BURST0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_MAX_BURST1 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_VC0_CNTL +#define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC1_CNTL +#define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC2_CNTL +#define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC3_CNTL +#define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC4_CNTL +#define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC5_CNTL +#define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC6_CNTL +#define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC7_CNTL +#define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_CNTL_MISC +#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB2_WR_TLB_CREDIT +#define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB2_WR_DATA_CREDIT +#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB2_WR_MISC_CREDIT +#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB2_WR_OSD_CREDIT_CNTL1 +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB2_WR_OSD_CREDIT_CNTL2 +#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_ASK_PENDING +#define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_GO_PENDING +#define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_GBLSEND_PENDING +#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_TLB_PENDING +#define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_OARB_PENDING +#define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_OSD_PENDING +#define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_DBUS_ASK_PENDING +#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_DBUS_GO_PENDING +#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_DAGB_DLY +#define DAGB2_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB2_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB2_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB2_CNTL_MISC +#define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB2_CNTL_MISC2 +#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB2_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB2_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB2_FATAL_ERROR_CNTL +#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB2_FATAL_ERROR_CLEAR +#define DAGB2_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB2_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB2_FATAL_ERROR_STATUS0 +#define DAGB2_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB2_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB2_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB2_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB2_FATAL_ERROR_STATUS1 +#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB2_FATAL_ERROR_STATUS2 +#define DAGB2_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB2_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB2_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB2_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB2_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB2_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB2_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB2_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB2_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB2_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB2_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB2_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB2_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB2_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB2_FATAL_ERROR_STATUS3 +#define DAGB2_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB2_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB2_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB2_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB2_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB2_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB2_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB2_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB2_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB2_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB2_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB2_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB2_FIFO_EMPTY +#define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB2_FIFO_FULL +#define DAGB2_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB2_WR_CREDITS_FULL +#define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB2_RD_CREDITS_FULL +#define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB2_PERFCOUNTER_LO +#define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB2_PERFCOUNTER_HI +#define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB2_PERFCOUNTER0_CFG +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER1_CFG +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER2_CFG +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER_RSLT_CNTL +#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB2_L1TLB_REG_RW +#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB2_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB2_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB2_RESERVE1 +#define DAGB2_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE2 +#define DAGB2_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE3 +#define DAGB2_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE4 +#define DAGB2_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec3 +//DAGB3_RDCLI0 +#define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI1 +#define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI2 +#define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI3 +#define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI4 +#define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI5 +#define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI6 +#define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI7 +#define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI8 +#define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI9 +#define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI10 +#define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI11 +#define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI12 +#define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI13 +#define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI14 +#define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI15 +#define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB3_RD_CNTL +#define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB3_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB3_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB3_RD_GMI_CNTL +#define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB3_RD_ADDR_DAGB +#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB3_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB3_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB3_RD_CGTT_CLK_CTRL +#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_RD_VC0_CNTL +#define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC1_CNTL +#define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC2_CNTL +#define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC3_CNTL +#define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC4_CNTL +#define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC5_CNTL +#define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC6_CNTL +#define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC7_CNTL +#define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_CNTL_MISC +#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB3_RD_TLB_CREDIT +#define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB3_RD_RDRET_CREDIT_CNTL +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB3_RD_RDRET_CREDIT_CNTL2 +#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB3_RDCLI_ASK_PENDING +#define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_GO_PENDING +#define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_GBLSEND_PENDING +#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_TLB_PENDING +#define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_OARB_PENDING +#define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_OSD_PENDING +#define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI0 +#define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI1 +#define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI2 +#define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI3 +#define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI4 +#define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI5 +#define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI6 +#define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI7 +#define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI8 +#define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI9 +#define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI10 +#define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI11 +#define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI12 +#define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI13 +#define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI14 +#define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI15 +#define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB3_WR_CNTL +#define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB3_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB3_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB3_WR_GMI_CNTL +#define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB3_WR_ADDR_DAGB +#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB3_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB3_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB3_WR_CGTT_CLK_CTRL +#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB +#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB3_WR_DATA_DAGB_MAX_BURST0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_MAX_BURST1 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_VC0_CNTL +#define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC1_CNTL +#define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC2_CNTL +#define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC3_CNTL +#define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC4_CNTL +#define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC5_CNTL +#define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC6_CNTL +#define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC7_CNTL +#define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_CNTL_MISC +#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB3_WR_TLB_CREDIT +#define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB3_WR_DATA_CREDIT +#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB3_WR_MISC_CREDIT +#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB3_WR_OSD_CREDIT_CNTL1 +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB3_WR_OSD_CREDIT_CNTL2 +#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_ASK_PENDING +#define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_GO_PENDING +#define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_GBLSEND_PENDING +#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_TLB_PENDING +#define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_OARB_PENDING +#define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_OSD_PENDING +#define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_DBUS_ASK_PENDING +#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_DBUS_GO_PENDING +#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_DAGB_DLY +#define DAGB3_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB3_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB3_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB3_CNTL_MISC +#define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB3_CNTL_MISC2 +#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB3_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB3_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB3_FATAL_ERROR_CNTL +#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB3_FATAL_ERROR_CLEAR +#define DAGB3_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB3_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB3_FATAL_ERROR_STATUS0 +#define DAGB3_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB3_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB3_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB3_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB3_FATAL_ERROR_STATUS1 +#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB3_FATAL_ERROR_STATUS2 +#define DAGB3_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB3_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB3_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB3_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB3_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB3_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB3_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB3_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB3_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB3_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB3_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB3_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB3_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB3_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB3_FATAL_ERROR_STATUS3 +#define DAGB3_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB3_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB3_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB3_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB3_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB3_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB3_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB3_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB3_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB3_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB3_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB3_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB3_FIFO_EMPTY +#define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB3_FIFO_FULL +#define DAGB3_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB3_WR_CREDITS_FULL +#define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB3_RD_CREDITS_FULL +#define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB3_PERFCOUNTER_LO +#define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB3_PERFCOUNTER_HI +#define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB3_PERFCOUNTER0_CFG +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER1_CFG +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER2_CFG +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER_RSLT_CNTL +#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB3_L1TLB_REG_RW +#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB3_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB3_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB3_RESERVE1 +#define DAGB3_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE2 +#define DAGB3_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE3 +#define DAGB3_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE4 +#define DAGB3_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec4 +//DAGB4_RDCLI0 +#define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI1 +#define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI2 +#define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI3 +#define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI4 +#define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI5 +#define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI6 +#define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI7 +#define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI8 +#define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI9 +#define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI10 +#define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI11 +#define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI12 +#define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI13 +#define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI14 +#define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI15 +#define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB4_RD_CNTL +#define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB4_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB4_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB4_RD_GMI_CNTL +#define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB4_RD_ADDR_DAGB +#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB4_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB4_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB4_RD_CGTT_CLK_CTRL +#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_RD_VC0_CNTL +#define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC1_CNTL +#define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC2_CNTL +#define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC3_CNTL +#define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC4_CNTL +#define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC5_CNTL +#define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC6_CNTL +#define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC7_CNTL +#define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_CNTL_MISC +#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB4_RD_TLB_CREDIT +#define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB4_RD_RDRET_CREDIT_CNTL +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB4_RD_RDRET_CREDIT_CNTL2 +#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB4_RDCLI_ASK_PENDING +#define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_GO_PENDING +#define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_GBLSEND_PENDING +#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_TLB_PENDING +#define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_OARB_PENDING +#define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_OSD_PENDING +#define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI0 +#define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI1 +#define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI2 +#define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI3 +#define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI4 +#define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI5 +#define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI6 +#define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI7 +#define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI8 +#define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI9 +#define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI10 +#define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI11 +#define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI12 +#define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI13 +#define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI14 +#define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI15 +#define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB4_WR_CNTL +#define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB4_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB4_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB4_WR_GMI_CNTL +#define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB4_WR_ADDR_DAGB +#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB4_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB4_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB4_WR_CGTT_CLK_CTRL +#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB +#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB4_WR_DATA_DAGB_MAX_BURST0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_MAX_BURST1 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_VC0_CNTL +#define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC1_CNTL +#define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC2_CNTL +#define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC3_CNTL +#define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC4_CNTL +#define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC5_CNTL +#define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC6_CNTL +#define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC7_CNTL +#define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_CNTL_MISC +#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB4_WR_TLB_CREDIT +#define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB4_WR_DATA_CREDIT +#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB4_WR_MISC_CREDIT +#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB4_WR_OSD_CREDIT_CNTL1 +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB4_WR_OSD_CREDIT_CNTL2 +#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_ASK_PENDING +#define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_GO_PENDING +#define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_GBLSEND_PENDING +#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_TLB_PENDING +#define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_OARB_PENDING +#define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_OSD_PENDING +#define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_DBUS_ASK_PENDING +#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_DBUS_GO_PENDING +#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_DAGB_DLY +#define DAGB4_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB4_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB4_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB4_CNTL_MISC +#define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB4_CNTL_MISC2 +#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB4_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB4_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB4_FATAL_ERROR_CNTL +#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB4_FATAL_ERROR_CLEAR +#define DAGB4_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB4_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB4_FATAL_ERROR_STATUS0 +#define DAGB4_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB4_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB4_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB4_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB4_FATAL_ERROR_STATUS1 +#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB4_FATAL_ERROR_STATUS2 +#define DAGB4_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB4_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB4_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB4_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB4_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB4_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB4_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB4_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB4_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB4_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB4_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB4_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB4_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB4_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB4_FATAL_ERROR_STATUS3 +#define DAGB4_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB4_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB4_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB4_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB4_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB4_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB4_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB4_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB4_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB4_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB4_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB4_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB4_FIFO_EMPTY +#define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB4_FIFO_FULL +#define DAGB4_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB4_WR_CREDITS_FULL +#define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB4_RD_CREDITS_FULL +#define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB4_PERFCOUNTER_LO +#define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB4_PERFCOUNTER_HI +#define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB4_PERFCOUNTER0_CFG +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER1_CFG +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER2_CFG +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER_RSLT_CNTL +#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB4_L1TLB_REG_RW +#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB4_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB4_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB4_RESERVE1 +#define DAGB4_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE2 +#define DAGB4_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE3 +#define DAGB4_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE4 +#define DAGB4_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec5 +//DAGB5_RDCLI0 +#define DAGB5_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI1 +#define DAGB5_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI2 +#define DAGB5_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI3 +#define DAGB5_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI4 +#define DAGB5_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI5 +#define DAGB5_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI6 +#define DAGB5_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI7 +#define DAGB5_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI8 +#define DAGB5_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI9 +#define DAGB5_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI10 +#define DAGB5_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI11 +#define DAGB5_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI12 +#define DAGB5_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI13 +#define DAGB5_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI14 +#define DAGB5_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI15 +#define DAGB5_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB5_RD_CNTL +#define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB5_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB5_RD_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB5_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB5_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB5_RD_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB5_RD_GMI_CNTL +#define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB5_RD_ADDR_DAGB +#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB5_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB5_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB5_RD_CGTT_CLK_CTRL +#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_RD_VC0_CNTL +#define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC1_CNTL +#define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC2_CNTL +#define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC3_CNTL +#define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC4_CNTL +#define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC5_CNTL +#define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC6_CNTL +#define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC7_CNTL +#define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_CNTL_MISC +#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB5_RD_TLB_CREDIT +#define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB5_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB5_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB5_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB5_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB5_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB5_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB5_RD_RDRET_CREDIT_CNTL +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L +#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB5_RD_RDRET_CREDIT_CNTL2 +#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 +#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 +#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc +#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L +#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L +//DAGB5_RDCLI_ASK_PENDING +#define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_GO_PENDING +#define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_GBLSEND_PENDING +#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_TLB_PENDING +#define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_OARB_PENDING +#define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_OSD_PENDING +#define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI0 +#define DAGB5_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI1 +#define DAGB5_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI2 +#define DAGB5_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI3 +#define DAGB5_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI4 +#define DAGB5_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI5 +#define DAGB5_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI6 +#define DAGB5_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI7 +#define DAGB5_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI8 +#define DAGB5_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI9 +#define DAGB5_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI10 +#define DAGB5_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI11 +#define DAGB5_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI12 +#define DAGB5_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI13 +#define DAGB5_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI14 +#define DAGB5_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI15 +#define DAGB5_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB5_WR_CNTL +#define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB5_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB5_WR_CNTL__FIX_JUMP__SHIFT 0x1a +#define DAGB5_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB5_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +#define DAGB5_WR_CNTL__FIX_JUMP_MASK 0x04000000L +//DAGB5_WR_GMI_CNTL +#define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB5_WR_ADDR_DAGB +#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB5_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB5_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB5_WR_CGTT_CLK_CTRL +#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB +#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB5_WR_DATA_DAGB_MAX_BURST0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_MAX_BURST1 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_VC0_CNTL +#define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC1_CNTL +#define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC2_CNTL +#define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC3_CNTL +#define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC4_CNTL +#define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC5_CNTL +#define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC6_CNTL +#define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC7_CNTL +#define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_CNTL_MISC +#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB5_WR_TLB_CREDIT +#define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB5_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB5_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB5_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB5_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB5_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB5_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB5_WR_DATA_CREDIT +#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB5_WR_MISC_CREDIT +#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB5_WR_OSD_CREDIT_CNTL1 +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc +#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 +#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 +#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L +#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L +#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L +#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L +#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L +//DAGB5_WR_OSD_CREDIT_CNTL2 +#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 +#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 +#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL +#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L +//DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L +#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L +//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_ASK_PENDING +#define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_GO_PENDING +#define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_GBLSEND_PENDING +#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_TLB_PENDING +#define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_OARB_PENDING +#define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_OSD_PENDING +#define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_DBUS_ASK_PENDING +#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_DBUS_GO_PENDING +#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_DAGB_DLY +#define DAGB5_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB5_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB5_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB5_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB5_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB5_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB5_CNTL_MISC +#define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB5_CNTL_MISC2 +#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB5_CNTL_MISC2__HDP_CID__SHIFT 0xc +#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB5_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB5_CNTL_MISC2__HDP_CID_MASK 0x0001F000L +#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB5_FATAL_ERROR_CNTL +#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB5_FATAL_ERROR_CLEAR +#define DAGB5_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB5_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB5_FATAL_ERROR_STATUS0 +#define DAGB5_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB5_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB5_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB5_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB5_FATAL_ERROR_STATUS1 +#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB5_FATAL_ERROR_STATUS2 +#define DAGB5_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 +#define DAGB5_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 +#define DAGB5_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 +#define DAGB5_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 +#define DAGB5_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 +#define DAGB5_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 +#define DAGB5_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 +#define DAGB5_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL +#define DAGB5_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L +#define DAGB5_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L +#define DAGB5_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L +#define DAGB5_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L +#define DAGB5_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L +#define DAGB5_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L +//DAGB5_FATAL_ERROR_STATUS3 +#define DAGB5_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB5_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB5_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB5_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB5_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB5_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 +#define DAGB5_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB5_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB5_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB5_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB5_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB5_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L +//DAGB5_FIFO_EMPTY +#define DAGB5_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB5_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB5_FIFO_FULL +#define DAGB5_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB5_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB5_WR_CREDITS_FULL +#define DAGB5_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB5_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB5_RD_CREDITS_FULL +#define DAGB5_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB5_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB5_PERFCOUNTER_LO +#define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB5_PERFCOUNTER_HI +#define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB5_PERFCOUNTER0_CFG +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER1_CFG +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER2_CFG +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER_RSLT_CNTL +#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB5_L1TLB_REG_RW +#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 +#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 +#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 +#define DAGB5_L1TLB_REG_RW__RESERVE__SHIFT 0x6 +#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L +#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L +#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L +#define DAGB5_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L +//DAGB5_RESERVE1 +#define DAGB5_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE2 +#define DAGB5_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE3 +#define DAGB5_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE4 +#define DAGB5_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE4__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_ea_mmeadec0 +//MMEA0_DRAM_RD_CLI2GRP_MAP0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_CLI2GRP_MAP1 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP1 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_GRP2VC_MAP +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_WR_GRP2VC_MAP +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_RD_LAZY +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_DRAM_WR_LAZY +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_DRAM_RD_CAM_CNTL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA0_DRAM_WR_CAM_CNTL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA0_DRAM_PAGE_BURST +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_AGE +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_WR_PRI_AGE +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_RD_PRI_QUEUING +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_QUEUING +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_FIXED +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_FIXED +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_URGENCY +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_WR_PRI_URGENCY +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_CLI2GRP_MAP0 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_GMI_RD_CLI2GRP_MAP1 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_GMI_WR_CLI2GRP_MAP0 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_GMI_WR_CLI2GRP_MAP1 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_GMI_RD_GRP2VC_MAP +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_GMI_WR_GRP2VC_MAP +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_GMI_RD_LAZY +#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_GMI_WR_LAZY +#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_GMI_RD_CAM_CNTL +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA0_GMI_WR_CAM_CNTL +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA0_GMI_PAGE_BURST +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_AGE +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_GMI_WR_PRI_AGE +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_GMI_RD_PRI_QUEUING +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_WR_PRI_QUEUING +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_RD_PRI_FIXED +#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_WR_PRI_FIXED +#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_RD_PRI_URGENCY +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_GMI_WR_PRI_URGENCY +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_GMI_RD_PRI_URGENCY_MASKING +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_GMI_WR_PRI_URGENCY_MASKING +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI1 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI2 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI3 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI1 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI2 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI3 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_ADDRNORM_BASE_ADDR0 +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR1 +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR1 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR1 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA0_ADDRNORM_BASE_ADDR2 +#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR2 +#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR3 +#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR3 +#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR3 +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA0_ADDRNORM_MEGABASE_ADDR0 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_MEGABASE_ADDR1 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORMDRAM_HOLE_CNTL +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA0_ADDRNORMGMI_HOLE_CNTL +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA0_ADDRDEC_BANK_CFG +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA0_ADDRDEC_MISC_CFG +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA0_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA0_ADDRDECGMI_HARVEST_ENABLE +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA0_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_RM_SEL_CS01 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_CS23 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_RM_SEL_CS01 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_CS23 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA0_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC2_RM_SEL_CS01 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_CS23 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA0_ADDRNORMGMI_GLOBAL_CNTL +//MMEA0_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA0_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA0_ADDRNORMDRAM_MASKING +#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA0_ADDRNORMGMI_MASKING +#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA0_IO_RD_CLI2GRP_MAP0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_CLI2GRP_MAP1 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP1 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_COMBINE_FLUSH +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA0_IO_WR_COMBINE_FLUSH +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA0_IO_GROUP_BURST +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_AGE +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_WR_PRI_AGE +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_RD_PRI_QUEUING +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_QUEUING +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_FIXED +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_FIXED +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_URGENCY +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_WR_PRI_URGENCY +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_RD_PRI_URGENCY_MASKING +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_WR_PRI_URGENCY_MASKING +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_RD_PRI_QUANT_PRI1 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI2 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI3 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI1 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI2 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI3 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_SDP_ARB_DRAM +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA0_SDP_ARB_GMI +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA0_SDP_ARB_FINAL +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA0_SDP_DRAM_PRIORITY +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_GMI_PRIORITY +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_IO_PRIORITY +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_CREDITS +#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA0_SDP_TAG_RESERVE0 +#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA0_SDP_TAG_RESERVE1 +#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA0_SDP_VCC_RESERVE0 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCC_RESERVE1 +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_VCD_RESERVE0 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCD_RESERVE1 +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_REQ_CNTL +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA0_MISC +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA0_LATENCY_SAMPLING +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA0_PERFCOUNTER_LO +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA0_PERFCOUNTER_HI +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA0_PERFCOUNTER0_CFG +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER1_CFG +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER_RSLT_CNTL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA0_EDC_CNT +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA0_EDC_CNT2 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA0_DSM_CNTL +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA0_DSM_CNTLA +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA0_DSM_CNTLB +//MMEA0_DSM_CNTL2 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA0_DSM_CNTL2A +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA0_DSM_CNTL2B +//MMEA0_CGTT_CLK_CTRL +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA0_EDC_MODE +#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA0_ERR_STATUS +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA0_MISC2 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA0_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA0_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA0_ADDRDEC_SELECT +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA0_EDC_CNT3 +#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA0_MISC_AON +#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_ea_mmeadec1 +//MMEA1_DRAM_RD_CLI2GRP_MAP0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_CLI2GRP_MAP1 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP1 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_GRP2VC_MAP +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_WR_GRP2VC_MAP +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_RD_LAZY +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_DRAM_WR_LAZY +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_DRAM_RD_CAM_CNTL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA1_DRAM_WR_CAM_CNTL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA1_DRAM_PAGE_BURST +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_AGE +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_WR_PRI_AGE +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_RD_PRI_QUEUING +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_QUEUING +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_FIXED +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_FIXED +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_URGENCY +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_WR_PRI_URGENCY +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_CLI2GRP_MAP0 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_GMI_RD_CLI2GRP_MAP1 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_GMI_WR_CLI2GRP_MAP0 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_GMI_WR_CLI2GRP_MAP1 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_GMI_RD_GRP2VC_MAP +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_GMI_WR_GRP2VC_MAP +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_GMI_RD_LAZY +#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_GMI_WR_LAZY +#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_GMI_RD_CAM_CNTL +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA1_GMI_WR_CAM_CNTL +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA1_GMI_PAGE_BURST +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_AGE +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_GMI_WR_PRI_AGE +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_GMI_RD_PRI_QUEUING +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_WR_PRI_QUEUING +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_RD_PRI_FIXED +#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_WR_PRI_FIXED +#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_RD_PRI_URGENCY +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_GMI_WR_PRI_URGENCY +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_GMI_RD_PRI_URGENCY_MASKING +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_GMI_WR_PRI_URGENCY_MASKING +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI1 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI2 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI3 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI1 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI2 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI3 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_ADDRNORM_BASE_ADDR0 +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR1 +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR1 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR1 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA1_ADDRNORM_BASE_ADDR2 +#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR2 +#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR3 +#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR3 +#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR3 +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA1_ADDRNORM_MEGABASE_ADDR0 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_MEGABASE_ADDR1 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORMDRAM_HOLE_CNTL +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA1_ADDRNORMGMI_HOLE_CNTL +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA1_ADDRDEC_BANK_CFG +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA1_ADDRDEC_MISC_CFG +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA1_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA1_ADDRDECGMI_HARVEST_ENABLE +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA1_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_RM_SEL_CS01 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_CS23 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_RM_SEL_CS01 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_CS23 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA1_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC2_RM_SEL_CS01 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_CS23 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA1_ADDRNORMGMI_GLOBAL_CNTL +//MMEA1_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA1_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA1_ADDRNORMDRAM_MASKING +#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA1_ADDRNORMGMI_MASKING +#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA1_IO_RD_CLI2GRP_MAP0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_CLI2GRP_MAP1 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP1 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_COMBINE_FLUSH +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA1_IO_WR_COMBINE_FLUSH +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA1_IO_GROUP_BURST +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_AGE +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_WR_PRI_AGE +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_RD_PRI_QUEUING +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_QUEUING +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_FIXED +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_FIXED +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_URGENCY +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_WR_PRI_URGENCY +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_RD_PRI_URGENCY_MASKING +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_WR_PRI_URGENCY_MASKING +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_RD_PRI_QUANT_PRI1 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI2 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI3 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI1 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI2 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI3 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_SDP_ARB_DRAM +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA1_SDP_ARB_GMI +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA1_SDP_ARB_FINAL +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA1_SDP_DRAM_PRIORITY +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_GMI_PRIORITY +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_IO_PRIORITY +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_CREDITS +#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA1_SDP_TAG_RESERVE0 +#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA1_SDP_TAG_RESERVE1 +#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA1_SDP_VCC_RESERVE0 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCC_RESERVE1 +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_VCD_RESERVE0 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCD_RESERVE1 +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_REQ_CNTL +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA1_MISC +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA1_LATENCY_SAMPLING +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA1_PERFCOUNTER_LO +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA1_PERFCOUNTER_HI +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA1_PERFCOUNTER0_CFG +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER1_CFG +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER_RSLT_CNTL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA1_EDC_CNT +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA1_EDC_CNT2 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA1_DSM_CNTL +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA1_DSM_CNTLA +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA1_DSM_CNTLB +//MMEA1_DSM_CNTL2 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA1_DSM_CNTL2A +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA1_DSM_CNTL2B +//MMEA1_CGTT_CLK_CTRL +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA1_EDC_MODE +#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA1_ERR_STATUS +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA1_MISC2 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA1_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA1_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA1_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA1_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA1_ADDRDEC_SELECT +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA1_EDC_CNT3 +#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA1_MISC_AON +#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_ea_mmeadec2 +//MMEA2_DRAM_RD_CLI2GRP_MAP0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_RD_CLI2GRP_MAP1 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_WR_CLI2GRP_MAP0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_WR_CLI2GRP_MAP1 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_RD_GRP2VC_MAP +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_DRAM_WR_GRP2VC_MAP +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_DRAM_RD_LAZY +#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_DRAM_WR_LAZY +#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_DRAM_RD_CAM_CNTL +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA2_DRAM_WR_CAM_CNTL +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA2_DRAM_PAGE_BURST +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_AGE +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_DRAM_WR_PRI_AGE +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_DRAM_RD_PRI_QUEUING +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_WR_PRI_QUEUING +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_RD_PRI_FIXED +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_WR_PRI_FIXED +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_RD_PRI_URGENCY +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_DRAM_WR_PRI_URGENCY +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_CLI2GRP_MAP0 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_GMI_RD_CLI2GRP_MAP1 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_GMI_WR_CLI2GRP_MAP0 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_GMI_WR_CLI2GRP_MAP1 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_GMI_RD_GRP2VC_MAP +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_GMI_WR_GRP2VC_MAP +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_GMI_RD_LAZY +#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_GMI_WR_LAZY +#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_GMI_RD_CAM_CNTL +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA2_GMI_WR_CAM_CNTL +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA2_GMI_PAGE_BURST +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_AGE +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_GMI_WR_PRI_AGE +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_GMI_RD_PRI_QUEUING +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_WR_PRI_QUEUING +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_RD_PRI_FIXED +#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_WR_PRI_FIXED +#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_RD_PRI_URGENCY +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_GMI_WR_PRI_URGENCY +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_GMI_RD_PRI_URGENCY_MASKING +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_GMI_WR_PRI_URGENCY_MASKING +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI1 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI2 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI3 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI1 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI2 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI3 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_ADDRNORM_BASE_ADDR0 +#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR0 +#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_BASE_ADDR1 +#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR1 +#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_OFFSET_ADDR1 +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA2_ADDRNORM_BASE_ADDR2 +#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR2 +#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_BASE_ADDR3 +#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR3 +#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_OFFSET_ADDR3 +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA2_ADDRNORM_MEGABASE_ADDR0 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_MEGABASE_ADDR1 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORMDRAM_HOLE_CNTL +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA2_ADDRNORMGMI_HOLE_CNTL +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA2_ADDRDEC_BANK_CFG +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA2_ADDRDEC_MISC_CFG +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA2_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA2_ADDRDECGMI_HARVEST_ENABLE +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA2_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC0_RM_SEL_CS01 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_CS23 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC1_RM_SEL_CS01 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_CS23 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA2_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC2_RM_SEL_CS01 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_CS23 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA2_ADDRNORMGMI_GLOBAL_CNTL +//MMEA2_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA2_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA2_ADDRNORMDRAM_MASKING +#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA2_ADDRNORMGMI_MASKING +#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA2_IO_RD_CLI2GRP_MAP0 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_IO_RD_CLI2GRP_MAP1 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_IO_WR_CLI2GRP_MAP0 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_IO_WR_CLI2GRP_MAP1 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_IO_RD_COMBINE_FLUSH +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA2_IO_WR_COMBINE_FLUSH +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA2_IO_GROUP_BURST +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_AGE +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_IO_WR_PRI_AGE +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_IO_RD_PRI_QUEUING +#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_WR_PRI_QUEUING +#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_RD_PRI_FIXED +#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_WR_PRI_FIXED +#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_RD_PRI_URGENCY +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_IO_WR_PRI_URGENCY +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_IO_RD_PRI_URGENCY_MASKING +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_IO_WR_PRI_URGENCY_MASKING +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_IO_RD_PRI_QUANT_PRI1 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_QUANT_PRI2 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_QUANT_PRI3 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI1 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI2 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI3 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_SDP_ARB_DRAM +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA2_SDP_ARB_GMI +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA2_SDP_ARB_FINAL +#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA2_SDP_DRAM_PRIORITY +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_GMI_PRIORITY +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_IO_PRIORITY +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_CREDITS +#define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA2_SDP_TAG_RESERVE0 +#define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA2_SDP_TAG_RESERVE1 +#define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA2_SDP_VCC_RESERVE0 +#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA2_SDP_VCC_RESERVE1 +#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA2_SDP_VCD_RESERVE0 +#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA2_SDP_VCD_RESERVE1 +#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA2_SDP_REQ_CNTL +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA2_MISC +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA2_LATENCY_SAMPLING +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA2_PERFCOUNTER_LO +#define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA2_PERFCOUNTER_HI +#define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA2_PERFCOUNTER0_CFG +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA2_PERFCOUNTER1_CFG +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA2_PERFCOUNTER_RSLT_CNTL +#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA2_EDC_CNT +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA2_EDC_CNT2 +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA2_DSM_CNTL +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA2_DSM_CNTLA +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA2_DSM_CNTLB +//MMEA2_DSM_CNTL2 +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA2_DSM_CNTL2A +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA2_DSM_CNTL2B +//MMEA2_CGTT_CLK_CTRL +#define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA2_EDC_MODE +#define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA2_ERR_STATUS +#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA2_MISC2 +#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA2_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA2_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA2_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA2_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA2_ADDRDEC_SELECT +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA2_EDC_CNT3 +#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA2_MISC_AON +#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_ea_mmeadec3 +//MMEA3_DRAM_RD_CLI2GRP_MAP0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_RD_CLI2GRP_MAP1 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_WR_CLI2GRP_MAP0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_WR_CLI2GRP_MAP1 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_RD_GRP2VC_MAP +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_DRAM_WR_GRP2VC_MAP +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_DRAM_RD_LAZY +#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_DRAM_WR_LAZY +#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_DRAM_RD_CAM_CNTL +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA3_DRAM_WR_CAM_CNTL +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA3_DRAM_PAGE_BURST +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_AGE +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_DRAM_WR_PRI_AGE +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_DRAM_RD_PRI_QUEUING +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_WR_PRI_QUEUING +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_RD_PRI_FIXED +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_WR_PRI_FIXED +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_RD_PRI_URGENCY +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_DRAM_WR_PRI_URGENCY +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_CLI2GRP_MAP0 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_GMI_RD_CLI2GRP_MAP1 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_GMI_WR_CLI2GRP_MAP0 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_GMI_WR_CLI2GRP_MAP1 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_GMI_RD_GRP2VC_MAP +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_GMI_WR_GRP2VC_MAP +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_GMI_RD_LAZY +#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_GMI_WR_LAZY +#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_GMI_RD_CAM_CNTL +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA3_GMI_WR_CAM_CNTL +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA3_GMI_PAGE_BURST +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_AGE +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_GMI_WR_PRI_AGE +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_GMI_RD_PRI_QUEUING +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_WR_PRI_QUEUING +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_RD_PRI_FIXED +#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_WR_PRI_FIXED +#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_RD_PRI_URGENCY +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_GMI_WR_PRI_URGENCY +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_GMI_RD_PRI_URGENCY_MASKING +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_GMI_WR_PRI_URGENCY_MASKING +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI1 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI2 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI3 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI1 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI2 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI3 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_ADDRNORM_BASE_ADDR0 +#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR0 +#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_BASE_ADDR1 +#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR1 +#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_OFFSET_ADDR1 +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA3_ADDRNORM_BASE_ADDR2 +#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR2 +#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_BASE_ADDR3 +#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR3 +#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_OFFSET_ADDR3 +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA3_ADDRNORM_MEGABASE_ADDR0 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_MEGABASE_ADDR1 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORMDRAM_HOLE_CNTL +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA3_ADDRNORMGMI_HOLE_CNTL +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA3_ADDRDEC_BANK_CFG +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA3_ADDRDEC_MISC_CFG +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA3_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA3_ADDRDECGMI_HARVEST_ENABLE +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA3_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC0_RM_SEL_CS01 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_CS23 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC1_RM_SEL_CS01 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_CS23 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA3_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC2_RM_SEL_CS01 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_CS23 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA3_ADDRNORMGMI_GLOBAL_CNTL +//MMEA3_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA3_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA3_ADDRNORMDRAM_MASKING +#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA3_ADDRNORMGMI_MASKING +#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA3_IO_RD_CLI2GRP_MAP0 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_IO_RD_CLI2GRP_MAP1 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_IO_WR_CLI2GRP_MAP0 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_IO_WR_CLI2GRP_MAP1 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_IO_RD_COMBINE_FLUSH +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA3_IO_WR_COMBINE_FLUSH +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA3_IO_GROUP_BURST +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_AGE +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_IO_WR_PRI_AGE +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_IO_RD_PRI_QUEUING +#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_WR_PRI_QUEUING +#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_RD_PRI_FIXED +#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_WR_PRI_FIXED +#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_RD_PRI_URGENCY +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_IO_WR_PRI_URGENCY +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_IO_RD_PRI_URGENCY_MASKING +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_IO_WR_PRI_URGENCY_MASKING +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_IO_RD_PRI_QUANT_PRI1 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_QUANT_PRI2 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_QUANT_PRI3 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI1 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI2 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI3 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_SDP_ARB_DRAM +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA3_SDP_ARB_GMI +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA3_SDP_ARB_FINAL +#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA3_SDP_DRAM_PRIORITY +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_GMI_PRIORITY +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_IO_PRIORITY +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_CREDITS +#define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA3_SDP_TAG_RESERVE0 +#define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA3_SDP_TAG_RESERVE1 +#define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA3_SDP_VCC_RESERVE0 +#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA3_SDP_VCC_RESERVE1 +#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA3_SDP_VCD_RESERVE0 +#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA3_SDP_VCD_RESERVE1 +#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA3_SDP_REQ_CNTL +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA3_MISC +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA3_LATENCY_SAMPLING +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA3_PERFCOUNTER_LO +#define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA3_PERFCOUNTER_HI +#define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA3_PERFCOUNTER0_CFG +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA3_PERFCOUNTER1_CFG +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA3_PERFCOUNTER_RSLT_CNTL +#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA3_EDC_CNT +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA3_EDC_CNT2 +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA3_DSM_CNTL +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA3_DSM_CNTLA +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA3_DSM_CNTLB +//MMEA3_DSM_CNTL2 +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA3_DSM_CNTL2A +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA3_DSM_CNTL2B +//MMEA3_CGTT_CLK_CTRL +#define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA3_EDC_MODE +#define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA3_ERR_STATUS +#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA3_MISC2 +#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA3_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA3_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA3_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA3_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA3_ADDRDEC_SELECT +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA3_EDC_CNT3 +#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA3_MISC_AON +#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_ea_mmeadec4 +//MMEA4_DRAM_RD_CLI2GRP_MAP0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_RD_CLI2GRP_MAP1 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_WR_CLI2GRP_MAP0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_WR_CLI2GRP_MAP1 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_RD_GRP2VC_MAP +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_DRAM_WR_GRP2VC_MAP +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_DRAM_RD_LAZY +#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_DRAM_WR_LAZY +#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_DRAM_RD_CAM_CNTL +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA4_DRAM_WR_CAM_CNTL +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA4_DRAM_PAGE_BURST +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_AGE +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_DRAM_WR_PRI_AGE +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_DRAM_RD_PRI_QUEUING +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_WR_PRI_QUEUING +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_RD_PRI_FIXED +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_WR_PRI_FIXED +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_RD_PRI_URGENCY +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_DRAM_WR_PRI_URGENCY +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_CLI2GRP_MAP0 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_GMI_RD_CLI2GRP_MAP1 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_GMI_WR_CLI2GRP_MAP0 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_GMI_WR_CLI2GRP_MAP1 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_GMI_RD_GRP2VC_MAP +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_GMI_WR_GRP2VC_MAP +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_GMI_RD_LAZY +#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_GMI_WR_LAZY +#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_GMI_RD_CAM_CNTL +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA4_GMI_WR_CAM_CNTL +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA4_GMI_PAGE_BURST +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_AGE +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_GMI_WR_PRI_AGE +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_GMI_RD_PRI_QUEUING +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_WR_PRI_QUEUING +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_RD_PRI_FIXED +#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_WR_PRI_FIXED +#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_RD_PRI_URGENCY +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_GMI_WR_PRI_URGENCY +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_GMI_RD_PRI_URGENCY_MASKING +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_GMI_WR_PRI_URGENCY_MASKING +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI1 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI2 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI3 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI1 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI2 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI3 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_ADDRNORM_BASE_ADDR0 +#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR0 +#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_BASE_ADDR1 +#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR1 +#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_OFFSET_ADDR1 +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA4_ADDRNORM_BASE_ADDR2 +#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR2 +#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_BASE_ADDR3 +#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR3 +#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_OFFSET_ADDR3 +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA4_ADDRNORM_MEGABASE_ADDR0 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_MEGABASE_ADDR1 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORMDRAM_HOLE_CNTL +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA4_ADDRNORMGMI_HOLE_CNTL +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA4_ADDRDEC_BANK_CFG +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA4_ADDRDEC_MISC_CFG +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA4_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA4_ADDRDECGMI_HARVEST_ENABLE +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA4_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC0_RM_SEL_CS01 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_CS23 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC1_RM_SEL_CS01 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_CS23 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA4_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC2_RM_SEL_CS01 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_CS23 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA4_ADDRNORMGMI_GLOBAL_CNTL +//MMEA4_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA4_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA4_ADDRNORMDRAM_MASKING +#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA4_ADDRNORMGMI_MASKING +#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA4_IO_RD_CLI2GRP_MAP0 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_IO_RD_CLI2GRP_MAP1 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_IO_WR_CLI2GRP_MAP0 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_IO_WR_CLI2GRP_MAP1 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_IO_RD_COMBINE_FLUSH +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA4_IO_WR_COMBINE_FLUSH +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA4_IO_GROUP_BURST +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_AGE +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_IO_WR_PRI_AGE +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_IO_RD_PRI_QUEUING +#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_WR_PRI_QUEUING +#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_RD_PRI_FIXED +#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_WR_PRI_FIXED +#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_RD_PRI_URGENCY +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_IO_WR_PRI_URGENCY +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_IO_RD_PRI_URGENCY_MASKING +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_IO_WR_PRI_URGENCY_MASKING +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_IO_RD_PRI_QUANT_PRI1 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_QUANT_PRI2 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_QUANT_PRI3 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI1 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI2 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI3 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_SDP_ARB_DRAM +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA4_SDP_ARB_GMI +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA4_SDP_ARB_FINAL +#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA4_SDP_DRAM_PRIORITY +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_GMI_PRIORITY +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_IO_PRIORITY +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_CREDITS +#define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA4_SDP_TAG_RESERVE0 +#define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA4_SDP_TAG_RESERVE1 +#define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA4_SDP_VCC_RESERVE0 +#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA4_SDP_VCC_RESERVE1 +#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA4_SDP_VCD_RESERVE0 +#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA4_SDP_VCD_RESERVE1 +#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA4_SDP_REQ_CNTL +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA4_MISC +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA4_LATENCY_SAMPLING +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA4_PERFCOUNTER_LO +#define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA4_PERFCOUNTER_HI +#define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA4_PERFCOUNTER0_CFG +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA4_PERFCOUNTER1_CFG +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA4_PERFCOUNTER_RSLT_CNTL +#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA4_EDC_CNT +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA4_EDC_CNT2 +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA4_DSM_CNTL +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA4_DSM_CNTLA +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA4_DSM_CNTLB +//MMEA4_DSM_CNTL2 +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA4_DSM_CNTL2A +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA4_DSM_CNTL2B +//MMEA4_CGTT_CLK_CTRL +#define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA4_EDC_MODE +#define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA4_ERR_STATUS +#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA4_MISC2 +#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA4_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA4_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA4_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA4_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA4_ADDRDEC_SELECT +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA4_EDC_CNT3 +#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA4_MISC_AON +#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_ea_mmeadec5 +//MMEA5_DRAM_RD_CLI2GRP_MAP0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_RD_CLI2GRP_MAP1 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_WR_CLI2GRP_MAP0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_WR_CLI2GRP_MAP1 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_RD_GRP2VC_MAP +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_DRAM_WR_GRP2VC_MAP +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_DRAM_RD_LAZY +#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_DRAM_WR_LAZY +#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_DRAM_RD_CAM_CNTL +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA5_DRAM_WR_CAM_CNTL +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA5_DRAM_PAGE_BURST +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_AGE +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_DRAM_WR_PRI_AGE +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_DRAM_RD_PRI_QUEUING +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_WR_PRI_QUEUING +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_RD_PRI_FIXED +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_WR_PRI_FIXED +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_RD_PRI_URGENCY +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_DRAM_WR_PRI_URGENCY +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_CLI2GRP_MAP0 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_GMI_RD_CLI2GRP_MAP1 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_GMI_WR_CLI2GRP_MAP0 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_GMI_WR_CLI2GRP_MAP1 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_GMI_RD_GRP2VC_MAP +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_GMI_WR_GRP2VC_MAP +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_GMI_RD_LAZY +#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_GMI_WR_LAZY +#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_GMI_RD_CAM_CNTL +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA5_GMI_WR_CAM_CNTL +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA5_GMI_PAGE_BURST +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_AGE +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_GMI_WR_PRI_AGE +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_GMI_RD_PRI_QUEUING +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_WR_PRI_QUEUING +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_RD_PRI_FIXED +#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_WR_PRI_FIXED +#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_RD_PRI_URGENCY +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_GMI_WR_PRI_URGENCY +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_GMI_RD_PRI_URGENCY_MASKING +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_GMI_WR_PRI_URGENCY_MASKING +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI1 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI2 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI3 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI1 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI2 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI3 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_ADDRNORM_BASE_ADDR0 +#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR0 +#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_BASE_ADDR1 +#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR1 +#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_OFFSET_ADDR1 +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA5_ADDRNORM_BASE_ADDR2 +#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR2 +#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_BASE_ADDR3 +#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR3 +#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_OFFSET_ADDR3 +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L +//MMEA5_ADDRNORM_MEGABASE_ADDR0 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_MEGALIMIT_ADDR0 +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_MEGABASE_ADDR1 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_MEGALIMIT_ADDR1 +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORMDRAM_HOLE_CNTL +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA5_ADDRNORMGMI_HOLE_CNTL +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA5_ADDRDEC_BANK_CFG +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA5_ADDRDEC_MISC_CFG +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA5_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA5_ADDRDECGMI_HARVEST_ENABLE +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA5_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC0_RM_SEL_CS01 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_CS23 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC1_RM_SEL_CS01 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_CS23 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L +//MMEA5_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC2_RM_SEL_CS01 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_CS23 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRNORMDRAM_GLOBAL_CNTL +//MMEA5_ADDRNORMGMI_GLOBAL_CNTL +//MMEA5_ADDRNORM_MEGACONTROL_ADDR0 +#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA5_ADDRNORM_MEGACONTROL_ADDR1 +#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 +#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL +//MMEA5_ADDRNORMDRAM_MASKING +#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA5_ADDRNORMGMI_MASKING +#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 +#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL +//MMEA5_IO_RD_CLI2GRP_MAP0 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_IO_RD_CLI2GRP_MAP1 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_IO_WR_CLI2GRP_MAP0 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_IO_WR_CLI2GRP_MAP1 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_IO_RD_COMBINE_FLUSH +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA5_IO_WR_COMBINE_FLUSH +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//MMEA5_IO_GROUP_BURST +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_AGE +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_IO_WR_PRI_AGE +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_IO_RD_PRI_QUEUING +#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_WR_PRI_QUEUING +#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_RD_PRI_FIXED +#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_WR_PRI_FIXED +#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_RD_PRI_URGENCY +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_IO_WR_PRI_URGENCY +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_IO_RD_PRI_URGENCY_MASKING +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_IO_WR_PRI_URGENCY_MASKING +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_IO_RD_PRI_QUANT_PRI1 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_QUANT_PRI2 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_QUANT_PRI3 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI1 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI2 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI3 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_SDP_ARB_DRAM +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA5_SDP_ARB_GMI +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA5_SDP_ARB_FINAL +#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c +#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d +#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e +#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f +#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L +#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L +#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L +#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L +//MMEA5_SDP_DRAM_PRIORITY +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_GMI_PRIORITY +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_IO_PRIORITY +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_CREDITS +#define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA5_SDP_TAG_RESERVE0 +#define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA5_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA5_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA5_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA5_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA5_SDP_TAG_RESERVE1 +#define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA5_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA5_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA5_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA5_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA5_SDP_VCC_RESERVE0 +#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA5_SDP_VCC_RESERVE1 +#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA5_SDP_VCD_RESERVE0 +#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA5_SDP_VCD_RESERVE1 +#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA5_SDP_REQ_CNTL +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//MMEA5_MISC +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA5_LATENCY_SAMPLING +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA5_PERFCOUNTER_LO +#define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA5_PERFCOUNTER_HI +#define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA5_PERFCOUNTER0_CFG +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA5_PERFCOUNTER1_CFG +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA5_PERFCOUNTER_RSLT_CNTL +#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA5_EDC_CNT +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 +#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 +#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 +#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a +#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c +#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L +#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L +#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L +#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L +#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L +//MMEA5_EDC_CNT2 +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 +#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a +#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c +#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L +#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L +#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L +#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L +//MMEA5_DSM_CNTL +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA5_DSM_CNTLA +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA5_DSM_CNTLB +//MMEA5_DSM_CNTL2 +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA5_DSM_CNTL2A +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA5_DSM_CNTL2B +//MMEA5_CGTT_CLK_CTRL +#define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA5_EDC_MODE +#define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA5_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA5_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA5_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA5_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA5_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA5_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA5_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA5_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA5_ERR_STATUS +#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA5_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//MMEA5_MISC2 +#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA5_MISC2__BLOCK_REQUESTS__SHIFT 0xe +#define MMEA5_MISC2__REQUESTS_BLOCKED__SHIFT 0xf +#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA5_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +#define MMEA5_MISC2__BLOCK_REQUESTS_MASK 0x00004000L +#define MMEA5_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L +//MMEA5_ADDRDEC_SELECT +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA5_EDC_CNT3 +#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L +//MMEA5_MISC_AON +#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L + + +// addressBlock: mmhub_l1tlb_vml1dec +//MC_VM_MX_L1_TLB0_STATUS +#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB1_STATUS +#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB2_STATUS +#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB3_STATUS +#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB4_STATUS +#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB5_STATUS +#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB6_STATUS +#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB7_STATUS +#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L + + +// addressBlock: mmhub_l1tlb_vml1pldec +//MC_VM_MX_L1_PERFCOUNTER0_CFG +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER1_CFG +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER2_CFG +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER3_CFG +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_vml1prdec +//MC_VM_MX_L1_PERFCOUNTER_LO +#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_MX_L1_PERFCOUNTER_HI +#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_pctldec0 +//PCTL0_CTRL +#define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 +#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 +#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 +#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 +#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 +#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 +#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK__SHIFT 0x16 +#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x17 +#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x18 +#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x19 +#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x1a +#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1b +#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK__SHIFT 0x1c +#define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L +#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L +#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L +#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L +#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L +#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L +#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L +#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK_MASK 0x00400000L +#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00800000L +#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x01000000L +#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x02000000L +#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x04000000L +#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x08000000L +#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK_MASK 0x10000000L +//PCTL0_MMHUB_DEEPSLEEP_IB +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL0_PG_IGNORE_DEEPSLEEP +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL0_PG_IGNORE_DEEPSLEEP_IB +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL0_SLICE0_CFG_DAGB_BUSY +#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE0_CFG_DS_ALLOW +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE0_CFG_DS_ALLOW_IB +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE1_CFG_DAGB_BUSY +#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE1_CFG_DS_ALLOW +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE1_CFG_DS_ALLOW_IB +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE2_CFG_DAGB_BUSY +#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE2_CFG_DS_ALLOW +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE2_CFG_DS_ALLOW_IB +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE3_CFG_DAGB_BUSY +#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE3_CFG_DS_ALLOW +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE3_CFG_DS_ALLOW_IB +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE4_CFG_DAGB_BUSY +#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE4_CFG_DS_ALLOW +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE4_CFG_DS_ALLOW_IB +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE5_CFG_DAGB_BUSY +#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE5_CFG_DS_ALLOW +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE5_CFG_DS_ALLOW_IB +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_UTCL2_MISC +#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE0_MISC +#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE1_MISC +#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE2_MISC +#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE3_MISC +#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE4_MISC +#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE5_MISC +#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE_MASK 0x00040000L + + +// addressBlock: mmhub_utcl2_atcl2dec +//ATC_L2_CNTL +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L +//ATC_L2_CNTL2 +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//ATC_L2_CACHE_DATA0 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATC_L2_CACHE_DATA1 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA2 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA3 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CNTL3 +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//ATC_L2_STATUS +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__BUSY_MASK 0x00000001L +//ATC_L2_STATUS2 +#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 +#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc +#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12 +#define ATC_L2_STATUS2__UCE__SHIFT 0x13 +#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL +#define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L +#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L +#define ATC_L2_STATUS2__UCE_MASK 0x00080000L +//ATC_L2_MISC_CG +#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATC_L2_MEM_POWER_LS +#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATC_L2_CGTT_CLK_CTRL +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//ATC_L2_CACHE_4K_DSM_INDEX +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_32K_DSM_INDEX +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_2M_DSM_INDEX +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_4K_DSM_CNTL +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_32K_DSM_CNTL +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_2M_DSM_CNTL +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CNTL4 +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//ATC_L2_MM_GROUP_RT_CLASSES +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +//ATC_L2_PERFCOUNTER0_CFG +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER1_CFG +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +//ATC_L2_PERFCOUNTER_LO +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_L2_PERFCOUNTER_HI +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_l2tlbdec +//L2TLB_TLB0_STATUS +#define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L + + +// addressBlock: mmhub_utcl2_l2tlbpldec +//L2TLB_PERFCOUNTER0_CFG +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER1_CFG +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER2_CFG +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER3_CFG +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER_RSLT_CNTL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_l2tlbprdec +//L2TLB_PERFCOUNTER_LO +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//L2TLB_PERFCOUNTER_HI +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_vml2pfdec +//VM_L2_CNTL +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VM_L2_CNTL2 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_CNTL3 +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_STATUS +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VM_DUMMY_PAGE_FAULT_CNTL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_CNTL +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VM_L2_PROTECTION_FAULT_CNTL2 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_STATUS +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L +//VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VM_L2_CNTL4 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +//VM_L2_MM_GROUP_RT_CLASSES +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VM_L2_BANK_SELECT_RESERVED_CID +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_BANK_SELECT_RESERVED_CID2 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_CACHE_PARITY_CNTL +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VM_L2_CGTT_CLK_CTRL +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//VM_L2_CGTT_BUSY_CTRL +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L +//VML2_MEM_ECC_INDEX +#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_WALKER_MEM_ECC_INDEX +#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//UTCL2_MEM_ECC_INDEX +#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_MEM_ECC_CNTL +#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_WALKER_MEM_ECC_CNTL +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//UTCL2_MEM_ECC_CNTL +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_MEM_ECC_STATUS +#define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//VML2_WALKER_MEM_ECC_STATUS +#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_MEM_ECC_STATUS +#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_EDC_MODE +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 +#define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d +#define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L +#define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L +#define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L +//UTCL2_EDC_CONFIG +#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L + + +// addressBlock: mmhub_utcl2_vml2pldec +//MC_VM_L2_PERFCOUNTER0_CFG +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER1_CFG +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER2_CFG +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER3_CFG +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER4_CFG +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER5_CFG +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER6_CFG +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER7_CFG +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2prdec +//MC_VM_L2_PERFCOUNTER_LO +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_L2_PERFCOUNTER_HI +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_vml2vcdec +//VM_CONTEXT0_CNTL +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT1_CNTL +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT2_CNTL +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT3_CNTL +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT4_CNTL +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT5_CNTL +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT6_CNTL +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT7_CNTL +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT8_CNTL +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT9_CNTL +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT10_CNTL +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT11_CNTL +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT12_CNTL +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT13_CNTL +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT14_CNTL +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT15_CNTL +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXTS_DISABLE +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_INVALIDATE_ENG0_SEM +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG1_SEM +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG2_SEM +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG3_SEM +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG4_SEM +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG5_SEM +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG6_SEM +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG7_SEM +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG8_SEM +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG9_SEM +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG10_SEM +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG11_SEM +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG12_SEM +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG13_SEM +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG14_SEM +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG15_SEM +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG16_SEM +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG17_SEM +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG0_REQ +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG1_REQ +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG2_REQ +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG3_REQ +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG4_REQ +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG5_REQ +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG6_REQ +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG7_REQ +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG8_REQ +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG9_REQ +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG10_REQ +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG11_REQ +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG12_REQ +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG13_REQ +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG14_REQ +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG15_REQ +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG16_REQ +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG17_REQ +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG0_ACK +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG1_ACK +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG2_ACK +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG3_ACK +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG4_ACK +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG5_ACK +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG6_ACK +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG7_ACK +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG8_ACK +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG9_ACK +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG10_ACK +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG11_ACK +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG12_ACK +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG13_ACK +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG14_ACK +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG15_ACK +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG16_ACK +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG17_ACK +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +//MC_VM_FB_SIZE_OFFSET_VF0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF1 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF2 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF3 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF4 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF5 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF6 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF7 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF8 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF9 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF11 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF12 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF13 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF14 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF15 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_MARC_BASE_LO_0 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_1 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_2 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_3 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_HI_0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_1 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_2 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_3 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_LO_0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_2 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_3 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_HI_0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_1 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_2 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_3 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_LO_0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_1 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_2 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_3 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_HI_0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_1 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_2 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_3 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VM_PCIE_ATS_CNTL +#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_0 +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_1 +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_2 +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_3 +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_4 +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_5 +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_6 +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_7 +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_8 +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_9 +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_10 +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_11 +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_12 +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_13 +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_14 +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_15 +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//MC_SHARED_ACTIVE_FCN_ID +#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MC_VM_XGMI_GPUIOV_ENABLE +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +//MC_VM_FB_OFFSET +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MC_VM_STEERING +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MC_SHARED_VIRT_RESET_REQ +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MC_MEM_POWER_LS +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_APT_CNTL +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 +#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L +#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L +//MC_VM_LOCAL_HBM_ADDRESS_START +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_END +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//UTCL2_CGTT_CLK_CTRL +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//MC_VM_XGMI_LFB_CNTL +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//MC_VM_XGMI_LFB_SIZE +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//MC_VM_CACHEABLE_DRAM_CNTL +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L +//MC_VM_HOST_MAPPING +#define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +//MC_VM_FB_LOCATION_BASE +#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MC_VM_FB_LOCATION_TOP +#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_TOP +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_BOT +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MC_VM_AGP_BASE +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_MX_L1_TLB_CNTL +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..0b1e781fed7e25403dd430442f7817f72c7d45c2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h @@ -0,0 +1,361 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_13_0_2_OFFSET_HEADER +#define _mp_13_0_2_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define regMP0_SMN_C2PMSG_32 0x0060 +#define regMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_33 0x0061 +#define regMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_34 0x0062 +#define regMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_35 0x0063 +#define regMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_36 0x0064 +#define regMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_37 0x0065 +#define regMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_38 0x0066 +#define regMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_39 0x0067 +#define regMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_40 0x0068 +#define regMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_41 0x0069 +#define regMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_42 0x006a +#define regMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_43 0x006b +#define regMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_44 0x006c +#define regMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_45 0x006d +#define regMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_46 0x006e +#define regMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_47 0x006f +#define regMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_48 0x0070 +#define regMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_49 0x0071 +#define regMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_50 0x0072 +#define regMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_51 0x0073 +#define regMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_52 0x0074 +#define regMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_53 0x0075 +#define regMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_54 0x0076 +#define regMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_55 0x0077 +#define regMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_56 0x0078 +#define regMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_57 0x0079 +#define regMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_58 0x007a +#define regMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_59 0x007b +#define regMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_60 0x007c +#define regMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_61 0x007d +#define regMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_62 0x007e +#define regMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_63 0x007f +#define regMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_64 0x0080 +#define regMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_65 0x0081 +#define regMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_66 0x0082 +#define regMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_67 0x0083 +#define regMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_68 0x0084 +#define regMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_69 0x0085 +#define regMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_70 0x0086 +#define regMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_71 0x0087 +#define regMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_72 0x0088 +#define regMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_73 0x0089 +#define regMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_74 0x008a +#define regMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_75 0x008b +#define regMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_76 0x008c +#define regMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_77 0x008d +#define regMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_78 0x008e +#define regMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_79 0x008f +#define regMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_80 0x0090 +#define regMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_81 0x0091 +#define regMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_82 0x0092 +#define regMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_83 0x0093 +#define regMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_84 0x0094 +#define regMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_85 0x0095 +#define regMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_86 0x0096 +#define regMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_87 0x0097 +#define regMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_88 0x0098 +#define regMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_89 0x0099 +#define regMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_90 0x009a +#define regMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_91 0x009b +#define regMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_92 0x009c +#define regMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_93 0x009d +#define regMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_94 0x009e +#define regMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_95 0x009f +#define regMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_96 0x00a0 +#define regMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_97 0x00a1 +#define regMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_98 0x00a2 +#define regMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_99 0x00a3 +#define regMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_100 0x00a4 +#define regMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_101 0x00a5 +#define regMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_102 0x00a6 +#define regMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_103 0x00a7 +#define regMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP0_SMN_IH_CREDIT 0x00c1 +#define regMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT 0x00c2 +#define regMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x0 +#define regMP1_FIRMWARE_FLAGS 0xbee009 +#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_32 0x0260 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_33 0x0261 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_34 0x0262 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_35 0x0263 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_36 0x0264 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_37 0x0265 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_38 0x0266 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_39 0x0267 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_40 0x0268 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_41 0x0269 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_42 0x026a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_43 0x026b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_44 0x026c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_45 0x026d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_46 0x026e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_47 0x026f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_48 0x0270 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_49 0x0271 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_50 0x0272 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_51 0x0273 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_52 0x0274 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_53 0x0275 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_54 0x0276 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_55 0x0277 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_56 0x0278 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_57 0x0279 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_58 0x027a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_59 0x027b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_60 0x027c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_61 0x027d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_62 0x027e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_63 0x027f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_64 0x0280 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_65 0x0281 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_66 0x0282 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_67 0x0283 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_68 0x0284 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_69 0x0285 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_70 0x0286 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_71 0x0287 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_72 0x0288 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_73 0x0289 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_74 0x028a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_75 0x028b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_76 0x028c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_77 0x028d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_78 0x028e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_79 0x028f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_80 0x0290 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_81 0x0291 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_82 0x0292 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_83 0x0293 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_84 0x0294 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_85 0x0295 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_86 0x0296 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_87 0x0297 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_88 0x0298 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_89 0x0299 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_90 0x029a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_91 0x029b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_92 0x029c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_93 0x029d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_94 0x029e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_95 0x029f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_96 0x02a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_97 0x02a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_98 0x02a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_99 0x02a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_100 0x02a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_101 0x02a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_102 0x02a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_103 0x02a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP1_SMN_IH_CREDIT 0x02c1 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT 0x02c2 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define regMP1_SMN_FPS_CNT 0x02c4 +#define regMP1_SMN_FPS_CNT_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH0 0x0340 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH1 0x0341 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH2 0x0342 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH3 0x0343 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH4 0x0344 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH5 0x0345 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH6 0x0346 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH7 0x0347 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..0af8e95dadabbf2c2217779ee217578139d4053f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h @@ -0,0 +1,531 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_13_0_2_SH_MASK_HEADER +#define _mp_13_0_2_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..9f156633fdb662ed7c6d0f8180ed63db0c9969fb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h @@ -0,0 +1,5224 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _sdma_4_4_0_OFFSET_HEADER +#define _sdma_4_4_0_OFFSET_HEADER + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define regSDMA0_UCODE_ADDR 0x0000 +#define regSDMA0_UCODE_ADDR_BASE_IDX 0 +#define regSDMA0_UCODE_DATA 0x0001 +#define regSDMA0_UCODE_DATA_BASE_IDX 0 +#define regSDMA0_VF_ENABLE 0x000a +#define regSDMA0_VF_ENABLE_BASE_IDX 0 +#define regSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define regSDMA0_POWER_CNTL 0x001a +#define regSDMA0_POWER_CNTL_BASE_IDX 0 +#define regSDMA0_CLK_CTRL 0x001b +#define regSDMA0_CLK_CTRL_BASE_IDX 0 +#define regSDMA0_CNTL 0x001c +#define regSDMA0_CNTL_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS 0x001d +#define regSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG 0x001e +#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA0_RB_RPTR_FETCH 0x0022 +#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA0_IB_OFFSET_FETCH 0x0023 +#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA0_PROGRAM 0x0024 +#define regSDMA0_PROGRAM_BASE_IDX 0 +#define regSDMA0_STATUS_REG 0x0025 +#define regSDMA0_STATUS_REG_BASE_IDX 0 +#define regSDMA0_STATUS1_REG 0x0026 +#define regSDMA0_STATUS1_REG_BASE_IDX 0 +#define regSDMA0_RD_BURST_CNTL 0x0027 +#define regSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define regSDMA0_HBM_PAGE_CONFIG 0x0028 +#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA0_UCODE_CHECKSUM 0x0029 +#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA0_F32_CNTL 0x002a +#define regSDMA0_F32_CNTL_BASE_IDX 0 +#define regSDMA0_FREEZE 0x002b +#define regSDMA0_FREEZE_BASE_IDX 0 +#define regSDMA0_PHASE0_QUANTUM 0x002c +#define regSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define regSDMA0_PHASE1_QUANTUM 0x002d +#define regSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define regSDMA_POWER_GATING 0x002e +#define regSDMA_POWER_GATING_BASE_IDX 0 +#define regSDMA_PGFSM_CONFIG 0x002f +#define regSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define regSDMA_PGFSM_WRITE 0x0030 +#define regSDMA_PGFSM_WRITE_BASE_IDX 0 +#define regSDMA_PGFSM_READ 0x0031 +#define regSDMA_PGFSM_READ_BASE_IDX 0 +#define regCC_SDMA0_EDC_CONFIG 0x0032 +#define regCC_SDMA0_EDC_CONFIG_BASE_IDX 0 +#define regSDMA0_BA_THRESHOLD 0x0033 +#define regSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA0_ID 0x0034 +#define regSDMA0_ID_BASE_IDX 0 +#define regSDMA0_VERSION 0x0035 +#define regSDMA0_VERSION_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER 0x0036 +#define regSDMA0_EDC_COUNTER_BASE_IDX 0 +#define regSDMA0_EDC_COUNTER2 0x0037 +#define regSDMA0_EDC_COUNTER2_BASE_IDX 0 +#define regSDMA0_STATUS2_REG 0x0038 +#define regSDMA0_STATUS2_REG_BASE_IDX 0 +#define regSDMA0_ATOMIC_CNTL 0x0039 +#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_LO 0x003a +#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA0_ATOMIC_PREOP_HI 0x003b +#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA0_UTCL1_CNTL 0x003c +#define regSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA0_UTCL1_WATERMK 0x003d +#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_STATUS 0x003e +#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_STATUS 0x003f +#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA0_UTCL1_INV0 0x0040 +#define regSDMA0_UTCL1_INV0_BASE_IDX 0 +#define regSDMA0_UTCL1_INV1 0x0041 +#define regSDMA0_UTCL1_INV1_BASE_IDX 0 +#define regSDMA0_UTCL1_INV2 0x0042 +#define regSDMA0_UTCL1_INV2_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK0 0x0043 +#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_RD_XNACK1 0x0044 +#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK0 0x0045 +#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA0_UTCL1_WR_XNACK1 0x0046 +#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA0_UTCL1_TIMEOUT 0x0047 +#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA0_UTCL1_PAGE 0x0048 +#define regSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA0_POWER_CNTL_IDLE 0x0049 +#define regSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define regSDMA0_RELAX_ORDERING_LUT 0x004a +#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA0_CHICKEN_BITS_2 0x004b +#define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA0_STATUS3_REG 0x004c +#define regSDMA0_STATUS3_REG_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_LO 0x004d +#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PHYSICAL_ADDR_HI 0x004e +#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_PHASE2_QUANTUM 0x004f +#define regSDMA0_PHASE2_QUANTUM_BASE_IDX 0 +#define regSDMA0_ERROR_LOG 0x0050 +#define regSDMA0_ERROR_LOG_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG0 0x0051 +#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG1 0x0052 +#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG2 0x0053 +#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_PUB_DUMMY_REG3 0x0054 +#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA0_F32_COUNTER 0x0055 +#define regSDMA0_F32_COUNTER_BASE_IDX 0 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x0057 +#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x0058 +#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059 +#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regSDMA0_PERFCNT_MISC_CNTL 0x005a +#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x005b +#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x005c +#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regSDMA0_CRD_CNTL 0x005d +#define regSDMA0_CRD_CNTL_BASE_IDX 0 +#define regSDMA0_ULV_CNTL 0x005f +#define regSDMA0_ULV_CNTL_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA0_STATUS4_REG 0x0063 +#define regSDMA0_STATUS4_REG_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_DATA 0x0064 +#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA0_SCRATCH_RAM_ADDR 0x0065 +#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA0_CE_CTRL 0x0066 +#define regSDMA0_CE_CTRL_BASE_IDX 0 +#define regSDMA0_RAS_STATUS 0x0067 +#define regSDMA0_RAS_STATUS_BASE_IDX 0 +#define regSDMA0_CLK_STATUS 0x0068 +#define regSDMA0_CLK_STATUS_BASE_IDX 0 +#define regSDMA0_GFX_RB_CNTL 0x0080 +#define regSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_RB_BASE 0x0081 +#define regSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define regSDMA0_GFX_RB_BASE_HI 0x0082 +#define regSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_GFX_RB_RPTR 0x0083 +#define regSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define regSDMA0_GFX_RB_RPTR_HI 0x0084 +#define regSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_GFX_RB_WPTR 0x0085 +#define regSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define regSDMA0_GFX_RB_WPTR_HI 0x0086 +#define regSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define regSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define regSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define regSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_GFX_IB_CNTL 0x008a +#define regSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_IB_RPTR 0x008b +#define regSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define regSDMA0_GFX_IB_OFFSET 0x008c +#define regSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_GFX_IB_BASE_LO 0x008d +#define regSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_GFX_IB_BASE_HI 0x008e +#define regSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_GFX_IB_SIZE 0x008f +#define regSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define regSDMA0_GFX_SKIP_CNTL 0x0090 +#define regSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define regSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_GFX_DOORBELL 0x0092 +#define regSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define regSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define regSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_STATUS 0x00a8 +#define regSDMA0_GFX_STATUS_BASE_IDX 0 +#define regSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define regSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_GFX_WATERMARK 0x00aa +#define regSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define regSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define regSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define regSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define regSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define regSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_GFX_PREEMPT 0x00b0 +#define regSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define regSDMA0_GFX_DUMMY_REG 0x00b1 +#define regSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define regSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define regSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define regSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define regSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define regSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define regSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define regSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define regSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define regSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define regSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define regSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA9 0x00c9 +#define regSDMA0_GFX_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_DATA10 0x00ca +#define regSDMA0_GFX_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_GFX_MIDCMD_CNTL 0x00cb +#define regSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_RB_CNTL 0x00d8 +#define regSDMA0_PAGE_RB_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_RB_BASE 0x00d9 +#define regSDMA0_PAGE_RB_BASE_BASE_IDX 0 +#define regSDMA0_PAGE_RB_BASE_HI 0x00da +#define regSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_PAGE_RB_RPTR 0x00db +#define regSDMA0_PAGE_RB_RPTR_BASE_IDX 0 +#define regSDMA0_PAGE_RB_RPTR_HI 0x00dc +#define regSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_PAGE_RB_WPTR 0x00dd +#define regSDMA0_PAGE_RB_WPTR_BASE_IDX 0 +#define regSDMA0_PAGE_RB_WPTR_HI 0x00de +#define regSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define regSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define regSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PAGE_IB_CNTL 0x00e2 +#define regSDMA0_PAGE_IB_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_IB_RPTR 0x00e3 +#define regSDMA0_PAGE_IB_RPTR_BASE_IDX 0 +#define regSDMA0_PAGE_IB_OFFSET 0x00e4 +#define regSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_PAGE_IB_BASE_LO 0x00e5 +#define regSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_PAGE_IB_BASE_HI 0x00e6 +#define regSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_PAGE_IB_SIZE 0x00e7 +#define regSDMA0_PAGE_IB_SIZE_BASE_IDX 0 +#define regSDMA0_PAGE_SKIP_CNTL 0x00e8 +#define regSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_CONTEXT_STATUS 0x00e9 +#define regSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_PAGE_DOORBELL 0x00ea +#define regSDMA0_PAGE_DOORBELL_BASE_IDX 0 +#define regSDMA0_PAGE_STATUS 0x0100 +#define regSDMA0_PAGE_STATUS_BASE_IDX 0 +#define regSDMA0_PAGE_DOORBELL_LOG 0x0101 +#define regSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_PAGE_WATERMARK 0x0102 +#define regSDMA0_PAGE_WATERMARK_BASE_IDX 0 +#define regSDMA0_PAGE_DOORBELL_OFFSET 0x0103 +#define regSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_PAGE_CSA_ADDR_LO 0x0104 +#define regSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PAGE_CSA_ADDR_HI 0x0105 +#define regSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_PAGE_IB_SUB_REMAIN 0x0107 +#define regSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_PAGE_PREEMPT 0x0108 +#define regSDMA0_PAGE_PREEMPT_BASE_IDX 0 +#define regSDMA0_PAGE_DUMMY_REG 0x0109 +#define regSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_PAGE_RB_AQL_CNTL 0x010c +#define regSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d +#define regSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA0 0x0118 +#define regSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA1 0x0119 +#define regSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA2 0x011a +#define regSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA3 0x011b +#define regSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA4 0x011c +#define regSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA5 0x011d +#define regSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA6 0x011e +#define regSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA7 0x011f +#define regSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA8 0x0120 +#define regSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA9 0x0121 +#define regSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_DATA10 0x0122 +#define regSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_PAGE_MIDCMD_CNTL 0x0123 +#define regSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_RB_CNTL 0x0130 +#define regSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_RB_BASE 0x0131 +#define regSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC0_RB_BASE_HI 0x0132 +#define regSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC0_RB_RPTR 0x0133 +#define regSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC0_RB_RPTR_HI 0x0134 +#define regSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC0_RB_WPTR 0x0135 +#define regSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC0_RB_WPTR_HI 0x0136 +#define regSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define regSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define regSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC0_IB_CNTL 0x013a +#define regSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_IB_RPTR 0x013b +#define regSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC0_IB_OFFSET 0x013c +#define regSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC0_IB_BASE_LO 0x013d +#define regSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC0_IB_BASE_HI 0x013e +#define regSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC0_IB_SIZE 0x013f +#define regSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC0_SKIP_CNTL 0x0140 +#define regSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_CONTEXT_STATUS 0x0141 +#define regSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC0_DOORBELL 0x0142 +#define regSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC0_STATUS 0x0158 +#define regSDMA0_RLC0_STATUS_BASE_IDX 0 +#define regSDMA0_RLC0_DOORBELL_LOG 0x0159 +#define regSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC0_WATERMARK 0x015a +#define regSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC0_DOORBELL_OFFSET 0x015b +#define regSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC0_CSA_ADDR_LO 0x015c +#define regSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC0_CSA_ADDR_HI 0x015d +#define regSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC0_IB_SUB_REMAIN 0x015f +#define regSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC0_PREEMPT 0x0160 +#define regSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC0_DUMMY_REG 0x0161 +#define regSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC0_RB_AQL_CNTL 0x0164 +#define regSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 +#define regSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA0 0x0170 +#define regSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA1 0x0171 +#define regSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA2 0x0172 +#define regSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA3 0x0173 +#define regSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA4 0x0174 +#define regSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA5 0x0175 +#define regSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA6 0x0176 +#define regSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA7 0x0177 +#define regSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA8 0x0178 +#define regSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA9 0x0179 +#define regSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_DATA10 0x017a +#define regSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC0_MIDCMD_CNTL 0x017b +#define regSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_RB_CNTL 0x0188 +#define regSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_RB_BASE 0x0189 +#define regSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC1_RB_BASE_HI 0x018a +#define regSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC1_RB_RPTR 0x018b +#define regSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC1_RB_RPTR_HI 0x018c +#define regSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC1_RB_WPTR 0x018d +#define regSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC1_RB_WPTR_HI 0x018e +#define regSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define regSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define regSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC1_IB_CNTL 0x0192 +#define regSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_IB_RPTR 0x0193 +#define regSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC1_IB_OFFSET 0x0194 +#define regSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC1_IB_BASE_LO 0x0195 +#define regSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC1_IB_BASE_HI 0x0196 +#define regSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC1_IB_SIZE 0x0197 +#define regSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC1_SKIP_CNTL 0x0198 +#define regSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_CONTEXT_STATUS 0x0199 +#define regSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC1_DOORBELL 0x019a +#define regSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC1_STATUS 0x01b0 +#define regSDMA0_RLC1_STATUS_BASE_IDX 0 +#define regSDMA0_RLC1_DOORBELL_LOG 0x01b1 +#define regSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC1_WATERMARK 0x01b2 +#define regSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 +#define regSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC1_CSA_ADDR_LO 0x01b4 +#define regSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC1_CSA_ADDR_HI 0x01b5 +#define regSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 +#define regSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC1_PREEMPT 0x01b8 +#define regSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC1_DUMMY_REG 0x01b9 +#define regSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC1_RB_AQL_CNTL 0x01bc +#define regSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd +#define regSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA0 0x01c8 +#define regSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA1 0x01c9 +#define regSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA2 0x01ca +#define regSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA3 0x01cb +#define regSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA4 0x01cc +#define regSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA5 0x01cd +#define regSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA6 0x01ce +#define regSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA7 0x01cf +#define regSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA8 0x01d0 +#define regSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA9 0x01d1 +#define regSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_DATA10 0x01d2 +#define regSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC1_MIDCMD_CNTL 0x01d3 +#define regSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_RB_CNTL 0x01e0 +#define regSDMA0_RLC2_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_RB_BASE 0x01e1 +#define regSDMA0_RLC2_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC2_RB_BASE_HI 0x01e2 +#define regSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC2_RB_RPTR 0x01e3 +#define regSDMA0_RLC2_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC2_RB_RPTR_HI 0x01e4 +#define regSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC2_RB_WPTR 0x01e5 +#define regSDMA0_RLC2_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC2_RB_WPTR_HI 0x01e6 +#define regSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define regSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define regSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC2_IB_CNTL 0x01ea +#define regSDMA0_RLC2_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_IB_RPTR 0x01eb +#define regSDMA0_RLC2_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC2_IB_OFFSET 0x01ec +#define regSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC2_IB_BASE_LO 0x01ed +#define regSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC2_IB_BASE_HI 0x01ee +#define regSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC2_IB_SIZE 0x01ef +#define regSDMA0_RLC2_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC2_SKIP_CNTL 0x01f0 +#define regSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_CONTEXT_STATUS 0x01f1 +#define regSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC2_DOORBELL 0x01f2 +#define regSDMA0_RLC2_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC2_STATUS 0x0208 +#define regSDMA0_RLC2_STATUS_BASE_IDX 0 +#define regSDMA0_RLC2_DOORBELL_LOG 0x0209 +#define regSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC2_WATERMARK 0x020a +#define regSDMA0_RLC2_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC2_DOORBELL_OFFSET 0x020b +#define regSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC2_CSA_ADDR_LO 0x020c +#define regSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC2_CSA_ADDR_HI 0x020d +#define regSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC2_IB_SUB_REMAIN 0x020f +#define regSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC2_PREEMPT 0x0210 +#define regSDMA0_RLC2_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC2_DUMMY_REG 0x0211 +#define regSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC2_RB_AQL_CNTL 0x0214 +#define regSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 +#define regSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA0 0x0220 +#define regSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA1 0x0221 +#define regSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA2 0x0222 +#define regSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA3 0x0223 +#define regSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA4 0x0224 +#define regSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA5 0x0225 +#define regSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA6 0x0226 +#define regSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA7 0x0227 +#define regSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA8 0x0228 +#define regSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA9 0x0229 +#define regSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_DATA10 0x022a +#define regSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC2_MIDCMD_CNTL 0x022b +#define regSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_RB_CNTL 0x0238 +#define regSDMA0_RLC3_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_RB_BASE 0x0239 +#define regSDMA0_RLC3_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC3_RB_BASE_HI 0x023a +#define regSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC3_RB_RPTR 0x023b +#define regSDMA0_RLC3_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC3_RB_RPTR_HI 0x023c +#define regSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC3_RB_WPTR 0x023d +#define regSDMA0_RLC3_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC3_RB_WPTR_HI 0x023e +#define regSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define regSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define regSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC3_IB_CNTL 0x0242 +#define regSDMA0_RLC3_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_IB_RPTR 0x0243 +#define regSDMA0_RLC3_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC3_IB_OFFSET 0x0244 +#define regSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC3_IB_BASE_LO 0x0245 +#define regSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC3_IB_BASE_HI 0x0246 +#define regSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC3_IB_SIZE 0x0247 +#define regSDMA0_RLC3_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC3_SKIP_CNTL 0x0248 +#define regSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_CONTEXT_STATUS 0x0249 +#define regSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC3_DOORBELL 0x024a +#define regSDMA0_RLC3_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC3_STATUS 0x0260 +#define regSDMA0_RLC3_STATUS_BASE_IDX 0 +#define regSDMA0_RLC3_DOORBELL_LOG 0x0261 +#define regSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC3_WATERMARK 0x0262 +#define regSDMA0_RLC3_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC3_DOORBELL_OFFSET 0x0263 +#define regSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC3_CSA_ADDR_LO 0x0264 +#define regSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC3_CSA_ADDR_HI 0x0265 +#define regSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC3_IB_SUB_REMAIN 0x0267 +#define regSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC3_PREEMPT 0x0268 +#define regSDMA0_RLC3_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC3_DUMMY_REG 0x0269 +#define regSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC3_RB_AQL_CNTL 0x026c +#define regSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d +#define regSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA0 0x0278 +#define regSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA1 0x0279 +#define regSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA2 0x027a +#define regSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA3 0x027b +#define regSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA4 0x027c +#define regSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA5 0x027d +#define regSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA6 0x027e +#define regSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA7 0x027f +#define regSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA8 0x0280 +#define regSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA9 0x0281 +#define regSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_DATA10 0x0282 +#define regSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC3_MIDCMD_CNTL 0x0283 +#define regSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_RB_CNTL 0x0290 +#define regSDMA0_RLC4_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_RB_BASE 0x0291 +#define regSDMA0_RLC4_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC4_RB_BASE_HI 0x0292 +#define regSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC4_RB_RPTR 0x0293 +#define regSDMA0_RLC4_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC4_RB_RPTR_HI 0x0294 +#define regSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC4_RB_WPTR 0x0295 +#define regSDMA0_RLC4_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC4_RB_WPTR_HI 0x0296 +#define regSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define regSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define regSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC4_IB_CNTL 0x029a +#define regSDMA0_RLC4_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_IB_RPTR 0x029b +#define regSDMA0_RLC4_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC4_IB_OFFSET 0x029c +#define regSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC4_IB_BASE_LO 0x029d +#define regSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC4_IB_BASE_HI 0x029e +#define regSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC4_IB_SIZE 0x029f +#define regSDMA0_RLC4_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC4_SKIP_CNTL 0x02a0 +#define regSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_CONTEXT_STATUS 0x02a1 +#define regSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC4_DOORBELL 0x02a2 +#define regSDMA0_RLC4_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC4_STATUS 0x02b8 +#define regSDMA0_RLC4_STATUS_BASE_IDX 0 +#define regSDMA0_RLC4_DOORBELL_LOG 0x02b9 +#define regSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC4_WATERMARK 0x02ba +#define regSDMA0_RLC4_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC4_DOORBELL_OFFSET 0x02bb +#define regSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC4_CSA_ADDR_LO 0x02bc +#define regSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC4_CSA_ADDR_HI 0x02bd +#define regSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC4_IB_SUB_REMAIN 0x02bf +#define regSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC4_PREEMPT 0x02c0 +#define regSDMA0_RLC4_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC4_DUMMY_REG 0x02c1 +#define regSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC4_RB_AQL_CNTL 0x02c4 +#define regSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define regSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA0 0x02d0 +#define regSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA1 0x02d1 +#define regSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA2 0x02d2 +#define regSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA3 0x02d3 +#define regSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA4 0x02d4 +#define regSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA5 0x02d5 +#define regSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA6 0x02d6 +#define regSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA7 0x02d7 +#define regSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA8 0x02d8 +#define regSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA9 0x02d9 +#define regSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_DATA10 0x02da +#define regSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC4_MIDCMD_CNTL 0x02db +#define regSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_RB_CNTL 0x02e8 +#define regSDMA0_RLC5_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_RB_BASE 0x02e9 +#define regSDMA0_RLC5_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC5_RB_BASE_HI 0x02ea +#define regSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC5_RB_RPTR 0x02eb +#define regSDMA0_RLC5_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC5_RB_RPTR_HI 0x02ec +#define regSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC5_RB_WPTR 0x02ed +#define regSDMA0_RLC5_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC5_RB_WPTR_HI 0x02ee +#define regSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define regSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define regSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC5_IB_CNTL 0x02f2 +#define regSDMA0_RLC5_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_IB_RPTR 0x02f3 +#define regSDMA0_RLC5_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC5_IB_OFFSET 0x02f4 +#define regSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC5_IB_BASE_LO 0x02f5 +#define regSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC5_IB_BASE_HI 0x02f6 +#define regSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC5_IB_SIZE 0x02f7 +#define regSDMA0_RLC5_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC5_SKIP_CNTL 0x02f8 +#define regSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_CONTEXT_STATUS 0x02f9 +#define regSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC5_DOORBELL 0x02fa +#define regSDMA0_RLC5_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC5_STATUS 0x0310 +#define regSDMA0_RLC5_STATUS_BASE_IDX 0 +#define regSDMA0_RLC5_DOORBELL_LOG 0x0311 +#define regSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC5_WATERMARK 0x0312 +#define regSDMA0_RLC5_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC5_DOORBELL_OFFSET 0x0313 +#define regSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC5_CSA_ADDR_LO 0x0314 +#define regSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC5_CSA_ADDR_HI 0x0315 +#define regSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC5_IB_SUB_REMAIN 0x0317 +#define regSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC5_PREEMPT 0x0318 +#define regSDMA0_RLC5_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC5_DUMMY_REG 0x0319 +#define regSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC5_RB_AQL_CNTL 0x031c +#define regSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d +#define regSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA0 0x0328 +#define regSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA1 0x0329 +#define regSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA2 0x032a +#define regSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA3 0x032b +#define regSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA4 0x032c +#define regSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA5 0x032d +#define regSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA6 0x032e +#define regSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA7 0x032f +#define regSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA8 0x0330 +#define regSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA9 0x0331 +#define regSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_DATA10 0x0332 +#define regSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC5_MIDCMD_CNTL 0x0333 +#define regSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_RB_CNTL 0x0340 +#define regSDMA0_RLC6_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_RB_BASE 0x0341 +#define regSDMA0_RLC6_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC6_RB_BASE_HI 0x0342 +#define regSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC6_RB_RPTR 0x0343 +#define regSDMA0_RLC6_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC6_RB_RPTR_HI 0x0344 +#define regSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC6_RB_WPTR 0x0345 +#define regSDMA0_RLC6_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC6_RB_WPTR_HI 0x0346 +#define regSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define regSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define regSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC6_IB_CNTL 0x034a +#define regSDMA0_RLC6_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_IB_RPTR 0x034b +#define regSDMA0_RLC6_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC6_IB_OFFSET 0x034c +#define regSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC6_IB_BASE_LO 0x034d +#define regSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC6_IB_BASE_HI 0x034e +#define regSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC6_IB_SIZE 0x034f +#define regSDMA0_RLC6_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC6_SKIP_CNTL 0x0350 +#define regSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_CONTEXT_STATUS 0x0351 +#define regSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC6_DOORBELL 0x0352 +#define regSDMA0_RLC6_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC6_STATUS 0x0368 +#define regSDMA0_RLC6_STATUS_BASE_IDX 0 +#define regSDMA0_RLC6_DOORBELL_LOG 0x0369 +#define regSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC6_WATERMARK 0x036a +#define regSDMA0_RLC6_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC6_DOORBELL_OFFSET 0x036b +#define regSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC6_CSA_ADDR_LO 0x036c +#define regSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC6_CSA_ADDR_HI 0x036d +#define regSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC6_IB_SUB_REMAIN 0x036f +#define regSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC6_PREEMPT 0x0370 +#define regSDMA0_RLC6_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC6_DUMMY_REG 0x0371 +#define regSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC6_RB_AQL_CNTL 0x0374 +#define regSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 +#define regSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA0 0x0380 +#define regSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA1 0x0381 +#define regSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA2 0x0382 +#define regSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA3 0x0383 +#define regSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA4 0x0384 +#define regSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA5 0x0385 +#define regSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA6 0x0386 +#define regSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA7 0x0387 +#define regSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA8 0x0388 +#define regSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA9 0x0389 +#define regSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_DATA10 0x038a +#define regSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC6_MIDCMD_CNTL 0x038b +#define regSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_RB_CNTL 0x0398 +#define regSDMA0_RLC7_RB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_RB_BASE 0x0399 +#define regSDMA0_RLC7_RB_BASE_BASE_IDX 0 +#define regSDMA0_RLC7_RB_BASE_HI 0x039a +#define regSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC7_RB_RPTR 0x039b +#define regSDMA0_RLC7_RB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC7_RB_RPTR_HI 0x039c +#define regSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC7_RB_WPTR 0x039d +#define regSDMA0_RLC7_RB_WPTR_BASE_IDX 0 +#define regSDMA0_RLC7_RB_WPTR_HI 0x039e +#define regSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define regSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define regSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC7_IB_CNTL 0x03a2 +#define regSDMA0_RLC7_IB_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_IB_RPTR 0x03a3 +#define regSDMA0_RLC7_IB_RPTR_BASE_IDX 0 +#define regSDMA0_RLC7_IB_OFFSET 0x03a4 +#define regSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC7_IB_BASE_LO 0x03a5 +#define regSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_RLC7_IB_BASE_HI 0x03a6 +#define regSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_RLC7_IB_SIZE 0x03a7 +#define regSDMA0_RLC7_IB_SIZE_BASE_IDX 0 +#define regSDMA0_RLC7_SKIP_CNTL 0x03a8 +#define regSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_CONTEXT_STATUS 0x03a9 +#define regSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_RLC7_DOORBELL 0x03aa +#define regSDMA0_RLC7_DOORBELL_BASE_IDX 0 +#define regSDMA0_RLC7_STATUS 0x03c0 +#define regSDMA0_RLC7_STATUS_BASE_IDX 0 +#define regSDMA0_RLC7_DOORBELL_LOG 0x03c1 +#define regSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_RLC7_WATERMARK 0x03c2 +#define regSDMA0_RLC7_WATERMARK_BASE_IDX 0 +#define regSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 +#define regSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_RLC7_CSA_ADDR_LO 0x03c4 +#define regSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC7_CSA_ADDR_HI 0x03c5 +#define regSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 +#define regSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_RLC7_PREEMPT 0x03c8 +#define regSDMA0_RLC7_PREEMPT_BASE_IDX 0 +#define regSDMA0_RLC7_DUMMY_REG 0x03c9 +#define regSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_RLC7_RB_AQL_CNTL 0x03cc +#define regSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd +#define regSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA0 0x03d8 +#define regSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA1 0x03d9 +#define regSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA2 0x03da +#define regSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA3 0x03db +#define regSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA4 0x03dc +#define regSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA5 0x03dd +#define regSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA6 0x03de +#define regSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA7 0x03df +#define regSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA8 0x03e0 +#define regSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA9 0x03e1 +#define regSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_DATA10 0x03e2 +#define regSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_RLC7_MIDCMD_CNTL 0x03e3 +#define regSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: sdma0_sdma1dec +// base address: 0x6180 +#define regSDMA1_UCODE_ADDR 0x0600 +#define regSDMA1_UCODE_ADDR_BASE_IDX 0 +#define regSDMA1_UCODE_DATA 0x0601 +#define regSDMA1_UCODE_DATA_BASE_IDX 0 +#define regSDMA1_VF_ENABLE 0x060a +#define regSDMA1_VF_ENABLE_BASE_IDX 0 +#define regSDMA1_CONTEXT_GROUP_BOUNDARY 0x0619 +#define regSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define regSDMA1_POWER_CNTL 0x061a +#define regSDMA1_POWER_CNTL_BASE_IDX 0 +#define regSDMA1_CLK_CTRL 0x061b +#define regSDMA1_CLK_CTRL_BASE_IDX 0 +#define regSDMA1_CNTL 0x061c +#define regSDMA1_CNTL_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS 0x061d +#define regSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG 0x061e +#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA1_GB_ADDR_CONFIG_READ 0x061f +#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH_HI 0x0620 +#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0621 +#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA1_RB_RPTR_FETCH 0x0622 +#define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA1_IB_OFFSET_FETCH 0x0623 +#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA1_PROGRAM 0x0624 +#define regSDMA1_PROGRAM_BASE_IDX 0 +#define regSDMA1_STATUS_REG 0x0625 +#define regSDMA1_STATUS_REG_BASE_IDX 0 +#define regSDMA1_STATUS1_REG 0x0626 +#define regSDMA1_STATUS1_REG_BASE_IDX 0 +#define regSDMA1_RD_BURST_CNTL 0x0627 +#define regSDMA1_RD_BURST_CNTL_BASE_IDX 0 +#define regSDMA1_HBM_PAGE_CONFIG 0x0628 +#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA1_UCODE_CHECKSUM 0x0629 +#define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA1_F32_CNTL 0x062a +#define regSDMA1_F32_CNTL_BASE_IDX 0 +#define regSDMA1_FREEZE 0x062b +#define regSDMA1_FREEZE_BASE_IDX 0 +#define regSDMA1_PHASE0_QUANTUM 0x062c +#define regSDMA1_PHASE0_QUANTUM_BASE_IDX 0 +#define regSDMA1_PHASE1_QUANTUM 0x062d +#define regSDMA1_PHASE1_QUANTUM_BASE_IDX 0 +#define regCC_SDMA1_EDC_CONFIG 0x0632 +#define regCC_SDMA1_EDC_CONFIG_BASE_IDX 0 +#define regSDMA1_BA_THRESHOLD 0x0633 +#define regSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA1_ID 0x0634 +#define regSDMA1_ID_BASE_IDX 0 +#define regSDMA1_VERSION 0x0635 +#define regSDMA1_VERSION_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER 0x0636 +#define regSDMA1_EDC_COUNTER_BASE_IDX 0 +#define regSDMA1_EDC_COUNTER2 0x0637 +#define regSDMA1_EDC_COUNTER2_BASE_IDX 0 +#define regSDMA1_STATUS2_REG 0x0638 +#define regSDMA1_STATUS2_REG_BASE_IDX 0 +#define regSDMA1_ATOMIC_CNTL 0x0639 +#define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_LO 0x063a +#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA1_ATOMIC_PREOP_HI 0x063b +#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA1_UTCL1_CNTL 0x063c +#define regSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA1_UTCL1_WATERMK 0x063d +#define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_STATUS 0x063e +#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_STATUS 0x063f +#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA1_UTCL1_INV0 0x0640 +#define regSDMA1_UTCL1_INV0_BASE_IDX 0 +#define regSDMA1_UTCL1_INV1 0x0641 +#define regSDMA1_UTCL1_INV1_BASE_IDX 0 +#define regSDMA1_UTCL1_INV2 0x0642 +#define regSDMA1_UTCL1_INV2_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK0 0x0643 +#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_RD_XNACK1 0x0644 +#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK0 0x0645 +#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA1_UTCL1_WR_XNACK1 0x0646 +#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA1_UTCL1_TIMEOUT 0x0647 +#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA1_UTCL1_PAGE 0x0648 +#define regSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA1_POWER_CNTL_IDLE 0x0649 +#define regSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 +#define regSDMA1_RELAX_ORDERING_LUT 0x064a +#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA1_CHICKEN_BITS_2 0x064b +#define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA1_STATUS3_REG 0x064c +#define regSDMA1_STATUS3_REG_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_LO 0x064d +#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PHYSICAL_ADDR_HI 0x064e +#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_PHASE2_QUANTUM 0x064f +#define regSDMA1_PHASE2_QUANTUM_BASE_IDX 0 +#define regSDMA1_ERROR_LOG 0x0650 +#define regSDMA1_ERROR_LOG_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG0 0x0651 +#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG1 0x0652 +#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG2 0x0653 +#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_PUB_DUMMY_REG3 0x0654 +#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA1_F32_COUNTER 0x0655 +#define regSDMA1_F32_COUNTER_BASE_IDX 0 +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x0657 +#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x0658 +#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0659 +#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regSDMA1_PERFCNT_MISC_CNTL 0x065a +#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x065b +#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x065c +#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regSDMA1_CRD_CNTL 0x065d +#define regSDMA1_CRD_CNTL_BASE_IDX 0 +#define regSDMA1_ULV_CNTL 0x065f +#define regSDMA1_ULV_CNTL_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 +#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 +#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA1_STATUS4_REG 0x0663 +#define regSDMA1_STATUS4_REG_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_DATA 0x0664 +#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA1_SCRATCH_RAM_ADDR 0x0665 +#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA1_CE_CTRL 0x0666 +#define regSDMA1_CE_CTRL_BASE_IDX 0 +#define regSDMA1_RAS_STATUS 0x0667 +#define regSDMA1_RAS_STATUS_BASE_IDX 0 +#define regSDMA1_CLK_STATUS 0x0668 +#define regSDMA1_CLK_STATUS_BASE_IDX 0 +#define regSDMA1_GFX_RB_CNTL 0x0680 +#define regSDMA1_GFX_RB_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_RB_BASE 0x0681 +#define regSDMA1_GFX_RB_BASE_BASE_IDX 0 +#define regSDMA1_GFX_RB_BASE_HI 0x0682 +#define regSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_GFX_RB_RPTR 0x0683 +#define regSDMA1_GFX_RB_RPTR_BASE_IDX 0 +#define regSDMA1_GFX_RB_RPTR_HI 0x0684 +#define regSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_GFX_RB_WPTR 0x0685 +#define regSDMA1_GFX_RB_WPTR_BASE_IDX 0 +#define regSDMA1_GFX_RB_WPTR_HI 0x0686 +#define regSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687 +#define regSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_RB_RPTR_ADDR_HI 0x0688 +#define regSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_GFX_RB_RPTR_ADDR_LO 0x0689 +#define regSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_GFX_IB_CNTL 0x068a +#define regSDMA1_GFX_IB_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_IB_RPTR 0x068b +#define regSDMA1_GFX_IB_RPTR_BASE_IDX 0 +#define regSDMA1_GFX_IB_OFFSET 0x068c +#define regSDMA1_GFX_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_GFX_IB_BASE_LO 0x068d +#define regSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_GFX_IB_BASE_HI 0x068e +#define regSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_GFX_IB_SIZE 0x068f +#define regSDMA1_GFX_IB_SIZE_BASE_IDX 0 +#define regSDMA1_GFX_SKIP_CNTL 0x0690 +#define regSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_CONTEXT_STATUS 0x0691 +#define regSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_GFX_DOORBELL 0x0692 +#define regSDMA1_GFX_DOORBELL_BASE_IDX 0 +#define regSDMA1_GFX_CONTEXT_CNTL 0x0693 +#define regSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_STATUS 0x06a8 +#define regSDMA1_GFX_STATUS_BASE_IDX 0 +#define regSDMA1_GFX_DOORBELL_LOG 0x06a9 +#define regSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_GFX_WATERMARK 0x06aa +#define regSDMA1_GFX_WATERMARK_BASE_IDX 0 +#define regSDMA1_GFX_DOORBELL_OFFSET 0x06ab +#define regSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_GFX_CSA_ADDR_LO 0x06ac +#define regSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_GFX_CSA_ADDR_HI 0x06ad +#define regSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_GFX_IB_SUB_REMAIN 0x06af +#define regSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_GFX_PREEMPT 0x06b0 +#define regSDMA1_GFX_PREEMPT_BASE_IDX 0 +#define regSDMA1_GFX_DUMMY_REG 0x06b1 +#define regSDMA1_GFX_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x06b2 +#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x06b3 +#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_GFX_RB_AQL_CNTL 0x06b4 +#define regSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_GFX_MINOR_PTR_UPDATE 0x06b5 +#define regSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA0 0x06c0 +#define regSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA1 0x06c1 +#define regSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA2 0x06c2 +#define regSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA3 0x06c3 +#define regSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA4 0x06c4 +#define regSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA5 0x06c5 +#define regSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA6 0x06c6 +#define regSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA7 0x06c7 +#define regSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA8 0x06c8 +#define regSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA9 0x06c9 +#define regSDMA1_GFX_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_DATA10 0x06ca +#define regSDMA1_GFX_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_GFX_MIDCMD_CNTL 0x06cb +#define regSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_RB_CNTL 0x06d8 +#define regSDMA1_PAGE_RB_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_RB_BASE 0x06d9 +#define regSDMA1_PAGE_RB_BASE_BASE_IDX 0 +#define regSDMA1_PAGE_RB_BASE_HI 0x06da +#define regSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_PAGE_RB_RPTR 0x06db +#define regSDMA1_PAGE_RB_RPTR_BASE_IDX 0 +#define regSDMA1_PAGE_RB_RPTR_HI 0x06dc +#define regSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_PAGE_RB_WPTR 0x06dd +#define regSDMA1_PAGE_RB_WPTR_BASE_IDX 0 +#define regSDMA1_PAGE_RB_WPTR_HI 0x06de +#define regSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06df +#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_RB_RPTR_ADDR_HI 0x06e0 +#define regSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_PAGE_RB_RPTR_ADDR_LO 0x06e1 +#define regSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PAGE_IB_CNTL 0x06e2 +#define regSDMA1_PAGE_IB_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_IB_RPTR 0x06e3 +#define regSDMA1_PAGE_IB_RPTR_BASE_IDX 0 +#define regSDMA1_PAGE_IB_OFFSET 0x06e4 +#define regSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_PAGE_IB_BASE_LO 0x06e5 +#define regSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_PAGE_IB_BASE_HI 0x06e6 +#define regSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_PAGE_IB_SIZE 0x06e7 +#define regSDMA1_PAGE_IB_SIZE_BASE_IDX 0 +#define regSDMA1_PAGE_SKIP_CNTL 0x06e8 +#define regSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_CONTEXT_STATUS 0x06e9 +#define regSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_PAGE_DOORBELL 0x06ea +#define regSDMA1_PAGE_DOORBELL_BASE_IDX 0 +#define regSDMA1_PAGE_STATUS 0x0700 +#define regSDMA1_PAGE_STATUS_BASE_IDX 0 +#define regSDMA1_PAGE_DOORBELL_LOG 0x0701 +#define regSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_PAGE_WATERMARK 0x0702 +#define regSDMA1_PAGE_WATERMARK_BASE_IDX 0 +#define regSDMA1_PAGE_DOORBELL_OFFSET 0x0703 +#define regSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_PAGE_CSA_ADDR_LO 0x0704 +#define regSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PAGE_CSA_ADDR_HI 0x0705 +#define regSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_PAGE_IB_SUB_REMAIN 0x0707 +#define regSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_PAGE_PREEMPT 0x0708 +#define regSDMA1_PAGE_PREEMPT_BASE_IDX 0 +#define regSDMA1_PAGE_DUMMY_REG 0x0709 +#define regSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x070a +#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x070b +#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_PAGE_RB_AQL_CNTL 0x070c +#define regSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_PAGE_MINOR_PTR_UPDATE 0x070d +#define regSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA0 0x0718 +#define regSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA1 0x0719 +#define regSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA2 0x071a +#define regSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA3 0x071b +#define regSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA4 0x071c +#define regSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA5 0x071d +#define regSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA6 0x071e +#define regSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA7 0x071f +#define regSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA8 0x0720 +#define regSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA9 0x0721 +#define regSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_DATA10 0x0722 +#define regSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_PAGE_MIDCMD_CNTL 0x0723 +#define regSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_RB_CNTL 0x0730 +#define regSDMA1_RLC0_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_RB_BASE 0x0731 +#define regSDMA1_RLC0_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC0_RB_BASE_HI 0x0732 +#define regSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC0_RB_RPTR 0x0733 +#define regSDMA1_RLC0_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC0_RB_RPTR_HI 0x0734 +#define regSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC0_RB_WPTR 0x0735 +#define regSDMA1_RLC0_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC0_RB_WPTR_HI 0x0736 +#define regSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0737 +#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0738 +#define regSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0739 +#define regSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC0_IB_CNTL 0x073a +#define regSDMA1_RLC0_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_IB_RPTR 0x073b +#define regSDMA1_RLC0_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC0_IB_OFFSET 0x073c +#define regSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC0_IB_BASE_LO 0x073d +#define regSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC0_IB_BASE_HI 0x073e +#define regSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC0_IB_SIZE 0x073f +#define regSDMA1_RLC0_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC0_SKIP_CNTL 0x0740 +#define regSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_CONTEXT_STATUS 0x0741 +#define regSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC0_DOORBELL 0x0742 +#define regSDMA1_RLC0_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC0_STATUS 0x0758 +#define regSDMA1_RLC0_STATUS_BASE_IDX 0 +#define regSDMA1_RLC0_DOORBELL_LOG 0x0759 +#define regSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC0_WATERMARK 0x075a +#define regSDMA1_RLC0_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC0_DOORBELL_OFFSET 0x075b +#define regSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC0_CSA_ADDR_LO 0x075c +#define regSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC0_CSA_ADDR_HI 0x075d +#define regSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC0_IB_SUB_REMAIN 0x075f +#define regSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC0_PREEMPT 0x0760 +#define regSDMA1_RLC0_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC0_DUMMY_REG 0x0761 +#define regSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0762 +#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0763 +#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC0_RB_AQL_CNTL 0x0764 +#define regSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC0_MINOR_PTR_UPDATE 0x0765 +#define regSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA0 0x0770 +#define regSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA1 0x0771 +#define regSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA2 0x0772 +#define regSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA3 0x0773 +#define regSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA4 0x0774 +#define regSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA5 0x0775 +#define regSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA6 0x0776 +#define regSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA7 0x0777 +#define regSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA8 0x0778 +#define regSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA9 0x0779 +#define regSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_DATA10 0x077a +#define regSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC0_MIDCMD_CNTL 0x077b +#define regSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_RB_CNTL 0x0788 +#define regSDMA1_RLC1_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_RB_BASE 0x0789 +#define regSDMA1_RLC1_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC1_RB_BASE_HI 0x078a +#define regSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC1_RB_RPTR 0x078b +#define regSDMA1_RLC1_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC1_RB_RPTR_HI 0x078c +#define regSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC1_RB_WPTR 0x078d +#define regSDMA1_RLC1_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC1_RB_WPTR_HI 0x078e +#define regSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x078f +#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0790 +#define regSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0791 +#define regSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC1_IB_CNTL 0x0792 +#define regSDMA1_RLC1_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_IB_RPTR 0x0793 +#define regSDMA1_RLC1_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC1_IB_OFFSET 0x0794 +#define regSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC1_IB_BASE_LO 0x0795 +#define regSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC1_IB_BASE_HI 0x0796 +#define regSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC1_IB_SIZE 0x0797 +#define regSDMA1_RLC1_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC1_SKIP_CNTL 0x0798 +#define regSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_CONTEXT_STATUS 0x0799 +#define regSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC1_DOORBELL 0x079a +#define regSDMA1_RLC1_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC1_STATUS 0x07b0 +#define regSDMA1_RLC1_STATUS_BASE_IDX 0 +#define regSDMA1_RLC1_DOORBELL_LOG 0x07b1 +#define regSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC1_WATERMARK 0x07b2 +#define regSDMA1_RLC1_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC1_DOORBELL_OFFSET 0x07b3 +#define regSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC1_CSA_ADDR_LO 0x07b4 +#define regSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC1_CSA_ADDR_HI 0x07b5 +#define regSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC1_IB_SUB_REMAIN 0x07b7 +#define regSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC1_PREEMPT 0x07b8 +#define regSDMA1_RLC1_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC1_DUMMY_REG 0x07b9 +#define regSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x07ba +#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x07bb +#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC1_RB_AQL_CNTL 0x07bc +#define regSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC1_MINOR_PTR_UPDATE 0x07bd +#define regSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA0 0x07c8 +#define regSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA1 0x07c9 +#define regSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA2 0x07ca +#define regSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA3 0x07cb +#define regSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA4 0x07cc +#define regSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA5 0x07cd +#define regSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA6 0x07ce +#define regSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA7 0x07cf +#define regSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA8 0x07d0 +#define regSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA9 0x07d1 +#define regSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_DATA10 0x07d2 +#define regSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC1_MIDCMD_CNTL 0x07d3 +#define regSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_RB_CNTL 0x07e0 +#define regSDMA1_RLC2_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_RB_BASE 0x07e1 +#define regSDMA1_RLC2_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC2_RB_BASE_HI 0x07e2 +#define regSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC2_RB_RPTR 0x07e3 +#define regSDMA1_RLC2_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC2_RB_RPTR_HI 0x07e4 +#define regSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC2_RB_WPTR 0x07e5 +#define regSDMA1_RLC2_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC2_RB_WPTR_HI 0x07e6 +#define regSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x07e7 +#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_RB_RPTR_ADDR_HI 0x07e8 +#define regSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC2_RB_RPTR_ADDR_LO 0x07e9 +#define regSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC2_IB_CNTL 0x07ea +#define regSDMA1_RLC2_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_IB_RPTR 0x07eb +#define regSDMA1_RLC2_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC2_IB_OFFSET 0x07ec +#define regSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC2_IB_BASE_LO 0x07ed +#define regSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC2_IB_BASE_HI 0x07ee +#define regSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC2_IB_SIZE 0x07ef +#define regSDMA1_RLC2_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC2_SKIP_CNTL 0x07f0 +#define regSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_CONTEXT_STATUS 0x07f1 +#define regSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC2_DOORBELL 0x07f2 +#define regSDMA1_RLC2_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC2_STATUS 0x0808 +#define regSDMA1_RLC2_STATUS_BASE_IDX 0 +#define regSDMA1_RLC2_DOORBELL_LOG 0x0809 +#define regSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC2_WATERMARK 0x080a +#define regSDMA1_RLC2_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC2_DOORBELL_OFFSET 0x080b +#define regSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC2_CSA_ADDR_LO 0x080c +#define regSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC2_CSA_ADDR_HI 0x080d +#define regSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC2_IB_SUB_REMAIN 0x080f +#define regSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC2_PREEMPT 0x0810 +#define regSDMA1_RLC2_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC2_DUMMY_REG 0x0811 +#define regSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0812 +#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0813 +#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC2_RB_AQL_CNTL 0x0814 +#define regSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC2_MINOR_PTR_UPDATE 0x0815 +#define regSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA0 0x0820 +#define regSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA1 0x0821 +#define regSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA2 0x0822 +#define regSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA3 0x0823 +#define regSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA4 0x0824 +#define regSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA5 0x0825 +#define regSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA6 0x0826 +#define regSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA7 0x0827 +#define regSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA8 0x0828 +#define regSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA9 0x0829 +#define regSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_DATA10 0x082a +#define regSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC2_MIDCMD_CNTL 0x082b +#define regSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_RB_CNTL 0x0838 +#define regSDMA1_RLC3_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_RB_BASE 0x0839 +#define regSDMA1_RLC3_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC3_RB_BASE_HI 0x083a +#define regSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC3_RB_RPTR 0x083b +#define regSDMA1_RLC3_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC3_RB_RPTR_HI 0x083c +#define regSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC3_RB_WPTR 0x083d +#define regSDMA1_RLC3_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC3_RB_WPTR_HI 0x083e +#define regSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x083f +#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0840 +#define regSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0841 +#define regSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC3_IB_CNTL 0x0842 +#define regSDMA1_RLC3_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_IB_RPTR 0x0843 +#define regSDMA1_RLC3_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC3_IB_OFFSET 0x0844 +#define regSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC3_IB_BASE_LO 0x0845 +#define regSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC3_IB_BASE_HI 0x0846 +#define regSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC3_IB_SIZE 0x0847 +#define regSDMA1_RLC3_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC3_SKIP_CNTL 0x0848 +#define regSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_CONTEXT_STATUS 0x0849 +#define regSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC3_DOORBELL 0x084a +#define regSDMA1_RLC3_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC3_STATUS 0x0860 +#define regSDMA1_RLC3_STATUS_BASE_IDX 0 +#define regSDMA1_RLC3_DOORBELL_LOG 0x0861 +#define regSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC3_WATERMARK 0x0862 +#define regSDMA1_RLC3_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC3_DOORBELL_OFFSET 0x0863 +#define regSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC3_CSA_ADDR_LO 0x0864 +#define regSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC3_CSA_ADDR_HI 0x0865 +#define regSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC3_IB_SUB_REMAIN 0x0867 +#define regSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC3_PREEMPT 0x0868 +#define regSDMA1_RLC3_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC3_DUMMY_REG 0x0869 +#define regSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x086a +#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x086b +#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC3_RB_AQL_CNTL 0x086c +#define regSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC3_MINOR_PTR_UPDATE 0x086d +#define regSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA0 0x0878 +#define regSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA1 0x0879 +#define regSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA2 0x087a +#define regSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA3 0x087b +#define regSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA4 0x087c +#define regSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA5 0x087d +#define regSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA6 0x087e +#define regSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA7 0x087f +#define regSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA8 0x0880 +#define regSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA9 0x0881 +#define regSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_DATA10 0x0882 +#define regSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC3_MIDCMD_CNTL 0x0883 +#define regSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_RB_CNTL 0x0890 +#define regSDMA1_RLC4_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_RB_BASE 0x0891 +#define regSDMA1_RLC4_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC4_RB_BASE_HI 0x0892 +#define regSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC4_RB_RPTR 0x0893 +#define regSDMA1_RLC4_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC4_RB_RPTR_HI 0x0894 +#define regSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC4_RB_WPTR 0x0895 +#define regSDMA1_RLC4_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC4_RB_WPTR_HI 0x0896 +#define regSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0897 +#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0898 +#define regSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0899 +#define regSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC4_IB_CNTL 0x089a +#define regSDMA1_RLC4_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_IB_RPTR 0x089b +#define regSDMA1_RLC4_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC4_IB_OFFSET 0x089c +#define regSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC4_IB_BASE_LO 0x089d +#define regSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC4_IB_BASE_HI 0x089e +#define regSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC4_IB_SIZE 0x089f +#define regSDMA1_RLC4_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC4_SKIP_CNTL 0x08a0 +#define regSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_CONTEXT_STATUS 0x08a1 +#define regSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC4_DOORBELL 0x08a2 +#define regSDMA1_RLC4_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC4_STATUS 0x08b8 +#define regSDMA1_RLC4_STATUS_BASE_IDX 0 +#define regSDMA1_RLC4_DOORBELL_LOG 0x08b9 +#define regSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC4_WATERMARK 0x08ba +#define regSDMA1_RLC4_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC4_DOORBELL_OFFSET 0x08bb +#define regSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC4_CSA_ADDR_LO 0x08bc +#define regSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC4_CSA_ADDR_HI 0x08bd +#define regSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC4_IB_SUB_REMAIN 0x08bf +#define regSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC4_PREEMPT 0x08c0 +#define regSDMA1_RLC4_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC4_DUMMY_REG 0x08c1 +#define regSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x08c2 +#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x08c3 +#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC4_RB_AQL_CNTL 0x08c4 +#define regSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC4_MINOR_PTR_UPDATE 0x08c5 +#define regSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA0 0x08d0 +#define regSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA1 0x08d1 +#define regSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA2 0x08d2 +#define regSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA3 0x08d3 +#define regSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA4 0x08d4 +#define regSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA5 0x08d5 +#define regSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA6 0x08d6 +#define regSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA7 0x08d7 +#define regSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA8 0x08d8 +#define regSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA9 0x08d9 +#define regSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_DATA10 0x08da +#define regSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC4_MIDCMD_CNTL 0x08db +#define regSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_RB_CNTL 0x08e8 +#define regSDMA1_RLC5_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_RB_BASE 0x08e9 +#define regSDMA1_RLC5_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC5_RB_BASE_HI 0x08ea +#define regSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC5_RB_RPTR 0x08eb +#define regSDMA1_RLC5_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC5_RB_RPTR_HI 0x08ec +#define regSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC5_RB_WPTR 0x08ed +#define regSDMA1_RLC5_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC5_RB_WPTR_HI 0x08ee +#define regSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x08ef +#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_RB_RPTR_ADDR_HI 0x08f0 +#define regSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC5_RB_RPTR_ADDR_LO 0x08f1 +#define regSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC5_IB_CNTL 0x08f2 +#define regSDMA1_RLC5_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_IB_RPTR 0x08f3 +#define regSDMA1_RLC5_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC5_IB_OFFSET 0x08f4 +#define regSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC5_IB_BASE_LO 0x08f5 +#define regSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC5_IB_BASE_HI 0x08f6 +#define regSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC5_IB_SIZE 0x08f7 +#define regSDMA1_RLC5_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC5_SKIP_CNTL 0x08f8 +#define regSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_CONTEXT_STATUS 0x08f9 +#define regSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC5_DOORBELL 0x08fa +#define regSDMA1_RLC5_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC5_STATUS 0x0910 +#define regSDMA1_RLC5_STATUS_BASE_IDX 0 +#define regSDMA1_RLC5_DOORBELL_LOG 0x0911 +#define regSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC5_WATERMARK 0x0912 +#define regSDMA1_RLC5_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC5_DOORBELL_OFFSET 0x0913 +#define regSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC5_CSA_ADDR_LO 0x0914 +#define regSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC5_CSA_ADDR_HI 0x0915 +#define regSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC5_IB_SUB_REMAIN 0x0917 +#define regSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC5_PREEMPT 0x0918 +#define regSDMA1_RLC5_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC5_DUMMY_REG 0x0919 +#define regSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x091a +#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x091b +#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC5_RB_AQL_CNTL 0x091c +#define regSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC5_MINOR_PTR_UPDATE 0x091d +#define regSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA0 0x0928 +#define regSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA1 0x0929 +#define regSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA2 0x092a +#define regSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA3 0x092b +#define regSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA4 0x092c +#define regSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA5 0x092d +#define regSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA6 0x092e +#define regSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA7 0x092f +#define regSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA8 0x0930 +#define regSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA9 0x0931 +#define regSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_DATA10 0x0932 +#define regSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC5_MIDCMD_CNTL 0x0933 +#define regSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_RB_CNTL 0x0940 +#define regSDMA1_RLC6_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_RB_BASE 0x0941 +#define regSDMA1_RLC6_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC6_RB_BASE_HI 0x0942 +#define regSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC6_RB_RPTR 0x0943 +#define regSDMA1_RLC6_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC6_RB_RPTR_HI 0x0944 +#define regSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC6_RB_WPTR 0x0945 +#define regSDMA1_RLC6_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC6_RB_WPTR_HI 0x0946 +#define regSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0947 +#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0948 +#define regSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0949 +#define regSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC6_IB_CNTL 0x094a +#define regSDMA1_RLC6_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_IB_RPTR 0x094b +#define regSDMA1_RLC6_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC6_IB_OFFSET 0x094c +#define regSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC6_IB_BASE_LO 0x094d +#define regSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC6_IB_BASE_HI 0x094e +#define regSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC6_IB_SIZE 0x094f +#define regSDMA1_RLC6_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC6_SKIP_CNTL 0x0950 +#define regSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_CONTEXT_STATUS 0x0951 +#define regSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC6_DOORBELL 0x0952 +#define regSDMA1_RLC6_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC6_STATUS 0x0968 +#define regSDMA1_RLC6_STATUS_BASE_IDX 0 +#define regSDMA1_RLC6_DOORBELL_LOG 0x0969 +#define regSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC6_WATERMARK 0x096a +#define regSDMA1_RLC6_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC6_DOORBELL_OFFSET 0x096b +#define regSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC6_CSA_ADDR_LO 0x096c +#define regSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC6_CSA_ADDR_HI 0x096d +#define regSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC6_IB_SUB_REMAIN 0x096f +#define regSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC6_PREEMPT 0x0970 +#define regSDMA1_RLC6_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC6_DUMMY_REG 0x0971 +#define regSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0972 +#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0973 +#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC6_RB_AQL_CNTL 0x0974 +#define regSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC6_MINOR_PTR_UPDATE 0x0975 +#define regSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA0 0x0980 +#define regSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA1 0x0981 +#define regSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA2 0x0982 +#define regSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA3 0x0983 +#define regSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA4 0x0984 +#define regSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA5 0x0985 +#define regSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA6 0x0986 +#define regSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA7 0x0987 +#define regSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA8 0x0988 +#define regSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA9 0x0989 +#define regSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_DATA10 0x098a +#define regSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC6_MIDCMD_CNTL 0x098b +#define regSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_RB_CNTL 0x0998 +#define regSDMA1_RLC7_RB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_RB_BASE 0x0999 +#define regSDMA1_RLC7_RB_BASE_BASE_IDX 0 +#define regSDMA1_RLC7_RB_BASE_HI 0x099a +#define regSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC7_RB_RPTR 0x099b +#define regSDMA1_RLC7_RB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC7_RB_RPTR_HI 0x099c +#define regSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC7_RB_WPTR 0x099d +#define regSDMA1_RLC7_RB_WPTR_BASE_IDX 0 +#define regSDMA1_RLC7_RB_WPTR_HI 0x099e +#define regSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x099f +#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_RB_RPTR_ADDR_HI 0x09a0 +#define regSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC7_RB_RPTR_ADDR_LO 0x09a1 +#define regSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC7_IB_CNTL 0x09a2 +#define regSDMA1_RLC7_IB_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_IB_RPTR 0x09a3 +#define regSDMA1_RLC7_IB_RPTR_BASE_IDX 0 +#define regSDMA1_RLC7_IB_OFFSET 0x09a4 +#define regSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC7_IB_BASE_LO 0x09a5 +#define regSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_RLC7_IB_BASE_HI 0x09a6 +#define regSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_RLC7_IB_SIZE 0x09a7 +#define regSDMA1_RLC7_IB_SIZE_BASE_IDX 0 +#define regSDMA1_RLC7_SKIP_CNTL 0x09a8 +#define regSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_CONTEXT_STATUS 0x09a9 +#define regSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_RLC7_DOORBELL 0x09aa +#define regSDMA1_RLC7_DOORBELL_BASE_IDX 0 +#define regSDMA1_RLC7_STATUS 0x09c0 +#define regSDMA1_RLC7_STATUS_BASE_IDX 0 +#define regSDMA1_RLC7_DOORBELL_LOG 0x09c1 +#define regSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_RLC7_WATERMARK 0x09c2 +#define regSDMA1_RLC7_WATERMARK_BASE_IDX 0 +#define regSDMA1_RLC7_DOORBELL_OFFSET 0x09c3 +#define regSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_RLC7_CSA_ADDR_LO 0x09c4 +#define regSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC7_CSA_ADDR_HI 0x09c5 +#define regSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC7_IB_SUB_REMAIN 0x09c7 +#define regSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_RLC7_PREEMPT 0x09c8 +#define regSDMA1_RLC7_PREEMPT_BASE_IDX 0 +#define regSDMA1_RLC7_DUMMY_REG 0x09c9 +#define regSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x09ca +#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x09cb +#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_RLC7_RB_AQL_CNTL 0x09cc +#define regSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_RLC7_MINOR_PTR_UPDATE 0x09cd +#define regSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA0 0x09d8 +#define regSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA1 0x09d9 +#define regSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA2 0x09da +#define regSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA3 0x09db +#define regSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA4 0x09dc +#define regSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA5 0x09dd +#define regSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA6 0x09de +#define regSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA7 0x09df +#define regSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA8 0x09e0 +#define regSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA9 0x09e1 +#define regSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_DATA10 0x09e2 +#define regSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_RLC7_MIDCMD_CNTL 0x09e3 +#define regSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: sdma0_sdma2dec +// base address: 0x78000 +#define regSDMA2_UCODE_ADDR 0x1cda0 +#define regSDMA2_UCODE_ADDR_BASE_IDX 0 +#define regSDMA2_UCODE_DATA 0x1cda1 +#define regSDMA2_UCODE_DATA_BASE_IDX 0 +#define regSDMA2_VF_ENABLE 0x1cdaa +#define regSDMA2_VF_ENABLE_BASE_IDX 0 +#define regSDMA2_CONTEXT_GROUP_BOUNDARY 0x1cdb9 +#define regSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define regSDMA2_POWER_CNTL 0x1cdba +#define regSDMA2_POWER_CNTL_BASE_IDX 0 +#define regSDMA2_CLK_CTRL 0x1cdbb +#define regSDMA2_CLK_CTRL_BASE_IDX 0 +#define regSDMA2_CNTL 0x1cdbc +#define regSDMA2_CNTL_BASE_IDX 0 +#define regSDMA2_CHICKEN_BITS 0x1cdbd +#define regSDMA2_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA2_GB_ADDR_CONFIG 0x1cdbe +#define regSDMA2_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA2_GB_ADDR_CONFIG_READ 0x1cdbf +#define regSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA2_RB_RPTR_FETCH_HI 0x1cdc0 +#define regSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x1cdc1 +#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA2_RB_RPTR_FETCH 0x1cdc2 +#define regSDMA2_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA2_IB_OFFSET_FETCH 0x1cdc3 +#define regSDMA2_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA2_PROGRAM 0x1cdc4 +#define regSDMA2_PROGRAM_BASE_IDX 0 +#define regSDMA2_STATUS_REG 0x1cdc5 +#define regSDMA2_STATUS_REG_BASE_IDX 0 +#define regSDMA2_STATUS1_REG 0x1cdc6 +#define regSDMA2_STATUS1_REG_BASE_IDX 0 +#define regSDMA2_RD_BURST_CNTL 0x1cdc7 +#define regSDMA2_RD_BURST_CNTL_BASE_IDX 0 +#define regSDMA2_HBM_PAGE_CONFIG 0x1cdc8 +#define regSDMA2_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA2_UCODE_CHECKSUM 0x1cdc9 +#define regSDMA2_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA2_F32_CNTL 0x1cdca +#define regSDMA2_F32_CNTL_BASE_IDX 0 +#define regSDMA2_FREEZE 0x1cdcb +#define regSDMA2_FREEZE_BASE_IDX 0 +#define regSDMA2_PHASE0_QUANTUM 0x1cdcc +#define regSDMA2_PHASE0_QUANTUM_BASE_IDX 0 +#define regSDMA2_PHASE1_QUANTUM 0x1cdcd +#define regSDMA2_PHASE1_QUANTUM_BASE_IDX 0 +#define regCC_SDMA2_EDC_CONFIG 0x1cdd2 +#define regCC_SDMA2_EDC_CONFIG_BASE_IDX 0 +#define regSDMA2_BA_THRESHOLD 0x1cdd3 +#define regSDMA2_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA2_ID 0x1cdd4 +#define regSDMA2_ID_BASE_IDX 0 +#define regSDMA2_VERSION 0x1cdd5 +#define regSDMA2_VERSION_BASE_IDX 0 +#define regSDMA2_EDC_COUNTER 0x1cdd6 +#define regSDMA2_EDC_COUNTER_BASE_IDX 0 +#define regSDMA2_EDC_COUNTER2 0x1cdd7 +#define regSDMA2_EDC_COUNTER2_BASE_IDX 0 +#define regSDMA2_STATUS2_REG 0x1cdd8 +#define regSDMA2_STATUS2_REG_BASE_IDX 0 +#define regSDMA2_ATOMIC_CNTL 0x1cdd9 +#define regSDMA2_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA2_ATOMIC_PREOP_LO 0x1cdda +#define regSDMA2_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA2_ATOMIC_PREOP_HI 0x1cddb +#define regSDMA2_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA2_UTCL1_CNTL 0x1cddc +#define regSDMA2_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA2_UTCL1_WATERMK 0x1cddd +#define regSDMA2_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA2_UTCL1_RD_STATUS 0x1cdde +#define regSDMA2_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA2_UTCL1_WR_STATUS 0x1cddf +#define regSDMA2_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA2_UTCL1_INV0 0x1cde0 +#define regSDMA2_UTCL1_INV0_BASE_IDX 0 +#define regSDMA2_UTCL1_INV1 0x1cde1 +#define regSDMA2_UTCL1_INV1_BASE_IDX 0 +#define regSDMA2_UTCL1_INV2 0x1cde2 +#define regSDMA2_UTCL1_INV2_BASE_IDX 0 +#define regSDMA2_UTCL1_RD_XNACK0 0x1cde3 +#define regSDMA2_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA2_UTCL1_RD_XNACK1 0x1cde4 +#define regSDMA2_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA2_UTCL1_WR_XNACK0 0x1cde5 +#define regSDMA2_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA2_UTCL1_WR_XNACK1 0x1cde6 +#define regSDMA2_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA2_UTCL1_TIMEOUT 0x1cde7 +#define regSDMA2_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA2_UTCL1_PAGE 0x1cde8 +#define regSDMA2_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA2_POWER_CNTL_IDLE 0x1cde9 +#define regSDMA2_POWER_CNTL_IDLE_BASE_IDX 0 +#define regSDMA2_RELAX_ORDERING_LUT 0x1cdea +#define regSDMA2_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA2_CHICKEN_BITS_2 0x1cdeb +#define regSDMA2_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA2_STATUS3_REG 0x1cdec +#define regSDMA2_STATUS3_REG_BASE_IDX 0 +#define regSDMA2_PHYSICAL_ADDR_LO 0x1cded +#define regSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_PHYSICAL_ADDR_HI 0x1cdee +#define regSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_PHASE2_QUANTUM 0x1cdef +#define regSDMA2_PHASE2_QUANTUM_BASE_IDX 0 +#define regSDMA2_ERROR_LOG 0x1cdf0 +#define regSDMA2_ERROR_LOG_BASE_IDX 0 +#define regSDMA2_PUB_DUMMY_REG0 0x1cdf1 +#define regSDMA2_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA2_PUB_DUMMY_REG1 0x1cdf2 +#define regSDMA2_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA2_PUB_DUMMY_REG2 0x1cdf3 +#define regSDMA2_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA2_PUB_DUMMY_REG3 0x1cdf4 +#define regSDMA2_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA2_F32_COUNTER 0x1cdf5 +#define regSDMA2_F32_COUNTER_BASE_IDX 0 +#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG 0x1cdf7 +#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG 0x1cdf8 +#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1cdf9 +#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regSDMA2_PERFCNT_MISC_CNTL 0x1cdfa +#define regSDMA2_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regSDMA2_PERFCNT_PERFCOUNTER_LO 0x1cdfb +#define regSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regSDMA2_PERFCNT_PERFCOUNTER_HI 0x1cdfc +#define regSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regSDMA2_CRD_CNTL 0x1cdfd +#define regSDMA2_CRD_CNTL_BASE_IDX 0 +#define regSDMA2_ULV_CNTL 0x1cdff +#define regSDMA2_ULV_CNTL_BASE_IDX 0 +#define regSDMA2_EA_DBIT_ADDR_DATA 0x1ce00 +#define regSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA2_EA_DBIT_ADDR_INDEX 0x1ce01 +#define regSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA2_STATUS4_REG 0x1ce03 +#define regSDMA2_STATUS4_REG_BASE_IDX 0 +#define regSDMA2_SCRATCH_RAM_DATA 0x1ce04 +#define regSDMA2_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA2_SCRATCH_RAM_ADDR 0x1ce05 +#define regSDMA2_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA2_CE_CTRL 0x1ce06 +#define regSDMA2_CE_CTRL_BASE_IDX 0 +#define regSDMA2_RAS_STATUS 0x1ce07 +#define regSDMA2_RAS_STATUS_BASE_IDX 0 +#define regSDMA2_CLK_STATUS 0x1ce08 +#define regSDMA2_CLK_STATUS_BASE_IDX 0 +#define regSDMA2_GFX_RB_CNTL 0x1ce20 +#define regSDMA2_GFX_RB_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_RB_BASE 0x1ce21 +#define regSDMA2_GFX_RB_BASE_BASE_IDX 0 +#define regSDMA2_GFX_RB_BASE_HI 0x1ce22 +#define regSDMA2_GFX_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_GFX_RB_RPTR 0x1ce23 +#define regSDMA2_GFX_RB_RPTR_BASE_IDX 0 +#define regSDMA2_GFX_RB_RPTR_HI 0x1ce24 +#define regSDMA2_GFX_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_GFX_RB_WPTR 0x1ce25 +#define regSDMA2_GFX_RB_WPTR_BASE_IDX 0 +#define regSDMA2_GFX_RB_WPTR_HI 0x1ce26 +#define regSDMA2_GFX_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_GFX_RB_WPTR_POLL_CNTL 0x1ce27 +#define regSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_RB_RPTR_ADDR_HI 0x1ce28 +#define regSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_GFX_RB_RPTR_ADDR_LO 0x1ce29 +#define regSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_GFX_IB_CNTL 0x1ce2a +#define regSDMA2_GFX_IB_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_IB_RPTR 0x1ce2b +#define regSDMA2_GFX_IB_RPTR_BASE_IDX 0 +#define regSDMA2_GFX_IB_OFFSET 0x1ce2c +#define regSDMA2_GFX_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_GFX_IB_BASE_LO 0x1ce2d +#define regSDMA2_GFX_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_GFX_IB_BASE_HI 0x1ce2e +#define regSDMA2_GFX_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_GFX_IB_SIZE 0x1ce2f +#define regSDMA2_GFX_IB_SIZE_BASE_IDX 0 +#define regSDMA2_GFX_SKIP_CNTL 0x1ce30 +#define regSDMA2_GFX_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_CONTEXT_STATUS 0x1ce31 +#define regSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_GFX_DOORBELL 0x1ce32 +#define regSDMA2_GFX_DOORBELL_BASE_IDX 0 +#define regSDMA2_GFX_CONTEXT_CNTL 0x1ce33 +#define regSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_STATUS 0x1ce48 +#define regSDMA2_GFX_STATUS_BASE_IDX 0 +#define regSDMA2_GFX_DOORBELL_LOG 0x1ce49 +#define regSDMA2_GFX_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_GFX_WATERMARK 0x1ce4a +#define regSDMA2_GFX_WATERMARK_BASE_IDX 0 +#define regSDMA2_GFX_DOORBELL_OFFSET 0x1ce4b +#define regSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_GFX_CSA_ADDR_LO 0x1ce4c +#define regSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_GFX_CSA_ADDR_HI 0x1ce4d +#define regSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_GFX_IB_SUB_REMAIN 0x1ce4f +#define regSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_GFX_PREEMPT 0x1ce50 +#define regSDMA2_GFX_PREEMPT_BASE_IDX 0 +#define regSDMA2_GFX_DUMMY_REG 0x1ce51 +#define regSDMA2_GFX_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x1ce52 +#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x1ce53 +#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_GFX_RB_AQL_CNTL 0x1ce54 +#define regSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_GFX_MINOR_PTR_UPDATE 0x1ce55 +#define regSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA0 0x1ce60 +#define regSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA1 0x1ce61 +#define regSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA2 0x1ce62 +#define regSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA3 0x1ce63 +#define regSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA4 0x1ce64 +#define regSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA5 0x1ce65 +#define regSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA6 0x1ce66 +#define regSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA7 0x1ce67 +#define regSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA8 0x1ce68 +#define regSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA9 0x1ce69 +#define regSDMA2_GFX_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_DATA10 0x1ce6a +#define regSDMA2_GFX_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_GFX_MIDCMD_CNTL 0x1ce6b +#define regSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_RB_CNTL 0x1ce78 +#define regSDMA2_PAGE_RB_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_RB_BASE 0x1ce79 +#define regSDMA2_PAGE_RB_BASE_BASE_IDX 0 +#define regSDMA2_PAGE_RB_BASE_HI 0x1ce7a +#define regSDMA2_PAGE_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_PAGE_RB_RPTR 0x1ce7b +#define regSDMA2_PAGE_RB_RPTR_BASE_IDX 0 +#define regSDMA2_PAGE_RB_RPTR_HI 0x1ce7c +#define regSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_PAGE_RB_WPTR 0x1ce7d +#define regSDMA2_PAGE_RB_WPTR_BASE_IDX 0 +#define regSDMA2_PAGE_RB_WPTR_HI 0x1ce7e +#define regSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x1ce7f +#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_RB_RPTR_ADDR_HI 0x1ce80 +#define regSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_PAGE_RB_RPTR_ADDR_LO 0x1ce81 +#define regSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_PAGE_IB_CNTL 0x1ce82 +#define regSDMA2_PAGE_IB_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_IB_RPTR 0x1ce83 +#define regSDMA2_PAGE_IB_RPTR_BASE_IDX 0 +#define regSDMA2_PAGE_IB_OFFSET 0x1ce84 +#define regSDMA2_PAGE_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_PAGE_IB_BASE_LO 0x1ce85 +#define regSDMA2_PAGE_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_PAGE_IB_BASE_HI 0x1ce86 +#define regSDMA2_PAGE_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_PAGE_IB_SIZE 0x1ce87 +#define regSDMA2_PAGE_IB_SIZE_BASE_IDX 0 +#define regSDMA2_PAGE_SKIP_CNTL 0x1ce88 +#define regSDMA2_PAGE_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_CONTEXT_STATUS 0x1ce89 +#define regSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_PAGE_DOORBELL 0x1ce8a +#define regSDMA2_PAGE_DOORBELL_BASE_IDX 0 +#define regSDMA2_PAGE_STATUS 0x1cea0 +#define regSDMA2_PAGE_STATUS_BASE_IDX 0 +#define regSDMA2_PAGE_DOORBELL_LOG 0x1cea1 +#define regSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_PAGE_WATERMARK 0x1cea2 +#define regSDMA2_PAGE_WATERMARK_BASE_IDX 0 +#define regSDMA2_PAGE_DOORBELL_OFFSET 0x1cea3 +#define regSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_PAGE_CSA_ADDR_LO 0x1cea4 +#define regSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_PAGE_CSA_ADDR_HI 0x1cea5 +#define regSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_PAGE_IB_SUB_REMAIN 0x1cea7 +#define regSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_PAGE_PREEMPT 0x1cea8 +#define regSDMA2_PAGE_PREEMPT_BASE_IDX 0 +#define regSDMA2_PAGE_DUMMY_REG 0x1cea9 +#define regSDMA2_PAGE_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x1ceaa +#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x1ceab +#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_PAGE_RB_AQL_CNTL 0x1ceac +#define regSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_PAGE_MINOR_PTR_UPDATE 0x1cead +#define regSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA0 0x1ceb8 +#define regSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA1 0x1ceb9 +#define regSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA2 0x1ceba +#define regSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA3 0x1cebb +#define regSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA4 0x1cebc +#define regSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA5 0x1cebd +#define regSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA6 0x1cebe +#define regSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA7 0x1cebf +#define regSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA8 0x1cec0 +#define regSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA9 0x1cec1 +#define regSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_DATA10 0x1cec2 +#define regSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_PAGE_MIDCMD_CNTL 0x1cec3 +#define regSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_RB_CNTL 0x1ced0 +#define regSDMA2_RLC0_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_RB_BASE 0x1ced1 +#define regSDMA2_RLC0_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC0_RB_BASE_HI 0x1ced2 +#define regSDMA2_RLC0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC0_RB_RPTR 0x1ced3 +#define regSDMA2_RLC0_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC0_RB_RPTR_HI 0x1ced4 +#define regSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC0_RB_WPTR 0x1ced5 +#define regSDMA2_RLC0_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC0_RB_WPTR_HI 0x1ced6 +#define regSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x1ced7 +#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_RB_RPTR_ADDR_HI 0x1ced8 +#define regSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC0_RB_RPTR_ADDR_LO 0x1ced9 +#define regSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC0_IB_CNTL 0x1ceda +#define regSDMA2_RLC0_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_IB_RPTR 0x1cedb +#define regSDMA2_RLC0_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC0_IB_OFFSET 0x1cedc +#define regSDMA2_RLC0_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC0_IB_BASE_LO 0x1cedd +#define regSDMA2_RLC0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC0_IB_BASE_HI 0x1cede +#define regSDMA2_RLC0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC0_IB_SIZE 0x1cedf +#define regSDMA2_RLC0_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC0_SKIP_CNTL 0x1cee0 +#define regSDMA2_RLC0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_CONTEXT_STATUS 0x1cee1 +#define regSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC0_DOORBELL 0x1cee2 +#define regSDMA2_RLC0_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC0_STATUS 0x1cef8 +#define regSDMA2_RLC0_STATUS_BASE_IDX 0 +#define regSDMA2_RLC0_DOORBELL_LOG 0x1cef9 +#define regSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC0_WATERMARK 0x1cefa +#define regSDMA2_RLC0_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC0_DOORBELL_OFFSET 0x1cefb +#define regSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC0_CSA_ADDR_LO 0x1cefc +#define regSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC0_CSA_ADDR_HI 0x1cefd +#define regSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC0_IB_SUB_REMAIN 0x1ceff +#define regSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC0_PREEMPT 0x1cf00 +#define regSDMA2_RLC0_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC0_DUMMY_REG 0x1cf01 +#define regSDMA2_RLC0_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x1cf02 +#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x1cf03 +#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC0_RB_AQL_CNTL 0x1cf04 +#define regSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC0_MINOR_PTR_UPDATE 0x1cf05 +#define regSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA0 0x1cf10 +#define regSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA1 0x1cf11 +#define regSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA2 0x1cf12 +#define regSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA3 0x1cf13 +#define regSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA4 0x1cf14 +#define regSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA5 0x1cf15 +#define regSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA6 0x1cf16 +#define regSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA7 0x1cf17 +#define regSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA8 0x1cf18 +#define regSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA9 0x1cf19 +#define regSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_DATA10 0x1cf1a +#define regSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC0_MIDCMD_CNTL 0x1cf1b +#define regSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_RB_CNTL 0x1cf28 +#define regSDMA2_RLC1_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_RB_BASE 0x1cf29 +#define regSDMA2_RLC1_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC1_RB_BASE_HI 0x1cf2a +#define regSDMA2_RLC1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC1_RB_RPTR 0x1cf2b +#define regSDMA2_RLC1_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC1_RB_RPTR_HI 0x1cf2c +#define regSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC1_RB_WPTR 0x1cf2d +#define regSDMA2_RLC1_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC1_RB_WPTR_HI 0x1cf2e +#define regSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x1cf2f +#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_RB_RPTR_ADDR_HI 0x1cf30 +#define regSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC1_RB_RPTR_ADDR_LO 0x1cf31 +#define regSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC1_IB_CNTL 0x1cf32 +#define regSDMA2_RLC1_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_IB_RPTR 0x1cf33 +#define regSDMA2_RLC1_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC1_IB_OFFSET 0x1cf34 +#define regSDMA2_RLC1_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC1_IB_BASE_LO 0x1cf35 +#define regSDMA2_RLC1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC1_IB_BASE_HI 0x1cf36 +#define regSDMA2_RLC1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC1_IB_SIZE 0x1cf37 +#define regSDMA2_RLC1_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC1_SKIP_CNTL 0x1cf38 +#define regSDMA2_RLC1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_CONTEXT_STATUS 0x1cf39 +#define regSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC1_DOORBELL 0x1cf3a +#define regSDMA2_RLC1_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC1_STATUS 0x1cf50 +#define regSDMA2_RLC1_STATUS_BASE_IDX 0 +#define regSDMA2_RLC1_DOORBELL_LOG 0x1cf51 +#define regSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC1_WATERMARK 0x1cf52 +#define regSDMA2_RLC1_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC1_DOORBELL_OFFSET 0x1cf53 +#define regSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC1_CSA_ADDR_LO 0x1cf54 +#define regSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC1_CSA_ADDR_HI 0x1cf55 +#define regSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC1_IB_SUB_REMAIN 0x1cf57 +#define regSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC1_PREEMPT 0x1cf58 +#define regSDMA2_RLC1_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC1_DUMMY_REG 0x1cf59 +#define regSDMA2_RLC1_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x1cf5a +#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x1cf5b +#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC1_RB_AQL_CNTL 0x1cf5c +#define regSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC1_MINOR_PTR_UPDATE 0x1cf5d +#define regSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA0 0x1cf68 +#define regSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA1 0x1cf69 +#define regSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA2 0x1cf6a +#define regSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA3 0x1cf6b +#define regSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA4 0x1cf6c +#define regSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA5 0x1cf6d +#define regSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA6 0x1cf6e +#define regSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA7 0x1cf6f +#define regSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA8 0x1cf70 +#define regSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA9 0x1cf71 +#define regSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_DATA10 0x1cf72 +#define regSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC1_MIDCMD_CNTL 0x1cf73 +#define regSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_RB_CNTL 0x1cf80 +#define regSDMA2_RLC2_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_RB_BASE 0x1cf81 +#define regSDMA2_RLC2_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC2_RB_BASE_HI 0x1cf82 +#define regSDMA2_RLC2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC2_RB_RPTR 0x1cf83 +#define regSDMA2_RLC2_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC2_RB_RPTR_HI 0x1cf84 +#define regSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC2_RB_WPTR 0x1cf85 +#define regSDMA2_RLC2_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC2_RB_WPTR_HI 0x1cf86 +#define regSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x1cf87 +#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_RB_RPTR_ADDR_HI 0x1cf88 +#define regSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC2_RB_RPTR_ADDR_LO 0x1cf89 +#define regSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC2_IB_CNTL 0x1cf8a +#define regSDMA2_RLC2_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_IB_RPTR 0x1cf8b +#define regSDMA2_RLC2_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC2_IB_OFFSET 0x1cf8c +#define regSDMA2_RLC2_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC2_IB_BASE_LO 0x1cf8d +#define regSDMA2_RLC2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC2_IB_BASE_HI 0x1cf8e +#define regSDMA2_RLC2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC2_IB_SIZE 0x1cf8f +#define regSDMA2_RLC2_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC2_SKIP_CNTL 0x1cf90 +#define regSDMA2_RLC2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_CONTEXT_STATUS 0x1cf91 +#define regSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC2_DOORBELL 0x1cf92 +#define regSDMA2_RLC2_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC2_STATUS 0x1cfa8 +#define regSDMA2_RLC2_STATUS_BASE_IDX 0 +#define regSDMA2_RLC2_DOORBELL_LOG 0x1cfa9 +#define regSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC2_WATERMARK 0x1cfaa +#define regSDMA2_RLC2_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC2_DOORBELL_OFFSET 0x1cfab +#define regSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC2_CSA_ADDR_LO 0x1cfac +#define regSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC2_CSA_ADDR_HI 0x1cfad +#define regSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC2_IB_SUB_REMAIN 0x1cfaf +#define regSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC2_PREEMPT 0x1cfb0 +#define regSDMA2_RLC2_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC2_DUMMY_REG 0x1cfb1 +#define regSDMA2_RLC2_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x1cfb2 +#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x1cfb3 +#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC2_RB_AQL_CNTL 0x1cfb4 +#define regSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC2_MINOR_PTR_UPDATE 0x1cfb5 +#define regSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA0 0x1cfc0 +#define regSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA1 0x1cfc1 +#define regSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA2 0x1cfc2 +#define regSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA3 0x1cfc3 +#define regSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA4 0x1cfc4 +#define regSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA5 0x1cfc5 +#define regSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA6 0x1cfc6 +#define regSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA7 0x1cfc7 +#define regSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA8 0x1cfc8 +#define regSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA9 0x1cfc9 +#define regSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_DATA10 0x1cfca +#define regSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC2_MIDCMD_CNTL 0x1cfcb +#define regSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_RB_CNTL 0x1cfd8 +#define regSDMA2_RLC3_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_RB_BASE 0x1cfd9 +#define regSDMA2_RLC3_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC3_RB_BASE_HI 0x1cfda +#define regSDMA2_RLC3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC3_RB_RPTR 0x1cfdb +#define regSDMA2_RLC3_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC3_RB_RPTR_HI 0x1cfdc +#define regSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC3_RB_WPTR 0x1cfdd +#define regSDMA2_RLC3_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC3_RB_WPTR_HI 0x1cfde +#define regSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x1cfdf +#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_RB_RPTR_ADDR_HI 0x1cfe0 +#define regSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC3_RB_RPTR_ADDR_LO 0x1cfe1 +#define regSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC3_IB_CNTL 0x1cfe2 +#define regSDMA2_RLC3_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_IB_RPTR 0x1cfe3 +#define regSDMA2_RLC3_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC3_IB_OFFSET 0x1cfe4 +#define regSDMA2_RLC3_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC3_IB_BASE_LO 0x1cfe5 +#define regSDMA2_RLC3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC3_IB_BASE_HI 0x1cfe6 +#define regSDMA2_RLC3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC3_IB_SIZE 0x1cfe7 +#define regSDMA2_RLC3_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC3_SKIP_CNTL 0x1cfe8 +#define regSDMA2_RLC3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_CONTEXT_STATUS 0x1cfe9 +#define regSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC3_DOORBELL 0x1cfea +#define regSDMA2_RLC3_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC3_STATUS 0x1d000 +#define regSDMA2_RLC3_STATUS_BASE_IDX 0 +#define regSDMA2_RLC3_DOORBELL_LOG 0x1d001 +#define regSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC3_WATERMARK 0x1d002 +#define regSDMA2_RLC3_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC3_DOORBELL_OFFSET 0x1d003 +#define regSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC3_CSA_ADDR_LO 0x1d004 +#define regSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC3_CSA_ADDR_HI 0x1d005 +#define regSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC3_IB_SUB_REMAIN 0x1d007 +#define regSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC3_PREEMPT 0x1d008 +#define regSDMA2_RLC3_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC3_DUMMY_REG 0x1d009 +#define regSDMA2_RLC3_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d00a +#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d00b +#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC3_RB_AQL_CNTL 0x1d00c +#define regSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC3_MINOR_PTR_UPDATE 0x1d00d +#define regSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA0 0x1d018 +#define regSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA1 0x1d019 +#define regSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA2 0x1d01a +#define regSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA3 0x1d01b +#define regSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA4 0x1d01c +#define regSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA5 0x1d01d +#define regSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA6 0x1d01e +#define regSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA7 0x1d01f +#define regSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA8 0x1d020 +#define regSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA9 0x1d021 +#define regSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_DATA10 0x1d022 +#define regSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC3_MIDCMD_CNTL 0x1d023 +#define regSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_RB_CNTL 0x1d030 +#define regSDMA2_RLC4_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_RB_BASE 0x1d031 +#define regSDMA2_RLC4_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC4_RB_BASE_HI 0x1d032 +#define regSDMA2_RLC4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC4_RB_RPTR 0x1d033 +#define regSDMA2_RLC4_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC4_RB_RPTR_HI 0x1d034 +#define regSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC4_RB_WPTR 0x1d035 +#define regSDMA2_RLC4_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC4_RB_WPTR_HI 0x1d036 +#define regSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x1d037 +#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_RB_RPTR_ADDR_HI 0x1d038 +#define regSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC4_RB_RPTR_ADDR_LO 0x1d039 +#define regSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC4_IB_CNTL 0x1d03a +#define regSDMA2_RLC4_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_IB_RPTR 0x1d03b +#define regSDMA2_RLC4_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC4_IB_OFFSET 0x1d03c +#define regSDMA2_RLC4_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC4_IB_BASE_LO 0x1d03d +#define regSDMA2_RLC4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC4_IB_BASE_HI 0x1d03e +#define regSDMA2_RLC4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC4_IB_SIZE 0x1d03f +#define regSDMA2_RLC4_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC4_SKIP_CNTL 0x1d040 +#define regSDMA2_RLC4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_CONTEXT_STATUS 0x1d041 +#define regSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC4_DOORBELL 0x1d042 +#define regSDMA2_RLC4_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC4_STATUS 0x1d058 +#define regSDMA2_RLC4_STATUS_BASE_IDX 0 +#define regSDMA2_RLC4_DOORBELL_LOG 0x1d059 +#define regSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC4_WATERMARK 0x1d05a +#define regSDMA2_RLC4_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC4_DOORBELL_OFFSET 0x1d05b +#define regSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC4_CSA_ADDR_LO 0x1d05c +#define regSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC4_CSA_ADDR_HI 0x1d05d +#define regSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC4_IB_SUB_REMAIN 0x1d05f +#define regSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC4_PREEMPT 0x1d060 +#define regSDMA2_RLC4_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC4_DUMMY_REG 0x1d061 +#define regSDMA2_RLC4_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d062 +#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d063 +#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC4_RB_AQL_CNTL 0x1d064 +#define regSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC4_MINOR_PTR_UPDATE 0x1d065 +#define regSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA0 0x1d070 +#define regSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA1 0x1d071 +#define regSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA2 0x1d072 +#define regSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA3 0x1d073 +#define regSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA4 0x1d074 +#define regSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA5 0x1d075 +#define regSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA6 0x1d076 +#define regSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA7 0x1d077 +#define regSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA8 0x1d078 +#define regSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA9 0x1d079 +#define regSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_DATA10 0x1d07a +#define regSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC4_MIDCMD_CNTL 0x1d07b +#define regSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_RB_CNTL 0x1d088 +#define regSDMA2_RLC5_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_RB_BASE 0x1d089 +#define regSDMA2_RLC5_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC5_RB_BASE_HI 0x1d08a +#define regSDMA2_RLC5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC5_RB_RPTR 0x1d08b +#define regSDMA2_RLC5_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC5_RB_RPTR_HI 0x1d08c +#define regSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC5_RB_WPTR 0x1d08d +#define regSDMA2_RLC5_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC5_RB_WPTR_HI 0x1d08e +#define regSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x1d08f +#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_RB_RPTR_ADDR_HI 0x1d090 +#define regSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC5_RB_RPTR_ADDR_LO 0x1d091 +#define regSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC5_IB_CNTL 0x1d092 +#define regSDMA2_RLC5_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_IB_RPTR 0x1d093 +#define regSDMA2_RLC5_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC5_IB_OFFSET 0x1d094 +#define regSDMA2_RLC5_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC5_IB_BASE_LO 0x1d095 +#define regSDMA2_RLC5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC5_IB_BASE_HI 0x1d096 +#define regSDMA2_RLC5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC5_IB_SIZE 0x1d097 +#define regSDMA2_RLC5_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC5_SKIP_CNTL 0x1d098 +#define regSDMA2_RLC5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_CONTEXT_STATUS 0x1d099 +#define regSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC5_DOORBELL 0x1d09a +#define regSDMA2_RLC5_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC5_STATUS 0x1d0b0 +#define regSDMA2_RLC5_STATUS_BASE_IDX 0 +#define regSDMA2_RLC5_DOORBELL_LOG 0x1d0b1 +#define regSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC5_WATERMARK 0x1d0b2 +#define regSDMA2_RLC5_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC5_DOORBELL_OFFSET 0x1d0b3 +#define regSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC5_CSA_ADDR_LO 0x1d0b4 +#define regSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC5_CSA_ADDR_HI 0x1d0b5 +#define regSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC5_IB_SUB_REMAIN 0x1d0b7 +#define regSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC5_PREEMPT 0x1d0b8 +#define regSDMA2_RLC5_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC5_DUMMY_REG 0x1d0b9 +#define regSDMA2_RLC5_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d0ba +#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d0bb +#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC5_RB_AQL_CNTL 0x1d0bc +#define regSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC5_MINOR_PTR_UPDATE 0x1d0bd +#define regSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA0 0x1d0c8 +#define regSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA1 0x1d0c9 +#define regSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA2 0x1d0ca +#define regSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA3 0x1d0cb +#define regSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA4 0x1d0cc +#define regSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA5 0x1d0cd +#define regSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA6 0x1d0ce +#define regSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA7 0x1d0cf +#define regSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA8 0x1d0d0 +#define regSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA9 0x1d0d1 +#define regSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_DATA10 0x1d0d2 +#define regSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC5_MIDCMD_CNTL 0x1d0d3 +#define regSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_RB_CNTL 0x1d0e0 +#define regSDMA2_RLC6_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_RB_BASE 0x1d0e1 +#define regSDMA2_RLC6_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC6_RB_BASE_HI 0x1d0e2 +#define regSDMA2_RLC6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC6_RB_RPTR 0x1d0e3 +#define regSDMA2_RLC6_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC6_RB_RPTR_HI 0x1d0e4 +#define regSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC6_RB_WPTR 0x1d0e5 +#define regSDMA2_RLC6_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC6_RB_WPTR_HI 0x1d0e6 +#define regSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x1d0e7 +#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_RB_RPTR_ADDR_HI 0x1d0e8 +#define regSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC6_RB_RPTR_ADDR_LO 0x1d0e9 +#define regSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC6_IB_CNTL 0x1d0ea +#define regSDMA2_RLC6_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_IB_RPTR 0x1d0eb +#define regSDMA2_RLC6_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC6_IB_OFFSET 0x1d0ec +#define regSDMA2_RLC6_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC6_IB_BASE_LO 0x1d0ed +#define regSDMA2_RLC6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC6_IB_BASE_HI 0x1d0ee +#define regSDMA2_RLC6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC6_IB_SIZE 0x1d0ef +#define regSDMA2_RLC6_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC6_SKIP_CNTL 0x1d0f0 +#define regSDMA2_RLC6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_CONTEXT_STATUS 0x1d0f1 +#define regSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC6_DOORBELL 0x1d0f2 +#define regSDMA2_RLC6_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC6_STATUS 0x1d108 +#define regSDMA2_RLC6_STATUS_BASE_IDX 0 +#define regSDMA2_RLC6_DOORBELL_LOG 0x1d109 +#define regSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC6_WATERMARK 0x1d10a +#define regSDMA2_RLC6_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC6_DOORBELL_OFFSET 0x1d10b +#define regSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC6_CSA_ADDR_LO 0x1d10c +#define regSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC6_CSA_ADDR_HI 0x1d10d +#define regSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC6_IB_SUB_REMAIN 0x1d10f +#define regSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC6_PREEMPT 0x1d110 +#define regSDMA2_RLC6_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC6_DUMMY_REG 0x1d111 +#define regSDMA2_RLC6_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d112 +#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d113 +#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC6_RB_AQL_CNTL 0x1d114 +#define regSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC6_MINOR_PTR_UPDATE 0x1d115 +#define regSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA0 0x1d120 +#define regSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA1 0x1d121 +#define regSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA2 0x1d122 +#define regSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA3 0x1d123 +#define regSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA4 0x1d124 +#define regSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA5 0x1d125 +#define regSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA6 0x1d126 +#define regSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA7 0x1d127 +#define regSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA8 0x1d128 +#define regSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA9 0x1d129 +#define regSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_DATA10 0x1d12a +#define regSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC6_MIDCMD_CNTL 0x1d12b +#define regSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_RB_CNTL 0x1d138 +#define regSDMA2_RLC7_RB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_RB_BASE 0x1d139 +#define regSDMA2_RLC7_RB_BASE_BASE_IDX 0 +#define regSDMA2_RLC7_RB_BASE_HI 0x1d13a +#define regSDMA2_RLC7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC7_RB_RPTR 0x1d13b +#define regSDMA2_RLC7_RB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC7_RB_RPTR_HI 0x1d13c +#define regSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC7_RB_WPTR 0x1d13d +#define regSDMA2_RLC7_RB_WPTR_BASE_IDX 0 +#define regSDMA2_RLC7_RB_WPTR_HI 0x1d13e +#define regSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x1d13f +#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_RB_RPTR_ADDR_HI 0x1d140 +#define regSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC7_RB_RPTR_ADDR_LO 0x1d141 +#define regSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC7_IB_CNTL 0x1d142 +#define regSDMA2_RLC7_IB_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_IB_RPTR 0x1d143 +#define regSDMA2_RLC7_IB_RPTR_BASE_IDX 0 +#define regSDMA2_RLC7_IB_OFFSET 0x1d144 +#define regSDMA2_RLC7_IB_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC7_IB_BASE_LO 0x1d145 +#define regSDMA2_RLC7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA2_RLC7_IB_BASE_HI 0x1d146 +#define regSDMA2_RLC7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA2_RLC7_IB_SIZE 0x1d147 +#define regSDMA2_RLC7_IB_SIZE_BASE_IDX 0 +#define regSDMA2_RLC7_SKIP_CNTL 0x1d148 +#define regSDMA2_RLC7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_CONTEXT_STATUS 0x1d149 +#define regSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA2_RLC7_DOORBELL 0x1d14a +#define regSDMA2_RLC7_DOORBELL_BASE_IDX 0 +#define regSDMA2_RLC7_STATUS 0x1d160 +#define regSDMA2_RLC7_STATUS_BASE_IDX 0 +#define regSDMA2_RLC7_DOORBELL_LOG 0x1d161 +#define regSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA2_RLC7_WATERMARK 0x1d162 +#define regSDMA2_RLC7_WATERMARK_BASE_IDX 0 +#define regSDMA2_RLC7_DOORBELL_OFFSET 0x1d163 +#define regSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA2_RLC7_CSA_ADDR_LO 0x1d164 +#define regSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC7_CSA_ADDR_HI 0x1d165 +#define regSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC7_IB_SUB_REMAIN 0x1d167 +#define regSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA2_RLC7_PREEMPT 0x1d168 +#define regSDMA2_RLC7_PREEMPT_BASE_IDX 0 +#define regSDMA2_RLC7_DUMMY_REG 0x1d169 +#define regSDMA2_RLC7_DUMMY_REG_BASE_IDX 0 +#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d16a +#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d16b +#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA2_RLC7_RB_AQL_CNTL 0x1d16c +#define regSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA2_RLC7_MINOR_PTR_UPDATE 0x1d16d +#define regSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA0 0x1d178 +#define regSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA1 0x1d179 +#define regSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA2 0x1d17a +#define regSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA3 0x1d17b +#define regSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA4 0x1d17c +#define regSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA5 0x1d17d +#define regSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA6 0x1d17e +#define regSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA7 0x1d17f +#define regSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA8 0x1d180 +#define regSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA9 0x1d181 +#define regSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_DATA10 0x1d182 +#define regSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA2_RLC7_MIDCMD_CNTL 0x1d183 +#define regSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: sdma0_sdma3dec +// base address: 0x79000 +#define regSDMA3_UCODE_ADDR 0x1d1a0 +#define regSDMA3_UCODE_ADDR_BASE_IDX 0 +#define regSDMA3_UCODE_DATA 0x1d1a1 +#define regSDMA3_UCODE_DATA_BASE_IDX 0 +#define regSDMA3_VF_ENABLE 0x1d1aa +#define regSDMA3_VF_ENABLE_BASE_IDX 0 +#define regSDMA3_CONTEXT_GROUP_BOUNDARY 0x1d1b9 +#define regSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define regSDMA3_POWER_CNTL 0x1d1ba +#define regSDMA3_POWER_CNTL_BASE_IDX 0 +#define regSDMA3_CLK_CTRL 0x1d1bb +#define regSDMA3_CLK_CTRL_BASE_IDX 0 +#define regSDMA3_CNTL 0x1d1bc +#define regSDMA3_CNTL_BASE_IDX 0 +#define regSDMA3_CHICKEN_BITS 0x1d1bd +#define regSDMA3_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA3_GB_ADDR_CONFIG 0x1d1be +#define regSDMA3_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA3_GB_ADDR_CONFIG_READ 0x1d1bf +#define regSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA3_RB_RPTR_FETCH_HI 0x1d1c0 +#define regSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x1d1c1 +#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA3_RB_RPTR_FETCH 0x1d1c2 +#define regSDMA3_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA3_IB_OFFSET_FETCH 0x1d1c3 +#define regSDMA3_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA3_PROGRAM 0x1d1c4 +#define regSDMA3_PROGRAM_BASE_IDX 0 +#define regSDMA3_STATUS_REG 0x1d1c5 +#define regSDMA3_STATUS_REG_BASE_IDX 0 +#define regSDMA3_STATUS1_REG 0x1d1c6 +#define regSDMA3_STATUS1_REG_BASE_IDX 0 +#define regSDMA3_RD_BURST_CNTL 0x1d1c7 +#define regSDMA3_RD_BURST_CNTL_BASE_IDX 0 +#define regSDMA3_HBM_PAGE_CONFIG 0x1d1c8 +#define regSDMA3_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA3_UCODE_CHECKSUM 0x1d1c9 +#define regSDMA3_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA3_F32_CNTL 0x1d1ca +#define regSDMA3_F32_CNTL_BASE_IDX 0 +#define regSDMA3_FREEZE 0x1d1cb +#define regSDMA3_FREEZE_BASE_IDX 0 +#define regSDMA3_PHASE0_QUANTUM 0x1d1cc +#define regSDMA3_PHASE0_QUANTUM_BASE_IDX 0 +#define regSDMA3_PHASE1_QUANTUM 0x1d1cd +#define regSDMA3_PHASE1_QUANTUM_BASE_IDX 0 +#define regCC_SDMA3_EDC_CONFIG 0x1d1d2 +#define regCC_SDMA3_EDC_CONFIG_BASE_IDX 0 +#define regSDMA3_BA_THRESHOLD 0x1d1d3 +#define regSDMA3_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA3_ID 0x1d1d4 +#define regSDMA3_ID_BASE_IDX 0 +#define regSDMA3_VERSION 0x1d1d5 +#define regSDMA3_VERSION_BASE_IDX 0 +#define regSDMA3_EDC_COUNTER 0x1d1d6 +#define regSDMA3_EDC_COUNTER_BASE_IDX 0 +#define regSDMA3_EDC_COUNTER2 0x1d1d7 +#define regSDMA3_EDC_COUNTER2_BASE_IDX 0 +#define regSDMA3_STATUS2_REG 0x1d1d8 +#define regSDMA3_STATUS2_REG_BASE_IDX 0 +#define regSDMA3_ATOMIC_CNTL 0x1d1d9 +#define regSDMA3_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA3_ATOMIC_PREOP_LO 0x1d1da +#define regSDMA3_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA3_ATOMIC_PREOP_HI 0x1d1db +#define regSDMA3_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA3_UTCL1_CNTL 0x1d1dc +#define regSDMA3_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA3_UTCL1_WATERMK 0x1d1dd +#define regSDMA3_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA3_UTCL1_RD_STATUS 0x1d1de +#define regSDMA3_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA3_UTCL1_WR_STATUS 0x1d1df +#define regSDMA3_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA3_UTCL1_INV0 0x1d1e0 +#define regSDMA3_UTCL1_INV0_BASE_IDX 0 +#define regSDMA3_UTCL1_INV1 0x1d1e1 +#define regSDMA3_UTCL1_INV1_BASE_IDX 0 +#define regSDMA3_UTCL1_INV2 0x1d1e2 +#define regSDMA3_UTCL1_INV2_BASE_IDX 0 +#define regSDMA3_UTCL1_RD_XNACK0 0x1d1e3 +#define regSDMA3_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA3_UTCL1_RD_XNACK1 0x1d1e4 +#define regSDMA3_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA3_UTCL1_WR_XNACK0 0x1d1e5 +#define regSDMA3_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA3_UTCL1_WR_XNACK1 0x1d1e6 +#define regSDMA3_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA3_UTCL1_TIMEOUT 0x1d1e7 +#define regSDMA3_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA3_UTCL1_PAGE 0x1d1e8 +#define regSDMA3_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA3_POWER_CNTL_IDLE 0x1d1e9 +#define regSDMA3_POWER_CNTL_IDLE_BASE_IDX 0 +#define regSDMA3_RELAX_ORDERING_LUT 0x1d1ea +#define regSDMA3_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA3_CHICKEN_BITS_2 0x1d1eb +#define regSDMA3_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA3_STATUS3_REG 0x1d1ec +#define regSDMA3_STATUS3_REG_BASE_IDX 0 +#define regSDMA3_PHYSICAL_ADDR_LO 0x1d1ed +#define regSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_PHYSICAL_ADDR_HI 0x1d1ee +#define regSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_PHASE2_QUANTUM 0x1d1ef +#define regSDMA3_PHASE2_QUANTUM_BASE_IDX 0 +#define regSDMA3_ERROR_LOG 0x1d1f0 +#define regSDMA3_ERROR_LOG_BASE_IDX 0 +#define regSDMA3_PUB_DUMMY_REG0 0x1d1f1 +#define regSDMA3_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA3_PUB_DUMMY_REG1 0x1d1f2 +#define regSDMA3_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA3_PUB_DUMMY_REG2 0x1d1f3 +#define regSDMA3_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA3_PUB_DUMMY_REG3 0x1d1f4 +#define regSDMA3_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA3_F32_COUNTER 0x1d1f5 +#define regSDMA3_F32_COUNTER_BASE_IDX 0 +#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG 0x1d1f7 +#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG 0x1d1f8 +#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d1f9 +#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regSDMA3_PERFCNT_MISC_CNTL 0x1d1fa +#define regSDMA3_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regSDMA3_PERFCNT_PERFCOUNTER_LO 0x1d1fb +#define regSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regSDMA3_PERFCNT_PERFCOUNTER_HI 0x1d1fc +#define regSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regSDMA3_CRD_CNTL 0x1d1fd +#define regSDMA3_CRD_CNTL_BASE_IDX 0 +#define regSDMA3_ULV_CNTL 0x1d1ff +#define regSDMA3_ULV_CNTL_BASE_IDX 0 +#define regSDMA3_EA_DBIT_ADDR_DATA 0x1d200 +#define regSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA3_EA_DBIT_ADDR_INDEX 0x1d201 +#define regSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA3_STATUS4_REG 0x1d203 +#define regSDMA3_STATUS4_REG_BASE_IDX 0 +#define regSDMA3_SCRATCH_RAM_DATA 0x1d204 +#define regSDMA3_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA3_SCRATCH_RAM_ADDR 0x1d205 +#define regSDMA3_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA3_CE_CTRL 0x1d206 +#define regSDMA3_CE_CTRL_BASE_IDX 0 +#define regSDMA3_RAS_STATUS 0x1d207 +#define regSDMA3_RAS_STATUS_BASE_IDX 0 +#define regSDMA3_CLK_STATUS 0x1d208 +#define regSDMA3_CLK_STATUS_BASE_IDX 0 +#define regSDMA3_GFX_RB_CNTL 0x1d220 +#define regSDMA3_GFX_RB_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_RB_BASE 0x1d221 +#define regSDMA3_GFX_RB_BASE_BASE_IDX 0 +#define regSDMA3_GFX_RB_BASE_HI 0x1d222 +#define regSDMA3_GFX_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_GFX_RB_RPTR 0x1d223 +#define regSDMA3_GFX_RB_RPTR_BASE_IDX 0 +#define regSDMA3_GFX_RB_RPTR_HI 0x1d224 +#define regSDMA3_GFX_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_GFX_RB_WPTR 0x1d225 +#define regSDMA3_GFX_RB_WPTR_BASE_IDX 0 +#define regSDMA3_GFX_RB_WPTR_HI 0x1d226 +#define regSDMA3_GFX_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_GFX_RB_WPTR_POLL_CNTL 0x1d227 +#define regSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_RB_RPTR_ADDR_HI 0x1d228 +#define regSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_GFX_RB_RPTR_ADDR_LO 0x1d229 +#define regSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_GFX_IB_CNTL 0x1d22a +#define regSDMA3_GFX_IB_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_IB_RPTR 0x1d22b +#define regSDMA3_GFX_IB_RPTR_BASE_IDX 0 +#define regSDMA3_GFX_IB_OFFSET 0x1d22c +#define regSDMA3_GFX_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_GFX_IB_BASE_LO 0x1d22d +#define regSDMA3_GFX_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_GFX_IB_BASE_HI 0x1d22e +#define regSDMA3_GFX_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_GFX_IB_SIZE 0x1d22f +#define regSDMA3_GFX_IB_SIZE_BASE_IDX 0 +#define regSDMA3_GFX_SKIP_CNTL 0x1d230 +#define regSDMA3_GFX_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_CONTEXT_STATUS 0x1d231 +#define regSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_GFX_DOORBELL 0x1d232 +#define regSDMA3_GFX_DOORBELL_BASE_IDX 0 +#define regSDMA3_GFX_CONTEXT_CNTL 0x1d233 +#define regSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_STATUS 0x1d248 +#define regSDMA3_GFX_STATUS_BASE_IDX 0 +#define regSDMA3_GFX_DOORBELL_LOG 0x1d249 +#define regSDMA3_GFX_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_GFX_WATERMARK 0x1d24a +#define regSDMA3_GFX_WATERMARK_BASE_IDX 0 +#define regSDMA3_GFX_DOORBELL_OFFSET 0x1d24b +#define regSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_GFX_CSA_ADDR_LO 0x1d24c +#define regSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_GFX_CSA_ADDR_HI 0x1d24d +#define regSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_GFX_IB_SUB_REMAIN 0x1d24f +#define regSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_GFX_PREEMPT 0x1d250 +#define regSDMA3_GFX_PREEMPT_BASE_IDX 0 +#define regSDMA3_GFX_DUMMY_REG 0x1d251 +#define regSDMA3_GFX_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x1d252 +#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x1d253 +#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_GFX_RB_AQL_CNTL 0x1d254 +#define regSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_GFX_MINOR_PTR_UPDATE 0x1d255 +#define regSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA0 0x1d260 +#define regSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA1 0x1d261 +#define regSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA2 0x1d262 +#define regSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA3 0x1d263 +#define regSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA4 0x1d264 +#define regSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA5 0x1d265 +#define regSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA6 0x1d266 +#define regSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA7 0x1d267 +#define regSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA8 0x1d268 +#define regSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA9 0x1d269 +#define regSDMA3_GFX_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_DATA10 0x1d26a +#define regSDMA3_GFX_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_GFX_MIDCMD_CNTL 0x1d26b +#define regSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_RB_CNTL 0x1d278 +#define regSDMA3_PAGE_RB_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_RB_BASE 0x1d279 +#define regSDMA3_PAGE_RB_BASE_BASE_IDX 0 +#define regSDMA3_PAGE_RB_BASE_HI 0x1d27a +#define regSDMA3_PAGE_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_PAGE_RB_RPTR 0x1d27b +#define regSDMA3_PAGE_RB_RPTR_BASE_IDX 0 +#define regSDMA3_PAGE_RB_RPTR_HI 0x1d27c +#define regSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_PAGE_RB_WPTR 0x1d27d +#define regSDMA3_PAGE_RB_WPTR_BASE_IDX 0 +#define regSDMA3_PAGE_RB_WPTR_HI 0x1d27e +#define regSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x1d27f +#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_RB_RPTR_ADDR_HI 0x1d280 +#define regSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_PAGE_RB_RPTR_ADDR_LO 0x1d281 +#define regSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_PAGE_IB_CNTL 0x1d282 +#define regSDMA3_PAGE_IB_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_IB_RPTR 0x1d283 +#define regSDMA3_PAGE_IB_RPTR_BASE_IDX 0 +#define regSDMA3_PAGE_IB_OFFSET 0x1d284 +#define regSDMA3_PAGE_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_PAGE_IB_BASE_LO 0x1d285 +#define regSDMA3_PAGE_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_PAGE_IB_BASE_HI 0x1d286 +#define regSDMA3_PAGE_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_PAGE_IB_SIZE 0x1d287 +#define regSDMA3_PAGE_IB_SIZE_BASE_IDX 0 +#define regSDMA3_PAGE_SKIP_CNTL 0x1d288 +#define regSDMA3_PAGE_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_CONTEXT_STATUS 0x1d289 +#define regSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_PAGE_DOORBELL 0x1d28a +#define regSDMA3_PAGE_DOORBELL_BASE_IDX 0 +#define regSDMA3_PAGE_STATUS 0x1d2a0 +#define regSDMA3_PAGE_STATUS_BASE_IDX 0 +#define regSDMA3_PAGE_DOORBELL_LOG 0x1d2a1 +#define regSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_PAGE_WATERMARK 0x1d2a2 +#define regSDMA3_PAGE_WATERMARK_BASE_IDX 0 +#define regSDMA3_PAGE_DOORBELL_OFFSET 0x1d2a3 +#define regSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_PAGE_CSA_ADDR_LO 0x1d2a4 +#define regSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_PAGE_CSA_ADDR_HI 0x1d2a5 +#define regSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_PAGE_IB_SUB_REMAIN 0x1d2a7 +#define regSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_PAGE_PREEMPT 0x1d2a8 +#define regSDMA3_PAGE_PREEMPT_BASE_IDX 0 +#define regSDMA3_PAGE_DUMMY_REG 0x1d2a9 +#define regSDMA3_PAGE_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d2aa +#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d2ab +#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_PAGE_RB_AQL_CNTL 0x1d2ac +#define regSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_PAGE_MINOR_PTR_UPDATE 0x1d2ad +#define regSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA0 0x1d2b8 +#define regSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA1 0x1d2b9 +#define regSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA2 0x1d2ba +#define regSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA3 0x1d2bb +#define regSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA4 0x1d2bc +#define regSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA5 0x1d2bd +#define regSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA6 0x1d2be +#define regSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA7 0x1d2bf +#define regSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA8 0x1d2c0 +#define regSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA9 0x1d2c1 +#define regSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_DATA10 0x1d2c2 +#define regSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_PAGE_MIDCMD_CNTL 0x1d2c3 +#define regSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_RB_CNTL 0x1d2d0 +#define regSDMA3_RLC0_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_RB_BASE 0x1d2d1 +#define regSDMA3_RLC0_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC0_RB_BASE_HI 0x1d2d2 +#define regSDMA3_RLC0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC0_RB_RPTR 0x1d2d3 +#define regSDMA3_RLC0_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC0_RB_RPTR_HI 0x1d2d4 +#define regSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC0_RB_WPTR 0x1d2d5 +#define regSDMA3_RLC0_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC0_RB_WPTR_HI 0x1d2d6 +#define regSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x1d2d7 +#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_RB_RPTR_ADDR_HI 0x1d2d8 +#define regSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC0_RB_RPTR_ADDR_LO 0x1d2d9 +#define regSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC0_IB_CNTL 0x1d2da +#define regSDMA3_RLC0_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_IB_RPTR 0x1d2db +#define regSDMA3_RLC0_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC0_IB_OFFSET 0x1d2dc +#define regSDMA3_RLC0_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC0_IB_BASE_LO 0x1d2dd +#define regSDMA3_RLC0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC0_IB_BASE_HI 0x1d2de +#define regSDMA3_RLC0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC0_IB_SIZE 0x1d2df +#define regSDMA3_RLC0_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC0_SKIP_CNTL 0x1d2e0 +#define regSDMA3_RLC0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_CONTEXT_STATUS 0x1d2e1 +#define regSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC0_DOORBELL 0x1d2e2 +#define regSDMA3_RLC0_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC0_STATUS 0x1d2f8 +#define regSDMA3_RLC0_STATUS_BASE_IDX 0 +#define regSDMA3_RLC0_DOORBELL_LOG 0x1d2f9 +#define regSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC0_WATERMARK 0x1d2fa +#define regSDMA3_RLC0_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC0_DOORBELL_OFFSET 0x1d2fb +#define regSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC0_CSA_ADDR_LO 0x1d2fc +#define regSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC0_CSA_ADDR_HI 0x1d2fd +#define regSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC0_IB_SUB_REMAIN 0x1d2ff +#define regSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC0_PREEMPT 0x1d300 +#define regSDMA3_RLC0_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC0_DUMMY_REG 0x1d301 +#define regSDMA3_RLC0_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d302 +#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d303 +#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC0_RB_AQL_CNTL 0x1d304 +#define regSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC0_MINOR_PTR_UPDATE 0x1d305 +#define regSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA0 0x1d310 +#define regSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA1 0x1d311 +#define regSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA2 0x1d312 +#define regSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA3 0x1d313 +#define regSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA4 0x1d314 +#define regSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA5 0x1d315 +#define regSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA6 0x1d316 +#define regSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA7 0x1d317 +#define regSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA8 0x1d318 +#define regSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA9 0x1d319 +#define regSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_DATA10 0x1d31a +#define regSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC0_MIDCMD_CNTL 0x1d31b +#define regSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_RB_CNTL 0x1d328 +#define regSDMA3_RLC1_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_RB_BASE 0x1d329 +#define regSDMA3_RLC1_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC1_RB_BASE_HI 0x1d32a +#define regSDMA3_RLC1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC1_RB_RPTR 0x1d32b +#define regSDMA3_RLC1_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC1_RB_RPTR_HI 0x1d32c +#define regSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC1_RB_WPTR 0x1d32d +#define regSDMA3_RLC1_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC1_RB_WPTR_HI 0x1d32e +#define regSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x1d32f +#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_RB_RPTR_ADDR_HI 0x1d330 +#define regSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC1_RB_RPTR_ADDR_LO 0x1d331 +#define regSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC1_IB_CNTL 0x1d332 +#define regSDMA3_RLC1_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_IB_RPTR 0x1d333 +#define regSDMA3_RLC1_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC1_IB_OFFSET 0x1d334 +#define regSDMA3_RLC1_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC1_IB_BASE_LO 0x1d335 +#define regSDMA3_RLC1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC1_IB_BASE_HI 0x1d336 +#define regSDMA3_RLC1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC1_IB_SIZE 0x1d337 +#define regSDMA3_RLC1_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC1_SKIP_CNTL 0x1d338 +#define regSDMA3_RLC1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_CONTEXT_STATUS 0x1d339 +#define regSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC1_DOORBELL 0x1d33a +#define regSDMA3_RLC1_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC1_STATUS 0x1d350 +#define regSDMA3_RLC1_STATUS_BASE_IDX 0 +#define regSDMA3_RLC1_DOORBELL_LOG 0x1d351 +#define regSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC1_WATERMARK 0x1d352 +#define regSDMA3_RLC1_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC1_DOORBELL_OFFSET 0x1d353 +#define regSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC1_CSA_ADDR_LO 0x1d354 +#define regSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC1_CSA_ADDR_HI 0x1d355 +#define regSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC1_IB_SUB_REMAIN 0x1d357 +#define regSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC1_PREEMPT 0x1d358 +#define regSDMA3_RLC1_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC1_DUMMY_REG 0x1d359 +#define regSDMA3_RLC1_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d35a +#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d35b +#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC1_RB_AQL_CNTL 0x1d35c +#define regSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC1_MINOR_PTR_UPDATE 0x1d35d +#define regSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA0 0x1d368 +#define regSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA1 0x1d369 +#define regSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA2 0x1d36a +#define regSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA3 0x1d36b +#define regSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA4 0x1d36c +#define regSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA5 0x1d36d +#define regSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA6 0x1d36e +#define regSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA7 0x1d36f +#define regSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA8 0x1d370 +#define regSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA9 0x1d371 +#define regSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_DATA10 0x1d372 +#define regSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC1_MIDCMD_CNTL 0x1d373 +#define regSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_RB_CNTL 0x1d380 +#define regSDMA3_RLC2_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_RB_BASE 0x1d381 +#define regSDMA3_RLC2_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC2_RB_BASE_HI 0x1d382 +#define regSDMA3_RLC2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC2_RB_RPTR 0x1d383 +#define regSDMA3_RLC2_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC2_RB_RPTR_HI 0x1d384 +#define regSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC2_RB_WPTR 0x1d385 +#define regSDMA3_RLC2_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC2_RB_WPTR_HI 0x1d386 +#define regSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x1d387 +#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_RB_RPTR_ADDR_HI 0x1d388 +#define regSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC2_RB_RPTR_ADDR_LO 0x1d389 +#define regSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC2_IB_CNTL 0x1d38a +#define regSDMA3_RLC2_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_IB_RPTR 0x1d38b +#define regSDMA3_RLC2_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC2_IB_OFFSET 0x1d38c +#define regSDMA3_RLC2_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC2_IB_BASE_LO 0x1d38d +#define regSDMA3_RLC2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC2_IB_BASE_HI 0x1d38e +#define regSDMA3_RLC2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC2_IB_SIZE 0x1d38f +#define regSDMA3_RLC2_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC2_SKIP_CNTL 0x1d390 +#define regSDMA3_RLC2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_CONTEXT_STATUS 0x1d391 +#define regSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC2_DOORBELL 0x1d392 +#define regSDMA3_RLC2_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC2_STATUS 0x1d3a8 +#define regSDMA3_RLC2_STATUS_BASE_IDX 0 +#define regSDMA3_RLC2_DOORBELL_LOG 0x1d3a9 +#define regSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC2_WATERMARK 0x1d3aa +#define regSDMA3_RLC2_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC2_DOORBELL_OFFSET 0x1d3ab +#define regSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC2_CSA_ADDR_LO 0x1d3ac +#define regSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC2_CSA_ADDR_HI 0x1d3ad +#define regSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC2_IB_SUB_REMAIN 0x1d3af +#define regSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC2_PREEMPT 0x1d3b0 +#define regSDMA3_RLC2_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC2_DUMMY_REG 0x1d3b1 +#define regSDMA3_RLC2_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d3b2 +#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d3b3 +#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC2_RB_AQL_CNTL 0x1d3b4 +#define regSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC2_MINOR_PTR_UPDATE 0x1d3b5 +#define regSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA0 0x1d3c0 +#define regSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA1 0x1d3c1 +#define regSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA2 0x1d3c2 +#define regSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA3 0x1d3c3 +#define regSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA4 0x1d3c4 +#define regSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA5 0x1d3c5 +#define regSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA6 0x1d3c6 +#define regSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA7 0x1d3c7 +#define regSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA8 0x1d3c8 +#define regSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA9 0x1d3c9 +#define regSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_DATA10 0x1d3ca +#define regSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC2_MIDCMD_CNTL 0x1d3cb +#define regSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_RB_CNTL 0x1d3d8 +#define regSDMA3_RLC3_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_RB_BASE 0x1d3d9 +#define regSDMA3_RLC3_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC3_RB_BASE_HI 0x1d3da +#define regSDMA3_RLC3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC3_RB_RPTR 0x1d3db +#define regSDMA3_RLC3_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC3_RB_RPTR_HI 0x1d3dc +#define regSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC3_RB_WPTR 0x1d3dd +#define regSDMA3_RLC3_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC3_RB_WPTR_HI 0x1d3de +#define regSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x1d3df +#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_RB_RPTR_ADDR_HI 0x1d3e0 +#define regSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC3_RB_RPTR_ADDR_LO 0x1d3e1 +#define regSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC3_IB_CNTL 0x1d3e2 +#define regSDMA3_RLC3_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_IB_RPTR 0x1d3e3 +#define regSDMA3_RLC3_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC3_IB_OFFSET 0x1d3e4 +#define regSDMA3_RLC3_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC3_IB_BASE_LO 0x1d3e5 +#define regSDMA3_RLC3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC3_IB_BASE_HI 0x1d3e6 +#define regSDMA3_RLC3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC3_IB_SIZE 0x1d3e7 +#define regSDMA3_RLC3_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC3_SKIP_CNTL 0x1d3e8 +#define regSDMA3_RLC3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_CONTEXT_STATUS 0x1d3e9 +#define regSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC3_DOORBELL 0x1d3ea +#define regSDMA3_RLC3_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC3_STATUS 0x1d400 +#define regSDMA3_RLC3_STATUS_BASE_IDX 0 +#define regSDMA3_RLC3_DOORBELL_LOG 0x1d401 +#define regSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC3_WATERMARK 0x1d402 +#define regSDMA3_RLC3_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC3_DOORBELL_OFFSET 0x1d403 +#define regSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC3_CSA_ADDR_LO 0x1d404 +#define regSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC3_CSA_ADDR_HI 0x1d405 +#define regSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC3_IB_SUB_REMAIN 0x1d407 +#define regSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC3_PREEMPT 0x1d408 +#define regSDMA3_RLC3_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC3_DUMMY_REG 0x1d409 +#define regSDMA3_RLC3_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d40a +#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d40b +#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC3_RB_AQL_CNTL 0x1d40c +#define regSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC3_MINOR_PTR_UPDATE 0x1d40d +#define regSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA0 0x1d418 +#define regSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA1 0x1d419 +#define regSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA2 0x1d41a +#define regSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA3 0x1d41b +#define regSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA4 0x1d41c +#define regSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA5 0x1d41d +#define regSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA6 0x1d41e +#define regSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA7 0x1d41f +#define regSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA8 0x1d420 +#define regSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA9 0x1d421 +#define regSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_DATA10 0x1d422 +#define regSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC3_MIDCMD_CNTL 0x1d423 +#define regSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_RB_CNTL 0x1d430 +#define regSDMA3_RLC4_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_RB_BASE 0x1d431 +#define regSDMA3_RLC4_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC4_RB_BASE_HI 0x1d432 +#define regSDMA3_RLC4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC4_RB_RPTR 0x1d433 +#define regSDMA3_RLC4_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC4_RB_RPTR_HI 0x1d434 +#define regSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC4_RB_WPTR 0x1d435 +#define regSDMA3_RLC4_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC4_RB_WPTR_HI 0x1d436 +#define regSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x1d437 +#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_RB_RPTR_ADDR_HI 0x1d438 +#define regSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC4_RB_RPTR_ADDR_LO 0x1d439 +#define regSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC4_IB_CNTL 0x1d43a +#define regSDMA3_RLC4_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_IB_RPTR 0x1d43b +#define regSDMA3_RLC4_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC4_IB_OFFSET 0x1d43c +#define regSDMA3_RLC4_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC4_IB_BASE_LO 0x1d43d +#define regSDMA3_RLC4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC4_IB_BASE_HI 0x1d43e +#define regSDMA3_RLC4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC4_IB_SIZE 0x1d43f +#define regSDMA3_RLC4_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC4_SKIP_CNTL 0x1d440 +#define regSDMA3_RLC4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_CONTEXT_STATUS 0x1d441 +#define regSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC4_DOORBELL 0x1d442 +#define regSDMA3_RLC4_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC4_STATUS 0x1d458 +#define regSDMA3_RLC4_STATUS_BASE_IDX 0 +#define regSDMA3_RLC4_DOORBELL_LOG 0x1d459 +#define regSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC4_WATERMARK 0x1d45a +#define regSDMA3_RLC4_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC4_DOORBELL_OFFSET 0x1d45b +#define regSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC4_CSA_ADDR_LO 0x1d45c +#define regSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC4_CSA_ADDR_HI 0x1d45d +#define regSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC4_IB_SUB_REMAIN 0x1d45f +#define regSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC4_PREEMPT 0x1d460 +#define regSDMA3_RLC4_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC4_DUMMY_REG 0x1d461 +#define regSDMA3_RLC4_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d462 +#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d463 +#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC4_RB_AQL_CNTL 0x1d464 +#define regSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC4_MINOR_PTR_UPDATE 0x1d465 +#define regSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA0 0x1d470 +#define regSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA1 0x1d471 +#define regSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA2 0x1d472 +#define regSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA3 0x1d473 +#define regSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA4 0x1d474 +#define regSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA5 0x1d475 +#define regSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA6 0x1d476 +#define regSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA7 0x1d477 +#define regSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA8 0x1d478 +#define regSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA9 0x1d479 +#define regSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_DATA10 0x1d47a +#define regSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC4_MIDCMD_CNTL 0x1d47b +#define regSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_RB_CNTL 0x1d488 +#define regSDMA3_RLC5_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_RB_BASE 0x1d489 +#define regSDMA3_RLC5_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC5_RB_BASE_HI 0x1d48a +#define regSDMA3_RLC5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC5_RB_RPTR 0x1d48b +#define regSDMA3_RLC5_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC5_RB_RPTR_HI 0x1d48c +#define regSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC5_RB_WPTR 0x1d48d +#define regSDMA3_RLC5_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC5_RB_WPTR_HI 0x1d48e +#define regSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x1d48f +#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_RB_RPTR_ADDR_HI 0x1d490 +#define regSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC5_RB_RPTR_ADDR_LO 0x1d491 +#define regSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC5_IB_CNTL 0x1d492 +#define regSDMA3_RLC5_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_IB_RPTR 0x1d493 +#define regSDMA3_RLC5_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC5_IB_OFFSET 0x1d494 +#define regSDMA3_RLC5_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC5_IB_BASE_LO 0x1d495 +#define regSDMA3_RLC5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC5_IB_BASE_HI 0x1d496 +#define regSDMA3_RLC5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC5_IB_SIZE 0x1d497 +#define regSDMA3_RLC5_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC5_SKIP_CNTL 0x1d498 +#define regSDMA3_RLC5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_CONTEXT_STATUS 0x1d499 +#define regSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC5_DOORBELL 0x1d49a +#define regSDMA3_RLC5_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC5_STATUS 0x1d4b0 +#define regSDMA3_RLC5_STATUS_BASE_IDX 0 +#define regSDMA3_RLC5_DOORBELL_LOG 0x1d4b1 +#define regSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC5_WATERMARK 0x1d4b2 +#define regSDMA3_RLC5_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC5_DOORBELL_OFFSET 0x1d4b3 +#define regSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC5_CSA_ADDR_LO 0x1d4b4 +#define regSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC5_CSA_ADDR_HI 0x1d4b5 +#define regSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC5_IB_SUB_REMAIN 0x1d4b7 +#define regSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC5_PREEMPT 0x1d4b8 +#define regSDMA3_RLC5_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC5_DUMMY_REG 0x1d4b9 +#define regSDMA3_RLC5_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d4ba +#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d4bb +#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC5_RB_AQL_CNTL 0x1d4bc +#define regSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC5_MINOR_PTR_UPDATE 0x1d4bd +#define regSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA0 0x1d4c8 +#define regSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA1 0x1d4c9 +#define regSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA2 0x1d4ca +#define regSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA3 0x1d4cb +#define regSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA4 0x1d4cc +#define regSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA5 0x1d4cd +#define regSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA6 0x1d4ce +#define regSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA7 0x1d4cf +#define regSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA8 0x1d4d0 +#define regSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA9 0x1d4d1 +#define regSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_DATA10 0x1d4d2 +#define regSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC5_MIDCMD_CNTL 0x1d4d3 +#define regSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_RB_CNTL 0x1d4e0 +#define regSDMA3_RLC6_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_RB_BASE 0x1d4e1 +#define regSDMA3_RLC6_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC6_RB_BASE_HI 0x1d4e2 +#define regSDMA3_RLC6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC6_RB_RPTR 0x1d4e3 +#define regSDMA3_RLC6_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC6_RB_RPTR_HI 0x1d4e4 +#define regSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC6_RB_WPTR 0x1d4e5 +#define regSDMA3_RLC6_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC6_RB_WPTR_HI 0x1d4e6 +#define regSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x1d4e7 +#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_RB_RPTR_ADDR_HI 0x1d4e8 +#define regSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC6_RB_RPTR_ADDR_LO 0x1d4e9 +#define regSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC6_IB_CNTL 0x1d4ea +#define regSDMA3_RLC6_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_IB_RPTR 0x1d4eb +#define regSDMA3_RLC6_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC6_IB_OFFSET 0x1d4ec +#define regSDMA3_RLC6_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC6_IB_BASE_LO 0x1d4ed +#define regSDMA3_RLC6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC6_IB_BASE_HI 0x1d4ee +#define regSDMA3_RLC6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC6_IB_SIZE 0x1d4ef +#define regSDMA3_RLC6_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC6_SKIP_CNTL 0x1d4f0 +#define regSDMA3_RLC6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_CONTEXT_STATUS 0x1d4f1 +#define regSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC6_DOORBELL 0x1d4f2 +#define regSDMA3_RLC6_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC6_STATUS 0x1d508 +#define regSDMA3_RLC6_STATUS_BASE_IDX 0 +#define regSDMA3_RLC6_DOORBELL_LOG 0x1d509 +#define regSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC6_WATERMARK 0x1d50a +#define regSDMA3_RLC6_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC6_DOORBELL_OFFSET 0x1d50b +#define regSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC6_CSA_ADDR_LO 0x1d50c +#define regSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC6_CSA_ADDR_HI 0x1d50d +#define regSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC6_IB_SUB_REMAIN 0x1d50f +#define regSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC6_PREEMPT 0x1d510 +#define regSDMA3_RLC6_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC6_DUMMY_REG 0x1d511 +#define regSDMA3_RLC6_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d512 +#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d513 +#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC6_RB_AQL_CNTL 0x1d514 +#define regSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC6_MINOR_PTR_UPDATE 0x1d515 +#define regSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA0 0x1d520 +#define regSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA1 0x1d521 +#define regSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA2 0x1d522 +#define regSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA3 0x1d523 +#define regSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA4 0x1d524 +#define regSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA5 0x1d525 +#define regSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA6 0x1d526 +#define regSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA7 0x1d527 +#define regSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA8 0x1d528 +#define regSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA9 0x1d529 +#define regSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_DATA10 0x1d52a +#define regSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC6_MIDCMD_CNTL 0x1d52b +#define regSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_RB_CNTL 0x1d538 +#define regSDMA3_RLC7_RB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_RB_BASE 0x1d539 +#define regSDMA3_RLC7_RB_BASE_BASE_IDX 0 +#define regSDMA3_RLC7_RB_BASE_HI 0x1d53a +#define regSDMA3_RLC7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC7_RB_RPTR 0x1d53b +#define regSDMA3_RLC7_RB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC7_RB_RPTR_HI 0x1d53c +#define regSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC7_RB_WPTR 0x1d53d +#define regSDMA3_RLC7_RB_WPTR_BASE_IDX 0 +#define regSDMA3_RLC7_RB_WPTR_HI 0x1d53e +#define regSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x1d53f +#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_RB_RPTR_ADDR_HI 0x1d540 +#define regSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC7_RB_RPTR_ADDR_LO 0x1d541 +#define regSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC7_IB_CNTL 0x1d542 +#define regSDMA3_RLC7_IB_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_IB_RPTR 0x1d543 +#define regSDMA3_RLC7_IB_RPTR_BASE_IDX 0 +#define regSDMA3_RLC7_IB_OFFSET 0x1d544 +#define regSDMA3_RLC7_IB_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC7_IB_BASE_LO 0x1d545 +#define regSDMA3_RLC7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA3_RLC7_IB_BASE_HI 0x1d546 +#define regSDMA3_RLC7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA3_RLC7_IB_SIZE 0x1d547 +#define regSDMA3_RLC7_IB_SIZE_BASE_IDX 0 +#define regSDMA3_RLC7_SKIP_CNTL 0x1d548 +#define regSDMA3_RLC7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_CONTEXT_STATUS 0x1d549 +#define regSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA3_RLC7_DOORBELL 0x1d54a +#define regSDMA3_RLC7_DOORBELL_BASE_IDX 0 +#define regSDMA3_RLC7_STATUS 0x1d560 +#define regSDMA3_RLC7_STATUS_BASE_IDX 0 +#define regSDMA3_RLC7_DOORBELL_LOG 0x1d561 +#define regSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA3_RLC7_WATERMARK 0x1d562 +#define regSDMA3_RLC7_WATERMARK_BASE_IDX 0 +#define regSDMA3_RLC7_DOORBELL_OFFSET 0x1d563 +#define regSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA3_RLC7_CSA_ADDR_LO 0x1d564 +#define regSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC7_CSA_ADDR_HI 0x1d565 +#define regSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC7_IB_SUB_REMAIN 0x1d567 +#define regSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA3_RLC7_PREEMPT 0x1d568 +#define regSDMA3_RLC7_PREEMPT_BASE_IDX 0 +#define regSDMA3_RLC7_DUMMY_REG 0x1d569 +#define regSDMA3_RLC7_DUMMY_REG_BASE_IDX 0 +#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d56a +#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d56b +#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA3_RLC7_RB_AQL_CNTL 0x1d56c +#define regSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA3_RLC7_MINOR_PTR_UPDATE 0x1d56d +#define regSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA0 0x1d578 +#define regSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA1 0x1d579 +#define regSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA2 0x1d57a +#define regSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA3 0x1d57b +#define regSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA4 0x1d57c +#define regSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA5 0x1d57d +#define regSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA6 0x1d57e +#define regSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA7 0x1d57f +#define regSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA8 0x1d580 +#define regSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA9 0x1d581 +#define regSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_DATA10 0x1d582 +#define regSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA3_RLC7_MIDCMD_CNTL 0x1d583 +#define regSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 0 + + +// addressBlock: sdma0_sdma4dec +// base address: 0x7a000 +#define regSDMA4_UCODE_ADDR 0x1d5a0 +#define regSDMA4_UCODE_ADDR_BASE_IDX 0 +#define regSDMA4_UCODE_DATA 0x1d5a1 +#define regSDMA4_UCODE_DATA_BASE_IDX 0 +#define regSDMA4_VF_ENABLE 0x1d5aa +#define regSDMA4_VF_ENABLE_BASE_IDX 0 +#define regSDMA4_CONTEXT_GROUP_BOUNDARY 0x1d5b9 +#define regSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define regSDMA4_POWER_CNTL 0x1d5ba +#define regSDMA4_POWER_CNTL_BASE_IDX 0 +#define regSDMA4_CLK_CTRL 0x1d5bb +#define regSDMA4_CLK_CTRL_BASE_IDX 0 +#define regSDMA4_CNTL 0x1d5bc +#define regSDMA4_CNTL_BASE_IDX 0 +#define regSDMA4_CHICKEN_BITS 0x1d5bd +#define regSDMA4_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA4_GB_ADDR_CONFIG 0x1d5be +#define regSDMA4_GB_ADDR_CONFIG_BASE_IDX 0 +#define regSDMA4_GB_ADDR_CONFIG_READ 0x1d5bf +#define regSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regSDMA4_RB_RPTR_FETCH_HI 0x1d5c0 +#define regSDMA4_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0x1d5c1 +#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define regSDMA4_RB_RPTR_FETCH 0x1d5c2 +#define regSDMA4_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA4_IB_OFFSET_FETCH 0x1d5c3 +#define regSDMA4_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA4_PROGRAM 0x1d5c4 +#define regSDMA4_PROGRAM_BASE_IDX 0 +#define regSDMA4_STATUS_REG 0x1d5c5 +#define regSDMA4_STATUS_REG_BASE_IDX 0 +#define regSDMA4_STATUS1_REG 0x1d5c6 +#define regSDMA4_STATUS1_REG_BASE_IDX 0 +#define regSDMA4_RD_BURST_CNTL 0x1d5c7 +#define regSDMA4_RD_BURST_CNTL_BASE_IDX 0 +#define regSDMA4_HBM_PAGE_CONFIG 0x1d5c8 +#define regSDMA4_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA4_UCODE_CHECKSUM 0x1d5c9 +#define regSDMA4_UCODE_CHECKSUM_BASE_IDX 0 +#define regSDMA4_F32_CNTL 0x1d5ca +#define regSDMA4_F32_CNTL_BASE_IDX 0 +#define regSDMA4_FREEZE 0x1d5cb +#define regSDMA4_FREEZE_BASE_IDX 0 +#define regSDMA4_PHASE0_QUANTUM 0x1d5cc +#define regSDMA4_PHASE0_QUANTUM_BASE_IDX 0 +#define regSDMA4_PHASE1_QUANTUM 0x1d5cd +#define regSDMA4_PHASE1_QUANTUM_BASE_IDX 0 +#define regCC_SDMA4_EDC_CONFIG 0x1d5d2 +#define regCC_SDMA4_EDC_CONFIG_BASE_IDX 0 +#define regSDMA4_BA_THRESHOLD 0x1d5d3 +#define regSDMA4_BA_THRESHOLD_BASE_IDX 0 +#define regSDMA4_ID 0x1d5d4 +#define regSDMA4_ID_BASE_IDX 0 +#define regSDMA4_VERSION 0x1d5d5 +#define regSDMA4_VERSION_BASE_IDX 0 +#define regSDMA4_EDC_COUNTER 0x1d5d6 +#define regSDMA4_EDC_COUNTER_BASE_IDX 0 +#define regSDMA4_EDC_COUNTER2 0x1d5d7 +#define regSDMA4_EDC_COUNTER2_BASE_IDX 0 +#define regSDMA4_STATUS2_REG 0x1d5d8 +#define regSDMA4_STATUS2_REG_BASE_IDX 0 +#define regSDMA4_ATOMIC_CNTL 0x1d5d9 +#define regSDMA4_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA4_ATOMIC_PREOP_LO 0x1d5da +#define regSDMA4_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA4_ATOMIC_PREOP_HI 0x1d5db +#define regSDMA4_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA4_UTCL1_CNTL 0x1d5dc +#define regSDMA4_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA4_UTCL1_WATERMK 0x1d5dd +#define regSDMA4_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA4_UTCL1_RD_STATUS 0x1d5de +#define regSDMA4_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA4_UTCL1_WR_STATUS 0x1d5df +#define regSDMA4_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA4_UTCL1_INV0 0x1d5e0 +#define regSDMA4_UTCL1_INV0_BASE_IDX 0 +#define regSDMA4_UTCL1_INV1 0x1d5e1 +#define regSDMA4_UTCL1_INV1_BASE_IDX 0 +#define regSDMA4_UTCL1_INV2 0x1d5e2 +#define regSDMA4_UTCL1_INV2_BASE_IDX 0 +#define regSDMA4_UTCL1_RD_XNACK0 0x1d5e3 +#define regSDMA4_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA4_UTCL1_RD_XNACK1 0x1d5e4 +#define regSDMA4_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA4_UTCL1_WR_XNACK0 0x1d5e5 +#define regSDMA4_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA4_UTCL1_WR_XNACK1 0x1d5e6 +#define regSDMA4_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA4_UTCL1_TIMEOUT 0x1d5e7 +#define regSDMA4_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA4_UTCL1_PAGE 0x1d5e8 +#define regSDMA4_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA4_POWER_CNTL_IDLE 0x1d5e9 +#define regSDMA4_POWER_CNTL_IDLE_BASE_IDX 0 +#define regSDMA4_RELAX_ORDERING_LUT 0x1d5ea +#define regSDMA4_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regSDMA4_CHICKEN_BITS_2 0x1d5eb +#define regSDMA4_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA4_STATUS3_REG 0x1d5ec +#define regSDMA4_STATUS3_REG_BASE_IDX 0 +#define regSDMA4_PHYSICAL_ADDR_LO 0x1d5ed +#define regSDMA4_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_PHYSICAL_ADDR_HI 0x1d5ee +#define regSDMA4_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_PHASE2_QUANTUM 0x1d5ef +#define regSDMA4_PHASE2_QUANTUM_BASE_IDX 0 +#define regSDMA4_ERROR_LOG 0x1d5f0 +#define regSDMA4_ERROR_LOG_BASE_IDX 0 +#define regSDMA4_PUB_DUMMY_REG0 0x1d5f1 +#define regSDMA4_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA4_PUB_DUMMY_REG1 0x1d5f2 +#define regSDMA4_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA4_PUB_DUMMY_REG2 0x1d5f3 +#define regSDMA4_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA4_PUB_DUMMY_REG3 0x1d5f4 +#define regSDMA4_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA4_F32_COUNTER 0x1d5f5 +#define regSDMA4_F32_COUNTER_BASE_IDX 0 +#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG 0x1d5f7 +#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG 0x1d5f8 +#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d5f9 +#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regSDMA4_PERFCNT_MISC_CNTL 0x1d5fa +#define regSDMA4_PERFCNT_MISC_CNTL_BASE_IDX 0 +#define regSDMA4_PERFCNT_PERFCOUNTER_LO 0x1d5fb +#define regSDMA4_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 +#define regSDMA4_PERFCNT_PERFCOUNTER_HI 0x1d5fc +#define regSDMA4_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 +#define regSDMA4_CRD_CNTL 0x1d5fd +#define regSDMA4_CRD_CNTL_BASE_IDX 0 +#define regSDMA4_ULV_CNTL 0x1d5ff +#define regSDMA4_ULV_CNTL_BASE_IDX 0 +#define regSDMA4_EA_DBIT_ADDR_DATA 0x1d600 +#define regSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define regSDMA4_EA_DBIT_ADDR_INDEX 0x1d601 +#define regSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define regSDMA4_STATUS4_REG 0x1d603 +#define regSDMA4_STATUS4_REG_BASE_IDX 0 +#define regSDMA4_SCRATCH_RAM_DATA 0x1d604 +#define regSDMA4_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA4_SCRATCH_RAM_ADDR 0x1d605 +#define regSDMA4_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA4_CE_CTRL 0x1d606 +#define regSDMA4_CE_CTRL_BASE_IDX 0 +#define regSDMA4_RAS_STATUS 0x1d607 +#define regSDMA4_RAS_STATUS_BASE_IDX 0 +#define regSDMA4_CLK_STATUS 0x1d608 +#define regSDMA4_CLK_STATUS_BASE_IDX 0 +#define regSDMA4_GFX_RB_CNTL 0x1d620 +#define regSDMA4_GFX_RB_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_RB_BASE 0x1d621 +#define regSDMA4_GFX_RB_BASE_BASE_IDX 0 +#define regSDMA4_GFX_RB_BASE_HI 0x1d622 +#define regSDMA4_GFX_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_GFX_RB_RPTR 0x1d623 +#define regSDMA4_GFX_RB_RPTR_BASE_IDX 0 +#define regSDMA4_GFX_RB_RPTR_HI 0x1d624 +#define regSDMA4_GFX_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_GFX_RB_WPTR 0x1d625 +#define regSDMA4_GFX_RB_WPTR_BASE_IDX 0 +#define regSDMA4_GFX_RB_WPTR_HI 0x1d626 +#define regSDMA4_GFX_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_GFX_RB_WPTR_POLL_CNTL 0x1d627 +#define regSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_RB_RPTR_ADDR_HI 0x1d628 +#define regSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_GFX_RB_RPTR_ADDR_LO 0x1d629 +#define regSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_GFX_IB_CNTL 0x1d62a +#define regSDMA4_GFX_IB_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_IB_RPTR 0x1d62b +#define regSDMA4_GFX_IB_RPTR_BASE_IDX 0 +#define regSDMA4_GFX_IB_OFFSET 0x1d62c +#define regSDMA4_GFX_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_GFX_IB_BASE_LO 0x1d62d +#define regSDMA4_GFX_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_GFX_IB_BASE_HI 0x1d62e +#define regSDMA4_GFX_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_GFX_IB_SIZE 0x1d62f +#define regSDMA4_GFX_IB_SIZE_BASE_IDX 0 +#define regSDMA4_GFX_SKIP_CNTL 0x1d630 +#define regSDMA4_GFX_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_CONTEXT_STATUS 0x1d631 +#define regSDMA4_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_GFX_DOORBELL 0x1d632 +#define regSDMA4_GFX_DOORBELL_BASE_IDX 0 +#define regSDMA4_GFX_CONTEXT_CNTL 0x1d633 +#define regSDMA4_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_STATUS 0x1d648 +#define regSDMA4_GFX_STATUS_BASE_IDX 0 +#define regSDMA4_GFX_DOORBELL_LOG 0x1d649 +#define regSDMA4_GFX_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_GFX_WATERMARK 0x1d64a +#define regSDMA4_GFX_WATERMARK_BASE_IDX 0 +#define regSDMA4_GFX_DOORBELL_OFFSET 0x1d64b +#define regSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_GFX_CSA_ADDR_LO 0x1d64c +#define regSDMA4_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_GFX_CSA_ADDR_HI 0x1d64d +#define regSDMA4_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_GFX_IB_SUB_REMAIN 0x1d64f +#define regSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_GFX_PREEMPT 0x1d650 +#define regSDMA4_GFX_PREEMPT_BASE_IDX 0 +#define regSDMA4_GFX_DUMMY_REG 0x1d651 +#define regSDMA4_GFX_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0x1d652 +#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0x1d653 +#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_GFX_RB_AQL_CNTL 0x1d654 +#define regSDMA4_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_GFX_MINOR_PTR_UPDATE 0x1d655 +#define regSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA0 0x1d660 +#define regSDMA4_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA1 0x1d661 +#define regSDMA4_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA2 0x1d662 +#define regSDMA4_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA3 0x1d663 +#define regSDMA4_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA4 0x1d664 +#define regSDMA4_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA5 0x1d665 +#define regSDMA4_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA6 0x1d666 +#define regSDMA4_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA7 0x1d667 +#define regSDMA4_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA8 0x1d668 +#define regSDMA4_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA9 0x1d669 +#define regSDMA4_GFX_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_DATA10 0x1d66a +#define regSDMA4_GFX_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_GFX_MIDCMD_CNTL 0x1d66b +#define regSDMA4_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_RB_CNTL 0x1d678 +#define regSDMA4_PAGE_RB_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_RB_BASE 0x1d679 +#define regSDMA4_PAGE_RB_BASE_BASE_IDX 0 +#define regSDMA4_PAGE_RB_BASE_HI 0x1d67a +#define regSDMA4_PAGE_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_PAGE_RB_RPTR 0x1d67b +#define regSDMA4_PAGE_RB_RPTR_BASE_IDX 0 +#define regSDMA4_PAGE_RB_RPTR_HI 0x1d67c +#define regSDMA4_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_PAGE_RB_WPTR 0x1d67d +#define regSDMA4_PAGE_RB_WPTR_BASE_IDX 0 +#define regSDMA4_PAGE_RB_WPTR_HI 0x1d67e +#define regSDMA4_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL 0x1d67f +#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_RB_RPTR_ADDR_HI 0x1d680 +#define regSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_PAGE_RB_RPTR_ADDR_LO 0x1d681 +#define regSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_PAGE_IB_CNTL 0x1d682 +#define regSDMA4_PAGE_IB_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_IB_RPTR 0x1d683 +#define regSDMA4_PAGE_IB_RPTR_BASE_IDX 0 +#define regSDMA4_PAGE_IB_OFFSET 0x1d684 +#define regSDMA4_PAGE_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_PAGE_IB_BASE_LO 0x1d685 +#define regSDMA4_PAGE_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_PAGE_IB_BASE_HI 0x1d686 +#define regSDMA4_PAGE_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_PAGE_IB_SIZE 0x1d687 +#define regSDMA4_PAGE_IB_SIZE_BASE_IDX 0 +#define regSDMA4_PAGE_SKIP_CNTL 0x1d688 +#define regSDMA4_PAGE_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_CONTEXT_STATUS 0x1d689 +#define regSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_PAGE_DOORBELL 0x1d68a +#define regSDMA4_PAGE_DOORBELL_BASE_IDX 0 +#define regSDMA4_PAGE_STATUS 0x1d6a0 +#define regSDMA4_PAGE_STATUS_BASE_IDX 0 +#define regSDMA4_PAGE_DOORBELL_LOG 0x1d6a1 +#define regSDMA4_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_PAGE_WATERMARK 0x1d6a2 +#define regSDMA4_PAGE_WATERMARK_BASE_IDX 0 +#define regSDMA4_PAGE_DOORBELL_OFFSET 0x1d6a3 +#define regSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_PAGE_CSA_ADDR_LO 0x1d6a4 +#define regSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_PAGE_CSA_ADDR_HI 0x1d6a5 +#define regSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_PAGE_IB_SUB_REMAIN 0x1d6a7 +#define regSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_PAGE_PREEMPT 0x1d6a8 +#define regSDMA4_PAGE_PREEMPT_BASE_IDX 0 +#define regSDMA4_PAGE_DUMMY_REG 0x1d6a9 +#define regSDMA4_PAGE_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d6aa +#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d6ab +#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_PAGE_RB_AQL_CNTL 0x1d6ac +#define regSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_PAGE_MINOR_PTR_UPDATE 0x1d6ad +#define regSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA0 0x1d6b8 +#define regSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA1 0x1d6b9 +#define regSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA2 0x1d6ba +#define regSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA3 0x1d6bb +#define regSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA4 0x1d6bc +#define regSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA5 0x1d6bd +#define regSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA6 0x1d6be +#define regSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA7 0x1d6bf +#define regSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA8 0x1d6c0 +#define regSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA9 0x1d6c1 +#define regSDMA4_PAGE_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_DATA10 0x1d6c2 +#define regSDMA4_PAGE_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_PAGE_MIDCMD_CNTL 0x1d6c3 +#define regSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_RB_CNTL 0x1d6d0 +#define regSDMA4_RLC0_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_RB_BASE 0x1d6d1 +#define regSDMA4_RLC0_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC0_RB_BASE_HI 0x1d6d2 +#define regSDMA4_RLC0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC0_RB_RPTR 0x1d6d3 +#define regSDMA4_RLC0_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC0_RB_RPTR_HI 0x1d6d4 +#define regSDMA4_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC0_RB_WPTR 0x1d6d5 +#define regSDMA4_RLC0_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC0_RB_WPTR_HI 0x1d6d6 +#define regSDMA4_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL 0x1d6d7 +#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_RB_RPTR_ADDR_HI 0x1d6d8 +#define regSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC0_RB_RPTR_ADDR_LO 0x1d6d9 +#define regSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC0_IB_CNTL 0x1d6da +#define regSDMA4_RLC0_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_IB_RPTR 0x1d6db +#define regSDMA4_RLC0_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC0_IB_OFFSET 0x1d6dc +#define regSDMA4_RLC0_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC0_IB_BASE_LO 0x1d6dd +#define regSDMA4_RLC0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC0_IB_BASE_HI 0x1d6de +#define regSDMA4_RLC0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC0_IB_SIZE 0x1d6df +#define regSDMA4_RLC0_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC0_SKIP_CNTL 0x1d6e0 +#define regSDMA4_RLC0_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_CONTEXT_STATUS 0x1d6e1 +#define regSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC0_DOORBELL 0x1d6e2 +#define regSDMA4_RLC0_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC0_STATUS 0x1d6f8 +#define regSDMA4_RLC0_STATUS_BASE_IDX 0 +#define regSDMA4_RLC0_DOORBELL_LOG 0x1d6f9 +#define regSDMA4_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC0_WATERMARK 0x1d6fa +#define regSDMA4_RLC0_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC0_DOORBELL_OFFSET 0x1d6fb +#define regSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC0_CSA_ADDR_LO 0x1d6fc +#define regSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC0_CSA_ADDR_HI 0x1d6fd +#define regSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC0_IB_SUB_REMAIN 0x1d6ff +#define regSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC0_PREEMPT 0x1d700 +#define regSDMA4_RLC0_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC0_DUMMY_REG 0x1d701 +#define regSDMA4_RLC0_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d702 +#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d703 +#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC0_RB_AQL_CNTL 0x1d704 +#define regSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC0_MINOR_PTR_UPDATE 0x1d705 +#define regSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA0 0x1d710 +#define regSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA1 0x1d711 +#define regSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA2 0x1d712 +#define regSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA3 0x1d713 +#define regSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA4 0x1d714 +#define regSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA5 0x1d715 +#define regSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA6 0x1d716 +#define regSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA7 0x1d717 +#define regSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA8 0x1d718 +#define regSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA9 0x1d719 +#define regSDMA4_RLC0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_DATA10 0x1d71a +#define regSDMA4_RLC0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC0_MIDCMD_CNTL 0x1d71b +#define regSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_RB_CNTL 0x1d728 +#define regSDMA4_RLC1_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_RB_BASE 0x1d729 +#define regSDMA4_RLC1_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC1_RB_BASE_HI 0x1d72a +#define regSDMA4_RLC1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC1_RB_RPTR 0x1d72b +#define regSDMA4_RLC1_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC1_RB_RPTR_HI 0x1d72c +#define regSDMA4_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC1_RB_WPTR 0x1d72d +#define regSDMA4_RLC1_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC1_RB_WPTR_HI 0x1d72e +#define regSDMA4_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL 0x1d72f +#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_RB_RPTR_ADDR_HI 0x1d730 +#define regSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC1_RB_RPTR_ADDR_LO 0x1d731 +#define regSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC1_IB_CNTL 0x1d732 +#define regSDMA4_RLC1_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_IB_RPTR 0x1d733 +#define regSDMA4_RLC1_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC1_IB_OFFSET 0x1d734 +#define regSDMA4_RLC1_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC1_IB_BASE_LO 0x1d735 +#define regSDMA4_RLC1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC1_IB_BASE_HI 0x1d736 +#define regSDMA4_RLC1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC1_IB_SIZE 0x1d737 +#define regSDMA4_RLC1_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC1_SKIP_CNTL 0x1d738 +#define regSDMA4_RLC1_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_CONTEXT_STATUS 0x1d739 +#define regSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC1_DOORBELL 0x1d73a +#define regSDMA4_RLC1_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC1_STATUS 0x1d750 +#define regSDMA4_RLC1_STATUS_BASE_IDX 0 +#define regSDMA4_RLC1_DOORBELL_LOG 0x1d751 +#define regSDMA4_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC1_WATERMARK 0x1d752 +#define regSDMA4_RLC1_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC1_DOORBELL_OFFSET 0x1d753 +#define regSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC1_CSA_ADDR_LO 0x1d754 +#define regSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC1_CSA_ADDR_HI 0x1d755 +#define regSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC1_IB_SUB_REMAIN 0x1d757 +#define regSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC1_PREEMPT 0x1d758 +#define regSDMA4_RLC1_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC1_DUMMY_REG 0x1d759 +#define regSDMA4_RLC1_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d75a +#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d75b +#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC1_RB_AQL_CNTL 0x1d75c +#define regSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC1_MINOR_PTR_UPDATE 0x1d75d +#define regSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA0 0x1d768 +#define regSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA1 0x1d769 +#define regSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA2 0x1d76a +#define regSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA3 0x1d76b +#define regSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA4 0x1d76c +#define regSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA5 0x1d76d +#define regSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA6 0x1d76e +#define regSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA7 0x1d76f +#define regSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA8 0x1d770 +#define regSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA9 0x1d771 +#define regSDMA4_RLC1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_DATA10 0x1d772 +#define regSDMA4_RLC1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC1_MIDCMD_CNTL 0x1d773 +#define regSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_RB_CNTL 0x1d780 +#define regSDMA4_RLC2_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_RB_BASE 0x1d781 +#define regSDMA4_RLC2_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC2_RB_BASE_HI 0x1d782 +#define regSDMA4_RLC2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC2_RB_RPTR 0x1d783 +#define regSDMA4_RLC2_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC2_RB_RPTR_HI 0x1d784 +#define regSDMA4_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC2_RB_WPTR 0x1d785 +#define regSDMA4_RLC2_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC2_RB_WPTR_HI 0x1d786 +#define regSDMA4_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL 0x1d787 +#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_RB_RPTR_ADDR_HI 0x1d788 +#define regSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC2_RB_RPTR_ADDR_LO 0x1d789 +#define regSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC2_IB_CNTL 0x1d78a +#define regSDMA4_RLC2_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_IB_RPTR 0x1d78b +#define regSDMA4_RLC2_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC2_IB_OFFSET 0x1d78c +#define regSDMA4_RLC2_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC2_IB_BASE_LO 0x1d78d +#define regSDMA4_RLC2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC2_IB_BASE_HI 0x1d78e +#define regSDMA4_RLC2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC2_IB_SIZE 0x1d78f +#define regSDMA4_RLC2_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC2_SKIP_CNTL 0x1d790 +#define regSDMA4_RLC2_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_CONTEXT_STATUS 0x1d791 +#define regSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC2_DOORBELL 0x1d792 +#define regSDMA4_RLC2_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC2_STATUS 0x1d7a8 +#define regSDMA4_RLC2_STATUS_BASE_IDX 0 +#define regSDMA4_RLC2_DOORBELL_LOG 0x1d7a9 +#define regSDMA4_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC2_WATERMARK 0x1d7aa +#define regSDMA4_RLC2_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC2_DOORBELL_OFFSET 0x1d7ab +#define regSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC2_CSA_ADDR_LO 0x1d7ac +#define regSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC2_CSA_ADDR_HI 0x1d7ad +#define regSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC2_IB_SUB_REMAIN 0x1d7af +#define regSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC2_PREEMPT 0x1d7b0 +#define regSDMA4_RLC2_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC2_DUMMY_REG 0x1d7b1 +#define regSDMA4_RLC2_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d7b2 +#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d7b3 +#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC2_RB_AQL_CNTL 0x1d7b4 +#define regSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC2_MINOR_PTR_UPDATE 0x1d7b5 +#define regSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA0 0x1d7c0 +#define regSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA1 0x1d7c1 +#define regSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA2 0x1d7c2 +#define regSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA3 0x1d7c3 +#define regSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA4 0x1d7c4 +#define regSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA5 0x1d7c5 +#define regSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA6 0x1d7c6 +#define regSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA7 0x1d7c7 +#define regSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA8 0x1d7c8 +#define regSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA9 0x1d7c9 +#define regSDMA4_RLC2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_DATA10 0x1d7ca +#define regSDMA4_RLC2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC2_MIDCMD_CNTL 0x1d7cb +#define regSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_RB_CNTL 0x1d7d8 +#define regSDMA4_RLC3_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_RB_BASE 0x1d7d9 +#define regSDMA4_RLC3_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC3_RB_BASE_HI 0x1d7da +#define regSDMA4_RLC3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC3_RB_RPTR 0x1d7db +#define regSDMA4_RLC3_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC3_RB_RPTR_HI 0x1d7dc +#define regSDMA4_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC3_RB_WPTR 0x1d7dd +#define regSDMA4_RLC3_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC3_RB_WPTR_HI 0x1d7de +#define regSDMA4_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL 0x1d7df +#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_RB_RPTR_ADDR_HI 0x1d7e0 +#define regSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC3_RB_RPTR_ADDR_LO 0x1d7e1 +#define regSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC3_IB_CNTL 0x1d7e2 +#define regSDMA4_RLC3_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_IB_RPTR 0x1d7e3 +#define regSDMA4_RLC3_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC3_IB_OFFSET 0x1d7e4 +#define regSDMA4_RLC3_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC3_IB_BASE_LO 0x1d7e5 +#define regSDMA4_RLC3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC3_IB_BASE_HI 0x1d7e6 +#define regSDMA4_RLC3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC3_IB_SIZE 0x1d7e7 +#define regSDMA4_RLC3_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC3_SKIP_CNTL 0x1d7e8 +#define regSDMA4_RLC3_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_CONTEXT_STATUS 0x1d7e9 +#define regSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC3_DOORBELL 0x1d7ea +#define regSDMA4_RLC3_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC3_STATUS 0x1d800 +#define regSDMA4_RLC3_STATUS_BASE_IDX 0 +#define regSDMA4_RLC3_DOORBELL_LOG 0x1d801 +#define regSDMA4_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC3_WATERMARK 0x1d802 +#define regSDMA4_RLC3_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC3_DOORBELL_OFFSET 0x1d803 +#define regSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC3_CSA_ADDR_LO 0x1d804 +#define regSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC3_CSA_ADDR_HI 0x1d805 +#define regSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC3_IB_SUB_REMAIN 0x1d807 +#define regSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC3_PREEMPT 0x1d808 +#define regSDMA4_RLC3_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC3_DUMMY_REG 0x1d809 +#define regSDMA4_RLC3_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d80a +#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d80b +#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC3_RB_AQL_CNTL 0x1d80c +#define regSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC3_MINOR_PTR_UPDATE 0x1d80d +#define regSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA0 0x1d818 +#define regSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA1 0x1d819 +#define regSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA2 0x1d81a +#define regSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA3 0x1d81b +#define regSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA4 0x1d81c +#define regSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA5 0x1d81d +#define regSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA6 0x1d81e +#define regSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA7 0x1d81f +#define regSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA8 0x1d820 +#define regSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA9 0x1d821 +#define regSDMA4_RLC3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_DATA10 0x1d822 +#define regSDMA4_RLC3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC3_MIDCMD_CNTL 0x1d823 +#define regSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_RB_CNTL 0x1d830 +#define regSDMA4_RLC4_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_RB_BASE 0x1d831 +#define regSDMA4_RLC4_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC4_RB_BASE_HI 0x1d832 +#define regSDMA4_RLC4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC4_RB_RPTR 0x1d833 +#define regSDMA4_RLC4_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC4_RB_RPTR_HI 0x1d834 +#define regSDMA4_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC4_RB_WPTR 0x1d835 +#define regSDMA4_RLC4_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC4_RB_WPTR_HI 0x1d836 +#define regSDMA4_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL 0x1d837 +#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_RB_RPTR_ADDR_HI 0x1d838 +#define regSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC4_RB_RPTR_ADDR_LO 0x1d839 +#define regSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC4_IB_CNTL 0x1d83a +#define regSDMA4_RLC4_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_IB_RPTR 0x1d83b +#define regSDMA4_RLC4_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC4_IB_OFFSET 0x1d83c +#define regSDMA4_RLC4_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC4_IB_BASE_LO 0x1d83d +#define regSDMA4_RLC4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC4_IB_BASE_HI 0x1d83e +#define regSDMA4_RLC4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC4_IB_SIZE 0x1d83f +#define regSDMA4_RLC4_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC4_SKIP_CNTL 0x1d840 +#define regSDMA4_RLC4_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_CONTEXT_STATUS 0x1d841 +#define regSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC4_DOORBELL 0x1d842 +#define regSDMA4_RLC4_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC4_STATUS 0x1d858 +#define regSDMA4_RLC4_STATUS_BASE_IDX 0 +#define regSDMA4_RLC4_DOORBELL_LOG 0x1d859 +#define regSDMA4_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC4_WATERMARK 0x1d85a +#define regSDMA4_RLC4_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC4_DOORBELL_OFFSET 0x1d85b +#define regSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC4_CSA_ADDR_LO 0x1d85c +#define regSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC4_CSA_ADDR_HI 0x1d85d +#define regSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC4_IB_SUB_REMAIN 0x1d85f +#define regSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC4_PREEMPT 0x1d860 +#define regSDMA4_RLC4_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC4_DUMMY_REG 0x1d861 +#define regSDMA4_RLC4_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d862 +#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d863 +#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC4_RB_AQL_CNTL 0x1d864 +#define regSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC4_MINOR_PTR_UPDATE 0x1d865 +#define regSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA0 0x1d870 +#define regSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA1 0x1d871 +#define regSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA2 0x1d872 +#define regSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA3 0x1d873 +#define regSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA4 0x1d874 +#define regSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA5 0x1d875 +#define regSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA6 0x1d876 +#define regSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA7 0x1d877 +#define regSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA8 0x1d878 +#define regSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA9 0x1d879 +#define regSDMA4_RLC4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_DATA10 0x1d87a +#define regSDMA4_RLC4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC4_MIDCMD_CNTL 0x1d87b +#define regSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_RB_CNTL 0x1d888 +#define regSDMA4_RLC5_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_RB_BASE 0x1d889 +#define regSDMA4_RLC5_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC5_RB_BASE_HI 0x1d88a +#define regSDMA4_RLC5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC5_RB_RPTR 0x1d88b +#define regSDMA4_RLC5_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC5_RB_RPTR_HI 0x1d88c +#define regSDMA4_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC5_RB_WPTR 0x1d88d +#define regSDMA4_RLC5_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC5_RB_WPTR_HI 0x1d88e +#define regSDMA4_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL 0x1d88f +#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_RB_RPTR_ADDR_HI 0x1d890 +#define regSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC5_RB_RPTR_ADDR_LO 0x1d891 +#define regSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC5_IB_CNTL 0x1d892 +#define regSDMA4_RLC5_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_IB_RPTR 0x1d893 +#define regSDMA4_RLC5_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC5_IB_OFFSET 0x1d894 +#define regSDMA4_RLC5_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC5_IB_BASE_LO 0x1d895 +#define regSDMA4_RLC5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC5_IB_BASE_HI 0x1d896 +#define regSDMA4_RLC5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC5_IB_SIZE 0x1d897 +#define regSDMA4_RLC5_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC5_SKIP_CNTL 0x1d898 +#define regSDMA4_RLC5_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_CONTEXT_STATUS 0x1d899 +#define regSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC5_DOORBELL 0x1d89a +#define regSDMA4_RLC5_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC5_STATUS 0x1d8b0 +#define regSDMA4_RLC5_STATUS_BASE_IDX 0 +#define regSDMA4_RLC5_DOORBELL_LOG 0x1d8b1 +#define regSDMA4_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC5_WATERMARK 0x1d8b2 +#define regSDMA4_RLC5_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC5_DOORBELL_OFFSET 0x1d8b3 +#define regSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC5_CSA_ADDR_LO 0x1d8b4 +#define regSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC5_CSA_ADDR_HI 0x1d8b5 +#define regSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC5_IB_SUB_REMAIN 0x1d8b7 +#define regSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC5_PREEMPT 0x1d8b8 +#define regSDMA4_RLC5_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC5_DUMMY_REG 0x1d8b9 +#define regSDMA4_RLC5_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d8ba +#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d8bb +#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC5_RB_AQL_CNTL 0x1d8bc +#define regSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC5_MINOR_PTR_UPDATE 0x1d8bd +#define regSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA0 0x1d8c8 +#define regSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA1 0x1d8c9 +#define regSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA2 0x1d8ca +#define regSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA3 0x1d8cb +#define regSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA4 0x1d8cc +#define regSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA5 0x1d8cd +#define regSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA6 0x1d8ce +#define regSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA7 0x1d8cf +#define regSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA8 0x1d8d0 +#define regSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA9 0x1d8d1 +#define regSDMA4_RLC5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_DATA10 0x1d8d2 +#define regSDMA4_RLC5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC5_MIDCMD_CNTL 0x1d8d3 +#define regSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_RB_CNTL 0x1d8e0 +#define regSDMA4_RLC6_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_RB_BASE 0x1d8e1 +#define regSDMA4_RLC6_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC6_RB_BASE_HI 0x1d8e2 +#define regSDMA4_RLC6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC6_RB_RPTR 0x1d8e3 +#define regSDMA4_RLC6_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC6_RB_RPTR_HI 0x1d8e4 +#define regSDMA4_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC6_RB_WPTR 0x1d8e5 +#define regSDMA4_RLC6_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC6_RB_WPTR_HI 0x1d8e6 +#define regSDMA4_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL 0x1d8e7 +#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_RB_RPTR_ADDR_HI 0x1d8e8 +#define regSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC6_RB_RPTR_ADDR_LO 0x1d8e9 +#define regSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC6_IB_CNTL 0x1d8ea +#define regSDMA4_RLC6_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_IB_RPTR 0x1d8eb +#define regSDMA4_RLC6_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC6_IB_OFFSET 0x1d8ec +#define regSDMA4_RLC6_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC6_IB_BASE_LO 0x1d8ed +#define regSDMA4_RLC6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC6_IB_BASE_HI 0x1d8ee +#define regSDMA4_RLC6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC6_IB_SIZE 0x1d8ef +#define regSDMA4_RLC6_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC6_SKIP_CNTL 0x1d8f0 +#define regSDMA4_RLC6_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_CONTEXT_STATUS 0x1d8f1 +#define regSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC6_DOORBELL 0x1d8f2 +#define regSDMA4_RLC6_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC6_STATUS 0x1d908 +#define regSDMA4_RLC6_STATUS_BASE_IDX 0 +#define regSDMA4_RLC6_DOORBELL_LOG 0x1d909 +#define regSDMA4_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC6_WATERMARK 0x1d90a +#define regSDMA4_RLC6_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC6_DOORBELL_OFFSET 0x1d90b +#define regSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC6_CSA_ADDR_LO 0x1d90c +#define regSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC6_CSA_ADDR_HI 0x1d90d +#define regSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC6_IB_SUB_REMAIN 0x1d90f +#define regSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC6_PREEMPT 0x1d910 +#define regSDMA4_RLC6_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC6_DUMMY_REG 0x1d911 +#define regSDMA4_RLC6_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d912 +#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d913 +#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC6_RB_AQL_CNTL 0x1d914 +#define regSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC6_MINOR_PTR_UPDATE 0x1d915 +#define regSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA0 0x1d920 +#define regSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA1 0x1d921 +#define regSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA2 0x1d922 +#define regSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA3 0x1d923 +#define regSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA4 0x1d924 +#define regSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA5 0x1d925 +#define regSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA6 0x1d926 +#define regSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA7 0x1d927 +#define regSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA8 0x1d928 +#define regSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA9 0x1d929 +#define regSDMA4_RLC6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_DATA10 0x1d92a +#define regSDMA4_RLC6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC6_MIDCMD_CNTL 0x1d92b +#define regSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_RB_CNTL 0x1d938 +#define regSDMA4_RLC7_RB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_RB_BASE 0x1d939 +#define regSDMA4_RLC7_RB_BASE_BASE_IDX 0 +#define regSDMA4_RLC7_RB_BASE_HI 0x1d93a +#define regSDMA4_RLC7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC7_RB_RPTR 0x1d93b +#define regSDMA4_RLC7_RB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC7_RB_RPTR_HI 0x1d93c +#define regSDMA4_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC7_RB_WPTR 0x1d93d +#define regSDMA4_RLC7_RB_WPTR_BASE_IDX 0 +#define regSDMA4_RLC7_RB_WPTR_HI 0x1d93e +#define regSDMA4_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL 0x1d93f +#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_RB_RPTR_ADDR_HI 0x1d940 +#define regSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC7_RB_RPTR_ADDR_LO 0x1d941 +#define regSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC7_IB_CNTL 0x1d942 +#define regSDMA4_RLC7_IB_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_IB_RPTR 0x1d943 +#define regSDMA4_RLC7_IB_RPTR_BASE_IDX 0 +#define regSDMA4_RLC7_IB_OFFSET 0x1d944 +#define regSDMA4_RLC7_IB_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC7_IB_BASE_LO 0x1d945 +#define regSDMA4_RLC7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA4_RLC7_IB_BASE_HI 0x1d946 +#define regSDMA4_RLC7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA4_RLC7_IB_SIZE 0x1d947 +#define regSDMA4_RLC7_IB_SIZE_BASE_IDX 0 +#define regSDMA4_RLC7_SKIP_CNTL 0x1d948 +#define regSDMA4_RLC7_SKIP_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_CONTEXT_STATUS 0x1d949 +#define regSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA4_RLC7_DOORBELL 0x1d94a +#define regSDMA4_RLC7_DOORBELL_BASE_IDX 0 +#define regSDMA4_RLC7_STATUS 0x1d960 +#define regSDMA4_RLC7_STATUS_BASE_IDX 0 +#define regSDMA4_RLC7_DOORBELL_LOG 0x1d961 +#define regSDMA4_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA4_RLC7_WATERMARK 0x1d962 +#define regSDMA4_RLC7_WATERMARK_BASE_IDX 0 +#define regSDMA4_RLC7_DOORBELL_OFFSET 0x1d963 +#define regSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA4_RLC7_CSA_ADDR_LO 0x1d964 +#define regSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC7_CSA_ADDR_HI 0x1d965 +#define regSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC7_IB_SUB_REMAIN 0x1d967 +#define regSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA4_RLC7_PREEMPT 0x1d968 +#define regSDMA4_RLC7_PREEMPT_BASE_IDX 0 +#define regSDMA4_RLC7_DUMMY_REG 0x1d969 +#define regSDMA4_RLC7_DUMMY_REG_BASE_IDX 0 +#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d96a +#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d96b +#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA4_RLC7_RB_AQL_CNTL 0x1d96c +#define regSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA4_RLC7_MINOR_PTR_UPDATE 0x1d96d +#define regSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA0 0x1d978 +#define regSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA1 0x1d979 +#define regSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA2 0x1d97a +#define regSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA3 0x1d97b +#define regSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA4 0x1d97c +#define regSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA5 0x1d97d +#define regSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA6 0x1d97e +#define regSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA7 0x1d97f +#define regSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA8 0x1d980 +#define regSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA9 0x1d981 +#define regSDMA4_RLC7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_DATA10 0x1d982 +#define regSDMA4_RLC7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA4_RLC7_MIDCMD_CNTL 0x1d983 +#define regSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..4464af3be22dd78405e699bea90a454e9363291b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h @@ -0,0 +1,13922 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _sdma_4_4_0_SH_MASK_HEADER +#define _sdma_4_4_0_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VF_ENABLE +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1b +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L +#define SDMA0_CHICKEN_BITS__RESERVED_MASK 0xF8000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__RESET__SHIFT 0x8 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +#define SDMA0_F32_CNTL__RESET_MASK 0x00000100L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//CC_SDMA0_EDC_CONFIG +#define CC_SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L +//SDMA0_EDC_COUNTER2 +#define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 +#define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L +#define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL +#define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L +#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L +#define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L +#define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L +#define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L +#define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 +#define SDMA0_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 +#define SDMA0_UTCL1_WATERMK__RESERVED__SHIFT 0x10 +#define SDMA0_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L +#define SDMA0_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L +#define SDMA0_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L +#define SDMA0_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_PHASE2_QUANTUM +#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PERFCNT_PERFCOUNTER0_CFG +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA0_PERFCNT_PERFCOUNTER1_CFG +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA0_PERFCNT_MISC_CNTL +#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA0_PERFCNT_PERFCOUNTER_LO +#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_PERFCNT_PERFCOUNTER_HI +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_STATUS4_REG +#define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 +#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 +#define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0x8 +#define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0x9 +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc +#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe +#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 +#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 +#define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L +#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L +#define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000100L +#define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000200L +#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L +#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L +#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L +#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L +#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L +//SDMA0_SCRATCH_RAM_DATA +#define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA0_SCRATCH_RAM_ADDR +#define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA0_CE_CTRL +#define SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA0_CE_CTRL__RESERVED__SHIFT 0x8 +#define SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA0_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//SDMA0_RAS_STATUS +#define SDMA0_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA0_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA0_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA0_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA0_RAS_STATUS__SRAM_ECC__SHIFT 0x5 +#define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 +#define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 +#define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa +#define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb +#define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc +#define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd +#define SDMA0_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA0_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA0_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA0_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA0_RAS_STATUS__SRAM_ECC_MASK 0x00000020L +#define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L +#define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L +#define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L +#define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L +#define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L +#define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L +//SDMA0_CLK_STATUS +#define SDMA0_CLK_STATUS__DYN_CLK__SHIFT 0x0 +#define SDMA0_CLK_STATUS__PTR_CLK__SHIFT 0x1 +#define SDMA0_CLK_STATUS__REG_CLK__SHIFT 0x2 +#define SDMA0_CLK_STATUS__F32_CLK__SHIFT 0x3 +#define SDMA0_CLK_STATUS__DYN_CLK_MASK 0x00000001L +#define SDMA0_CLK_STATUS__PTR_CLK_MASK 0x00000002L +#define SDMA0_CLK_STATUS__REG_CLK_MASK 0x00000004L +#define SDMA0_CLK_STATUS__F32_CLK_MASK 0x00000008L +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA9 +#define SDMA0_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA10 +#define SDMA0_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_PAGE_RB_CNTL +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_PAGE_RB_BASE +#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_BASE_HI +#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_PAGE_RB_RPTR +#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_HI +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR +#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_HI +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_CNTL +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_PAGE_RB_RPTR_ADDR_HI +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_ADDR_LO +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_IB_CNTL +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_PAGE_IB_RPTR +#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_OFFSET +#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_BASE_LO +#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_PAGE_IB_BASE_HI +#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SIZE +#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_SKIP_CNTL +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_PAGE_CONTEXT_STATUS +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_PAGE_DOORBELL +#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_PAGE_STATUS +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_PAGE_DOORBELL_LOG +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_PAGE_WATERMARK +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_PAGE_DOORBELL_OFFSET +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_PAGE_CSA_ADDR_LO +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_CSA_ADDR_HI +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SUB_REMAIN +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_PREEMPT +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_PAGE_DUMMY_REG +#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_RB_AQL_CNTL +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_PAGE_MINOR_PTR_UPDATE +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_PAGE_MIDCMD_DATA0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA1 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA2 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA3 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA4 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA5 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA6 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA7 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA8 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA9 +#define SDMA0_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA10 +#define SDMA0_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_CNTL +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA9 +#define SDMA0_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA10 +#define SDMA0_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA9 +#define SDMA0_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA10 +#define SDMA0_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC2_RB_CNTL +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC2_RB_BASE +#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_BASE_HI +#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC2_RB_RPTR +#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_HI +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR +#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_HI +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_CNTL +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC2_RB_RPTR_ADDR_HI +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_ADDR_LO +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_IB_CNTL +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC2_IB_RPTR +#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_OFFSET +#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_BASE_LO +#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC2_IB_BASE_HI +#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SIZE +#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_SKIP_CNTL +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC2_CONTEXT_STATUS +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC2_DOORBELL +#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC2_STATUS +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC2_DOORBELL_LOG +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC2_WATERMARK +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC2_DOORBELL_OFFSET +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC2_CSA_ADDR_LO +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_CSA_ADDR_HI +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SUB_REMAIN +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_PREEMPT +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC2_DUMMY_REG +#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_RB_AQL_CNTL +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC2_MINOR_PTR_UPDATE +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC2_MIDCMD_DATA0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA1 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA2 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA3 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA4 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA5 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA6 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA7 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA8 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA9 +#define SDMA0_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA10 +#define SDMA0_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_CNTL +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC3_RB_CNTL +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC3_RB_BASE +#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_BASE_HI +#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC3_RB_RPTR +#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_HI +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR +#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_HI +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_CNTL +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC3_RB_RPTR_ADDR_HI +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_ADDR_LO +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_IB_CNTL +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC3_IB_RPTR +#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_OFFSET +#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_BASE_LO +#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC3_IB_BASE_HI +#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SIZE +#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_SKIP_CNTL +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC3_CONTEXT_STATUS +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC3_DOORBELL +#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC3_STATUS +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC3_DOORBELL_LOG +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC3_WATERMARK +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC3_DOORBELL_OFFSET +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC3_CSA_ADDR_LO +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_CSA_ADDR_HI +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SUB_REMAIN +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_PREEMPT +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC3_DUMMY_REG +#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_RB_AQL_CNTL +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC3_MINOR_PTR_UPDATE +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC3_MIDCMD_DATA0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA1 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA2 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA3 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA4 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA5 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA6 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA7 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA8 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA9 +#define SDMA0_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA10 +#define SDMA0_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_CNTL +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC4_RB_CNTL +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC4_RB_BASE +#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_BASE_HI +#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC4_RB_RPTR +#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_HI +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR +#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_HI +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_CNTL +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC4_RB_RPTR_ADDR_HI +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_ADDR_LO +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_IB_CNTL +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC4_IB_RPTR +#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_OFFSET +#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_BASE_LO +#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC4_IB_BASE_HI +#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SIZE +#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_SKIP_CNTL +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC4_CONTEXT_STATUS +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC4_DOORBELL +#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC4_STATUS +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC4_DOORBELL_LOG +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC4_WATERMARK +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC4_DOORBELL_OFFSET +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC4_CSA_ADDR_LO +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_CSA_ADDR_HI +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SUB_REMAIN +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_PREEMPT +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC4_DUMMY_REG +#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_RB_AQL_CNTL +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC4_MINOR_PTR_UPDATE +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC4_MIDCMD_DATA0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA1 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA2 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA3 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA4 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA5 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA6 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA7 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA8 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA9 +#define SDMA0_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA10 +#define SDMA0_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_CNTL +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC5_RB_CNTL +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC5_RB_BASE +#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_BASE_HI +#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC5_RB_RPTR +#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_HI +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR +#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_HI +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_CNTL +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC5_RB_RPTR_ADDR_HI +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_ADDR_LO +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_IB_CNTL +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC5_IB_RPTR +#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_OFFSET +#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_BASE_LO +#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC5_IB_BASE_HI +#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SIZE +#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_SKIP_CNTL +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC5_CONTEXT_STATUS +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC5_DOORBELL +#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC5_STATUS +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC5_DOORBELL_LOG +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC5_WATERMARK +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC5_DOORBELL_OFFSET +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC5_CSA_ADDR_LO +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_CSA_ADDR_HI +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SUB_REMAIN +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_PREEMPT +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC5_DUMMY_REG +#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_RB_AQL_CNTL +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC5_MINOR_PTR_UPDATE +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC5_MIDCMD_DATA0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA1 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA2 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA3 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA4 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA5 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA6 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA7 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA8 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA9 +#define SDMA0_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA10 +#define SDMA0_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_CNTL +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC6_RB_CNTL +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC6_RB_BASE +#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_BASE_HI +#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC6_RB_RPTR +#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_HI +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR +#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_HI +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_CNTL +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC6_RB_RPTR_ADDR_HI +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_ADDR_LO +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_IB_CNTL +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC6_IB_RPTR +#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_OFFSET +#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_BASE_LO +#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC6_IB_BASE_HI +#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SIZE +#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_SKIP_CNTL +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC6_CONTEXT_STATUS +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC6_DOORBELL +#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC6_STATUS +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC6_DOORBELL_LOG +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC6_WATERMARK +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC6_DOORBELL_OFFSET +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC6_CSA_ADDR_LO +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_CSA_ADDR_HI +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SUB_REMAIN +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_PREEMPT +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC6_DUMMY_REG +#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_RB_AQL_CNTL +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC6_MINOR_PTR_UPDATE +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC6_MIDCMD_DATA0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA1 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA2 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA3 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA4 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA5 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA6 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA7 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA8 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA9 +#define SDMA0_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA10 +#define SDMA0_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_CNTL +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC7_RB_CNTL +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC7_RB_BASE +#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_BASE_HI +#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC7_RB_RPTR +#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_HI +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR +#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_HI +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_CNTL +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC7_RB_RPTR_ADDR_HI +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_ADDR_LO +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_IB_CNTL +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC7_IB_RPTR +#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_OFFSET +#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_BASE_LO +#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC7_IB_BASE_HI +#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SIZE +#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_SKIP_CNTL +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC7_CONTEXT_STATUS +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC7_DOORBELL +#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC7_STATUS +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC7_DOORBELL_LOG +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC7_WATERMARK +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC7_DOORBELL_OFFSET +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC7_CSA_ADDR_LO +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_CSA_ADDR_HI +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SUB_REMAIN +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_PREEMPT +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC7_DUMMY_REG +#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_RB_AQL_CNTL +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC7_MINOR_PTR_UPDATE +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC7_MIDCMD_DATA0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA1 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA2 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA3 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA4 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA5 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA6 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA7 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA8 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA9 +#define SDMA0_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA10 +#define SDMA0_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_CNTL +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: sdma0_sdma1dec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_VF_ENABLE +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L +//SDMA1_CONTEXT_GROUP_BOUNDARY +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA1_CLK_CTRL +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__RESERVED__SHIFT 0x1b +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L +#define SDMA1_CHICKEN_BITS__RESERVED_MASK 0xF8000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA1_RD_BURST_CNTL +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__RESET__SHIFT 0x8 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L +#define SDMA1_F32_CNTL__RESET_MASK 0x00000100L +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PHASE0_QUANTUM +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_PHASE1_QUANTUM +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//CC_SDMA1_EDC_CONFIG +#define CC_SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L +//SDMA1_EDC_COUNTER2 +#define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 +#define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L +#define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL +#define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L +#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L +#define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L +#define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L +#define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L +#define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 +#define SDMA1_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 +#define SDMA1_UTCL1_WATERMK__RESERVED__SHIFT 0x10 +#define SDMA1_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L +#define SDMA1_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L +#define SDMA1_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L +#define SDMA1_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA1_POWER_CNTL_IDLE +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_PHASE2_QUANTUM +#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PERFCNT_PERFCOUNTER0_CFG +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA1_PERFCNT_PERFCOUNTER1_CFG +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA1_PERFCNT_MISC_CNTL +#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA1_PERFCNT_PERFCOUNTER_LO +#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_PERFCNT_PERFCOUNTER_HI +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA1_ULV_CNTL +#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_STATUS4_REG +#define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 +#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 +#define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0x8 +#define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0x9 +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc +#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe +#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 +#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 +#define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L +#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L +#define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000100L +#define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000200L +#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L +#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L +#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L +#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L +#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L +//SDMA1_SCRATCH_RAM_DATA +#define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA1_SCRATCH_RAM_ADDR +#define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA1_CE_CTRL +#define SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA1_CE_CTRL__RESERVED__SHIFT 0x8 +#define SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA1_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//SDMA1_RAS_STATUS +#define SDMA1_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA1_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA1_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA1_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA1_RAS_STATUS__SRAM_ECC__SHIFT 0x5 +#define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 +#define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 +#define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa +#define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb +#define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc +#define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd +#define SDMA1_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA1_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA1_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA1_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA1_RAS_STATUS__SRAM_ECC_MASK 0x00000020L +#define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L +#define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L +#define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L +#define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L +#define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L +#define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L +//SDMA1_CLK_STATUS +#define SDMA1_CLK_STATUS__DYN_CLK__SHIFT 0x0 +#define SDMA1_CLK_STATUS__PTR_CLK__SHIFT 0x1 +#define SDMA1_CLK_STATUS__REG_CLK__SHIFT 0x2 +#define SDMA1_CLK_STATUS__F32_CLK__SHIFT 0x3 +#define SDMA1_CLK_STATUS__DYN_CLK_MASK 0x00000001L +#define SDMA1_CLK_STATUS__PTR_CLK_MASK 0x00000002L +#define SDMA1_CLK_STATUS__REG_CLK_MASK 0x00000004L +#define SDMA1_CLK_STATUS__F32_CLK_MASK 0x00000008L +//SDMA1_GFX_RB_CNTL +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_GFX_RB_BASE +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_BASE_HI +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_GFX_RB_RPTR +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_HI +#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_HI +#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_CNTL +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_GFX_RB_RPTR_ADDR_HI +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_ADDR_LO +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_IB_CNTL +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_GFX_IB_RPTR +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_OFFSET +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_BASE_LO +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_GFX_IB_BASE_HI +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SIZE +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_SKIP_CNTL +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_GFX_CONTEXT_STATUS +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_GFX_DOORBELL +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_GFX_CONTEXT_CNTL +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L +//SDMA1_GFX_STATUS +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_GFX_DOORBELL_LOG +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_GFX_WATERMARK +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_GFX_DOORBELL_OFFSET +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_GFX_CSA_ADDR_LO +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_CSA_ADDR_HI +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SUB_REMAIN +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_PREEMPT +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_GFX_DUMMY_REG +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_RB_AQL_CNTL +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_GFX_MINOR_PTR_UPDATE +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_GFX_MIDCMD_DATA0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA1 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA2 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA3 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA4 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA5 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA6 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA7 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA8 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA9 +#define SDMA1_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA10 +#define SDMA1_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_CNTL +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_PAGE_RB_CNTL +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_PAGE_RB_BASE +#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_BASE_HI +#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_PAGE_RB_RPTR +#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_HI +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR +#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_HI +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_CNTL +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_PAGE_RB_RPTR_ADDR_HI +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_ADDR_LO +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_IB_CNTL +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_PAGE_IB_RPTR +#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_OFFSET +#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_BASE_LO +#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_PAGE_IB_BASE_HI +#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SIZE +#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_SKIP_CNTL +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_PAGE_CONTEXT_STATUS +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_PAGE_DOORBELL +#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_PAGE_STATUS +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_PAGE_DOORBELL_LOG +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_PAGE_WATERMARK +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_PAGE_DOORBELL_OFFSET +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_PAGE_CSA_ADDR_LO +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_CSA_ADDR_HI +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SUB_REMAIN +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_PREEMPT +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_PAGE_DUMMY_REG +#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_RB_AQL_CNTL +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_PAGE_MINOR_PTR_UPDATE +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_PAGE_MIDCMD_DATA0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA1 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA2 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA3 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA4 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA5 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA6 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA7 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA8 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA9 +#define SDMA1_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA10 +#define SDMA1_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_CNTL +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC0_RB_CNTL +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC0_RB_BASE +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_BASE_HI +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC0_RB_RPTR +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_HI +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_HI +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_CNTL +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC0_RB_RPTR_ADDR_HI +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_ADDR_LO +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_IB_CNTL +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC0_IB_RPTR +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_OFFSET +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_BASE_LO +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC0_IB_BASE_HI +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SIZE +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_SKIP_CNTL +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC0_CONTEXT_STATUS +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC0_DOORBELL +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC0_STATUS +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC0_DOORBELL_LOG +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC0_WATERMARK +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC0_DOORBELL_OFFSET +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC0_CSA_ADDR_LO +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_CSA_ADDR_HI +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SUB_REMAIN +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_PREEMPT +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC0_DUMMY_REG +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_RB_AQL_CNTL +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC0_MINOR_PTR_UPDATE +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC0_MIDCMD_DATA0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA1 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA2 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA3 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA4 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA5 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA6 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA7 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA8 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA9 +#define SDMA1_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA10 +#define SDMA1_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_CNTL +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC1_RB_CNTL +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC1_RB_BASE +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_BASE_HI +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC1_RB_RPTR +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_HI +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_HI +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_CNTL +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC1_RB_RPTR_ADDR_HI +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_ADDR_LO +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_IB_CNTL +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC1_IB_RPTR +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_OFFSET +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_BASE_LO +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC1_IB_BASE_HI +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SIZE +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_SKIP_CNTL +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC1_CONTEXT_STATUS +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC1_DOORBELL +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC1_STATUS +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC1_DOORBELL_LOG +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC1_WATERMARK +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC1_DOORBELL_OFFSET +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC1_CSA_ADDR_LO +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_CSA_ADDR_HI +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SUB_REMAIN +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_PREEMPT +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC1_DUMMY_REG +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_RB_AQL_CNTL +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC1_MINOR_PTR_UPDATE +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC1_MIDCMD_DATA0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA1 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA2 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA3 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA4 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA5 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA6 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA7 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA8 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA9 +#define SDMA1_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA10 +#define SDMA1_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_CNTL +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC2_RB_CNTL +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC2_RB_BASE +#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_BASE_HI +#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC2_RB_RPTR +#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_HI +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR +#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_HI +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_CNTL +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC2_RB_RPTR_ADDR_HI +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_ADDR_LO +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_IB_CNTL +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC2_IB_RPTR +#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_OFFSET +#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_BASE_LO +#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC2_IB_BASE_HI +#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SIZE +#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_SKIP_CNTL +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC2_CONTEXT_STATUS +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC2_DOORBELL +#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC2_STATUS +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC2_DOORBELL_LOG +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC2_WATERMARK +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC2_DOORBELL_OFFSET +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC2_CSA_ADDR_LO +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_CSA_ADDR_HI +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SUB_REMAIN +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_PREEMPT +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC2_DUMMY_REG +#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_RB_AQL_CNTL +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC2_MINOR_PTR_UPDATE +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC2_MIDCMD_DATA0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA1 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA2 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA3 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA4 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA5 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA6 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA7 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA8 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA9 +#define SDMA1_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA10 +#define SDMA1_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_CNTL +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC3_RB_CNTL +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC3_RB_BASE +#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_BASE_HI +#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC3_RB_RPTR +#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_HI +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR +#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_HI +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_CNTL +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC3_RB_RPTR_ADDR_HI +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_ADDR_LO +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_IB_CNTL +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC3_IB_RPTR +#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_OFFSET +#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_BASE_LO +#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC3_IB_BASE_HI +#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SIZE +#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_SKIP_CNTL +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC3_CONTEXT_STATUS +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC3_DOORBELL +#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC3_STATUS +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC3_DOORBELL_LOG +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC3_WATERMARK +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC3_DOORBELL_OFFSET +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC3_CSA_ADDR_LO +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_CSA_ADDR_HI +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SUB_REMAIN +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_PREEMPT +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC3_DUMMY_REG +#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_RB_AQL_CNTL +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC3_MINOR_PTR_UPDATE +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC3_MIDCMD_DATA0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA1 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA2 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA3 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA4 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA5 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA6 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA7 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA8 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA9 +#define SDMA1_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA10 +#define SDMA1_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_CNTL +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC4_RB_CNTL +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC4_RB_BASE +#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_BASE_HI +#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC4_RB_RPTR +#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_HI +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR +#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_HI +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_CNTL +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC4_RB_RPTR_ADDR_HI +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_ADDR_LO +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_IB_CNTL +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC4_IB_RPTR +#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_OFFSET +#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_BASE_LO +#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC4_IB_BASE_HI +#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SIZE +#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_SKIP_CNTL +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC4_CONTEXT_STATUS +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC4_DOORBELL +#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC4_STATUS +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC4_DOORBELL_LOG +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC4_WATERMARK +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC4_DOORBELL_OFFSET +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC4_CSA_ADDR_LO +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_CSA_ADDR_HI +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SUB_REMAIN +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_PREEMPT +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC4_DUMMY_REG +#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_RB_AQL_CNTL +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC4_MINOR_PTR_UPDATE +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC4_MIDCMD_DATA0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA1 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA2 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA3 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA4 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA5 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA6 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA7 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA8 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA9 +#define SDMA1_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA10 +#define SDMA1_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_CNTL +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC5_RB_CNTL +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC5_RB_BASE +#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_BASE_HI +#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC5_RB_RPTR +#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_HI +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR +#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_HI +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_CNTL +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC5_RB_RPTR_ADDR_HI +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_ADDR_LO +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_IB_CNTL +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC5_IB_RPTR +#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_OFFSET +#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_BASE_LO +#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC5_IB_BASE_HI +#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SIZE +#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_SKIP_CNTL +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC5_CONTEXT_STATUS +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC5_DOORBELL +#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC5_STATUS +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC5_DOORBELL_LOG +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC5_WATERMARK +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC5_DOORBELL_OFFSET +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC5_CSA_ADDR_LO +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_CSA_ADDR_HI +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SUB_REMAIN +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_PREEMPT +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC5_DUMMY_REG +#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_RB_AQL_CNTL +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC5_MINOR_PTR_UPDATE +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC5_MIDCMD_DATA0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA1 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA2 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA3 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA4 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA5 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA6 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA7 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA8 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA9 +#define SDMA1_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA10 +#define SDMA1_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_CNTL +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC6_RB_CNTL +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC6_RB_BASE +#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_BASE_HI +#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC6_RB_RPTR +#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_HI +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR +#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_HI +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_CNTL +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC6_RB_RPTR_ADDR_HI +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_ADDR_LO +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_IB_CNTL +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC6_IB_RPTR +#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_OFFSET +#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_BASE_LO +#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC6_IB_BASE_HI +#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SIZE +#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_SKIP_CNTL +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC6_CONTEXT_STATUS +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC6_DOORBELL +#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC6_STATUS +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC6_DOORBELL_LOG +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC6_WATERMARK +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC6_DOORBELL_OFFSET +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC6_CSA_ADDR_LO +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_CSA_ADDR_HI +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SUB_REMAIN +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_PREEMPT +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC6_DUMMY_REG +#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_RB_AQL_CNTL +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC6_MINOR_PTR_UPDATE +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC6_MIDCMD_DATA0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA1 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA2 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA3 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA4 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA5 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA6 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA7 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA8 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA9 +#define SDMA1_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA10 +#define SDMA1_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_CNTL +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC7_RB_CNTL +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC7_RB_BASE +#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_BASE_HI +#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC7_RB_RPTR +#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_HI +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR +#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_HI +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_CNTL +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC7_RB_RPTR_ADDR_HI +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_ADDR_LO +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_IB_CNTL +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC7_IB_RPTR +#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_OFFSET +#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_BASE_LO +#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC7_IB_BASE_HI +#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SIZE +#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_SKIP_CNTL +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC7_CONTEXT_STATUS +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC7_DOORBELL +#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC7_STATUS +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC7_DOORBELL_LOG +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC7_WATERMARK +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC7_DOORBELL_OFFSET +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC7_CSA_ADDR_LO +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_CSA_ADDR_HI +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SUB_REMAIN +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_PREEMPT +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC7_DUMMY_REG +#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_RB_AQL_CNTL +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC7_MINOR_PTR_UPDATE +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC7_MIDCMD_DATA0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA1 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA2 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA3 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA4 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA5 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA6 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA7 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA8 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA9 +#define SDMA1_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA10 +#define SDMA1_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_CNTL +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: sdma0_sdma2dec +//SDMA2_UCODE_ADDR +#define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_ADDR__VALUE_MASK 0x00003FFFL +//SDMA2_UCODE_DATA +#define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_VF_ENABLE +#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L +//SDMA2_CONTEXT_GROUP_BOUNDARY +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA2_POWER_CNTL +#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA2_CLK_CTRL +#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA2_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA2_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA2_CNTL +#define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA2_CHICKEN_BITS +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a +#define SDMA2_CHICKEN_BITS__RESERVED__SHIFT 0x1b +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L +#define SDMA2_CHICKEN_BITS__RESERVED_MASK 0xF8000000L +//SDMA2_GB_ADDR_CONFIG +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_GB_ADDR_CONFIG_READ +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_RB_RPTR_FETCH_HI +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA2_RB_RPTR_FETCH +#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA2_IB_OFFSET_FETCH +#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA2_PROGRAM +#define SDMA2_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA2_STATUS_REG +#define SDMA2_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA2_STATUS1_REG +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA2_RD_BURST_CNTL +#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA2_HBM_PAGE_CONFIG +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA2_UCODE_CHECKSUM +#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA2_F32_CNTL +#define SDMA2_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA2_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA2_F32_CNTL__RESET__SHIFT 0x8 +#define SDMA2_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA2_F32_CNTL__STEP_MASK 0x00000002L +#define SDMA2_F32_CNTL__RESET_MASK 0x00000100L +//SDMA2_FREEZE +#define SDMA2_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA2_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA2_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA2_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA2_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA2_PHASE0_QUANTUM +#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_PHASE1_QUANTUM +#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//CC_SDMA2_EDC_CONFIG +#define CC_SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//SDMA2_BA_THRESHOLD +#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA2_ID +#define SDMA2_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA2_VERSION +#define SDMA2_VERSION__MINVER__SHIFT 0x0 +#define SDMA2_VERSION__MAJVER__SHIFT 0x8 +#define SDMA2_VERSION__REV__SHIFT 0x10 +#define SDMA2_VERSION__MINVER_MASK 0x0000007FL +#define SDMA2_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA2_VERSION__REV_MASK 0x003F0000L +//SDMA2_EDC_COUNTER +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L +//SDMA2_EDC_COUNTER2 +#define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa +#define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc +#define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe +#define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 +#define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L +#define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL +#define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L +#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L +#define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L +#define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L +#define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L +#define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L +//SDMA2_STATUS2_REG +#define SDMA2_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA2_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA2_ATOMIC_CNTL +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA2_ATOMIC_PREOP_LO +#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA2_ATOMIC_PREOP_HI +#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_CNTL +#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA2_UTCL1_WATERMK +#define SDMA2_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 +#define SDMA2_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 +#define SDMA2_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 +#define SDMA2_UTCL1_WATERMK__RESERVED__SHIFT 0x10 +#define SDMA2_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L +#define SDMA2_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L +#define SDMA2_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L +#define SDMA2_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L +//SDMA2_UTCL1_RD_STATUS +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA2_UTCL1_WR_STATUS +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA2_UTCL1_INV0 +#define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA2_UTCL1_INV1 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_INV2 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK1 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_WR_XNACK0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_WR_XNACK1 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_TIMEOUT +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA2_UTCL1_PAGE +#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA2_POWER_CNTL_IDLE +#define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA2_RELAX_ORDERING_LUT +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA2_CHICKEN_BITS_2 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +//SDMA2_STATUS3_REG +#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA2_PHYSICAL_ADDR_LO +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA2_PHYSICAL_ADDR_HI +#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA2_PHASE2_QUANTUM +#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_ERROR_LOG +#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA2_PUB_DUMMY_REG0 +#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG1 +#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG2 +#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG3 +#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA2_F32_COUNTER +#define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PERFCNT_PERFCOUNTER0_CFG +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA2_PERFCNT_PERFCOUNTER1_CFG +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA2_PERFCNT_MISC_CNTL +#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA2_PERFCNT_PERFCOUNTER_LO +#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA2_PERFCNT_PERFCOUNTER_HI +#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA2_CRD_CNTL +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA2_ULV_CNTL +#define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA2_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA2_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA2_EA_DBIT_ADDR_DATA +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_EA_DBIT_ADDR_INDEX +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA2_STATUS4_REG +#define SDMA2_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA2_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA2_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 +#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 +#define SDMA2_STATUS4_REG__REG_POLLING__SHIFT 0x8 +#define SDMA2_STATUS4_REG__MEM_POLLING__SHIFT 0x9 +#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa +#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc +#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe +#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 +#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 +#define SDMA2_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA2_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA2_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L +#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L +#define SDMA2_STATUS4_REG__REG_POLLING_MASK 0x00000100L +#define SDMA2_STATUS4_REG__MEM_POLLING_MASK 0x00000200L +#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L +#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L +#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L +#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L +#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L +//SDMA2_SCRATCH_RAM_DATA +#define SDMA2_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA2_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA2_SCRATCH_RAM_ADDR +#define SDMA2_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA2_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA2_CE_CTRL +#define SDMA2_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA2_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA2_CE_CTRL__RESERVED__SHIFT 0x8 +#define SDMA2_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA2_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA2_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//SDMA2_RAS_STATUS +#define SDMA2_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA2_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA2_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA2_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA2_RAS_STATUS__SRAM_ECC__SHIFT 0x5 +#define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 +#define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 +#define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa +#define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb +#define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc +#define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd +#define SDMA2_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA2_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA2_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA2_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA2_RAS_STATUS__SRAM_ECC_MASK 0x00000020L +#define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L +#define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L +#define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L +#define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L +#define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L +#define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L +//SDMA2_CLK_STATUS +#define SDMA2_CLK_STATUS__DYN_CLK__SHIFT 0x0 +#define SDMA2_CLK_STATUS__PTR_CLK__SHIFT 0x1 +#define SDMA2_CLK_STATUS__REG_CLK__SHIFT 0x2 +#define SDMA2_CLK_STATUS__F32_CLK__SHIFT 0x3 +#define SDMA2_CLK_STATUS__DYN_CLK_MASK 0x00000001L +#define SDMA2_CLK_STATUS__PTR_CLK_MASK 0x00000002L +#define SDMA2_CLK_STATUS__REG_CLK_MASK 0x00000004L +#define SDMA2_CLK_STATUS__F32_CLK_MASK 0x00000008L +//SDMA2_GFX_RB_CNTL +#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_GFX_RB_BASE +#define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_BASE_HI +#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_GFX_RB_RPTR +#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_HI +#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR +#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_HI +#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_CNTL +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_GFX_RB_RPTR_ADDR_HI +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_ADDR_LO +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_IB_CNTL +#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_GFX_IB_RPTR +#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_OFFSET +#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_BASE_LO +#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_GFX_IB_BASE_HI +#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SIZE +#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_SKIP_CNTL +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_GFX_CONTEXT_STATUS +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_GFX_DOORBELL +#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_GFX_CONTEXT_CNTL +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L +//SDMA2_GFX_STATUS +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_GFX_DOORBELL_LOG +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_GFX_WATERMARK +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_GFX_DOORBELL_OFFSET +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_GFX_CSA_ADDR_LO +#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_CSA_ADDR_HI +#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SUB_REMAIN +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_PREEMPT +#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_GFX_DUMMY_REG +#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_RB_AQL_CNTL +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_GFX_MINOR_PTR_UPDATE +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_GFX_MIDCMD_DATA0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA1 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA2 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA3 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA4 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA5 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA6 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA7 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA8 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA9 +#define SDMA2_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA10 +#define SDMA2_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_CNTL +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_PAGE_RB_CNTL +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_PAGE_RB_BASE +#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_BASE_HI +#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_PAGE_RB_RPTR +#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_HI +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR +#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_HI +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_CNTL +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_PAGE_RB_RPTR_ADDR_HI +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_ADDR_LO +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_IB_CNTL +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_PAGE_IB_RPTR +#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_OFFSET +#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_BASE_LO +#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_PAGE_IB_BASE_HI +#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SIZE +#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_SKIP_CNTL +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_PAGE_CONTEXT_STATUS +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_PAGE_DOORBELL +#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_PAGE_STATUS +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_PAGE_DOORBELL_LOG +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_PAGE_WATERMARK +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_PAGE_DOORBELL_OFFSET +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_PAGE_CSA_ADDR_LO +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_CSA_ADDR_HI +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SUB_REMAIN +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_PREEMPT +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_PAGE_DUMMY_REG +#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_RB_AQL_CNTL +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_PAGE_MINOR_PTR_UPDATE +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_PAGE_MIDCMD_DATA0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA1 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA2 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA3 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA4 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA5 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA6 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA7 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA8 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA9 +#define SDMA2_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA10 +#define SDMA2_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_CNTL +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC0_RB_CNTL +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC0_RB_BASE +#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_BASE_HI +#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC0_RB_RPTR +#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_HI +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR +#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_HI +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_CNTL +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC0_RB_RPTR_ADDR_HI +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_ADDR_LO +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_IB_CNTL +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC0_IB_RPTR +#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_OFFSET +#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_BASE_LO +#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC0_IB_BASE_HI +#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SIZE +#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_SKIP_CNTL +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC0_CONTEXT_STATUS +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC0_DOORBELL +#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC0_STATUS +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC0_DOORBELL_LOG +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC0_WATERMARK +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC0_DOORBELL_OFFSET +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC0_CSA_ADDR_LO +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_CSA_ADDR_HI +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SUB_REMAIN +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_PREEMPT +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC0_DUMMY_REG +#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_RB_AQL_CNTL +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC0_MINOR_PTR_UPDATE +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC0_MIDCMD_DATA0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA1 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA2 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA3 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA4 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA5 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA6 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA7 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA8 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA9 +#define SDMA2_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA10 +#define SDMA2_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_CNTL +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC1_RB_CNTL +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC1_RB_BASE +#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_BASE_HI +#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC1_RB_RPTR +#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_HI +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR +#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_HI +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_CNTL +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC1_RB_RPTR_ADDR_HI +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_ADDR_LO +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_IB_CNTL +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC1_IB_RPTR +#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_OFFSET +#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_BASE_LO +#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC1_IB_BASE_HI +#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SIZE +#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_SKIP_CNTL +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC1_CONTEXT_STATUS +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC1_DOORBELL +#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC1_STATUS +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC1_DOORBELL_LOG +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC1_WATERMARK +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC1_DOORBELL_OFFSET +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC1_CSA_ADDR_LO +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_CSA_ADDR_HI +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SUB_REMAIN +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_PREEMPT +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC1_DUMMY_REG +#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_RB_AQL_CNTL +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC1_MINOR_PTR_UPDATE +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC1_MIDCMD_DATA0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA1 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA2 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA3 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA4 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA5 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA6 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA7 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA8 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA9 +#define SDMA2_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA10 +#define SDMA2_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_CNTL +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC2_RB_CNTL +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC2_RB_BASE +#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_BASE_HI +#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC2_RB_RPTR +#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_HI +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR +#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_HI +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_CNTL +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC2_RB_RPTR_ADDR_HI +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_ADDR_LO +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_IB_CNTL +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC2_IB_RPTR +#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_OFFSET +#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_BASE_LO +#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC2_IB_BASE_HI +#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SIZE +#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_SKIP_CNTL +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC2_CONTEXT_STATUS +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC2_DOORBELL +#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC2_STATUS +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC2_DOORBELL_LOG +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC2_WATERMARK +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC2_DOORBELL_OFFSET +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC2_CSA_ADDR_LO +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_CSA_ADDR_HI +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SUB_REMAIN +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_PREEMPT +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC2_DUMMY_REG +#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_RB_AQL_CNTL +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC2_MINOR_PTR_UPDATE +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC2_MIDCMD_DATA0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA1 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA2 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA3 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA4 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA5 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA6 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA7 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA8 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA9 +#define SDMA2_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA10 +#define SDMA2_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_CNTL +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC3_RB_CNTL +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC3_RB_BASE +#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_BASE_HI +#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC3_RB_RPTR +#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_HI +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR +#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_HI +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_CNTL +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC3_RB_RPTR_ADDR_HI +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_ADDR_LO +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_IB_CNTL +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC3_IB_RPTR +#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_OFFSET +#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_BASE_LO +#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC3_IB_BASE_HI +#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SIZE +#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_SKIP_CNTL +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC3_CONTEXT_STATUS +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC3_DOORBELL +#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC3_STATUS +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC3_DOORBELL_LOG +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC3_WATERMARK +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC3_DOORBELL_OFFSET +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC3_CSA_ADDR_LO +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_CSA_ADDR_HI +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SUB_REMAIN +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_PREEMPT +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC3_DUMMY_REG +#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_RB_AQL_CNTL +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC3_MINOR_PTR_UPDATE +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC3_MIDCMD_DATA0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA1 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA2 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA3 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA4 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA5 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA6 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA7 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA8 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA9 +#define SDMA2_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA10 +#define SDMA2_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_CNTL +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC4_RB_CNTL +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC4_RB_BASE +#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_BASE_HI +#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC4_RB_RPTR +#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_HI +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR +#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_HI +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_CNTL +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC4_RB_RPTR_ADDR_HI +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_ADDR_LO +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_IB_CNTL +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC4_IB_RPTR +#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_OFFSET +#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_BASE_LO +#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC4_IB_BASE_HI +#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SIZE +#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_SKIP_CNTL +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC4_CONTEXT_STATUS +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC4_DOORBELL +#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC4_STATUS +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC4_DOORBELL_LOG +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC4_WATERMARK +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC4_DOORBELL_OFFSET +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC4_CSA_ADDR_LO +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_CSA_ADDR_HI +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SUB_REMAIN +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_PREEMPT +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC4_DUMMY_REG +#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_RB_AQL_CNTL +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC4_MINOR_PTR_UPDATE +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC4_MIDCMD_DATA0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA1 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA2 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA3 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA4 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA5 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA6 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA7 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA8 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA9 +#define SDMA2_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA10 +#define SDMA2_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_CNTL +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC5_RB_CNTL +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC5_RB_BASE +#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_BASE_HI +#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC5_RB_RPTR +#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_HI +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR +#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_HI +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_CNTL +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC5_RB_RPTR_ADDR_HI +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_ADDR_LO +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_IB_CNTL +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC5_IB_RPTR +#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_OFFSET +#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_BASE_LO +#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC5_IB_BASE_HI +#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SIZE +#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_SKIP_CNTL +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC5_CONTEXT_STATUS +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC5_DOORBELL +#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC5_STATUS +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC5_DOORBELL_LOG +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC5_WATERMARK +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC5_DOORBELL_OFFSET +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC5_CSA_ADDR_LO +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_CSA_ADDR_HI +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SUB_REMAIN +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_PREEMPT +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC5_DUMMY_REG +#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_RB_AQL_CNTL +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC5_MINOR_PTR_UPDATE +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC5_MIDCMD_DATA0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA1 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA2 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA3 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA4 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA5 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA6 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA7 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA8 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA9 +#define SDMA2_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA10 +#define SDMA2_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_CNTL +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC6_RB_CNTL +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC6_RB_BASE +#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_BASE_HI +#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC6_RB_RPTR +#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_HI +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR +#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_HI +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_CNTL +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC6_RB_RPTR_ADDR_HI +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_ADDR_LO +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_IB_CNTL +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC6_IB_RPTR +#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_OFFSET +#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_BASE_LO +#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC6_IB_BASE_HI +#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SIZE +#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_SKIP_CNTL +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC6_CONTEXT_STATUS +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC6_DOORBELL +#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC6_STATUS +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC6_DOORBELL_LOG +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC6_WATERMARK +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC6_DOORBELL_OFFSET +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC6_CSA_ADDR_LO +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_CSA_ADDR_HI +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SUB_REMAIN +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_PREEMPT +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC6_DUMMY_REG +#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_RB_AQL_CNTL +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC6_MINOR_PTR_UPDATE +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC6_MIDCMD_DATA0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA1 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA2 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA3 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA4 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA5 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA6 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA7 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA8 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA9 +#define SDMA2_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA10 +#define SDMA2_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_CNTL +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC7_RB_CNTL +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC7_RB_BASE +#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_BASE_HI +#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC7_RB_RPTR +#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_HI +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR +#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_HI +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_CNTL +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC7_RB_RPTR_ADDR_HI +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_ADDR_LO +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_IB_CNTL +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC7_IB_RPTR +#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_OFFSET +#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_BASE_LO +#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC7_IB_BASE_HI +#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SIZE +#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_SKIP_CNTL +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC7_CONTEXT_STATUS +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC7_DOORBELL +#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC7_STATUS +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC7_DOORBELL_LOG +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC7_WATERMARK +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC7_DOORBELL_OFFSET +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC7_CSA_ADDR_LO +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_CSA_ADDR_HI +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SUB_REMAIN +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_PREEMPT +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC7_DUMMY_REG +#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_RB_AQL_CNTL +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC7_MINOR_PTR_UPDATE +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC7_MIDCMD_DATA0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA1 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA2 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA3 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA4 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA5 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA6 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA7 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA8 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA9 +#define SDMA2_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA10 +#define SDMA2_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_CNTL +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: sdma0_sdma3dec +//SDMA3_UCODE_ADDR +#define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_ADDR__VALUE_MASK 0x00003FFFL +//SDMA3_UCODE_DATA +#define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_VF_ENABLE +#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L +//SDMA3_CONTEXT_GROUP_BOUNDARY +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA3_POWER_CNTL +#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA3_CLK_CTRL +#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA3_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA3_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA3_CNTL +#define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA3_CHICKEN_BITS +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a +#define SDMA3_CHICKEN_BITS__RESERVED__SHIFT 0x1b +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L +#define SDMA3_CHICKEN_BITS__RESERVED_MASK 0xF8000000L +//SDMA3_GB_ADDR_CONFIG +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_GB_ADDR_CONFIG_READ +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_RB_RPTR_FETCH_HI +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA3_RB_RPTR_FETCH +#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA3_IB_OFFSET_FETCH +#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA3_PROGRAM +#define SDMA3_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA3_STATUS_REG +#define SDMA3_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA3_STATUS1_REG +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA3_RD_BURST_CNTL +#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA3_HBM_PAGE_CONFIG +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA3_UCODE_CHECKSUM +#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA3_F32_CNTL +#define SDMA3_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA3_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA3_F32_CNTL__RESET__SHIFT 0x8 +#define SDMA3_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA3_F32_CNTL__STEP_MASK 0x00000002L +#define SDMA3_F32_CNTL__RESET_MASK 0x00000100L +//SDMA3_FREEZE +#define SDMA3_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA3_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA3_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA3_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA3_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA3_PHASE0_QUANTUM +#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_PHASE1_QUANTUM +#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//CC_SDMA3_EDC_CONFIG +#define CC_SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//SDMA3_BA_THRESHOLD +#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA3_ID +#define SDMA3_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA3_VERSION +#define SDMA3_VERSION__MINVER__SHIFT 0x0 +#define SDMA3_VERSION__MAJVER__SHIFT 0x8 +#define SDMA3_VERSION__REV__SHIFT 0x10 +#define SDMA3_VERSION__MINVER_MASK 0x0000007FL +#define SDMA3_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA3_VERSION__REV_MASK 0x003F0000L +//SDMA3_EDC_COUNTER +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L +//SDMA3_EDC_COUNTER2 +#define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa +#define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc +#define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe +#define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 +#define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L +#define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL +#define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L +#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L +#define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L +#define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L +#define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L +#define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L +//SDMA3_STATUS2_REG +#define SDMA3_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA3_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA3_ATOMIC_CNTL +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA3_ATOMIC_PREOP_LO +#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA3_ATOMIC_PREOP_HI +#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_CNTL +#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA3_UTCL1_WATERMK +#define SDMA3_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 +#define SDMA3_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 +#define SDMA3_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 +#define SDMA3_UTCL1_WATERMK__RESERVED__SHIFT 0x10 +#define SDMA3_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L +#define SDMA3_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L +#define SDMA3_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L +#define SDMA3_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L +//SDMA3_UTCL1_RD_STATUS +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA3_UTCL1_WR_STATUS +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA3_UTCL1_INV0 +#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA3_UTCL1_INV1 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_INV2 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK1 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_WR_XNACK0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_WR_XNACK1 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_TIMEOUT +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA3_UTCL1_PAGE +#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA3_POWER_CNTL_IDLE +#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA3_RELAX_ORDERING_LUT +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA3_CHICKEN_BITS_2 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +//SDMA3_STATUS3_REG +#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA3_PHYSICAL_ADDR_LO +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA3_PHYSICAL_ADDR_HI +#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA3_PHASE2_QUANTUM +#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_ERROR_LOG +#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA3_PUB_DUMMY_REG0 +#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG1 +#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG2 +#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG3 +#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA3_F32_COUNTER +#define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PERFCNT_PERFCOUNTER0_CFG +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA3_PERFCNT_PERFCOUNTER1_CFG +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA3_PERFCNT_MISC_CNTL +#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA3_PERFCNT_PERFCOUNTER_LO +#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA3_PERFCNT_PERFCOUNTER_HI +#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA3_CRD_CNTL +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA3_ULV_CNTL +#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA3_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA3_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA3_EA_DBIT_ADDR_DATA +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_EA_DBIT_ADDR_INDEX +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA3_STATUS4_REG +#define SDMA3_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA3_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA3_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 +#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 +#define SDMA3_STATUS4_REG__REG_POLLING__SHIFT 0x8 +#define SDMA3_STATUS4_REG__MEM_POLLING__SHIFT 0x9 +#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa +#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc +#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe +#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 +#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 +#define SDMA3_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA3_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA3_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L +#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L +#define SDMA3_STATUS4_REG__REG_POLLING_MASK 0x00000100L +#define SDMA3_STATUS4_REG__MEM_POLLING_MASK 0x00000200L +#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L +#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L +#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L +#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L +#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L +//SDMA3_SCRATCH_RAM_DATA +#define SDMA3_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA3_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA3_SCRATCH_RAM_ADDR +#define SDMA3_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA3_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA3_CE_CTRL +#define SDMA3_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA3_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA3_CE_CTRL__RESERVED__SHIFT 0x8 +#define SDMA3_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA3_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA3_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//SDMA3_RAS_STATUS +#define SDMA3_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA3_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA3_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA3_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA3_RAS_STATUS__SRAM_ECC__SHIFT 0x5 +#define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 +#define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 +#define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa +#define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb +#define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc +#define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd +#define SDMA3_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA3_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA3_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA3_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA3_RAS_STATUS__SRAM_ECC_MASK 0x00000020L +#define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L +#define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L +#define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L +#define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L +#define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L +#define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L +//SDMA3_CLK_STATUS +#define SDMA3_CLK_STATUS__DYN_CLK__SHIFT 0x0 +#define SDMA3_CLK_STATUS__PTR_CLK__SHIFT 0x1 +#define SDMA3_CLK_STATUS__REG_CLK__SHIFT 0x2 +#define SDMA3_CLK_STATUS__F32_CLK__SHIFT 0x3 +#define SDMA3_CLK_STATUS__DYN_CLK_MASK 0x00000001L +#define SDMA3_CLK_STATUS__PTR_CLK_MASK 0x00000002L +#define SDMA3_CLK_STATUS__REG_CLK_MASK 0x00000004L +#define SDMA3_CLK_STATUS__F32_CLK_MASK 0x00000008L +//SDMA3_GFX_RB_CNTL +#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_GFX_RB_BASE +#define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_BASE_HI +#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_GFX_RB_RPTR +#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_HI +#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR +#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_HI +#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_CNTL +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_GFX_RB_RPTR_ADDR_HI +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_ADDR_LO +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_IB_CNTL +#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_GFX_IB_RPTR +#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_OFFSET +#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_BASE_LO +#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_GFX_IB_BASE_HI +#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SIZE +#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_SKIP_CNTL +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_GFX_CONTEXT_STATUS +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_GFX_DOORBELL +#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_GFX_CONTEXT_CNTL +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L +//SDMA3_GFX_STATUS +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_GFX_DOORBELL_LOG +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_GFX_WATERMARK +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_GFX_DOORBELL_OFFSET +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_GFX_CSA_ADDR_LO +#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_CSA_ADDR_HI +#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SUB_REMAIN +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_PREEMPT +#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_GFX_DUMMY_REG +#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_RB_AQL_CNTL +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_GFX_MINOR_PTR_UPDATE +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_GFX_MIDCMD_DATA0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA1 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA2 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA3 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA4 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA5 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA6 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA7 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA8 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA9 +#define SDMA3_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA10 +#define SDMA3_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_CNTL +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_PAGE_RB_CNTL +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_PAGE_RB_BASE +#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_BASE_HI +#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_PAGE_RB_RPTR +#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_HI +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR +#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_HI +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_CNTL +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_PAGE_RB_RPTR_ADDR_HI +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_ADDR_LO +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_IB_CNTL +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_PAGE_IB_RPTR +#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_OFFSET +#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_BASE_LO +#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_PAGE_IB_BASE_HI +#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SIZE +#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_SKIP_CNTL +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_PAGE_CONTEXT_STATUS +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_PAGE_DOORBELL +#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_PAGE_STATUS +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_PAGE_DOORBELL_LOG +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_PAGE_WATERMARK +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_PAGE_DOORBELL_OFFSET +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_PAGE_CSA_ADDR_LO +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_CSA_ADDR_HI +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SUB_REMAIN +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_PREEMPT +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_PAGE_DUMMY_REG +#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_RB_AQL_CNTL +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_PAGE_MINOR_PTR_UPDATE +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_PAGE_MIDCMD_DATA0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA1 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA2 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA3 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA4 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA5 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA6 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA7 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA8 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA9 +#define SDMA3_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA10 +#define SDMA3_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_CNTL +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC0_RB_CNTL +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC0_RB_BASE +#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_BASE_HI +#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC0_RB_RPTR +#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_HI +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR +#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_HI +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_CNTL +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC0_RB_RPTR_ADDR_HI +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_ADDR_LO +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_IB_CNTL +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC0_IB_RPTR +#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_OFFSET +#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_BASE_LO +#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC0_IB_BASE_HI +#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SIZE +#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_SKIP_CNTL +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC0_CONTEXT_STATUS +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC0_DOORBELL +#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC0_STATUS +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC0_DOORBELL_LOG +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC0_WATERMARK +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC0_DOORBELL_OFFSET +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC0_CSA_ADDR_LO +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_CSA_ADDR_HI +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SUB_REMAIN +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_PREEMPT +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC0_DUMMY_REG +#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_RB_AQL_CNTL +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC0_MINOR_PTR_UPDATE +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC0_MIDCMD_DATA0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA1 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA2 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA3 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA4 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA5 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA6 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA7 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA8 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA9 +#define SDMA3_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA10 +#define SDMA3_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_CNTL +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC1_RB_CNTL +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC1_RB_BASE +#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_BASE_HI +#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC1_RB_RPTR +#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_HI +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR +#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_HI +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_CNTL +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC1_RB_RPTR_ADDR_HI +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_ADDR_LO +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_IB_CNTL +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC1_IB_RPTR +#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_OFFSET +#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_BASE_LO +#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC1_IB_BASE_HI +#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SIZE +#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_SKIP_CNTL +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC1_CONTEXT_STATUS +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC1_DOORBELL +#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC1_STATUS +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC1_DOORBELL_LOG +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC1_WATERMARK +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC1_DOORBELL_OFFSET +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC1_CSA_ADDR_LO +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_CSA_ADDR_HI +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SUB_REMAIN +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_PREEMPT +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC1_DUMMY_REG +#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_RB_AQL_CNTL +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC1_MINOR_PTR_UPDATE +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC1_MIDCMD_DATA0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA1 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA2 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA3 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA4 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA5 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA6 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA7 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA8 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA9 +#define SDMA3_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA10 +#define SDMA3_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_CNTL +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC2_RB_CNTL +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC2_RB_BASE +#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_BASE_HI +#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC2_RB_RPTR +#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_HI +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR +#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_HI +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_CNTL +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC2_RB_RPTR_ADDR_HI +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_ADDR_LO +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_IB_CNTL +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC2_IB_RPTR +#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_OFFSET +#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_BASE_LO +#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC2_IB_BASE_HI +#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SIZE +#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_SKIP_CNTL +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC2_CONTEXT_STATUS +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC2_DOORBELL +#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC2_STATUS +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC2_DOORBELL_LOG +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC2_WATERMARK +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC2_DOORBELL_OFFSET +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC2_CSA_ADDR_LO +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_CSA_ADDR_HI +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SUB_REMAIN +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_PREEMPT +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC2_DUMMY_REG +#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_RB_AQL_CNTL +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC2_MINOR_PTR_UPDATE +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC2_MIDCMD_DATA0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA1 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA2 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA3 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA4 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA5 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA6 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA7 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA8 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA9 +#define SDMA3_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA10 +#define SDMA3_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_CNTL +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC3_RB_CNTL +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC3_RB_BASE +#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_BASE_HI +#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC3_RB_RPTR +#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_HI +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR +#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_HI +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_CNTL +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC3_RB_RPTR_ADDR_HI +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_ADDR_LO +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_IB_CNTL +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC3_IB_RPTR +#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_OFFSET +#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_BASE_LO +#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC3_IB_BASE_HI +#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SIZE +#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_SKIP_CNTL +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC3_CONTEXT_STATUS +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC3_DOORBELL +#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC3_STATUS +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC3_DOORBELL_LOG +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC3_WATERMARK +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC3_DOORBELL_OFFSET +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC3_CSA_ADDR_LO +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_CSA_ADDR_HI +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SUB_REMAIN +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_PREEMPT +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC3_DUMMY_REG +#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_RB_AQL_CNTL +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC3_MINOR_PTR_UPDATE +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC3_MIDCMD_DATA0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA1 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA2 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA3 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA4 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA5 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA6 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA7 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA8 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA9 +#define SDMA3_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA10 +#define SDMA3_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_CNTL +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC4_RB_CNTL +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC4_RB_BASE +#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_BASE_HI +#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC4_RB_RPTR +#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_HI +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR +#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_HI +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_CNTL +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC4_RB_RPTR_ADDR_HI +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_ADDR_LO +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_IB_CNTL +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC4_IB_RPTR +#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_OFFSET +#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_BASE_LO +#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC4_IB_BASE_HI +#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SIZE +#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_SKIP_CNTL +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC4_CONTEXT_STATUS +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC4_DOORBELL +#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC4_STATUS +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC4_DOORBELL_LOG +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC4_WATERMARK +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC4_DOORBELL_OFFSET +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC4_CSA_ADDR_LO +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_CSA_ADDR_HI +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SUB_REMAIN +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_PREEMPT +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC4_DUMMY_REG +#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_RB_AQL_CNTL +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC4_MINOR_PTR_UPDATE +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC4_MIDCMD_DATA0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA1 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA2 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA3 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA4 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA5 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA6 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA7 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA8 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA9 +#define SDMA3_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA10 +#define SDMA3_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_CNTL +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC5_RB_CNTL +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC5_RB_BASE +#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_BASE_HI +#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC5_RB_RPTR +#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_HI +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR +#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_HI +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_CNTL +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC5_RB_RPTR_ADDR_HI +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_ADDR_LO +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_IB_CNTL +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC5_IB_RPTR +#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_OFFSET +#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_BASE_LO +#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC5_IB_BASE_HI +#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SIZE +#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_SKIP_CNTL +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC5_CONTEXT_STATUS +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC5_DOORBELL +#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC5_STATUS +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC5_DOORBELL_LOG +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC5_WATERMARK +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC5_DOORBELL_OFFSET +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC5_CSA_ADDR_LO +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_CSA_ADDR_HI +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SUB_REMAIN +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_PREEMPT +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC5_DUMMY_REG +#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_RB_AQL_CNTL +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC5_MINOR_PTR_UPDATE +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC5_MIDCMD_DATA0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA1 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA2 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA3 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA4 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA5 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA6 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA7 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA8 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA9 +#define SDMA3_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA10 +#define SDMA3_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_CNTL +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC6_RB_CNTL +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC6_RB_BASE +#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_BASE_HI +#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC6_RB_RPTR +#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_HI +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR +#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_HI +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_CNTL +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC6_RB_RPTR_ADDR_HI +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_ADDR_LO +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_IB_CNTL +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC6_IB_RPTR +#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_OFFSET +#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_BASE_LO +#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC6_IB_BASE_HI +#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SIZE +#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_SKIP_CNTL +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC6_CONTEXT_STATUS +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC6_DOORBELL +#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC6_STATUS +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC6_DOORBELL_LOG +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC6_WATERMARK +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC6_DOORBELL_OFFSET +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC6_CSA_ADDR_LO +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_CSA_ADDR_HI +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SUB_REMAIN +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_PREEMPT +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC6_DUMMY_REG +#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_RB_AQL_CNTL +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC6_MINOR_PTR_UPDATE +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC6_MIDCMD_DATA0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA1 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA2 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA3 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA4 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA5 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA6 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA7 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA8 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA9 +#define SDMA3_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA10 +#define SDMA3_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_CNTL +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC7_RB_CNTL +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC7_RB_BASE +#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_BASE_HI +#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC7_RB_RPTR +#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_HI +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR +#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_HI +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_CNTL +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC7_RB_RPTR_ADDR_HI +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_ADDR_LO +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_IB_CNTL +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC7_IB_RPTR +#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_OFFSET +#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_BASE_LO +#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC7_IB_BASE_HI +#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SIZE +#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_SKIP_CNTL +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC7_CONTEXT_STATUS +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC7_DOORBELL +#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC7_STATUS +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC7_DOORBELL_LOG +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC7_WATERMARK +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC7_DOORBELL_OFFSET +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC7_CSA_ADDR_LO +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_CSA_ADDR_HI +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SUB_REMAIN +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_PREEMPT +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC7_DUMMY_REG +#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_RB_AQL_CNTL +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC7_MINOR_PTR_UPDATE +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC7_MIDCMD_DATA0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA1 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA2 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA3 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA4 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA5 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA6 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA7 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA8 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA9 +#define SDMA3_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA10 +#define SDMA3_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_CNTL +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + + +// addressBlock: sdma0_sdma4dec +//SDMA4_UCODE_ADDR +#define SDMA4_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_ADDR__VALUE_MASK 0x00003FFFL +//SDMA4_UCODE_DATA +#define SDMA4_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_VF_ENABLE +#define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA4_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK 0x00000002L +//SDMA4_CONTEXT_GROUP_BOUNDARY +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA4_POWER_CNTL +#define SDMA4_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA4_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA4_CLK_CTRL +#define SDMA4_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA4_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA4_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA4_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA4_CNTL +#define SDMA4_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA4_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA4_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA4_CHICKEN_BITS +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a +#define SDMA4_CHICKEN_BITS__RESERVED__SHIFT 0x1b +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L +#define SDMA4_CHICKEN_BITS__RESERVED_MASK 0xF8000000L +//SDMA4_GB_ADDR_CONFIG +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_GB_ADDR_CONFIG_READ +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_RB_RPTR_FETCH_HI +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA4_RB_RPTR_FETCH +#define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA4_IB_OFFSET_FETCH +#define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA4_PROGRAM +#define SDMA4_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA4_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA4_STATUS_REG +#define SDMA4_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA4_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA4_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA4_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA4_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA4_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA4_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA4_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA4_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA4_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA4_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA4_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA4_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA4_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA4_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA4_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA4_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA4_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA4_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA4_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA4_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA4_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA4_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA4_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA4_STATUS1_REG +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA4_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA4_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA4_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA4_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA4_RD_BURST_CNTL +#define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA4_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA4_HBM_PAGE_CONFIG +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA4_UCODE_CHECKSUM +#define SDMA4_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA4_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA4_F32_CNTL +#define SDMA4_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA4_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA4_F32_CNTL__RESET__SHIFT 0x8 +#define SDMA4_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA4_F32_CNTL__STEP_MASK 0x00000002L +#define SDMA4_F32_CNTL__RESET_MASK 0x00000100L +//SDMA4_FREEZE +#define SDMA4_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA4_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA4_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA4_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA4_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA4_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA4_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA4_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA4_PHASE0_QUANTUM +#define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_PHASE1_QUANTUM +#define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//CC_SDMA4_EDC_CONFIG +#define CC_SDMA4_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_SDMA4_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//SDMA4_BA_THRESHOLD +#define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA4_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA4_ID +#define SDMA4_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA4_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA4_VERSION +#define SDMA4_VERSION__MINVER__SHIFT 0x0 +#define SDMA4_VERSION__MAJVER__SHIFT 0x8 +#define SDMA4_VERSION__REV__SHIFT 0x10 +#define SDMA4_VERSION__MINVER_MASK 0x0000007FL +#define SDMA4_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA4_VERSION__REV_MASK 0x003F0000L +//SDMA4_EDC_COUNTER +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L +//SDMA4_EDC_COUNTER2 +#define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa +#define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc +#define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe +#define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 +#define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L +#define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL +#define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L +#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L +#define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L +#define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L +#define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L +#define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L +//SDMA4_STATUS2_REG +#define SDMA4_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA4_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA4_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA4_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA4_ATOMIC_CNTL +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA4_ATOMIC_PREOP_LO +#define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA4_ATOMIC_PREOP_HI +#define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_CNTL +#define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA4_UTCL1_WATERMK +#define SDMA4_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 +#define SDMA4_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 +#define SDMA4_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 +#define SDMA4_UTCL1_WATERMK__RESERVED__SHIFT 0x10 +#define SDMA4_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L +#define SDMA4_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L +#define SDMA4_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L +#define SDMA4_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L +//SDMA4_UTCL1_RD_STATUS +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA4_UTCL1_WR_STATUS +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA4_UTCL1_INV0 +#define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA4_UTCL1_INV1 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_INV2 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK1 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_WR_XNACK0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_WR_XNACK1 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_TIMEOUT +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA4_UTCL1_PAGE +#define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA4_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA4_POWER_CNTL_IDLE +#define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA4_RELAX_ORDERING_LUT +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA4_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA4_CHICKEN_BITS_2 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +//SDMA4_STATUS3_REG +#define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA4_PHYSICAL_ADDR_LO +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA4_PHYSICAL_ADDR_HI +#define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA4_PHASE2_QUANTUM +#define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_ERROR_LOG +#define SDMA4_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA4_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA4_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA4_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA4_PUB_DUMMY_REG0 +#define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG1 +#define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG2 +#define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG3 +#define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA4_F32_COUNTER +#define SDMA4_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA4_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PERFCNT_PERFCOUNTER0_CFG +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA4_PERFCNT_PERFCOUNTER1_CFG +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA4_PERFCNT_MISC_CNTL +#define SDMA4_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA4_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA4_PERFCNT_PERFCOUNTER_LO +#define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA4_PERFCNT_PERFCOUNTER_HI +#define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA4_CRD_CNTL +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA4_ULV_CNTL +#define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA4_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA4_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA4_EA_DBIT_ADDR_DATA +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_EA_DBIT_ADDR_INDEX +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA4_STATUS4_REG +#define SDMA4_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA4_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA4_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 +#define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 +#define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 +#define SDMA4_STATUS4_REG__REG_POLLING__SHIFT 0x8 +#define SDMA4_STATUS4_REG__MEM_POLLING__SHIFT 0x9 +#define SDMA4_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa +#define SDMA4_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc +#define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe +#define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 +#define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 +#define SDMA4_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA4_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA4_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L +#define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L +#define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L +#define SDMA4_STATUS4_REG__REG_POLLING_MASK 0x00000100L +#define SDMA4_STATUS4_REG__MEM_POLLING_MASK 0x00000200L +#define SDMA4_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L +#define SDMA4_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L +#define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L +#define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L +#define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L +//SDMA4_SCRATCH_RAM_DATA +#define SDMA4_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA4_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA4_SCRATCH_RAM_ADDR +#define SDMA4_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA4_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA4_CE_CTRL +#define SDMA4_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA4_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA4_CE_CTRL__RESERVED__SHIFT 0x8 +#define SDMA4_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA4_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA4_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//SDMA4_RAS_STATUS +#define SDMA4_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA4_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA4_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 +#define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 +#define SDMA4_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA4_RAS_STATUS__SRAM_ECC__SHIFT 0x5 +#define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 +#define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 +#define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa +#define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb +#define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc +#define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd +#define SDMA4_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA4_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA4_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L +#define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L +#define SDMA4_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA4_RAS_STATUS__SRAM_ECC_MASK 0x00000020L +#define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L +#define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L +#define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L +#define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L +#define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L +#define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L +//SDMA4_CLK_STATUS +#define SDMA4_CLK_STATUS__DYN_CLK__SHIFT 0x0 +#define SDMA4_CLK_STATUS__PTR_CLK__SHIFT 0x1 +#define SDMA4_CLK_STATUS__REG_CLK__SHIFT 0x2 +#define SDMA4_CLK_STATUS__F32_CLK__SHIFT 0x3 +#define SDMA4_CLK_STATUS__DYN_CLK_MASK 0x00000001L +#define SDMA4_CLK_STATUS__PTR_CLK_MASK 0x00000002L +#define SDMA4_CLK_STATUS__REG_CLK_MASK 0x00000004L +#define SDMA4_CLK_STATUS__F32_CLK_MASK 0x00000008L +//SDMA4_GFX_RB_CNTL +#define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_GFX_RB_BASE +#define SDMA4_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_BASE_HI +#define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_GFX_RB_RPTR +#define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_HI +#define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR +#define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_HI +#define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_CNTL +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_GFX_RB_RPTR_ADDR_HI +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_ADDR_LO +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_IB_CNTL +#define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_GFX_IB_RPTR +#define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_OFFSET +#define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_BASE_LO +#define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_GFX_IB_BASE_HI +#define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SIZE +#define SDMA4_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_SKIP_CNTL +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_GFX_CONTEXT_STATUS +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_GFX_DOORBELL +#define SDMA4_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_GFX_CONTEXT_CNTL +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +#define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L +//SDMA4_GFX_STATUS +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_GFX_DOORBELL_LOG +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_GFX_WATERMARK +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_GFX_DOORBELL_OFFSET +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_GFX_CSA_ADDR_LO +#define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_CSA_ADDR_HI +#define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SUB_REMAIN +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_PREEMPT +#define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_GFX_DUMMY_REG +#define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_RB_AQL_CNTL +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_GFX_MINOR_PTR_UPDATE +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_GFX_MIDCMD_DATA0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA1 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA2 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA3 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA4 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA5 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA6 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA7 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA8 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA9 +#define SDMA4_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA10 +#define SDMA4_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_CNTL +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_PAGE_RB_CNTL +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_PAGE_RB_BASE +#define SDMA4_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_BASE_HI +#define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_PAGE_RB_RPTR +#define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_HI +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR +#define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_HI +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_CNTL +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_PAGE_RB_RPTR_ADDR_HI +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_ADDR_LO +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_IB_CNTL +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_PAGE_IB_RPTR +#define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_OFFSET +#define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_BASE_LO +#define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_PAGE_IB_BASE_HI +#define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SIZE +#define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_SKIP_CNTL +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_PAGE_CONTEXT_STATUS +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_PAGE_DOORBELL +#define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_PAGE_STATUS +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_PAGE_DOORBELL_LOG +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_PAGE_WATERMARK +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_PAGE_DOORBELL_OFFSET +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_PAGE_CSA_ADDR_LO +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_CSA_ADDR_HI +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SUB_REMAIN +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_PREEMPT +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_PAGE_DUMMY_REG +#define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_RB_AQL_CNTL +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_PAGE_MINOR_PTR_UPDATE +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_PAGE_MIDCMD_DATA0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA1 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA2 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA3 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA4 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA5 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA6 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA7 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA8 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA9 +#define SDMA4_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA10 +#define SDMA4_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_CNTL +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC0_RB_CNTL +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC0_RB_BASE +#define SDMA4_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_BASE_HI +#define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC0_RB_RPTR +#define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_HI +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR +#define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_HI +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_CNTL +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC0_RB_RPTR_ADDR_HI +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_ADDR_LO +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_IB_CNTL +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC0_IB_RPTR +#define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_OFFSET +#define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_BASE_LO +#define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC0_IB_BASE_HI +#define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SIZE +#define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_SKIP_CNTL +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC0_CONTEXT_STATUS +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC0_DOORBELL +#define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC0_STATUS +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC0_DOORBELL_LOG +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC0_WATERMARK +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC0_DOORBELL_OFFSET +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC0_CSA_ADDR_LO +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_CSA_ADDR_HI +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SUB_REMAIN +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_PREEMPT +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC0_DUMMY_REG +#define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_RB_AQL_CNTL +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC0_MINOR_PTR_UPDATE +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC0_MIDCMD_DATA0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA1 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA2 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA3 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA4 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA5 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA6 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA7 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA8 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA9 +#define SDMA4_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA10 +#define SDMA4_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_CNTL +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC1_RB_CNTL +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC1_RB_BASE +#define SDMA4_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_BASE_HI +#define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC1_RB_RPTR +#define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_HI +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR +#define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_HI +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_CNTL +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC1_RB_RPTR_ADDR_HI +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_ADDR_LO +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_IB_CNTL +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC1_IB_RPTR +#define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_OFFSET +#define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_BASE_LO +#define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC1_IB_BASE_HI +#define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SIZE +#define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_SKIP_CNTL +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC1_CONTEXT_STATUS +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC1_DOORBELL +#define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC1_STATUS +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC1_DOORBELL_LOG +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC1_WATERMARK +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC1_DOORBELL_OFFSET +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC1_CSA_ADDR_LO +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_CSA_ADDR_HI +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SUB_REMAIN +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_PREEMPT +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC1_DUMMY_REG +#define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_RB_AQL_CNTL +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC1_MINOR_PTR_UPDATE +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC1_MIDCMD_DATA0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA1 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA2 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA3 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA4 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA5 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA6 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA7 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA8 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA9 +#define SDMA4_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA10 +#define SDMA4_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_CNTL +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC2_RB_CNTL +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC2_RB_BASE +#define SDMA4_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_BASE_HI +#define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC2_RB_RPTR +#define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_HI +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR +#define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_HI +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_CNTL +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC2_RB_RPTR_ADDR_HI +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_ADDR_LO +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_IB_CNTL +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC2_IB_RPTR +#define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_OFFSET +#define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_BASE_LO +#define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC2_IB_BASE_HI +#define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SIZE +#define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_SKIP_CNTL +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC2_CONTEXT_STATUS +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC2_DOORBELL +#define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC2_STATUS +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC2_DOORBELL_LOG +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC2_WATERMARK +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC2_DOORBELL_OFFSET +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC2_CSA_ADDR_LO +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_CSA_ADDR_HI +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SUB_REMAIN +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_PREEMPT +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC2_DUMMY_REG +#define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_RB_AQL_CNTL +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC2_MINOR_PTR_UPDATE +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC2_MIDCMD_DATA0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA1 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA2 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA3 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA4 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA5 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA6 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA7 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA8 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA9 +#define SDMA4_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA10 +#define SDMA4_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_CNTL +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC3_RB_CNTL +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC3_RB_BASE +#define SDMA4_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_BASE_HI +#define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC3_RB_RPTR +#define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_HI +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR +#define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_HI +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_CNTL +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC3_RB_RPTR_ADDR_HI +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_ADDR_LO +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_IB_CNTL +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC3_IB_RPTR +#define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_OFFSET +#define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_BASE_LO +#define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC3_IB_BASE_HI +#define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SIZE +#define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_SKIP_CNTL +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC3_CONTEXT_STATUS +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC3_DOORBELL +#define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC3_STATUS +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC3_DOORBELL_LOG +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC3_WATERMARK +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC3_DOORBELL_OFFSET +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC3_CSA_ADDR_LO +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_CSA_ADDR_HI +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SUB_REMAIN +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_PREEMPT +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC3_DUMMY_REG +#define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_RB_AQL_CNTL +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC3_MINOR_PTR_UPDATE +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC3_MIDCMD_DATA0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA1 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA2 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA3 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA4 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA5 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA6 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA7 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA8 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA9 +#define SDMA4_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA10 +#define SDMA4_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_CNTL +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC4_RB_CNTL +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC4_RB_BASE +#define SDMA4_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_BASE_HI +#define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC4_RB_RPTR +#define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_HI +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR +#define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_HI +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_CNTL +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC4_RB_RPTR_ADDR_HI +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_ADDR_LO +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_IB_CNTL +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC4_IB_RPTR +#define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_OFFSET +#define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_BASE_LO +#define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC4_IB_BASE_HI +#define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SIZE +#define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_SKIP_CNTL +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC4_CONTEXT_STATUS +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC4_DOORBELL +#define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC4_STATUS +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC4_DOORBELL_LOG +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC4_WATERMARK +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC4_DOORBELL_OFFSET +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC4_CSA_ADDR_LO +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_CSA_ADDR_HI +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SUB_REMAIN +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_PREEMPT +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC4_DUMMY_REG +#define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_RB_AQL_CNTL +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC4_MINOR_PTR_UPDATE +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC4_MIDCMD_DATA0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA1 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA2 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA3 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA4 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA5 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA6 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA7 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA8 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA9 +#define SDMA4_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA10 +#define SDMA4_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_CNTL +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC5_RB_CNTL +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC5_RB_BASE +#define SDMA4_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_BASE_HI +#define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC5_RB_RPTR +#define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_HI +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR +#define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_HI +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_CNTL +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC5_RB_RPTR_ADDR_HI +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_ADDR_LO +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_IB_CNTL +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC5_IB_RPTR +#define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_OFFSET +#define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_BASE_LO +#define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC5_IB_BASE_HI +#define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SIZE +#define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_SKIP_CNTL +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC5_CONTEXT_STATUS +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC5_DOORBELL +#define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC5_STATUS +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC5_DOORBELL_LOG +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC5_WATERMARK +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC5_DOORBELL_OFFSET +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC5_CSA_ADDR_LO +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_CSA_ADDR_HI +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SUB_REMAIN +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_PREEMPT +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC5_DUMMY_REG +#define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_RB_AQL_CNTL +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC5_MINOR_PTR_UPDATE +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC5_MIDCMD_DATA0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA1 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA2 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA3 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA4 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA5 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA6 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA7 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA8 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA9 +#define SDMA4_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA10 +#define SDMA4_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_CNTL +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC6_RB_CNTL +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC6_RB_BASE +#define SDMA4_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_BASE_HI +#define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC6_RB_RPTR +#define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_HI +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR +#define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_HI +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_CNTL +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC6_RB_RPTR_ADDR_HI +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_ADDR_LO +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_IB_CNTL +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC6_IB_RPTR +#define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_OFFSET +#define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_BASE_LO +#define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC6_IB_BASE_HI +#define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SIZE +#define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_SKIP_CNTL +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC6_CONTEXT_STATUS +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC6_DOORBELL +#define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC6_STATUS +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC6_DOORBELL_LOG +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC6_WATERMARK +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC6_DOORBELL_OFFSET +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC6_CSA_ADDR_LO +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_CSA_ADDR_HI +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SUB_REMAIN +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_PREEMPT +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC6_DUMMY_REG +#define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_RB_AQL_CNTL +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC6_MINOR_PTR_UPDATE +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC6_MIDCMD_DATA0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA1 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA2 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA3 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA4 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA5 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA6 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA7 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA8 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA9 +#define SDMA4_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA10 +#define SDMA4_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_CNTL +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC7_RB_CNTL +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC7_RB_BASE +#define SDMA4_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_BASE_HI +#define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC7_RB_RPTR +#define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_HI +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR +#define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_HI +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_CNTL +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC7_RB_RPTR_ADDR_HI +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_ADDR_LO +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_IB_CNTL +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC7_IB_RPTR +#define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_OFFSET +#define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_BASE_LO +#define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC7_IB_BASE_HI +#define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SIZE +#define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_SKIP_CNTL +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC7_CONTEXT_STATUS +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC7_DOORBELL +#define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC7_STATUS +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC7_DOORBELL_LOG +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC7_WATERMARK +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC7_DOORBELL_OFFSET +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC7_CSA_ADDR_LO +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_CSA_ADDR_HI +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SUB_REMAIN +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_PREEMPT +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC7_DUMMY_REG +#define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_RB_AQL_CNTL +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC7_MINOR_PTR_UPDATE +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC7_MIDCMD_DATA0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA1 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA2 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA3 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA4 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA5 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA6 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA7 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA8 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA9 +#define SDMA4_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA10 +#define SDMA4_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_CNTL +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..f542268bdb2ba00b657791efe9ffc99b3b861b27 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h @@ -0,0 +1,516 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _smuio_13_0_2_OFFSET_HEADER +#define _smuio_13_0_2_OFFSET_HEADER + + + +// addressBlock: smuio_smuio_SmuSmuioDec +// base address: 0x5a000 +#define regSMUSVI0_TEL_PLANE0 0x0004 +#define regSMUSVI0_TEL_PLANE0_BASE_IDX 0 +#define regSMUSVI0_PLANE0_CURRENTVID 0x0014 +#define regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0 +#define regSMUIO_MCM_CONFIG 0x0024 +#define regSMUIO_MCM_CONFIG_BASE_IDX 0 +#define regCKSVII2C_IC_CON 0x0040 +#define regCKSVII2C_IC_CON_BASE_IDX 0 +#define regCKSVII2C_IC_TAR 0x0041 +#define regCKSVII2C_IC_TAR_BASE_IDX 0 +#define regCKSVII2C_IC_SAR 0x0042 +#define regCKSVII2C_IC_SAR_BASE_IDX 0 +#define regCKSVII2C_IC_HS_MADDR 0x0043 +#define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0 +#define regCKSVII2C_IC_DATA_CMD 0x0044 +#define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0 +#define regCKSVII2C_IC_SS_SCL_HCNT 0x0045 +#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_SS_SCL_LCNT 0x0046 +#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SCL_HCNT 0x0047 +#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SCL_LCNT 0x0048 +#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SCL_HCNT 0x0049 +#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SCL_LCNT 0x004a +#define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_INTR_STAT 0x004b +#define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C_IC_INTR_MASK 0x004c +#define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0 +#define regCKSVII2C_IC_RAW_INTR_STAT 0x004d +#define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C_IC_RX_TL 0x004e +#define regCKSVII2C_IC_RX_TL_BASE_IDX 0 +#define regCKSVII2C_IC_TX_TL 0x004f +#define regCKSVII2C_IC_TX_TL_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_INTR 0x0050 +#define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_UNDER 0x0051 +#define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_OVER 0x0052 +#define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_TX_OVER 0x0053 +#define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RD_REQ 0x0054 +#define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_TX_ABRT 0x0055 +#define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_DONE 0x0056 +#define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_ACTIVITY 0x0057 +#define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_STOP_DET 0x0058 +#define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_START_DET 0x0059 +#define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_GEN_CALL 0x005a +#define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 +#define regCKSVII2C_IC_ENABLE 0x005b +#define regCKSVII2C_IC_ENABLE_BASE_IDX 0 +#define regCKSVII2C_IC_STATUS 0x005c +#define regCKSVII2C_IC_STATUS_BASE_IDX 0 +#define regCKSVII2C_IC_TXFLR 0x005d +#define regCKSVII2C_IC_TXFLR_BASE_IDX 0 +#define regCKSVII2C_IC_RXFLR 0x005e +#define regCKSVII2C_IC_RXFLR_BASE_IDX 0 +#define regCKSVII2C_IC_SDA_HOLD 0x005f +#define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 +#define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 +#define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 +#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 +#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_CR 0x0062 +#define regCKSVII2C_IC_DMA_CR_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_TDLR 0x0063 +#define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_RDLR 0x0064 +#define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 +#define regCKSVII2C_IC_SDA_SETUP 0x0065 +#define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 +#define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 +#define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 +#define regCKSVII2C_IC_ENABLE_STATUS 0x0067 +#define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SPKLEN 0x0068 +#define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SPKLEN 0x0069 +#define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RESTART_DET 0x006a +#define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_PARAM_1 0x006b +#define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_VERSION 0x006c +#define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_TYPE 0x006d +#define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 +#define regCKSVII2C1_IC_CON 0x0080 +#define regCKSVII2C1_IC_CON_BASE_IDX 0 +#define regCKSVII2C1_IC_TAR 0x0081 +#define regCKSVII2C1_IC_TAR_BASE_IDX 0 +#define regCKSVII2C1_IC_SAR 0x0082 +#define regCKSVII2C1_IC_SAR_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_MADDR 0x0083 +#define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 +#define regCKSVII2C1_IC_DATA_CMD 0x0084 +#define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 +#define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085 +#define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086 +#define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087 +#define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088 +#define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089 +#define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a +#define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_INTR_STAT 0x008b +#define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C1_IC_INTR_MASK 0x008c +#define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 +#define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d +#define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C1_IC_RX_TL 0x008e +#define regCKSVII2C1_IC_RX_TL_BASE_IDX 0 +#define regCKSVII2C1_IC_TX_TL 0x008f +#define regCKSVII2C1_IC_TX_TL_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_INTR 0x0090 +#define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091 +#define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_OVER 0x0092 +#define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_TX_OVER 0x0093 +#define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RD_REQ 0x0094 +#define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095 +#define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_DONE 0x0096 +#define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097 +#define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_STOP_DET 0x0098 +#define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_START_DET 0x0099 +#define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a +#define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 +#define regCKSVII2C1_IC_ENABLE 0x009b +#define regCKSVII2C1_IC_ENABLE_BASE_IDX 0 +#define regCKSVII2C1_IC_STATUS 0x009c +#define regCKSVII2C1_IC_STATUS_BASE_IDX 0 +#define regCKSVII2C1_IC_TXFLR 0x009d +#define regCKSVII2C1_IC_TXFLR_BASE_IDX 0 +#define regCKSVII2C1_IC_RXFLR 0x009e +#define regCKSVII2C1_IC_RXFLR_BASE_IDX 0 +#define regCKSVII2C1_IC_SDA_HOLD 0x009f +#define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 +#define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 +#define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 +#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 +#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_CR 0x00a2 +#define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_TDLR 0x00a3 +#define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_RDLR 0x00a4 +#define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 +#define regCKSVII2C1_IC_SDA_SETUP 0x00a5 +#define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 +#define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 +#define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 +#define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7 +#define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SPKLEN 0x00a8 +#define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SPKLEN 0x00a9 +#define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa +#define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_PARAM_1 0x00ab +#define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_VERSION 0x00ac +#define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_TYPE 0x00ad +#define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 +#define regSMUIO_MP_RESET_INTR 0x00c1 +#define regSMUIO_MP_RESET_INTR_BASE_IDX 0 +#define regSMUIO_SOC_HALT 0x00c2 +#define regSMUIO_SOC_HALT_BASE_IDX 0 +#define regSMUIO_PWRMGT 0x00cd +#define regSMUIO_PWRMGT_BASE_IDX 0 +#define regSMUIO_GFX_MISC_CNTL 0x00d1 +#define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0 +#define regROM_CNTL 0x00e1 +#define regROM_CNTL_BASE_IDX 0 +#define regPAGE_MIRROR_CNTL 0x00e2 +#define regPAGE_MIRROR_CNTL_BASE_IDX 0 +#define regROM_STATUS 0x00e3 +#define regROM_STATUS_BASE_IDX 0 +#define regCGTT_ROM_CLK_CTRL0 0x00e4 +#define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0 +#define regROM_INDEX 0x00e5 +#define regROM_INDEX_BASE_IDX 0 +#define regROM_DATA 0x00e6 +#define regROM_DATA_BASE_IDX 0 +#define regROM_START 0x00e7 +#define regROM_START_BASE_IDX 0 +#define regROM_SW_CNTL 0x00e9 +#define regROM_SW_CNTL_BASE_IDX 0 +#define regROM_SW_STATUS 0x00ea +#define regROM_SW_STATUS_BASE_IDX 0 +#define regROM_SW_COMMAND 0x00eb +#define regROM_SW_COMMAND_BASE_IDX 0 +#define regROM_SW_DATA_1 0x00ed +#define regROM_SW_DATA_1_BASE_IDX 0 +#define regROM_SW_DATA_2 0x00ee +#define regROM_SW_DATA_2_BASE_IDX 0 +#define regROM_SW_DATA_3 0x00ef +#define regROM_SW_DATA_3_BASE_IDX 0 +#define regROM_SW_DATA_4 0x00f0 +#define regROM_SW_DATA_4_BASE_IDX 0 +#define regROM_SW_DATA_5 0x00f1 +#define regROM_SW_DATA_5_BASE_IDX 0 +#define regROM_SW_DATA_6 0x00f2 +#define regROM_SW_DATA_6_BASE_IDX 0 +#define regROM_SW_DATA_7 0x00f3 +#define regROM_SW_DATA_7_BASE_IDX 0 +#define regROM_SW_DATA_8 0x00f4 +#define regROM_SW_DATA_8_BASE_IDX 0 +#define regROM_SW_DATA_9 0x00f5 +#define regROM_SW_DATA_9_BASE_IDX 0 +#define regROM_SW_DATA_10 0x00f6 +#define regROM_SW_DATA_10_BASE_IDX 0 +#define regROM_SW_DATA_11 0x00f7 +#define regROM_SW_DATA_11_BASE_IDX 0 +#define regROM_SW_DATA_12 0x00f8 +#define regROM_SW_DATA_12_BASE_IDX 0 +#define regROM_SW_DATA_13 0x00f9 +#define regROM_SW_DATA_13_BASE_IDX 0 +#define regROM_SW_DATA_14 0x00fa +#define regROM_SW_DATA_14_BASE_IDX 0 +#define regROM_SW_DATA_15 0x00fb +#define regROM_SW_DATA_15_BASE_IDX 0 +#define regROM_SW_DATA_16 0x00fc +#define regROM_SW_DATA_16_BASE_IDX 0 +#define regROM_SW_DATA_17 0x00fd +#define regROM_SW_DATA_17_BASE_IDX 0 +#define regROM_SW_DATA_18 0x00fe +#define regROM_SW_DATA_18_BASE_IDX 0 +#define regROM_SW_DATA_19 0x00ff +#define regROM_SW_DATA_19_BASE_IDX 0 +#define regROM_SW_DATA_20 0x0100 +#define regROM_SW_DATA_20_BASE_IDX 0 +#define regROM_SW_DATA_21 0x0101 +#define regROM_SW_DATA_21_BASE_IDX 0 +#define regROM_SW_DATA_22 0x0102 +#define regROM_SW_DATA_22_BASE_IDX 0 +#define regROM_SW_DATA_23 0x0103 +#define regROM_SW_DATA_23_BASE_IDX 0 +#define regROM_SW_DATA_24 0x0104 +#define regROM_SW_DATA_24_BASE_IDX 0 +#define regROM_SW_DATA_25 0x0105 +#define regROM_SW_DATA_25_BASE_IDX 0 +#define regROM_SW_DATA_26 0x0106 +#define regROM_SW_DATA_26_BASE_IDX 0 +#define regROM_SW_DATA_27 0x0107 +#define regROM_SW_DATA_27_BASE_IDX 0 +#define regROM_SW_DATA_28 0x0108 +#define regROM_SW_DATA_28_BASE_IDX 0 +#define regROM_SW_DATA_29 0x0109 +#define regROM_SW_DATA_29_BASE_IDX 0 +#define regROM_SW_DATA_30 0x010a +#define regROM_SW_DATA_30_BASE_IDX 0 +#define regROM_SW_DATA_31 0x010b +#define regROM_SW_DATA_31_BASE_IDX 0 +#define regROM_SW_DATA_32 0x010c +#define regROM_SW_DATA_32_BASE_IDX 0 +#define regROM_SW_DATA_33 0x010d +#define regROM_SW_DATA_33_BASE_IDX 0 +#define regROM_SW_DATA_34 0x010e +#define regROM_SW_DATA_34_BASE_IDX 0 +#define regROM_SW_DATA_35 0x010f +#define regROM_SW_DATA_35_BASE_IDX 0 +#define regROM_SW_DATA_36 0x0110 +#define regROM_SW_DATA_36_BASE_IDX 0 +#define regROM_SW_DATA_37 0x0111 +#define regROM_SW_DATA_37_BASE_IDX 0 +#define regROM_SW_DATA_38 0x0112 +#define regROM_SW_DATA_38_BASE_IDX 0 +#define regROM_SW_DATA_39 0x0113 +#define regROM_SW_DATA_39_BASE_IDX 0 +#define regROM_SW_DATA_40 0x0114 +#define regROM_SW_DATA_40_BASE_IDX 0 +#define regROM_SW_DATA_41 0x0115 +#define regROM_SW_DATA_41_BASE_IDX 0 +#define regROM_SW_DATA_42 0x0116 +#define regROM_SW_DATA_42_BASE_IDX 0 +#define regROM_SW_DATA_43 0x0117 +#define regROM_SW_DATA_43_BASE_IDX 0 +#define regROM_SW_DATA_44 0x0118 +#define regROM_SW_DATA_44_BASE_IDX 0 +#define regROM_SW_DATA_45 0x0119 +#define regROM_SW_DATA_45_BASE_IDX 0 +#define regROM_SW_DATA_46 0x011a +#define regROM_SW_DATA_46_BASE_IDX 0 +#define regROM_SW_DATA_47 0x011b +#define regROM_SW_DATA_47_BASE_IDX 0 +#define regROM_SW_DATA_48 0x011c +#define regROM_SW_DATA_48_BASE_IDX 0 +#define regROM_SW_DATA_49 0x011d +#define regROM_SW_DATA_49_BASE_IDX 0 +#define regROM_SW_DATA_50 0x011e +#define regROM_SW_DATA_50_BASE_IDX 0 +#define regROM_SW_DATA_51 0x011f +#define regROM_SW_DATA_51_BASE_IDX 0 +#define regROM_SW_DATA_52 0x0120 +#define regROM_SW_DATA_52_BASE_IDX 0 +#define regROM_SW_DATA_53 0x0121 +#define regROM_SW_DATA_53_BASE_IDX 0 +#define regROM_SW_DATA_54 0x0122 +#define regROM_SW_DATA_54_BASE_IDX 0 +#define regROM_SW_DATA_55 0x0123 +#define regROM_SW_DATA_55_BASE_IDX 0 +#define regROM_SW_DATA_56 0x0124 +#define regROM_SW_DATA_56_BASE_IDX 0 +#define regROM_SW_DATA_57 0x0125 +#define regROM_SW_DATA_57_BASE_IDX 0 +#define regROM_SW_DATA_58 0x0126 +#define regROM_SW_DATA_58_BASE_IDX 0 +#define regROM_SW_DATA_59 0x0127 +#define regROM_SW_DATA_59_BASE_IDX 0 +#define regROM_SW_DATA_60 0x0128 +#define regROM_SW_DATA_60_BASE_IDX 0 +#define regROM_SW_DATA_61 0x0129 +#define regROM_SW_DATA_61_BASE_IDX 0 +#define regROM_SW_DATA_62 0x012a +#define regROM_SW_DATA_62_BASE_IDX 0 +#define regROM_SW_DATA_63 0x012b +#define regROM_SW_DATA_63_BASE_IDX 0 +#define regROM_SW_DATA_64 0x012c +#define regROM_SW_DATA_64_BASE_IDX 0 +#define regSMU_GPIOPAD_SW_INT_STAT 0x0140 +#define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MASK 0x0141 +#define regSMU_GPIOPAD_MASK_BASE_IDX 0 +#define regSMU_GPIOPAD_A 0x0142 +#define regSMU_GPIOPAD_A_BASE_IDX 0 +#define regSMU_GPIOPAD_TXIMPSEL 0x0143 +#define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 +#define regSMU_GPIOPAD_EN 0x0144 +#define regSMU_GPIOPAD_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_Y 0x0145 +#define regSMU_GPIOPAD_Y_BASE_IDX 0 +#define regSMU_GPIOPAD_RXEN 0x0146 +#define regSMU_GPIOPAD_RXEN_BASE_IDX 0 +#define regSMU_GPIOPAD_RCVR_SEL0 0x0147 +#define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 +#define regSMU_GPIOPAD_RCVR_SEL1 0x0148 +#define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 +#define regSMU_GPIOPAD_PU_EN 0x0149 +#define regSMU_GPIOPAD_PU_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_PD_EN 0x014a +#define regSMU_GPIOPAD_PD_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_PINSTRAPS 0x014b +#define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 +#define regDFT_PINSTRAPS 0x014c +#define regDFT_PINSTRAPS_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT_EN 0x014d +#define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT 0x014e +#define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT_AK 0x014f +#define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_EN 0x0150 +#define regSMU_GPIOPAD_INT_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_TYPE 0x0151 +#define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_POLARITY 0x0152 +#define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 +#define regROM_CC_BIF_PINSTRAP 0x0153 +#define regROM_CC_BIF_PINSTRAP_BASE_IDX 0 +#define regIO_SMUIO_PINSTRAP 0x0154 +#define regIO_SMUIO_PINSTRAP_BASE_IDX 0 +#define regSMUIO_PCC_CONTROL 0x0155 +#define regSMUIO_PCC_CONTROL_BASE_IDX 0 +#define regSMUIO_PCC_GPIO_SELECT 0x0156 +#define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT0_SELECT 0x0157 +#define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT1_SELECT 0x0158 +#define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT2_SELECT 0x0159 +#define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT3_SELECT 0x015a +#define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT0_STAT 0x015b +#define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT1_STAT 0x015c +#define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT2_STAT 0x015d +#define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT3_STAT 0x015e +#define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 +#define regSMIO_INDEX 0x015f +#define regSMIO_INDEX_BASE_IDX 0 +#define regS0_VID_SMIO_CNTL 0x0160 +#define regS0_VID_SMIO_CNTL_BASE_IDX 0 +#define regS1_VID_SMIO_CNTL 0x0161 +#define regS1_VID_SMIO_CNTL_BASE_IDX 0 +#define regOPEN_DRAIN_SELECT 0x0162 +#define regOPEN_DRAIN_SELECT_BASE_IDX 0 +#define regSMIO_ENABLE 0x0163 +#define regSMIO_ENABLE_BASE_IDX 0 +#define regSMU_GPIOPAD_S0 0x0164 +#define regSMU_GPIOPAD_S0_BASE_IDX 0 +#define regSMU_GPIOPAD_S1 0x0165 +#define regSMU_GPIOPAD_S1_BASE_IDX 0 +#define regSMU_GPIOPAD_SCL_EN 0x0166 +#define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_SDA_EN 0x0167 +#define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_SCHMEN 0x0168 +#define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0 + + +// addressBlock: smuio_smuio_pwr_SmuSmuioDec +// base address: 0x5a800 +#define regIP_DISCOVERY_VERSION 0x0000 +#define regIP_DISCOVERY_VERSION_BASE_IDX 1 +#define regSOC_GAP_PWROK 0x00fc +#define regSOC_GAP_PWROK_BASE_IDX 1 +#define regGFX_GAP_PWROK 0x00fd +#define regGFX_GAP_PWROK_BASE_IDX 1 +#define regPWROK_REFCLK_GAP_CYCLES 0x00fe +#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_UPPER 0x0104 +#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_LOWER 0x0105 +#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_UPPER 0x0106 +#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_LOWER 0x0107 +#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0108 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0109 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define regGFX_GOLDEN_TSC_SHADOW_UPPER 0x010a +#define regGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define regGFX_GOLDEN_TSC_SHADOW_LOWER 0x010b +#define regGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define regSCRATCH_REGISTER0 0x0114 +#define regSCRATCH_REGISTER0_BASE_IDX 1 +#define regSCRATCH_REGISTER1 0x0115 +#define regSCRATCH_REGISTER1_BASE_IDX 1 +#define regSCRATCH_REGISTER2 0x0116 +#define regSCRATCH_REGISTER2_BASE_IDX 1 +#define regSCRATCH_REGISTER3 0x0117 +#define regSCRATCH_REGISTER3_BASE_IDX 1 +#define regSCRATCH_REGISTER4 0x0118 +#define regSCRATCH_REGISTER4_BASE_IDX 1 +#define regSCRATCH_REGISTER5 0x0119 +#define regSCRATCH_REGISTER5_BASE_IDX 1 +#define regSCRATCH_REGISTER6 0x011a +#define regSCRATCH_REGISTER6_BASE_IDX 1 +#define regSCRATCH_REGISTER7 0x011b +#define regSCRATCH_REGISTER7_BASE_IDX 1 +#define regPWR_DISP_TIMER_CONTROL 0x0134 +#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER_DEBUG 0x0135 +#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER2_CONTROL 0x0136 +#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER2_DEBUG 0x0137 +#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0138 +#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 +#define regPWR_IH_CONTROL 0x0139 +#define regPWR_IH_CONTROL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..7040b99b522481ce8124aee46d99cf435b519336 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h @@ -0,0 +1,1163 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _smuio_13_0_2_SH_MASK_HEADER +#define _smuio_13_0_2_SH_MASK_HEADER + + +// addressBlock: smuio_smuio_SmuSmuioDec +//SMUSVI0_TEL_PLANE0 +#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0 +#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 +#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL +#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L +//SMUSVI0_PLANE0_CURRENTVID +#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18 +#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L +//SMUIO_MCM_CONFIG +#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 +#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x1 +#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x4 +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x8 +#define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0xa +#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000001L +#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000000EL +#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x000000F0L +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00000300L +#define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00007C00L +//CKSVII2C_IC_CON +#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 +#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 +#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L +#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L +//CKSVII2C_IC_TAR +#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 +#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa +#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc +#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL +#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L +#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L +//CKSVII2C_IC_SAR +#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 +#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL +//CKSVII2C_IC_HS_MADDR +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L +//CKSVII2C_IC_DATA_CMD +#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 +#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 +#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 +#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa +#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL +#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L +#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L +#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L +//CKSVII2C_IC_SS_SCL_HCNT +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_SS_SCL_LCNT +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_HCNT +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_LCNT +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_HCNT +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_LCNT +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_INTR_STAT +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_INTR_MASK +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_RAW_INTR_STAT +//CKSVII2C_IC_RX_TL +#define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 +#define CKSVII2C_IC_RX_TL__RX_TL_MASK 0x000000FFL +//CKSVII2C_IC_TX_TL +#define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 +#define CKSVII2C_IC_TX_TL__TX_TL_MASK 0x000000FFL +//CKSVII2C_IC_CLR_INTR +//CKSVII2C_IC_CLR_RX_UNDER +//CKSVII2C_IC_CLR_RX_OVER +//CKSVII2C_IC_CLR_TX_OVER +//CKSVII2C_IC_CLR_RD_REQ +//CKSVII2C_IC_CLR_TX_ABRT +//CKSVII2C_IC_CLR_RX_DONE +//CKSVII2C_IC_CLR_ACTIVITY +//CKSVII2C_IC_CLR_STOP_DET +//CKSVII2C_IC_CLR_START_DET +//CKSVII2C_IC_CLR_GEN_CALL +//CKSVII2C_IC_ENABLE +#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 +#define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L +#define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L +#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK_MASK 0x00000004L +//CKSVII2C_IC_STATUS +#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 +#define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 +#define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 +#define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 +#define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 +#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 +#define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L +#define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L +#define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L +#define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L +#define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L +#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L +//CKSVII2C_IC_TXFLR +#define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 +#define CKSVII2C_IC_TXFLR__TXFLR_MASK 0x0000003FL +//CKSVII2C_IC_RXFLR +#define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 +#define CKSVII2C_IC_RXFLR__RXFLR_MASK 0x0000003FL +//CKSVII2C_IC_SDA_HOLD +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD_MASK 0x0000FFFFL +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD_MASK 0x00FF0000L +//CKSVII2C_IC_TX_ABRT_SOURCE +//CKSVII2C_IC_SLV_DATA_NACK_ONLY +//CKSVII2C_IC_DMA_CR +//CKSVII2C_IC_DMA_TDLR +//CKSVII2C_IC_DMA_RDLR +//CKSVII2C_IC_SDA_SETUP +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL +//CKSVII2C_IC_ACK_GENERAL_CALL +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL__SHIFT 0x0 +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL_MASK 0x00000001L +//CKSVII2C_IC_ENABLE_STATUS +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L +#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY_MASK 0x00000002L +#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST_MASK 0x00000004L +//CKSVII2C_IC_FS_SPKLEN +#define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_HS_SPKLEN +#define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_CLR_RESTART_DET +//CKSVII2C_IC_COMP_PARAM_1 +#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 +#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 +#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 +#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 +#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 +#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 +#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 +#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 +#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH_MASK 0x00000003L +#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE_MASK 0x0000000CL +#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES_MASK 0x00000010L +#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO_MASK 0x00000020L +#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA_MASK 0x00000040L +#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS_MASK 0x00000080L +#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH_MASK 0x0000FF00L +#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH_MASK 0x00FF0000L +//CKSVII2C_IC_COMP_VERSION +#define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION__SHIFT 0x0 +#define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION_MASK 0xFFFFFFFFL +//CKSVII2C_IC_COMP_TYPE +#define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE__SHIFT 0x0 +#define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE_MASK 0xFFFFFFFFL +//CKSVII2C1_IC_CON +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 +#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L +#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L +//CKSVII2C1_IC_TAR +#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 +#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa +#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc +#define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL +#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L +#define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L +//CKSVII2C1_IC_SAR +#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 +#define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL +//CKSVII2C1_IC_HS_MADDR +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L +//CKSVII2C1_IC_DATA_CMD +#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 +#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 +#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 +#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa +#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL +#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L +#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L +#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L +//CKSVII2C1_IC_SS_SCL_HCNT +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_SS_SCL_LCNT +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_FS_SCL_HCNT +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_FS_SCL_LCNT +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_HS_SCL_HCNT +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_HS_SCL_LCNT +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_INTR_STAT +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C1_IC_INTR_MASK +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C1_IC_RAW_INTR_STAT +//CKSVII2C1_IC_RX_TL +#define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 +#define CKSVII2C1_IC_RX_TL__RX1_TL_MASK 0x000000FFL +//CKSVII2C1_IC_TX_TL +#define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 +#define CKSVII2C1_IC_TX_TL__TX1_TL_MASK 0x000000FFL +//CKSVII2C1_IC_CLR_INTR +//CKSVII2C1_IC_CLR_RX_UNDER +//CKSVII2C1_IC_CLR_RX_OVER +//CKSVII2C1_IC_CLR_TX_OVER +//CKSVII2C1_IC_CLR_RD_REQ +//CKSVII2C1_IC_CLR_TX_ABRT +//CKSVII2C1_IC_CLR_RX_DONE +//CKSVII2C1_IC_CLR_ACTIVITY +//CKSVII2C1_IC_CLR_STOP_DET +//CKSVII2C1_IC_CLR_START_DET +//CKSVII2C1_IC_CLR_GEN_CALL +//CKSVII2C1_IC_ENABLE +#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 +#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 +#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 +#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L +#define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L +#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK_MASK 0x00000004L +//CKSVII2C1_IC_STATUS +#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 +#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 +#define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 +#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 +#define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 +#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L +#define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L +#define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L +#define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L +#define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L +//CKSVII2C1_IC_TXFLR +#define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 +#define CKSVII2C1_IC_TXFLR__TXFLR1_MASK 0x0000003FL +//CKSVII2C1_IC_RXFLR +#define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 +#define CKSVII2C1_IC_RXFLR__RXFLR1_MASK 0x0000003FL +//CKSVII2C1_IC_SDA_HOLD +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD_MASK 0x0000FFFFL +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD_MASK 0x00FF0000L +//CKSVII2C1_IC_TX_ABRT_SOURCE +//CKSVII2C1_IC_SLV_DATA_NACK_ONLY +//CKSVII2C1_IC_DMA_CR +//CKSVII2C1_IC_DMA_TDLR +//CKSVII2C1_IC_DMA_RDLR +//CKSVII2C1_IC_SDA_SETUP +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL +//CKSVII2C1_IC_ACK_GENERAL_CALL +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL__SHIFT 0x0 +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL_MASK 0x00000001L +//CKSVII2C1_IC_ENABLE_STATUS +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY_MASK 0x00000002L +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST_MASK 0x00000004L +//CKSVII2C1_IC_FS_SPKLEN +#define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN__SHIFT 0x0 +#define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN_MASK 0x000000FFL +//CKSVII2C1_IC_HS_SPKLEN +#define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN__SHIFT 0x0 +#define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN_MASK 0x000000FFL +//CKSVII2C1_IC_CLR_RESTART_DET +//CKSVII2C1_IC_COMP_PARAM_1 +#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 +#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 +#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 +#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 +#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 +#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 +#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 +#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 +#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH_MASK 0x00000003L +#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE_MASK 0x0000000CL +#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES_MASK 0x00000010L +#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO_MASK 0x00000020L +#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA_MASK 0x00000040L +#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS_MASK 0x00000080L +#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH_MASK 0x0000FF00L +#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH_MASK 0x00FF0000L +//CKSVII2C1_IC_COMP_VERSION +#define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION__SHIFT 0x0 +#define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION_MASK 0xFFFFFFFFL +//CKSVII2C1_IC_COMP_TYPE +#define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE__SHIFT 0x0 +#define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE_MASK 0xFFFFFFFFL +//SMUIO_MP_RESET_INTR +#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 +#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L +//SMUIO_SOC_HALT +#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 +#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 +#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L +#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L +//SMUIO_PWRMGT +#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 +#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 +#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L +#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L +//SMUIO_GFX_MISC_CNTL +#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 +#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L +//ROM_CNTL +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 +#define ROM_CNTL__READ_MODE__SHIFT 0x1 +#define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 +#define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 +#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 +#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 +#define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 +#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14 +#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15 +#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16 +#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c +#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L +#define ROM_CNTL__READ_MODE_MASK 0x00000006L +#define ROM_CNTL__READ_MODE_OVERRIDE_MASK 0x00000008L +#define ROM_CNTL__SPI_TIMING_RELAX_SCK_MASK 0x00000010L +#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE_MASK 0x00000020L +#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE_MASK 0x00000040L +#define ROM_CNTL__DUMMY_CYCLE_NUM_MASK 0x00000F00L +#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L +#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L +#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L +#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L +#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L +#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE_MASK 0x20000000L +//PAGE_MIRROR_CNTL +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L +//ROM_STATUS +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L +//CGTT_ROM_CLK_CTRL0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//ROM_INDEX +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL +//ROM_DATA +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL +//ROM_START +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0x01FFFFFFL +//ROM_SW_CNTL +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L +//ROM_SW_STATUS +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L +//ROM_SW_COMMAND +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L +//ROM_SW_DATA_1 +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_2 +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_3 +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_4 +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_5 +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_6 +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_7 +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_8 +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_9 +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_10 +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_11 +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_12 +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_13 +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_14 +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_15 +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_16 +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_17 +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_18 +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_19 +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_20 +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_21 +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_22 +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_23 +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_24 +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_25 +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_26 +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_27 +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_28 +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_29 +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_30 +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_31 +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_32 +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_33 +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_34 +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_35 +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_36 +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_37 +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_38 +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_39 +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_40 +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_41 +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_42 +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_43 +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_44 +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_45 +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_46 +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_47 +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_48 +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_49 +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_50 +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_51 +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_52 +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_53 +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_54 +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_55 +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_56 +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_57 +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_58 +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_59 +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_60 +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_61 +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_62 +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_63 +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_64 +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL +//SMU_GPIOPAD_SW_INT_STAT +#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L +//SMU_GPIOPAD_MASK +#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_A +#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_TXIMPSEL +#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 +#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_EN +#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_Y +#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RXEN +#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 +#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RCVR_SEL0 +#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 +#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RCVR_SEL1 +#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 +#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PU_EN +#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PD_EN +#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PINSTRAPS +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L +//DFT_PINSTRAPS +#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 +#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL +//SMU_GPIOPAD_INT_STAT_EN +#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L +//SMU_GPIOPAD_INT_STAT +#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L +//SMU_GPIOPAD_INT_STAT_AK +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L +#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L +//SMU_GPIOPAD_INT_EN +#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L +//SMU_GPIOPAD_INT_TYPE +#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L +//SMU_GPIOPAD_INT_POLARITY +#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L +//ROM_CC_BIF_PINSTRAP +#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0 +#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1 +#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4 +#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7 +#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8 +#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9 +#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa +#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L +#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL +#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L +#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L +#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L +#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L +#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L +//IO_SMUIO_PINSTRAP +#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 +#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 +#define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5 +#define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8 +#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L +#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L +#define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L +#define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L +//SMUIO_PCC_CONTROL +#define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 +#define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L +//SMUIO_PCC_GPIO_SELECT +#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT0_SELECT +#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT1_SELECT +#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT2_SELECT +#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT3_SELECT +#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL +//SMU_GPIOPAD_MP_INT0_STAT +#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT1_STAT +#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT2_STAT +#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT3_STAT +#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL +//SMIO_INDEX +#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 +#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L +//S0_VID_SMIO_CNTL +#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 +#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL +//S1_VID_SMIO_CNTL +#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 +#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL +//OPEN_DRAIN_SELECT +#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 +#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f +#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL +#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L +//SMIO_ENABLE +#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 +#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL +//SMU_GPIOPAD_S0 +#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 +#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_S1 +#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 +#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SCL_EN +#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 +#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SDA_EN +#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 +#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SCHMEN +#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 +#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL + + +// addressBlock: smuio_smuio_pwr_SmuSmuioDec +//IP_DISCOVERY_VERSION +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL +//SOC_GAP_PWROK +#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 +#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L +//GFX_GAP_PWROK +#define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0 +#define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L +//PWROK_REFCLK_GAP_CYCLES +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L +//GOLDEN_TSC_INCREMENT_UPPER +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_INCREMENT_LOWER +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL +//GOLDEN_TSC_COUNT_UPPER +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_COUNT_LOWER +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL +//SOC_GOLDEN_TSC_SHADOW_UPPER +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL +//SOC_GOLDEN_TSC_SHADOW_LOWER +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL +//GFX_GOLDEN_TSC_SHADOW_UPPER +#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0 +#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL +//GFX_GOLDEN_TSC_SHADOW_LOWER +#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0 +#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER0 +#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 +#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER1 +#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 +#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER2 +#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 +#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER3 +#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 +#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER4 +#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 +#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER5 +#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 +#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER6 +#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 +#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER7 +#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 +#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL +//PWR_DISP_TIMER_CONTROL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER_DEBUG +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER2_CONTROL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER2_DEBUG +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER_GLOBAL_CONTROL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L +//PWR_IH_CONTROL +#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 +#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..ea03c9d135e995c80373e80a0880fc8546dbde36 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h @@ -0,0 +1,346 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _thm_13_0_2_OFFSET_HEADER +#define _thm_13_0_2_OFFSET_HEADER + + + +// addressBlock: thm_thm_SmuThmDec +// base address: 0x59800 +#define regTHM_TCON_CUR_TMP 0x0000 +#define regTHM_TCON_CUR_TMP_BASE_IDX 0 +#define regTHM_TCON_HTC 0x0001 +#define regTHM_TCON_HTC_BASE_IDX 0 +#define regTHM_TCON_THERM_TRIP 0x0002 +#define regTHM_TCON_THERM_TRIP_BASE_IDX 0 +#define regTHM_CTF_DELAY 0x0003 +#define regTHM_CTF_DELAY_BASE_IDX 0 +#define regTHM_GPIO_PROCHOT_CTRL 0x0004 +#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 +#define regTHM_GPIO_THERMTRIP_CTRL 0x0005 +#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PWM_CTRL 0x0006 +#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0 +#define regTHM_GPIO_TACHIN_CTRL 0x0007 +#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PUMPOUT_CTRL 0x0008 +#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PUMPIN_CTRL 0x0009 +#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 +#define regTHM_THERMAL_INT_ENA 0x000a +#define regTHM_THERMAL_INT_ENA_BASE_IDX 0 +#define regTHM_THERMAL_INT_CTRL 0x000b +#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0 +#define regTHM_THERMAL_INT_STATUS 0x000c +#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0 +#define regTHM_TMON0_RDIL0_DATA 0x000d +#define regTHM_TMON0_RDIL0_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL1_DATA 0x000e +#define regTHM_TMON0_RDIL1_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL2_DATA 0x000f +#define regTHM_TMON0_RDIL2_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL3_DATA 0x0010 +#define regTHM_TMON0_RDIL3_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL4_DATA 0x0011 +#define regTHM_TMON0_RDIL4_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL5_DATA 0x0012 +#define regTHM_TMON0_RDIL5_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL6_DATA 0x0013 +#define regTHM_TMON0_RDIL6_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL7_DATA 0x0014 +#define regTHM_TMON0_RDIL7_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL8_DATA 0x0015 +#define regTHM_TMON0_RDIL8_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL9_DATA 0x0016 +#define regTHM_TMON0_RDIL9_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL10_DATA 0x0017 +#define regTHM_TMON0_RDIL10_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL11_DATA 0x0018 +#define regTHM_TMON0_RDIL11_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL12_DATA 0x0019 +#define regTHM_TMON0_RDIL12_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL13_DATA 0x001a +#define regTHM_TMON0_RDIL13_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL14_DATA 0x001b +#define regTHM_TMON0_RDIL14_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIL15_DATA 0x001c +#define regTHM_TMON0_RDIL15_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR0_DATA 0x001d +#define regTHM_TMON0_RDIR0_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR1_DATA 0x001e +#define regTHM_TMON0_RDIR1_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR2_DATA 0x001f +#define regTHM_TMON0_RDIR2_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR3_DATA 0x0020 +#define regTHM_TMON0_RDIR3_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR4_DATA 0x0021 +#define regTHM_TMON0_RDIR4_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR5_DATA 0x0022 +#define regTHM_TMON0_RDIR5_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR6_DATA 0x0023 +#define regTHM_TMON0_RDIR6_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR7_DATA 0x0024 +#define regTHM_TMON0_RDIR7_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR8_DATA 0x0025 +#define regTHM_TMON0_RDIR8_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR9_DATA 0x0026 +#define regTHM_TMON0_RDIR9_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR10_DATA 0x0027 +#define regTHM_TMON0_RDIR10_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR11_DATA 0x0028 +#define regTHM_TMON0_RDIR11_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR12_DATA 0x0029 +#define regTHM_TMON0_RDIR12_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR13_DATA 0x002a +#define regTHM_TMON0_RDIR13_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR14_DATA 0x002b +#define regTHM_TMON0_RDIR14_DATA_BASE_IDX 0 +#define regTHM_TMON0_RDIR15_DATA 0x002c +#define regTHM_TMON0_RDIR15_DATA_BASE_IDX 0 +#define regTHM_TMON0_INT_DATA 0x002d +#define regTHM_TMON0_INT_DATA_BASE_IDX 0 +#define regTHM_TMON0_CTRL 0x002e +#define regTHM_TMON0_CTRL_BASE_IDX 0 +#define regTHM_TMON0_CTRL2 0x002f +#define regTHM_TMON0_CTRL2_BASE_IDX 0 +#define regTHM_TMON1_RDIL0_DATA 0x0031 +#define regTHM_TMON1_RDIL0_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL1_DATA 0x0032 +#define regTHM_TMON1_RDIL1_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL2_DATA 0x0033 +#define regTHM_TMON1_RDIL2_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL3_DATA 0x0034 +#define regTHM_TMON1_RDIL3_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL4_DATA 0x0035 +#define regTHM_TMON1_RDIL4_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL5_DATA 0x0036 +#define regTHM_TMON1_RDIL5_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL6_DATA 0x0037 +#define regTHM_TMON1_RDIL6_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL7_DATA 0x0038 +#define regTHM_TMON1_RDIL7_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL8_DATA 0x0039 +#define regTHM_TMON1_RDIL8_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL9_DATA 0x003a +#define regTHM_TMON1_RDIL9_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL10_DATA 0x003b +#define regTHM_TMON1_RDIL10_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL11_DATA 0x003c +#define regTHM_TMON1_RDIL11_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL12_DATA 0x003d +#define regTHM_TMON1_RDIL12_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL13_DATA 0x003e +#define regTHM_TMON1_RDIL13_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL14_DATA 0x003f +#define regTHM_TMON1_RDIL14_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIL15_DATA 0x0040 +#define regTHM_TMON1_RDIL15_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR0_DATA 0x0041 +#define regTHM_TMON1_RDIR0_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR1_DATA 0x0042 +#define regTHM_TMON1_RDIR1_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR2_DATA 0x0043 +#define regTHM_TMON1_RDIR2_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR3_DATA 0x0044 +#define regTHM_TMON1_RDIR3_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR4_DATA 0x0045 +#define regTHM_TMON1_RDIR4_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR5_DATA 0x0046 +#define regTHM_TMON1_RDIR5_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR6_DATA 0x0047 +#define regTHM_TMON1_RDIR6_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR7_DATA 0x0048 +#define regTHM_TMON1_RDIR7_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR8_DATA 0x0049 +#define regTHM_TMON1_RDIR8_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR9_DATA 0x004a +#define regTHM_TMON1_RDIR9_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR10_DATA 0x004b +#define regTHM_TMON1_RDIR10_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR11_DATA 0x004c +#define regTHM_TMON1_RDIR11_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR12_DATA 0x004d +#define regTHM_TMON1_RDIR12_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR13_DATA 0x004e +#define regTHM_TMON1_RDIR13_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR14_DATA 0x004f +#define regTHM_TMON1_RDIR14_DATA_BASE_IDX 0 +#define regTHM_TMON1_RDIR15_DATA 0x0050 +#define regTHM_TMON1_RDIR15_DATA_BASE_IDX 0 +#define regTHM_TMON1_INT_DATA 0x0051 +#define regTHM_TMON1_INT_DATA_BASE_IDX 0 +#define regTHM_DIE1_TEMP 0x0079 +#define regTHM_DIE1_TEMP_BASE_IDX 0 +#define regTHM_DIE2_TEMP 0x007a +#define regTHM_DIE2_TEMP_BASE_IDX 0 +#define regTHM_DIE3_TEMP 0x007b +#define regTHM_DIE3_TEMP_BASE_IDX 0 +#define regTHM_SW_TEMP 0x0081 +#define regTHM_SW_TEMP_BASE_IDX 0 +#define regCG_MULT_THERMAL_CTRL 0x0082 +#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 +#define regCG_MULT_THERMAL_STATUS 0x0083 +#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 +#define regCG_THERMAL_RANGE 0x0084 +#define regCG_THERMAL_RANGE_BASE_IDX 0 +#define regTHM_TMON_CONFIG 0x0085 +#define regTHM_TMON_CONFIG_BASE_IDX 0 +#define regTHM_TMON_CONFIG2 0x0086 +#define regTHM_TMON_CONFIG2_BASE_IDX 0 +#define regTHM_TMON0_COEFF 0x0087 +#define regTHM_TMON0_COEFF_BASE_IDX 0 +#define regTHM_TMON1_COEFF 0x0088 +#define regTHM_TMON1_COEFF_BASE_IDX 0 +#define regCG_FDO_CTRL0 0x008b +#define regCG_FDO_CTRL0_BASE_IDX 0 +#define regCG_FDO_CTRL1 0x008c +#define regCG_FDO_CTRL1_BASE_IDX 0 +#define regCG_FDO_CTRL2 0x008d +#define regCG_FDO_CTRL2_BASE_IDX 0 +#define regCG_TACH_CTRL 0x008e +#define regCG_TACH_CTRL_BASE_IDX 0 +#define regCG_TACH_STATUS 0x008f +#define regCG_TACH_STATUS_BASE_IDX 0 +#define regCG_THERMAL_STATUS 0x0090 +#define regCG_THERMAL_STATUS_BASE_IDX 0 +#define regCG_PUMP_CTRL0 0x0091 +#define regCG_PUMP_CTRL0_BASE_IDX 0 +#define regCG_PUMP_CTRL1 0x0092 +#define regCG_PUMP_CTRL1_BASE_IDX 0 +#define regCG_PUMP_CTRL2 0x0093 +#define regCG_PUMP_CTRL2_BASE_IDX 0 +#define regCG_PUMP_TACH_CTRL 0x0094 +#define regCG_PUMP_TACH_CTRL_BASE_IDX 0 +#define regCG_PUMP_TACH_STATUS 0x0095 +#define regCG_PUMP_TACH_STATUS_BASE_IDX 0 +#define regCG_PUMP_STATUS 0x0096 +#define regCG_PUMP_STATUS_BASE_IDX 0 +#define regTHM_TCON_LOCAL0 0x0097 +#define regTHM_TCON_LOCAL0_BASE_IDX 0 +#define regTHM_TCON_LOCAL1 0x0098 +#define regTHM_TCON_LOCAL1_BASE_IDX 0 +#define regTHM_TCON_LOCAL2 0x0099 +#define regTHM_TCON_LOCAL2_BASE_IDX 0 +#define regTHM_TCON_LOCAL3 0x009a +#define regTHM_TCON_LOCAL3_BASE_IDX 0 +#define regTHM_TCON_LOCAL4 0x009b +#define regTHM_TCON_LOCAL4_BASE_IDX 0 +#define regTHM_TCON_LOCAL5 0x009c +#define regTHM_TCON_LOCAL5_BASE_IDX 0 +#define regTHM_TCON_LOCAL6 0x009d +#define regTHM_TCON_LOCAL6_BASE_IDX 0 +#define regTHM_TCON_LOCAL7 0x009e +#define regTHM_TCON_LOCAL7_BASE_IDX 0 +#define regTHM_TCON_LOCAL8 0x009f +#define regTHM_TCON_LOCAL8_BASE_IDX 0 +#define regTHM_TCON_LOCAL9 0x00a0 +#define regTHM_TCON_LOCAL9_BASE_IDX 0 +#define regTHM_TCON_LOCAL10 0x00a1 +#define regTHM_TCON_LOCAL10_BASE_IDX 0 +#define regTHM_TCON_LOCAL11 0x00a2 +#define regTHM_TCON_LOCAL11_BASE_IDX 0 +#define regTHM_TCON_LOCAL12 0x00a3 +#define regTHM_TCON_LOCAL12_BASE_IDX 0 +#define regTHM_TCON_LOCAL14 0x00a4 +#define regTHM_TCON_LOCAL14_BASE_IDX 0 +#define regTHM_TCON_LOCAL15 0x00a5 +#define regTHM_TCON_LOCAL15_BASE_IDX 0 +#define regTHM_TCON_LOCAL13 0x00a6 +#define regTHM_TCON_LOCAL13_BASE_IDX 0 +#define regXTAL_CNTL 0x00ac +#define regXTAL_CNTL_BASE_IDX 0 +#define regTHM_PWRMGT 0x00ad +#define regTHM_PWRMGT_BASE_IDX 0 +#define regTHM_GPIO_MACO_EN_CTRL 0x00ae +#define regTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0 +#define regSBTSI_REMOTE_TEMP 0x00ca +#define regSBTSI_REMOTE_TEMP_BASE_IDX 0 +#define regSBRMI_CONTROL 0x00cb +#define regSBRMI_CONTROL_BASE_IDX 0 +#define regSBRMI_COMMAND 0x00cc +#define regSBRMI_COMMAND_BASE_IDX 0 +#define regSBRMI_WRITE_DATA0 0x00cd +#define regSBRMI_WRITE_DATA0_BASE_IDX 0 +#define regSBRMI_WRITE_DATA1 0x00ce +#define regSBRMI_WRITE_DATA1_BASE_IDX 0 +#define regSBRMI_WRITE_DATA2 0x00cf +#define regSBRMI_WRITE_DATA2_BASE_IDX 0 +#define regSBRMI_READ_DATA0 0x00d0 +#define regSBRMI_READ_DATA0_BASE_IDX 0 +#define regSBRMI_READ_DATA1 0x00d1 +#define regSBRMI_READ_DATA1_BASE_IDX 0 +#define regSBRMI_CORE_EN_NUMBER 0x00d2 +#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS0 0x00d3 +#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS1 0x00d4 +#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 +#define regSBRMI_APIC_STATUS0 0x00d5 +#define regSBRMI_APIC_STATUS0_BASE_IDX 0 +#define regSBRMI_APIC_STATUS1 0x00d6 +#define regSBRMI_APIC_STATUS1_BASE_IDX 0 +#define regSBRMI_MCE_STATUS0 0x00db +#define regSBRMI_MCE_STATUS0_BASE_IDX 0 +#define regSBRMI_MCE_STATUS1 0x00dc +#define regSBRMI_MCE_STATUS1_BASE_IDX 0 +#define regSMBUS_CNTL0 0x00df +#define regSMBUS_CNTL0_BASE_IDX 0 +#define regSMBUS_CNTL1 0x00e0 +#define regSMBUS_CNTL1_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL0 0x00e1 +#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL1 0x00e2 +#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL0 0x00e3 +#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL1 0x00e4 +#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL0 0x00e5 +#define regSMBUS_TIMING_CNTL0_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL1 0x00e6 +#define regSMBUS_TIMING_CNTL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL2 0x00e7 +#define regSMBUS_TIMING_CNTL2_BASE_IDX 0 +#define regSMBUS_TRIGGER_CNTL 0x00e8 +#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 +#define regSMBUS_UDID_CNTL0 0x00e9 +#define regSMBUS_UDID_CNTL0_BASE_IDX 0 +#define regSMBUS_UDID_CNTL1 0x00ea +#define regSMBUS_UDID_CNTL1_BASE_IDX 0 +#define regSMBUS_UDID_CNTL2 0x00eb +#define regSMBUS_UDID_CNTL2_BASE_IDX 0 +#define regTHM_TMON0_REMOTE_START 0x0100 +#define regTHM_TMON0_REMOTE_START_BASE_IDX 0 +#define regTHM_TMON0_REMOTE_END 0x013f +#define regTHM_TMON0_REMOTE_END_BASE_IDX 0 +#define regTHM_TMON1_REMOTE_START 0x0140 +#define regTHM_TMON1_REMOTE_START_BASE_IDX 0 +#define regTHM_TMON1_REMOTE_END 0x017f +#define regTHM_TMON1_REMOTE_END_BASE_IDX 0 +#define regTHM_TMON2_REMOTE_START 0x0180 +#define regTHM_TMON2_REMOTE_START_BASE_IDX 0 +#define regTHM_TMON2_REMOTE_END 0x01bf +#define regTHM_TMON2_REMOTE_END_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..3d81ae1549011533779a21e01e8b4350d912dccf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h @@ -0,0 +1,1297 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _thm_13_0_2_SH_MASK_HEADER +#define _thm_13_0_2_SH_MASK_HEADER + + +// addressBlock: thm_thm_SmuThmDec +//THM_TCON_CUR_TMP +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L +#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L +//THM_TCON_HTC +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 +#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb +#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b +#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L +#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L +#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L +#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L +#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L +#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L +#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L +//THM_TCON_THERM_TRIP +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L +#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L +#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L +#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L +//THM_CTF_DELAY +#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 +#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL +//THM_GPIO_PROCHOT_CTRL +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L +//THM_GPIO_THERMTRIP_CTRL +#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 +#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 +#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L +#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L +#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L +//THM_GPIO_PWM_CTRL +#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L +//THM_GPIO_TACHIN_CTRL +#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 +#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L +#define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L +//THM_GPIO_PUMPOUT_CTRL +#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L +//THM_GPIO_PUMPIN_CTRL +#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L +//THM_THERMAL_INT_ENA +#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L +#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L +//THM_THERMAL_INT_CTRL +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b +#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c +#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L +#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L +#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L +#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L +#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L +//THM_THERMAL_INT_STATUS +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L +#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L +//THM_TMON0_RDIL0_DATA +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL1_DATA +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL2_DATA +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL3_DATA +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL4_DATA +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL5_DATA +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL6_DATA +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL7_DATA +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL8_DATA +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL9_DATA +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL10_DATA +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL11_DATA +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL12_DATA +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL13_DATA +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL14_DATA +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL15_DATA +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR0_DATA +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR1_DATA +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR2_DATA +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR3_DATA +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR4_DATA +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR5_DATA +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR6_DATA +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR7_DATA +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR8_DATA +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR9_DATA +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR10_DATA +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR11_DATA +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR12_DATA +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR13_DATA +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR14_DATA +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR15_DATA +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_INT_DATA +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_CTRL +#define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0 +#define THM_TMON0_CTRL__BGADJ__SHIFT 0x1 +#define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9 +#define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa +#define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb +#define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd +#define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L +#define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL +#define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L +#define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L +#define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L +#define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L +//THM_TMON0_CTRL2 +#define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0 +#define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10 +#define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL +#define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L +//THM_TMON1_RDIL0_DATA +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL1_DATA +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL2_DATA +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL3_DATA +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL4_DATA +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL5_DATA +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL6_DATA +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL7_DATA +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL8_DATA +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL9_DATA +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL10_DATA +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL11_DATA +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL12_DATA +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL13_DATA +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL14_DATA +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIL15_DATA +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR0_DATA +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR1_DATA +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR2_DATA +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR3_DATA +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR4_DATA +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR5_DATA +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR6_DATA +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR7_DATA +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR8_DATA +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR9_DATA +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR10_DATA +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR11_DATA +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR12_DATA +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR13_DATA +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR14_DATA +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_RDIR15_DATA +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON1_INT_DATA +#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL +#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L +//THM_DIE1_TEMP +#define THM_DIE1_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE1_TEMP__VALID__SHIFT 0xb +#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE1_TEMP__VALID_MASK 0x00000800L +//THM_DIE2_TEMP +#define THM_DIE2_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE2_TEMP__VALID__SHIFT 0xb +#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE2_TEMP__VALID_MASK 0x00000800L +//THM_DIE3_TEMP +#define THM_DIE3_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE3_TEMP__VALID__SHIFT 0xb +#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE3_TEMP__VALID_MASK 0x00000800L +//THM_SW_TEMP +#define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 +#define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL +//CG_MULT_THERMAL_CTRL +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L +//CG_MULT_THERMAL_STATUS +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L +//CG_THERMAL_RANGE +#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 +#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 +#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL +#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L +//THM_TMON_CONFIG +#define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0 +#define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define THM_TMON_CONFIG__TSEN_TMON_MODE__SHIFT 0x4 +#define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5 +#define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define THM_TMON_CONFIG__Z__SHIFT 0x15 +#define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L +#define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L +#define THM_TMON_CONFIG__TSEN_TMON_MODE_MASK 0x00000010L +#define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L +#define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L +#define THM_TMON_CONFIG__Z_MASK 0xFFE00000L +//THM_TMON_CONFIG2 +#define THM_TMON_CONFIG2__A__SHIFT 0x0 +#define THM_TMON_CONFIG2__B__SHIFT 0xc +#define THM_TMON_CONFIG2__C__SHIFT 0x12 +#define THM_TMON_CONFIG2__K__SHIFT 0x1d +#define THM_TMON_CONFIG2__A_MASK 0x00000FFFL +#define THM_TMON_CONFIG2__B_MASK 0x0003F000L +#define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L +#define THM_TMON_CONFIG2__K_MASK 0x20000000L +//THM_TMON0_COEFF +#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 +#define THM_TMON0_COEFF__D__SHIFT 0xb +#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL +#define THM_TMON0_COEFF__D_MASK 0x0003F800L +//THM_TMON1_COEFF +#define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0 +#define THM_TMON1_COEFF__D__SHIFT 0xb +#define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL +#define THM_TMON1_COEFF__D_MASK 0x0003F800L +//CG_FDO_CTRL0 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L +//CG_FDO_CTRL1 +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__TACH_IN_MAX__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L +#define CG_FDO_CTRL1__M_MASK 0x00FF0000L +#define CG_FDO_CTRL1__TACH_IN_MAX_MASK 0xFF000000L +//CG_FDO_CTRL2 +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L +#define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L +//CG_TACH_CTRL +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L +//CG_TACH_STATUS +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL +//CG_THERMAL_STATUS +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT__SHIFT 0x11 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L +#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L +//CG_PUMP_CTRL0 +#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0 +#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8 +#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10 +#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11 +#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17 +#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18 +#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL +#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L +#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L +#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L +#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L +#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L +//CG_PUMP_CTRL1 +#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0 +#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8 +#define CG_PUMP_CTRL1__M__SHIFT 0x10 +#define CG_PUMP_CTRL1__TACH_IN_MAX__SHIFT 0x18 +#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL +#define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L +#define CG_PUMP_CTRL1__M_MASK 0x00FF0000L +#define CG_PUMP_CTRL1__TACH_IN_MAX_MASK 0xFF000000L +//CG_PUMP_CTRL2 +#define CG_PUMP_CTRL2__TMIN__SHIFT 0x0 +#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8 +#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb +#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_PUMP_CTRL2__TMAX__SHIFT 0x11 +#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL +#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L +#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L +#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L +#define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L +#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L +//CG_PUMP_TACH_CTRL +#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L +#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L +//CG_PUMP_TACH_STATUS +#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL +//CG_PUMP_STATUS +#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9 +#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT__SHIFT 0x11 +#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L +#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L +//THM_TCON_LOCAL0 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 +#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis__SHIFT 0x3 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L +#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis_MASK 0x00000008L +//THM_TCON_LOCAL1 +#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 +#define THM_TCON_LOCAL1__Turn_Off_TMON2__SHIFT 0x2 +#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 +#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 +#define THM_TCON_LOCAL1__PowerDownTmon2__SHIFT 0x6 +#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L +#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L +#define THM_TCON_LOCAL1__Turn_Off_TMON2_MASK 0x00000004L +#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L +#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L +#define THM_TCON_LOCAL1__PowerDownTmon2_MASK 0x00000040L +//THM_TCON_LOCAL2 +#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 +#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 +#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 +#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa +#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb +#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL +#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L +#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L +#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L +#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L +//THM_TCON_LOCAL3 +#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 +#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL +//THM_TCON_LOCAL4 +#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 +#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL +//THM_TCON_LOCAL5 +#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 +#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL +//THM_TCON_LOCAL6 +#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 +#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL +//THM_TCON_LOCAL7 +#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 +#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL +//THM_TCON_LOCAL8 +#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 +#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL +//THM_TCON_LOCAL9 +#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL +//THM_TCON_LOCAL10 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL +//THM_TCON_LOCAL11 +#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 +#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL +//THM_TCON_LOCAL12 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL +//THM_TCON_LOCAL14 +#define THM_TCON_LOCAL14__Tj_Max_TMON2__SHIFT 0x0 +#define THM_TCON_LOCAL14__Tj_Max_TMON2_MASK 0x000007FFL +//THM_TCON_LOCAL15 +#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID_MASK 0x000000FFL +//THM_TCON_LOCAL13 +#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 +#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L +//XTAL_CNTL +#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0 +#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4 +#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8 +#define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc +#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L +#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L +#define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L +#define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L +//THM_PWRMGT +#define THM_PWRMGT__CLK_GATE_EN__SHIFT 0x0 +#define THM_PWRMGT__CLK_GATE_ST__SHIFT 0x1 +#define THM_PWRMGT__PUMP_CTL_GATE_EN__SHIFT 0x6 +#define THM_PWRMGT__FAN_CTL_GATE_EN__SHIFT 0x7 +#define THM_PWRMGT__CLK_GATE_MAX_CNT__SHIFT 0x8 +#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN__SHIFT 0x18 +#define THM_PWRMGT__CLK_GATE_EN_MASK 0x00000001L +#define THM_PWRMGT__CLK_GATE_ST_MASK 0x00000002L +#define THM_PWRMGT__PUMP_CTL_GATE_EN_MASK 0x00000040L +#define THM_PWRMGT__FAN_CTL_GATE_EN_MASK 0x00000080L +#define THM_PWRMGT__CLK_GATE_MAX_CNT_MASK 0x00FFFF00L +#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN_MASK 0x01000000L +//THM_GPIO_MACO_EN_CTRL +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13 +#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L +#define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L +//SBTSI_REMOTE_TEMP +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L +//SBRMI_CONTROL +#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 +#define SBRMI_CONTROL__DPD__SHIFT 0x1 +#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 +#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L +#define SBRMI_CONTROL__DPD_MASK 0x00000002L +#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L +//SBRMI_COMMAND +#define SBRMI_COMMAND__Command__SHIFT 0x0 +#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 +#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 +#define SBRMI_COMMAND__CommandSent__SHIFT 0x18 +#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 +#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a +#define SBRMI_COMMAND__Status__SHIFT 0x1c +#define SBRMI_COMMAND__Command_MASK 0x000000FFL +#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L +#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L +#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L +#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L +#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L +#define SBRMI_COMMAND__Status_MASK 0xF0000000L +//SBRMI_WRITE_DATA0 +#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 +#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 +#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 +#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 +#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL +#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L +//SBRMI_WRITE_DATA1 +#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 +#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 +#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 +#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 +#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL +#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L +//SBRMI_WRITE_DATA2 +#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 +#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 +#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 +#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 +#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL +#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L +//SBRMI_READ_DATA0 +#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 +#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 +#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 +#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 +#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL +#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L +#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L +#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L +//SBRMI_READ_DATA1 +#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 +#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 +#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 +#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 +#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL +#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L +#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L +#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L +//SBRMI_CORE_EN_NUMBER +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL +//SBRMI_CORE_EN_STATUS0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL +//SBRMI_CORE_EN_STATUS1 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS0 +#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 +#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS1 +#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 +#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS0 +#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 +#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS1 +#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 +#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL +//SMBUS_CNTL0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 +#define SMBUS_CNTL0__THM_READY__SHIFT 0x14 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L +#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L +//SMBUS_CNTL1 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L +//SMBUS_BLKWR_CMD_CTRL0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L +//SMBUS_BLKWR_CMD_CTRL1 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL1 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L +//SMBUS_TIMING_CNTL0 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L +//SMBUS_TIMING_CNTL1 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L +//SMBUS_TIMING_CNTL2 +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L +//SMBUS_TRIGGER_CNTL +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L +//SMBUS_UDID_CNTL0 +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L +//SMBUS_UDID_CNTL1 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL +//SMBUS_UDID_CNTL2 +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 +#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 +#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 +#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 +#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 +#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L +#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL +#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L +#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L +#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L +#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L +//THM_TMON0_REMOTE_START +#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON0_REMOTE_END +#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL +//THM_TMON1_REMOTE_START +#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON1_REMOTE_END +#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL +//THM_TMON2_REMOTE_START +#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON2_REMOTE_END +#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..912955f75b14499994a8fd1aa478a73782930c13 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h @@ -0,0 +1,2620 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _umc_6_7_0_OFFSET_HEADER +#define _umc_6_7_0_OFFSET_HEADER + + + +// addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map +// base address: 0x50f00 +#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2 +#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0 +#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4 +#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0 + + +// addressBlock: umc_w_phy_umc0_umcch0_umcchdec +// base address: 0x50000 +#define regUMCCH0_0_BaseAddrCS0 0x0000 +#define regUMCCH0_0_BaseAddrCS0_BASE_IDX 0 +#define regUMCCH0_0_AddrMaskCS01 0x0008 +#define regUMCCH0_0_AddrMaskCS01_BASE_IDX 0 +#define regUMCCH0_0_AddrSelCS01 0x0010 +#define regUMCCH0_0_AddrSelCS01_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank0 0x0032 +#define regUMCCH0_0_AddrHashBank0_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank1 0x0033 +#define regUMCCH0_0_AddrHashBank1_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank2 0x0034 +#define regUMCCH0_0_AddrHashBank2_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank3 0x0035 +#define regUMCCH0_0_AddrHashBank3_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank4 0x0036 +#define regUMCCH0_0_AddrHashBank4_BASE_IDX 0 +#define regUMCCH0_0_AddrHashBank5 0x0037 +#define regUMCCH0_0_AddrHashBank5_BASE_IDX 0 +#define regUMCCH0_0_UMC_CONFIG 0x0040 +#define regUMCCH0_0_UMC_CONFIG_BASE_IDX 0 +#define regUMCCH0_0_EccCtrl 0x0053 +#define regUMCCH0_0_EccCtrl_BASE_IDX 0 +#define regUMCCH0_0_UmcLocalCap 0x0306 +#define regUMCCH0_0_UmcLocalCap_BASE_IDX 0 +#define regUMCCH0_0_EccErrCntSel 0x0328 +#define regUMCCH0_0_EccErrCntSel_BASE_IDX 0 +#define regUMCCH0_0_EccErrCnt 0x0329 +#define regUMCCH0_0_EccErrCnt_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtlClk 0x0340 +#define regUMCCH0_0_PerfMonCtlClk_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtrClk_Lo 0x0341 +#define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtrClk_Hi 0x0342 +#define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl1 0x0344 +#define regUMCCH0_0_PerfMonCtl1_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr1_Lo 0x0345 +#define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr1_Hi 0x0346 +#define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl2 0x0347 +#define regUMCCH0_0_PerfMonCtl2_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr2_Lo 0x0348 +#define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr2_Hi 0x0349 +#define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl3 0x034a +#define regUMCCH0_0_PerfMonCtl3_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr3_Lo 0x034b +#define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr3_Hi 0x034c +#define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl4 0x034d +#define regUMCCH0_0_PerfMonCtl4_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr4_Lo 0x034e +#define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr4_Hi 0x034f +#define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl5 0x0350 +#define regUMCCH0_0_PerfMonCtl5_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr5_Lo 0x0351 +#define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr5_Hi 0x0352 +#define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl6 0x0353 +#define regUMCCH0_0_PerfMonCtl6_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr6_Lo 0x0354 +#define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr6_Hi 0x0355 +#define regUMCCH0_0_PerfMonCtr6_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl7 0x0356 +#define regUMCCH0_0_PerfMonCtl7_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr7_Lo 0x0357 +#define regUMCCH0_0_PerfMonCtr7_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr7_Hi 0x0358 +#define regUMCCH0_0_PerfMonCtr7_Hi_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtl8 0x0359 +#define regUMCCH0_0_PerfMonCtl8_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr8_Lo 0x035a +#define regUMCCH0_0_PerfMonCtr8_Lo_BASE_IDX 0 +#define regUMCCH0_0_PerfMonCtr8_Hi 0x035b +#define regUMCCH0_0_PerfMonCtr8_Hi_BASE_IDX 0 + + +// addressBlock: umc_w_phy_umc0_umcch1_umcchdec +// base address: 0x51000 +#define regUMCCH1_0_BaseAddrCS0 0x0400 +#define regUMCCH1_0_BaseAddrCS0_BASE_IDX 0 +#define regUMCCH1_0_AddrMaskCS01 0x0408 +#define regUMCCH1_0_AddrMaskCS01_BASE_IDX 0 +#define regUMCCH1_0_AddrSelCS01 0x0410 +#define regUMCCH1_0_AddrSelCS01_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank0 0x0432 +#define regUMCCH1_0_AddrHashBank0_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank1 0x0433 +#define regUMCCH1_0_AddrHashBank1_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank2 0x0434 +#define regUMCCH1_0_AddrHashBank2_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank3 0x0435 +#define regUMCCH1_0_AddrHashBank3_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank4 0x0436 +#define regUMCCH1_0_AddrHashBank4_BASE_IDX 0 +#define regUMCCH1_0_AddrHashBank5 0x0437 +#define regUMCCH1_0_AddrHashBank5_BASE_IDX 0 +#define regUMCCH1_0_UMC_CONFIG 0x0440 +#define regUMCCH1_0_UMC_CONFIG_BASE_IDX 0 +#define regUMCCH1_0_EccCtrl 0x0453 +#define regUMCCH1_0_EccCtrl_BASE_IDX 0 +#define regUMCCH1_0_UmcLocalCap 0x0706 +#define regUMCCH1_0_UmcLocalCap_BASE_IDX 0 +#define regUMCCH1_0_EccErrCntSel 0x0728 +#define regUMCCH1_0_EccErrCntSel_BASE_IDX 0 +#define regUMCCH1_0_EccErrCnt 0x0729 +#define regUMCCH1_0_EccErrCnt_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtlClk 0x0740 +#define regUMCCH1_0_PerfMonCtlClk_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtrClk_Lo 0x0741 +#define regUMCCH1_0_PerfMonCtrClk_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtrClk_Hi 0x0742 +#define regUMCCH1_0_PerfMonCtrClk_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl1 0x0744 +#define regUMCCH1_0_PerfMonCtl1_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr1_Lo 0x0745 +#define regUMCCH1_0_PerfMonCtr1_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr1_Hi 0x0746 +#define regUMCCH1_0_PerfMonCtr1_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl2 0x0747 +#define regUMCCH1_0_PerfMonCtl2_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr2_Lo 0x0748 +#define regUMCCH1_0_PerfMonCtr2_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr2_Hi 0x0749 +#define regUMCCH1_0_PerfMonCtr2_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl3 0x074a +#define regUMCCH1_0_PerfMonCtl3_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr3_Lo 0x074b +#define regUMCCH1_0_PerfMonCtr3_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr3_Hi 0x074c +#define regUMCCH1_0_PerfMonCtr3_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl4 0x074d +#define regUMCCH1_0_PerfMonCtl4_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr4_Lo 0x074e +#define regUMCCH1_0_PerfMonCtr4_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr4_Hi 0x074f +#define regUMCCH1_0_PerfMonCtr4_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl5 0x0750 +#define regUMCCH1_0_PerfMonCtl5_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr5_Lo 0x0751 +#define regUMCCH1_0_PerfMonCtr5_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr5_Hi 0x0752 +#define regUMCCH1_0_PerfMonCtr5_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl6 0x0753 +#define regUMCCH1_0_PerfMonCtl6_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr6_Lo 0x0754 +#define regUMCCH1_0_PerfMonCtr6_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr6_Hi 0x0755 +#define regUMCCH1_0_PerfMonCtr6_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl7 0x0756 +#define regUMCCH1_0_PerfMonCtl7_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr7_Lo 0x0757 +#define regUMCCH1_0_PerfMonCtr7_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr7_Hi 0x0758 +#define regUMCCH1_0_PerfMonCtr7_Hi_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtl8 0x0759 +#define regUMCCH1_0_PerfMonCtl8_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr8_Lo 0x075a +#define regUMCCH1_0_PerfMonCtr8_Lo_BASE_IDX 0 +#define regUMCCH1_0_PerfMonCtr8_Hi 0x075b +#define regUMCCH1_0_PerfMonCtr8_Hi_BASE_IDX 0 + + +// addressBlock: umc_w_phy_umc0_umcch2_umcchdec +// base address: 0x52000 +#define regUMCCH2_0_BaseAddrCS0 0x0800 +#define regUMCCH2_0_BaseAddrCS0_BASE_IDX 0 +#define regUMCCH2_0_AddrMaskCS01 0x0808 +#define regUMCCH2_0_AddrMaskCS01_BASE_IDX 0 +#define regUMCCH2_0_AddrSelCS01 0x0810 +#define regUMCCH2_0_AddrSelCS01_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank0 0x0832 +#define regUMCCH2_0_AddrHashBank0_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank1 0x0833 +#define regUMCCH2_0_AddrHashBank1_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank2 0x0834 +#define regUMCCH2_0_AddrHashBank2_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank3 0x0835 +#define regUMCCH2_0_AddrHashBank3_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank4 0x0836 +#define regUMCCH2_0_AddrHashBank4_BASE_IDX 0 +#define regUMCCH2_0_AddrHashBank5 0x0837 +#define regUMCCH2_0_AddrHashBank5_BASE_IDX 0 +#define regUMCCH2_0_UMC_CONFIG 0x0840 +#define regUMCCH2_0_UMC_CONFIG_BASE_IDX 0 +#define regUMCCH2_0_EccCtrl 0x0853 +#define regUMCCH2_0_EccCtrl_BASE_IDX 0 +#define regUMCCH2_0_UmcLocalCap 0x0b06 +#define regUMCCH2_0_UmcLocalCap_BASE_IDX 0 +#define regUMCCH2_0_EccErrCntSel 0x0b28 +#define regUMCCH2_0_EccErrCntSel_BASE_IDX 0 +#define regUMCCH2_0_EccErrCnt 0x0b29 +#define regUMCCH2_0_EccErrCnt_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtlClk 0x0b40 +#define regUMCCH2_0_PerfMonCtlClk_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtrClk_Lo 0x0b41 +#define regUMCCH2_0_PerfMonCtrClk_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtrClk_Hi 0x0b42 +#define regUMCCH2_0_PerfMonCtrClk_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl1 0x0b44 +#define regUMCCH2_0_PerfMonCtl1_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr1_Lo 0x0b45 +#define regUMCCH2_0_PerfMonCtr1_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr1_Hi 0x0b46 +#define regUMCCH2_0_PerfMonCtr1_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl2 0x0b47 +#define regUMCCH2_0_PerfMonCtl2_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr2_Lo 0x0b48 +#define regUMCCH2_0_PerfMonCtr2_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr2_Hi 0x0b49 +#define regUMCCH2_0_PerfMonCtr2_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl3 0x0b4a +#define regUMCCH2_0_PerfMonCtl3_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr3_Lo 0x0b4b +#define regUMCCH2_0_PerfMonCtr3_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr3_Hi 0x0b4c +#define regUMCCH2_0_PerfMonCtr3_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl4 0x0b4d +#define regUMCCH2_0_PerfMonCtl4_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr4_Lo 0x0b4e +#define regUMCCH2_0_PerfMonCtr4_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr4_Hi 0x0b4f +#define regUMCCH2_0_PerfMonCtr4_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl5 0x0b50 +#define regUMCCH2_0_PerfMonCtl5_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr5_Lo 0x0b51 +#define regUMCCH2_0_PerfMonCtr5_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr5_Hi 0x0b52 +#define regUMCCH2_0_PerfMonCtr5_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl6 0x0b53 +#define regUMCCH2_0_PerfMonCtl6_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr6_Lo 0x0b54 +#define regUMCCH2_0_PerfMonCtr6_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr6_Hi 0x0b55 +#define regUMCCH2_0_PerfMonCtr6_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl7 0x0b56 +#define regUMCCH2_0_PerfMonCtl7_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr7_Lo 0x0b57 +#define regUMCCH2_0_PerfMonCtr7_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr7_Hi 0x0b58 +#define regUMCCH2_0_PerfMonCtr7_Hi_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtl8 0x0b59 +#define regUMCCH2_0_PerfMonCtl8_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr8_Lo 0x0b5a +#define regUMCCH2_0_PerfMonCtr8_Lo_BASE_IDX 0 +#define regUMCCH2_0_PerfMonCtr8_Hi 0x0b5b +#define regUMCCH2_0_PerfMonCtr8_Hi_BASE_IDX 0 + + +// addressBlock: umc_w_phy_umc0_umcch3_umcchdec +// base address: 0x53000 +#define regUMCCH3_0_BaseAddrCS0 0x0c00 +#define regUMCCH3_0_BaseAddrCS0_BASE_IDX 0 +#define regUMCCH3_0_AddrMaskCS01 0x0c08 +#define regUMCCH3_0_AddrMaskCS01_BASE_IDX 0 +#define regUMCCH3_0_AddrSelCS01 0x0c10 +#define regUMCCH3_0_AddrSelCS01_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank0 0x0c32 +#define regUMCCH3_0_AddrHashBank0_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank1 0x0c33 +#define regUMCCH3_0_AddrHashBank1_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank2 0x0c34 +#define regUMCCH3_0_AddrHashBank2_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank3 0x0c35 +#define regUMCCH3_0_AddrHashBank3_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank4 0x0c36 +#define regUMCCH3_0_AddrHashBank4_BASE_IDX 0 +#define regUMCCH3_0_AddrHashBank5 0x0c37 +#define regUMCCH3_0_AddrHashBank5_BASE_IDX 0 +#define regUMCCH3_0_UMC_CONFIG 0x0c40 +#define regUMCCH3_0_UMC_CONFIG_BASE_IDX 0 +#define regUMCCH3_0_EccCtrl 0x0c53 +#define regUMCCH3_0_EccCtrl_BASE_IDX 0 +#define regUMCCH3_0_UmcLocalCap 0x0f06 +#define regUMCCH3_0_UmcLocalCap_BASE_IDX 0 +#define regUMCCH3_0_EccErrCntSel 0x0f28 +#define regUMCCH3_0_EccErrCntSel_BASE_IDX 0 +#define regUMCCH3_0_EccErrCnt 0x0f29 +#define regUMCCH3_0_EccErrCnt_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtlClk 0x0f40 +#define regUMCCH3_0_PerfMonCtlClk_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtrClk_Lo 0x0f41 +#define regUMCCH3_0_PerfMonCtrClk_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtrClk_Hi 0x0f42 +#define regUMCCH3_0_PerfMonCtrClk_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl1 0x0f44 +#define regUMCCH3_0_PerfMonCtl1_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr1_Lo 0x0f45 +#define regUMCCH3_0_PerfMonCtr1_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr1_Hi 0x0f46 +#define regUMCCH3_0_PerfMonCtr1_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl2 0x0f47 +#define regUMCCH3_0_PerfMonCtl2_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr2_Lo 0x0f48 +#define regUMCCH3_0_PerfMonCtr2_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr2_Hi 0x0f49 +#define regUMCCH3_0_PerfMonCtr2_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl3 0x0f4a +#define regUMCCH3_0_PerfMonCtl3_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr3_Lo 0x0f4b +#define regUMCCH3_0_PerfMonCtr3_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr3_Hi 0x0f4c +#define regUMCCH3_0_PerfMonCtr3_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl4 0x0f4d +#define regUMCCH3_0_PerfMonCtl4_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr4_Lo 0x0f4e +#define regUMCCH3_0_PerfMonCtr4_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr4_Hi 0x0f4f +#define regUMCCH3_0_PerfMonCtr4_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl5 0x0f50 +#define regUMCCH3_0_PerfMonCtl5_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr5_Lo 0x0f51 +#define regUMCCH3_0_PerfMonCtr5_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr5_Hi 0x0f52 +#define regUMCCH3_0_PerfMonCtr5_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl6 0x0f53 +#define regUMCCH3_0_PerfMonCtl6_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr6_Lo 0x0f54 +#define regUMCCH3_0_PerfMonCtr6_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr6_Hi 0x0f55 +#define regUMCCH3_0_PerfMonCtr6_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl7 0x0f56 +#define regUMCCH3_0_PerfMonCtl7_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr7_Lo 0x0f57 +#define regUMCCH3_0_PerfMonCtr7_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr7_Hi 0x0f58 +#define regUMCCH3_0_PerfMonCtr7_Hi_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtl8 0x0f59 +#define regUMCCH3_0_PerfMonCtl8_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr8_Lo 0x0f5a +#define regUMCCH3_0_PerfMonCtr8_Lo_BASE_IDX 0 +#define regUMCCH3_0_PerfMonCtr8_Hi 0x0f5b +#define regUMCCH3_0_PerfMonCtr8_Hi_BASE_IDX 0 + + +// addressBlock: umc_w_phy_umc0_umcch4_umcchdec +// base address: 0x150000 +#define regUMCCH4_0_BaseAddrCS0 0x0000 +#define regUMCCH4_0_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH4_0_AddrMaskCS01 0x0008 +#define regUMCCH4_0_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH4_0_AddrSelCS01 0x0010 +#define regUMCCH4_0_AddrSelCS01_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank0 0x0032 +#define regUMCCH4_0_AddrHashBank0_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank1 0x0033 +#define regUMCCH4_0_AddrHashBank1_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank2 0x0034 +#define regUMCCH4_0_AddrHashBank2_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank3 0x0035 +#define regUMCCH4_0_AddrHashBank3_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank4 0x0036 +#define regUMCCH4_0_AddrHashBank4_BASE_IDX 1 +#define regUMCCH4_0_AddrHashBank5 0x0037 +#define regUMCCH4_0_AddrHashBank5_BASE_IDX 1 +#define regUMCCH4_0_EccErrCntSel 0x0328 +#define regUMCCH4_0_EccErrCntSel_BASE_IDX 1 +#define regUMCCH4_0_EccErrCnt 0x0329 +#define regUMCCH4_0_EccErrCnt_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtlClk 0x0340 +#define regUMCCH4_0_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtrClk_Lo 0x0341 +#define regUMCCH4_0_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtrClk_Hi 0x0342 +#define regUMCCH4_0_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl1 0x0344 +#define regUMCCH4_0_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr1_Lo 0x0345 +#define regUMCCH4_0_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr1_Hi 0x0346 +#define regUMCCH4_0_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl2 0x0347 +#define regUMCCH4_0_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr2_Lo 0x0348 +#define regUMCCH4_0_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr2_Hi 0x0349 +#define regUMCCH4_0_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl3 0x034a +#define regUMCCH4_0_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr3_Lo 0x034b +#define regUMCCH4_0_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr3_Hi 0x034c +#define regUMCCH4_0_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl4 0x034d +#define regUMCCH4_0_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr4_Lo 0x034e +#define regUMCCH4_0_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr4_Hi 0x034f +#define regUMCCH4_0_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl5 0x0350 +#define regUMCCH4_0_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr5_Lo 0x0351 +#define regUMCCH4_0_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr5_Hi 0x0352 +#define regUMCCH4_0_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl6 0x0353 +#define regUMCCH4_0_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr6_Lo 0x0354 +#define regUMCCH4_0_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr6_Hi 0x0355 +#define regUMCCH4_0_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl7 0x0356 +#define regUMCCH4_0_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr7_Lo 0x0357 +#define regUMCCH4_0_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr7_Hi 0x0358 +#define regUMCCH4_0_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtl8 0x0359 +#define regUMCCH4_0_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr8_Lo 0x035a +#define regUMCCH4_0_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH4_0_PerfMonCtr8_Hi 0x035b +#define regUMCCH4_0_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc0_umcch5_umcchdec +// base address: 0x151000 +#define regUMCCH5_0_BaseAddrCS0 0x0400 +#define regUMCCH5_0_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH5_0_AddrMaskCS01 0x0408 +#define regUMCCH5_0_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH5_0_AddrSelCS01 0x0410 +#define regUMCCH5_0_AddrSelCS01_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank0 0x0432 +#define regUMCCH5_0_AddrHashBank0_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank1 0x0433 +#define regUMCCH5_0_AddrHashBank1_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank2 0x0434 +#define regUMCCH5_0_AddrHashBank2_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank3 0x0435 +#define regUMCCH5_0_AddrHashBank3_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank4 0x0436 +#define regUMCCH5_0_AddrHashBank4_BASE_IDX 1 +#define regUMCCH5_0_AddrHashBank5 0x0437 +#define regUMCCH5_0_AddrHashBank5_BASE_IDX 1 +#define regUMCCH5_0_EccErrCntSel 0x0728 +#define regUMCCH5_0_EccErrCntSel_BASE_IDX 1 +#define regUMCCH5_0_EccErrCnt 0x0729 +#define regUMCCH5_0_EccErrCnt_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtlClk 0x0740 +#define regUMCCH5_0_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtrClk_Lo 0x0741 +#define regUMCCH5_0_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtrClk_Hi 0x0742 +#define regUMCCH5_0_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl1 0x0744 +#define regUMCCH5_0_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr1_Lo 0x0745 +#define regUMCCH5_0_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr1_Hi 0x0746 +#define regUMCCH5_0_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl2 0x0747 +#define regUMCCH5_0_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr2_Lo 0x0748 +#define regUMCCH5_0_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr2_Hi 0x0749 +#define regUMCCH5_0_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl3 0x074a +#define regUMCCH5_0_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr3_Lo 0x074b +#define regUMCCH5_0_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr3_Hi 0x074c +#define regUMCCH5_0_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl4 0x074d +#define regUMCCH5_0_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr4_Lo 0x074e +#define regUMCCH5_0_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr4_Hi 0x074f +#define regUMCCH5_0_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl5 0x0750 +#define regUMCCH5_0_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr5_Lo 0x0751 +#define regUMCCH5_0_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr5_Hi 0x0752 +#define regUMCCH5_0_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl6 0x0753 +#define regUMCCH5_0_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr6_Lo 0x0754 +#define regUMCCH5_0_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr6_Hi 0x0755 +#define regUMCCH5_0_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl7 0x0756 +#define regUMCCH5_0_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr7_Lo 0x0757 +#define regUMCCH5_0_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr7_Hi 0x0758 +#define regUMCCH5_0_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtl8 0x0759 +#define regUMCCH5_0_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr8_Lo 0x075a +#define regUMCCH5_0_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH5_0_PerfMonCtr8_Hi 0x075b +#define regUMCCH5_0_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc0_umcch6_umcchdec +// base address: 0x152000 +#define regUMCCH6_0_BaseAddrCS0 0x0800 +#define regUMCCH6_0_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH6_0_AddrMaskCS01 0x0808 +#define regUMCCH6_0_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH6_0_AddrSelCS01 0x0810 +#define regUMCCH6_0_AddrSelCS01_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank0 0x0832 +#define regUMCCH6_0_AddrHashBank0_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank1 0x0833 +#define regUMCCH6_0_AddrHashBank1_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank2 0x0834 +#define regUMCCH6_0_AddrHashBank2_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank3 0x0835 +#define regUMCCH6_0_AddrHashBank3_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank4 0x0836 +#define regUMCCH6_0_AddrHashBank4_BASE_IDX 1 +#define regUMCCH6_0_AddrHashBank5 0x0837 +#define regUMCCH6_0_AddrHashBank5_BASE_IDX 1 +#define regUMCCH6_0_EccErrCntSel 0x0b28 +#define regUMCCH6_0_EccErrCntSel_BASE_IDX 1 +#define regUMCCH6_0_EccErrCnt 0x0b29 +#define regUMCCH6_0_EccErrCnt_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtlClk 0x0b40 +#define regUMCCH6_0_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtrClk_Lo 0x0b41 +#define regUMCCH6_0_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtrClk_Hi 0x0b42 +#define regUMCCH6_0_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl1 0x0b44 +#define regUMCCH6_0_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr1_Lo 0x0b45 +#define regUMCCH6_0_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr1_Hi 0x0b46 +#define regUMCCH6_0_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl2 0x0b47 +#define regUMCCH6_0_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr2_Lo 0x0b48 +#define regUMCCH6_0_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr2_Hi 0x0b49 +#define regUMCCH6_0_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl3 0x0b4a +#define regUMCCH6_0_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr3_Lo 0x0b4b +#define regUMCCH6_0_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr3_Hi 0x0b4c +#define regUMCCH6_0_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl4 0x0b4d +#define regUMCCH6_0_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr4_Lo 0x0b4e +#define regUMCCH6_0_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr4_Hi 0x0b4f +#define regUMCCH6_0_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl5 0x0b50 +#define regUMCCH6_0_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr5_Lo 0x0b51 +#define regUMCCH6_0_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr5_Hi 0x0b52 +#define regUMCCH6_0_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl6 0x0b53 +#define regUMCCH6_0_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr6_Lo 0x0b54 +#define regUMCCH6_0_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr6_Hi 0x0b55 +#define regUMCCH6_0_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl7 0x0b56 +#define regUMCCH6_0_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr7_Lo 0x0b57 +#define regUMCCH6_0_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr7_Hi 0x0b58 +#define regUMCCH6_0_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtl8 0x0b59 +#define regUMCCH6_0_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr8_Lo 0x0b5a +#define regUMCCH6_0_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH6_0_PerfMonCtr8_Hi 0x0b5b +#define regUMCCH6_0_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc0_umcch7_umcchdec +// base address: 0x153000 +#define regUMCCH7_0_BaseAddrCS0 0x0c00 +#define regUMCCH7_0_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH7_0_AddrMaskCS01 0x0c08 +#define regUMCCH7_0_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH7_0_AddrSelCS01 0x0c10 +#define regUMCCH7_0_AddrSelCS01_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank0 0x0c32 +#define regUMCCH7_0_AddrHashBank0_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank1 0x0c33 +#define regUMCCH7_0_AddrHashBank1_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank2 0x0c34 +#define regUMCCH7_0_AddrHashBank2_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank3 0x0c35 +#define regUMCCH7_0_AddrHashBank3_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank4 0x0c36 +#define regUMCCH7_0_AddrHashBank4_BASE_IDX 1 +#define regUMCCH7_0_AddrHashBank5 0x0c37 +#define regUMCCH7_0_AddrHashBank5_BASE_IDX 1 +#define regUMCCH7_0_EccErrCntSel 0x0f28 +#define regUMCCH7_0_EccErrCntSel_BASE_IDX 1 +#define regUMCCH7_0_EccErrCnt 0x0f29 +#define regUMCCH7_0_EccErrCnt_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtlClk 0x0f40 +#define regUMCCH7_0_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtrClk_Lo 0x0f41 +#define regUMCCH7_0_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtrClk_Hi 0x0f42 +#define regUMCCH7_0_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl1 0x0f44 +#define regUMCCH7_0_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr1_Lo 0x0f45 +#define regUMCCH7_0_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr1_Hi 0x0f46 +#define regUMCCH7_0_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl2 0x0f47 +#define regUMCCH7_0_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr2_Lo 0x0f48 +#define regUMCCH7_0_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr2_Hi 0x0f49 +#define regUMCCH7_0_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl3 0x0f4a +#define regUMCCH7_0_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr3_Lo 0x0f4b +#define regUMCCH7_0_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr3_Hi 0x0f4c +#define regUMCCH7_0_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl4 0x0f4d +#define regUMCCH7_0_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr4_Lo 0x0f4e +#define regUMCCH7_0_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr4_Hi 0x0f4f +#define regUMCCH7_0_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl5 0x0f50 +#define regUMCCH7_0_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr5_Lo 0x0f51 +#define regUMCCH7_0_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr5_Hi 0x0f52 +#define regUMCCH7_0_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl6 0x0f53 +#define regUMCCH7_0_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr6_Lo 0x0f54 +#define regUMCCH7_0_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr6_Hi 0x0f55 +#define regUMCCH7_0_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl7 0x0f56 +#define regUMCCH7_0_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr7_Lo 0x0f57 +#define regUMCCH7_0_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr7_Hi 0x0f58 +#define regUMCCH7_0_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtl8 0x0f59 +#define regUMCCH7_0_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr8_Lo 0x0f5a +#define regUMCCH7_0_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH7_0_PerfMonCtr8_Hi 0x0f5b +#define regUMCCH7_0_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch0_umcchdec +// base address: 0x250000 +#define regUMCCH0_1_BaseAddrCS0 0x40000 +#define regUMCCH0_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH0_1_AddrMaskCS01 0x40008 +#define regUMCCH0_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH0_1_AddrSelCS01 0x40010 +#define regUMCCH0_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank0 0x40032 +#define regUMCCH0_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank1 0x40033 +#define regUMCCH0_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank2 0x40034 +#define regUMCCH0_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank3 0x40035 +#define regUMCCH0_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank4 0x40036 +#define regUMCCH0_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH0_1_AddrHashBank5 0x40037 +#define regUMCCH0_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH0_1_EccErrCntSel 0x40328 +#define regUMCCH0_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH0_1_EccErrCnt 0x40329 +#define regUMCCH0_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtlClk 0x40340 +#define regUMCCH0_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtrClk_Lo 0x40341 +#define regUMCCH0_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtrClk_Hi 0x40342 +#define regUMCCH0_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl1 0x40344 +#define regUMCCH0_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr1_Lo 0x40345 +#define regUMCCH0_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr1_Hi 0x40346 +#define regUMCCH0_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl2 0x40347 +#define regUMCCH0_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr2_Lo 0x40348 +#define regUMCCH0_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr2_Hi 0x40349 +#define regUMCCH0_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl3 0x4034a +#define regUMCCH0_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr3_Lo 0x4034b +#define regUMCCH0_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr3_Hi 0x4034c +#define regUMCCH0_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl4 0x4034d +#define regUMCCH0_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr4_Lo 0x4034e +#define regUMCCH0_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr4_Hi 0x4034f +#define regUMCCH0_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl5 0x40350 +#define regUMCCH0_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr5_Lo 0x40351 +#define regUMCCH0_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr5_Hi 0x40352 +#define regUMCCH0_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl6 0x40353 +#define regUMCCH0_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr6_Lo 0x40354 +#define regUMCCH0_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr6_Hi 0x40355 +#define regUMCCH0_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl7 0x40356 +#define regUMCCH0_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr7_Lo 0x40357 +#define regUMCCH0_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr7_Hi 0x40358 +#define regUMCCH0_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtl8 0x40359 +#define regUMCCH0_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr8_Lo 0x4035a +#define regUMCCH0_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH0_1_PerfMonCtr8_Hi 0x4035b +#define regUMCCH0_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch1_umcchdec +// base address: 0x251000 +#define regUMCCH1_1_BaseAddrCS0 0x40400 +#define regUMCCH1_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH1_1_AddrMaskCS01 0x40408 +#define regUMCCH1_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH1_1_AddrSelCS01 0x40410 +#define regUMCCH1_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank0 0x40432 +#define regUMCCH1_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank1 0x40433 +#define regUMCCH1_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank2 0x40434 +#define regUMCCH1_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank3 0x40435 +#define regUMCCH1_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank4 0x40436 +#define regUMCCH1_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH1_1_AddrHashBank5 0x40437 +#define regUMCCH1_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH1_1_EccErrCntSel 0x40728 +#define regUMCCH1_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH1_1_EccErrCnt 0x40729 +#define regUMCCH1_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtlClk 0x40740 +#define regUMCCH1_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtrClk_Lo 0x40741 +#define regUMCCH1_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtrClk_Hi 0x40742 +#define regUMCCH1_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl1 0x40744 +#define regUMCCH1_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr1_Lo 0x40745 +#define regUMCCH1_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr1_Hi 0x40746 +#define regUMCCH1_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl2 0x40747 +#define regUMCCH1_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr2_Lo 0x40748 +#define regUMCCH1_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr2_Hi 0x40749 +#define regUMCCH1_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl3 0x4074a +#define regUMCCH1_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr3_Lo 0x4074b +#define regUMCCH1_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr3_Hi 0x4074c +#define regUMCCH1_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl4 0x4074d +#define regUMCCH1_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr4_Lo 0x4074e +#define regUMCCH1_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr4_Hi 0x4074f +#define regUMCCH1_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl5 0x40750 +#define regUMCCH1_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr5_Lo 0x40751 +#define regUMCCH1_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr5_Hi 0x40752 +#define regUMCCH1_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl6 0x40753 +#define regUMCCH1_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr6_Lo 0x40754 +#define regUMCCH1_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr6_Hi 0x40755 +#define regUMCCH1_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl7 0x40756 +#define regUMCCH1_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr7_Lo 0x40757 +#define regUMCCH1_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr7_Hi 0x40758 +#define regUMCCH1_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtl8 0x40759 +#define regUMCCH1_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr8_Lo 0x4075a +#define regUMCCH1_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH1_1_PerfMonCtr8_Hi 0x4075b +#define regUMCCH1_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch2_umcchdec +// base address: 0x252000 +#define regUMCCH2_1_BaseAddrCS0 0x40800 +#define regUMCCH2_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH2_1_AddrMaskCS01 0x40808 +#define regUMCCH2_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH2_1_AddrSelCS01 0x40810 +#define regUMCCH2_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank0 0x40832 +#define regUMCCH2_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank1 0x40833 +#define regUMCCH2_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank2 0x40834 +#define regUMCCH2_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank3 0x40835 +#define regUMCCH2_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank4 0x40836 +#define regUMCCH2_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH2_1_AddrHashBank5 0x40837 +#define regUMCCH2_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH2_1_EccErrCntSel 0x40b28 +#define regUMCCH2_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH2_1_EccErrCnt 0x40b29 +#define regUMCCH2_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtlClk 0x40b40 +#define regUMCCH2_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtrClk_Lo 0x40b41 +#define regUMCCH2_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtrClk_Hi 0x40b42 +#define regUMCCH2_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl1 0x40b44 +#define regUMCCH2_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr1_Lo 0x40b45 +#define regUMCCH2_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr1_Hi 0x40b46 +#define regUMCCH2_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl2 0x40b47 +#define regUMCCH2_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr2_Lo 0x40b48 +#define regUMCCH2_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr2_Hi 0x40b49 +#define regUMCCH2_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl3 0x40b4a +#define regUMCCH2_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr3_Lo 0x40b4b +#define regUMCCH2_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr3_Hi 0x40b4c +#define regUMCCH2_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl4 0x40b4d +#define regUMCCH2_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr4_Lo 0x40b4e +#define regUMCCH2_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr4_Hi 0x40b4f +#define regUMCCH2_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl5 0x40b50 +#define regUMCCH2_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr5_Lo 0x40b51 +#define regUMCCH2_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr5_Hi 0x40b52 +#define regUMCCH2_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl6 0x40b53 +#define regUMCCH2_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr6_Lo 0x40b54 +#define regUMCCH2_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr6_Hi 0x40b55 +#define regUMCCH2_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl7 0x40b56 +#define regUMCCH2_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr7_Lo 0x40b57 +#define regUMCCH2_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr7_Hi 0x40b58 +#define regUMCCH2_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtl8 0x40b59 +#define regUMCCH2_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr8_Lo 0x40b5a +#define regUMCCH2_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH2_1_PerfMonCtr8_Hi 0x40b5b +#define regUMCCH2_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch3_umcchdec +// base address: 0x253000 +#define regUMCCH3_1_BaseAddrCS0 0x40c00 +#define regUMCCH3_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH3_1_AddrMaskCS01 0x40c08 +#define regUMCCH3_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH3_1_AddrSelCS01 0x40c10 +#define regUMCCH3_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank0 0x40c32 +#define regUMCCH3_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank1 0x40c33 +#define regUMCCH3_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank2 0x40c34 +#define regUMCCH3_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank3 0x40c35 +#define regUMCCH3_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank4 0x40c36 +#define regUMCCH3_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH3_1_AddrHashBank5 0x40c37 +#define regUMCCH3_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH3_1_EccErrCntSel 0x40f28 +#define regUMCCH3_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH3_1_EccErrCnt 0x40f29 +#define regUMCCH3_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtlClk 0x40f40 +#define regUMCCH3_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtrClk_Lo 0x40f41 +#define regUMCCH3_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtrClk_Hi 0x40f42 +#define regUMCCH3_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl1 0x40f44 +#define regUMCCH3_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr1_Lo 0x40f45 +#define regUMCCH3_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr1_Hi 0x40f46 +#define regUMCCH3_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl2 0x40f47 +#define regUMCCH3_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr2_Lo 0x40f48 +#define regUMCCH3_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr2_Hi 0x40f49 +#define regUMCCH3_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl3 0x40f4a +#define regUMCCH3_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr3_Lo 0x40f4b +#define regUMCCH3_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr3_Hi 0x40f4c +#define regUMCCH3_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl4 0x40f4d +#define regUMCCH3_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr4_Lo 0x40f4e +#define regUMCCH3_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr4_Hi 0x40f4f +#define regUMCCH3_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl5 0x40f50 +#define regUMCCH3_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr5_Lo 0x40f51 +#define regUMCCH3_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr5_Hi 0x40f52 +#define regUMCCH3_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl6 0x40f53 +#define regUMCCH3_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr6_Lo 0x40f54 +#define regUMCCH3_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr6_Hi 0x40f55 +#define regUMCCH3_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl7 0x40f56 +#define regUMCCH3_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr7_Lo 0x40f57 +#define regUMCCH3_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr7_Hi 0x40f58 +#define regUMCCH3_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtl8 0x40f59 +#define regUMCCH3_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr8_Lo 0x40f5a +#define regUMCCH3_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH3_1_PerfMonCtr8_Hi 0x40f5b +#define regUMCCH3_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch4_umcchdec +// base address: 0x350000 +#define regUMCCH4_1_BaseAddrCS0 0x80000 +#define regUMCCH4_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH4_1_AddrMaskCS01 0x80008 +#define regUMCCH4_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH4_1_AddrSelCS01 0x80010 +#define regUMCCH4_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank0 0x80032 +#define regUMCCH4_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank1 0x80033 +#define regUMCCH4_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank2 0x80034 +#define regUMCCH4_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank3 0x80035 +#define regUMCCH4_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank4 0x80036 +#define regUMCCH4_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH4_1_AddrHashBank5 0x80037 +#define regUMCCH4_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH4_1_EccErrCntSel 0x80328 +#define regUMCCH4_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH4_1_EccErrCnt 0x80329 +#define regUMCCH4_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtlClk 0x80340 +#define regUMCCH4_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtrClk_Lo 0x80341 +#define regUMCCH4_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtrClk_Hi 0x80342 +#define regUMCCH4_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl1 0x80344 +#define regUMCCH4_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr1_Lo 0x80345 +#define regUMCCH4_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr1_Hi 0x80346 +#define regUMCCH4_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl2 0x80347 +#define regUMCCH4_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr2_Lo 0x80348 +#define regUMCCH4_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr2_Hi 0x80349 +#define regUMCCH4_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl3 0x8034a +#define regUMCCH4_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr3_Lo 0x8034b +#define regUMCCH4_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr3_Hi 0x8034c +#define regUMCCH4_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl4 0x8034d +#define regUMCCH4_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr4_Lo 0x8034e +#define regUMCCH4_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr4_Hi 0x8034f +#define regUMCCH4_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl5 0x80350 +#define regUMCCH4_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr5_Lo 0x80351 +#define regUMCCH4_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr5_Hi 0x80352 +#define regUMCCH4_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl6 0x80353 +#define regUMCCH4_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr6_Lo 0x80354 +#define regUMCCH4_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr6_Hi 0x80355 +#define regUMCCH4_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl7 0x80356 +#define regUMCCH4_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr7_Lo 0x80357 +#define regUMCCH4_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr7_Hi 0x80358 +#define regUMCCH4_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtl8 0x80359 +#define regUMCCH4_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr8_Lo 0x8035a +#define regUMCCH4_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH4_1_PerfMonCtr8_Hi 0x8035b +#define regUMCCH4_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch5_umcchdec +// base address: 0x351000 +#define regUMCCH5_1_BaseAddrCS0 0x80400 +#define regUMCCH5_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH5_1_AddrMaskCS01 0x80408 +#define regUMCCH5_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH5_1_AddrSelCS01 0x80410 +#define regUMCCH5_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank0 0x80432 +#define regUMCCH5_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank1 0x80433 +#define regUMCCH5_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank2 0x80434 +#define regUMCCH5_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank3 0x80435 +#define regUMCCH5_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank4 0x80436 +#define regUMCCH5_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH5_1_AddrHashBank5 0x80437 +#define regUMCCH5_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH5_1_EccErrCntSel 0x80728 +#define regUMCCH5_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH5_1_EccErrCnt 0x80729 +#define regUMCCH5_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtlClk 0x80740 +#define regUMCCH5_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtrClk_Lo 0x80741 +#define regUMCCH5_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtrClk_Hi 0x80742 +#define regUMCCH5_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl1 0x80744 +#define regUMCCH5_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr1_Lo 0x80745 +#define regUMCCH5_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr1_Hi 0x80746 +#define regUMCCH5_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl2 0x80747 +#define regUMCCH5_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr2_Lo 0x80748 +#define regUMCCH5_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr2_Hi 0x80749 +#define regUMCCH5_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl3 0x8074a +#define regUMCCH5_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr3_Lo 0x8074b +#define regUMCCH5_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr3_Hi 0x8074c +#define regUMCCH5_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl4 0x8074d +#define regUMCCH5_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr4_Lo 0x8074e +#define regUMCCH5_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr4_Hi 0x8074f +#define regUMCCH5_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl5 0x80750 +#define regUMCCH5_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr5_Lo 0x80751 +#define regUMCCH5_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr5_Hi 0x80752 +#define regUMCCH5_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl6 0x80753 +#define regUMCCH5_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr6_Lo 0x80754 +#define regUMCCH5_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr6_Hi 0x80755 +#define regUMCCH5_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl7 0x80756 +#define regUMCCH5_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr7_Lo 0x80757 +#define regUMCCH5_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr7_Hi 0x80758 +#define regUMCCH5_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtl8 0x80759 +#define regUMCCH5_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr8_Lo 0x8075a +#define regUMCCH5_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH5_1_PerfMonCtr8_Hi 0x8075b +#define regUMCCH5_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch6_umcchdec +// base address: 0x352000 +#define regUMCCH6_1_BaseAddrCS0 0x80800 +#define regUMCCH6_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH6_1_AddrMaskCS01 0x80808 +#define regUMCCH6_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH6_1_AddrSelCS01 0x80810 +#define regUMCCH6_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank0 0x80832 +#define regUMCCH6_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank1 0x80833 +#define regUMCCH6_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank2 0x80834 +#define regUMCCH6_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank3 0x80835 +#define regUMCCH6_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank4 0x80836 +#define regUMCCH6_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH6_1_AddrHashBank5 0x80837 +#define regUMCCH6_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH6_1_EccErrCntSel 0x80b28 +#define regUMCCH6_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH6_1_EccErrCnt 0x80b29 +#define regUMCCH6_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtlClk 0x80b40 +#define regUMCCH6_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtrClk_Lo 0x80b41 +#define regUMCCH6_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtrClk_Hi 0x80b42 +#define regUMCCH6_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl1 0x80b44 +#define regUMCCH6_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr1_Lo 0x80b45 +#define regUMCCH6_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr1_Hi 0x80b46 +#define regUMCCH6_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl2 0x80b47 +#define regUMCCH6_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr2_Lo 0x80b48 +#define regUMCCH6_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr2_Hi 0x80b49 +#define regUMCCH6_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl3 0x80b4a +#define regUMCCH6_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr3_Lo 0x80b4b +#define regUMCCH6_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr3_Hi 0x80b4c +#define regUMCCH6_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl4 0x80b4d +#define regUMCCH6_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr4_Lo 0x80b4e +#define regUMCCH6_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr4_Hi 0x80b4f +#define regUMCCH6_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl5 0x80b50 +#define regUMCCH6_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr5_Lo 0x80b51 +#define regUMCCH6_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr5_Hi 0x80b52 +#define regUMCCH6_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl6 0x80b53 +#define regUMCCH6_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr6_Lo 0x80b54 +#define regUMCCH6_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr6_Hi 0x80b55 +#define regUMCCH6_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl7 0x80b56 +#define regUMCCH6_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr7_Lo 0x80b57 +#define regUMCCH6_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr7_Hi 0x80b58 +#define regUMCCH6_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtl8 0x80b59 +#define regUMCCH6_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr8_Lo 0x80b5a +#define regUMCCH6_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH6_1_PerfMonCtr8_Hi 0x80b5b +#define regUMCCH6_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc1_umcch7_umcchdec +// base address: 0x353000 +#define regUMCCH7_1_BaseAddrCS0 0x80c00 +#define regUMCCH7_1_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH7_1_AddrMaskCS01 0x80c08 +#define regUMCCH7_1_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH7_1_AddrSelCS01 0x80c10 +#define regUMCCH7_1_AddrSelCS01_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank0 0x80c32 +#define regUMCCH7_1_AddrHashBank0_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank1 0x80c33 +#define regUMCCH7_1_AddrHashBank1_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank2 0x80c34 +#define regUMCCH7_1_AddrHashBank2_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank3 0x80c35 +#define regUMCCH7_1_AddrHashBank3_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank4 0x80c36 +#define regUMCCH7_1_AddrHashBank4_BASE_IDX 1 +#define regUMCCH7_1_AddrHashBank5 0x80c37 +#define regUMCCH7_1_AddrHashBank5_BASE_IDX 1 +#define regUMCCH7_1_EccErrCntSel 0x80f28 +#define regUMCCH7_1_EccErrCntSel_BASE_IDX 1 +#define regUMCCH7_1_EccErrCnt 0x80f29 +#define regUMCCH7_1_EccErrCnt_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtlClk 0x80f40 +#define regUMCCH7_1_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtrClk_Lo 0x80f41 +#define regUMCCH7_1_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtrClk_Hi 0x80f42 +#define regUMCCH7_1_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl1 0x80f44 +#define regUMCCH7_1_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr1_Lo 0x80f45 +#define regUMCCH7_1_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr1_Hi 0x80f46 +#define regUMCCH7_1_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl2 0x80f47 +#define regUMCCH7_1_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr2_Lo 0x80f48 +#define regUMCCH7_1_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr2_Hi 0x80f49 +#define regUMCCH7_1_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl3 0x80f4a +#define regUMCCH7_1_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr3_Lo 0x80f4b +#define regUMCCH7_1_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr3_Hi 0x80f4c +#define regUMCCH7_1_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl4 0x80f4d +#define regUMCCH7_1_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr4_Lo 0x80f4e +#define regUMCCH7_1_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr4_Hi 0x80f4f +#define regUMCCH7_1_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl5 0x80f50 +#define regUMCCH7_1_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr5_Lo 0x80f51 +#define regUMCCH7_1_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr5_Hi 0x80f52 +#define regUMCCH7_1_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl6 0x80f53 +#define regUMCCH7_1_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr6_Lo 0x80f54 +#define regUMCCH7_1_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr6_Hi 0x80f55 +#define regUMCCH7_1_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl7 0x80f56 +#define regUMCCH7_1_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr7_Lo 0x80f57 +#define regUMCCH7_1_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr7_Hi 0x80f58 +#define regUMCCH7_1_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtl8 0x80f59 +#define regUMCCH7_1_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr8_Lo 0x80f5a +#define regUMCCH7_1_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH7_1_PerfMonCtr8_Hi 0x80f5b +#define regUMCCH7_1_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch0_umcchdec +// base address: 0x450000 +#define regUMCCH0_2_BaseAddrCS0 0xc0000 +#define regUMCCH0_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH0_2_AddrMaskCS01 0xc0008 +#define regUMCCH0_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH0_2_AddrSelCS01 0xc0010 +#define regUMCCH0_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank0 0xc0032 +#define regUMCCH0_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank1 0xc0033 +#define regUMCCH0_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank2 0xc0034 +#define regUMCCH0_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank3 0xc0035 +#define regUMCCH0_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank4 0xc0036 +#define regUMCCH0_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH0_2_AddrHashBank5 0xc0037 +#define regUMCCH0_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH0_2_EccErrCntSel 0xc0328 +#define regUMCCH0_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH0_2_EccErrCnt 0xc0329 +#define regUMCCH0_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtlClk 0xc0340 +#define regUMCCH0_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtrClk_Lo 0xc0341 +#define regUMCCH0_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtrClk_Hi 0xc0342 +#define regUMCCH0_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl1 0xc0344 +#define regUMCCH0_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr1_Lo 0xc0345 +#define regUMCCH0_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr1_Hi 0xc0346 +#define regUMCCH0_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl2 0xc0347 +#define regUMCCH0_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr2_Lo 0xc0348 +#define regUMCCH0_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr2_Hi 0xc0349 +#define regUMCCH0_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl3 0xc034a +#define regUMCCH0_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr3_Lo 0xc034b +#define regUMCCH0_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr3_Hi 0xc034c +#define regUMCCH0_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl4 0xc034d +#define regUMCCH0_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr4_Lo 0xc034e +#define regUMCCH0_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr4_Hi 0xc034f +#define regUMCCH0_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl5 0xc0350 +#define regUMCCH0_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr5_Lo 0xc0351 +#define regUMCCH0_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr5_Hi 0xc0352 +#define regUMCCH0_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl6 0xc0353 +#define regUMCCH0_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr6_Lo 0xc0354 +#define regUMCCH0_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr6_Hi 0xc0355 +#define regUMCCH0_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl7 0xc0356 +#define regUMCCH0_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr7_Lo 0xc0357 +#define regUMCCH0_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr7_Hi 0xc0358 +#define regUMCCH0_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtl8 0xc0359 +#define regUMCCH0_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr8_Lo 0xc035a +#define regUMCCH0_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH0_2_PerfMonCtr8_Hi 0xc035b +#define regUMCCH0_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch1_umcchdec +// base address: 0x451000 +#define regUMCCH1_2_BaseAddrCS0 0xc0400 +#define regUMCCH1_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH1_2_AddrMaskCS01 0xc0408 +#define regUMCCH1_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH1_2_AddrSelCS01 0xc0410 +#define regUMCCH1_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank0 0xc0432 +#define regUMCCH1_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank1 0xc0433 +#define regUMCCH1_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank2 0xc0434 +#define regUMCCH1_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank3 0xc0435 +#define regUMCCH1_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank4 0xc0436 +#define regUMCCH1_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH1_2_AddrHashBank5 0xc0437 +#define regUMCCH1_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH1_2_EccErrCntSel 0xc0728 +#define regUMCCH1_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH1_2_EccErrCnt 0xc0729 +#define regUMCCH1_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtlClk 0xc0740 +#define regUMCCH1_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtrClk_Lo 0xc0741 +#define regUMCCH1_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtrClk_Hi 0xc0742 +#define regUMCCH1_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl1 0xc0744 +#define regUMCCH1_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr1_Lo 0xc0745 +#define regUMCCH1_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr1_Hi 0xc0746 +#define regUMCCH1_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl2 0xc0747 +#define regUMCCH1_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr2_Lo 0xc0748 +#define regUMCCH1_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr2_Hi 0xc0749 +#define regUMCCH1_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl3 0xc074a +#define regUMCCH1_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr3_Lo 0xc074b +#define regUMCCH1_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr3_Hi 0xc074c +#define regUMCCH1_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl4 0xc074d +#define regUMCCH1_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr4_Lo 0xc074e +#define regUMCCH1_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr4_Hi 0xc074f +#define regUMCCH1_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl5 0xc0750 +#define regUMCCH1_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr5_Lo 0xc0751 +#define regUMCCH1_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr5_Hi 0xc0752 +#define regUMCCH1_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl6 0xc0753 +#define regUMCCH1_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr6_Lo 0xc0754 +#define regUMCCH1_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr6_Hi 0xc0755 +#define regUMCCH1_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl7 0xc0756 +#define regUMCCH1_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr7_Lo 0xc0757 +#define regUMCCH1_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr7_Hi 0xc0758 +#define regUMCCH1_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtl8 0xc0759 +#define regUMCCH1_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr8_Lo 0xc075a +#define regUMCCH1_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH1_2_PerfMonCtr8_Hi 0xc075b +#define regUMCCH1_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch2_umcchdec +// base address: 0x452000 +#define regUMCCH2_2_BaseAddrCS0 0xc0800 +#define regUMCCH2_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH2_2_AddrMaskCS01 0xc0808 +#define regUMCCH2_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH2_2_AddrSelCS01 0xc0810 +#define regUMCCH2_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank0 0xc0832 +#define regUMCCH2_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank1 0xc0833 +#define regUMCCH2_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank2 0xc0834 +#define regUMCCH2_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank3 0xc0835 +#define regUMCCH2_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank4 0xc0836 +#define regUMCCH2_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH2_2_AddrHashBank5 0xc0837 +#define regUMCCH2_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH2_2_EccErrCntSel 0xc0b28 +#define regUMCCH2_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH2_2_EccErrCnt 0xc0b29 +#define regUMCCH2_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtlClk 0xc0b40 +#define regUMCCH2_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtrClk_Lo 0xc0b41 +#define regUMCCH2_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtrClk_Hi 0xc0b42 +#define regUMCCH2_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl1 0xc0b44 +#define regUMCCH2_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr1_Lo 0xc0b45 +#define regUMCCH2_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr1_Hi 0xc0b46 +#define regUMCCH2_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl2 0xc0b47 +#define regUMCCH2_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr2_Lo 0xc0b48 +#define regUMCCH2_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr2_Hi 0xc0b49 +#define regUMCCH2_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl3 0xc0b4a +#define regUMCCH2_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr3_Lo 0xc0b4b +#define regUMCCH2_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr3_Hi 0xc0b4c +#define regUMCCH2_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl4 0xc0b4d +#define regUMCCH2_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr4_Lo 0xc0b4e +#define regUMCCH2_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr4_Hi 0xc0b4f +#define regUMCCH2_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl5 0xc0b50 +#define regUMCCH2_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr5_Lo 0xc0b51 +#define regUMCCH2_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr5_Hi 0xc0b52 +#define regUMCCH2_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl6 0xc0b53 +#define regUMCCH2_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr6_Lo 0xc0b54 +#define regUMCCH2_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr6_Hi 0xc0b55 +#define regUMCCH2_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl7 0xc0b56 +#define regUMCCH2_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr7_Lo 0xc0b57 +#define regUMCCH2_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr7_Hi 0xc0b58 +#define regUMCCH2_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtl8 0xc0b59 +#define regUMCCH2_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr8_Lo 0xc0b5a +#define regUMCCH2_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH2_2_PerfMonCtr8_Hi 0xc0b5b +#define regUMCCH2_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch3_umcchdec +// base address: 0x453000 +#define regUMCCH3_2_BaseAddrCS0 0xc0c00 +#define regUMCCH3_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH3_2_AddrMaskCS01 0xc0c08 +#define regUMCCH3_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH3_2_AddrSelCS01 0xc0c10 +#define regUMCCH3_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank0 0xc0c32 +#define regUMCCH3_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank1 0xc0c33 +#define regUMCCH3_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank2 0xc0c34 +#define regUMCCH3_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank3 0xc0c35 +#define regUMCCH3_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank4 0xc0c36 +#define regUMCCH3_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH3_2_AddrHashBank5 0xc0c37 +#define regUMCCH3_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH3_2_EccErrCntSel 0xc0f28 +#define regUMCCH3_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH3_2_EccErrCnt 0xc0f29 +#define regUMCCH3_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtlClk 0xc0f40 +#define regUMCCH3_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtrClk_Lo 0xc0f41 +#define regUMCCH3_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtrClk_Hi 0xc0f42 +#define regUMCCH3_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl1 0xc0f44 +#define regUMCCH3_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr1_Lo 0xc0f45 +#define regUMCCH3_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr1_Hi 0xc0f46 +#define regUMCCH3_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl2 0xc0f47 +#define regUMCCH3_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr2_Lo 0xc0f48 +#define regUMCCH3_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr2_Hi 0xc0f49 +#define regUMCCH3_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl3 0xc0f4a +#define regUMCCH3_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr3_Lo 0xc0f4b +#define regUMCCH3_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr3_Hi 0xc0f4c +#define regUMCCH3_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl4 0xc0f4d +#define regUMCCH3_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr4_Lo 0xc0f4e +#define regUMCCH3_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr4_Hi 0xc0f4f +#define regUMCCH3_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl5 0xc0f50 +#define regUMCCH3_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr5_Lo 0xc0f51 +#define regUMCCH3_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr5_Hi 0xc0f52 +#define regUMCCH3_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl6 0xc0f53 +#define regUMCCH3_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr6_Lo 0xc0f54 +#define regUMCCH3_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr6_Hi 0xc0f55 +#define regUMCCH3_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl7 0xc0f56 +#define regUMCCH3_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr7_Lo 0xc0f57 +#define regUMCCH3_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr7_Hi 0xc0f58 +#define regUMCCH3_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtl8 0xc0f59 +#define regUMCCH3_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr8_Lo 0xc0f5a +#define regUMCCH3_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH3_2_PerfMonCtr8_Hi 0xc0f5b +#define regUMCCH3_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch4_umcchdec +// base address: 0x550000 +#define regUMCCH4_2_BaseAddrCS0 0x100000 +#define regUMCCH4_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH4_2_AddrMaskCS01 0x100008 +#define regUMCCH4_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH4_2_AddrSelCS01 0x100010 +#define regUMCCH4_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank0 0x100032 +#define regUMCCH4_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank1 0x100033 +#define regUMCCH4_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank2 0x100034 +#define regUMCCH4_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank3 0x100035 +#define regUMCCH4_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank4 0x100036 +#define regUMCCH4_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH4_2_AddrHashBank5 0x100037 +#define regUMCCH4_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH4_2_EccErrCntSel 0x100328 +#define regUMCCH4_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH4_2_EccErrCnt 0x100329 +#define regUMCCH4_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtlClk 0x100340 +#define regUMCCH4_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtrClk_Lo 0x100341 +#define regUMCCH4_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtrClk_Hi 0x100342 +#define regUMCCH4_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl1 0x100344 +#define regUMCCH4_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr1_Lo 0x100345 +#define regUMCCH4_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr1_Hi 0x100346 +#define regUMCCH4_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl2 0x100347 +#define regUMCCH4_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr2_Lo 0x100348 +#define regUMCCH4_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr2_Hi 0x100349 +#define regUMCCH4_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl3 0x10034a +#define regUMCCH4_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr3_Lo 0x10034b +#define regUMCCH4_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr3_Hi 0x10034c +#define regUMCCH4_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl4 0x10034d +#define regUMCCH4_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr4_Lo 0x10034e +#define regUMCCH4_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr4_Hi 0x10034f +#define regUMCCH4_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl5 0x100350 +#define regUMCCH4_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr5_Lo 0x100351 +#define regUMCCH4_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr5_Hi 0x100352 +#define regUMCCH4_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl6 0x100353 +#define regUMCCH4_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr6_Lo 0x100354 +#define regUMCCH4_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr6_Hi 0x100355 +#define regUMCCH4_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl7 0x100356 +#define regUMCCH4_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr7_Lo 0x100357 +#define regUMCCH4_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr7_Hi 0x100358 +#define regUMCCH4_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtl8 0x100359 +#define regUMCCH4_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr8_Lo 0x10035a +#define regUMCCH4_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH4_2_PerfMonCtr8_Hi 0x10035b +#define regUMCCH4_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch5_umcchdec +// base address: 0x551000 +#define regUMCCH5_2_BaseAddrCS0 0x100400 +#define regUMCCH5_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH5_2_AddrMaskCS01 0x100408 +#define regUMCCH5_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH5_2_AddrSelCS01 0x100410 +#define regUMCCH5_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank0 0x100432 +#define regUMCCH5_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank1 0x100433 +#define regUMCCH5_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank2 0x100434 +#define regUMCCH5_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank3 0x100435 +#define regUMCCH5_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank4 0x100436 +#define regUMCCH5_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH5_2_AddrHashBank5 0x100437 +#define regUMCCH5_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH5_2_EccErrCntSel 0x100728 +#define regUMCCH5_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH5_2_EccErrCnt 0x100729 +#define regUMCCH5_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtlClk 0x100740 +#define regUMCCH5_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtrClk_Lo 0x100741 +#define regUMCCH5_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtrClk_Hi 0x100742 +#define regUMCCH5_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl1 0x100744 +#define regUMCCH5_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr1_Lo 0x100745 +#define regUMCCH5_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr1_Hi 0x100746 +#define regUMCCH5_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl2 0x100747 +#define regUMCCH5_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr2_Lo 0x100748 +#define regUMCCH5_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr2_Hi 0x100749 +#define regUMCCH5_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl3 0x10074a +#define regUMCCH5_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr3_Lo 0x10074b +#define regUMCCH5_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr3_Hi 0x10074c +#define regUMCCH5_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl4 0x10074d +#define regUMCCH5_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr4_Lo 0x10074e +#define regUMCCH5_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr4_Hi 0x10074f +#define regUMCCH5_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl5 0x100750 +#define regUMCCH5_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr5_Lo 0x100751 +#define regUMCCH5_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr5_Hi 0x100752 +#define regUMCCH5_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl6 0x100753 +#define regUMCCH5_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr6_Lo 0x100754 +#define regUMCCH5_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr6_Hi 0x100755 +#define regUMCCH5_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl7 0x100756 +#define regUMCCH5_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr7_Lo 0x100757 +#define regUMCCH5_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr7_Hi 0x100758 +#define regUMCCH5_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtl8 0x100759 +#define regUMCCH5_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr8_Lo 0x10075a +#define regUMCCH5_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH5_2_PerfMonCtr8_Hi 0x10075b +#define regUMCCH5_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch6_umcchdec +// base address: 0x552000 +#define regUMCCH6_2_BaseAddrCS0 0x100800 +#define regUMCCH6_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH6_2_AddrMaskCS01 0x100808 +#define regUMCCH6_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH6_2_AddrSelCS01 0x100810 +#define regUMCCH6_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank0 0x100832 +#define regUMCCH6_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank1 0x100833 +#define regUMCCH6_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank2 0x100834 +#define regUMCCH6_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank3 0x100835 +#define regUMCCH6_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank4 0x100836 +#define regUMCCH6_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH6_2_AddrHashBank5 0x100837 +#define regUMCCH6_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH6_2_EccErrCntSel 0x100b28 +#define regUMCCH6_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH6_2_EccErrCnt 0x100b29 +#define regUMCCH6_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtlClk 0x100b40 +#define regUMCCH6_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtrClk_Lo 0x100b41 +#define regUMCCH6_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtrClk_Hi 0x100b42 +#define regUMCCH6_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl1 0x100b44 +#define regUMCCH6_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr1_Lo 0x100b45 +#define regUMCCH6_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr1_Hi 0x100b46 +#define regUMCCH6_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl2 0x100b47 +#define regUMCCH6_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr2_Lo 0x100b48 +#define regUMCCH6_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr2_Hi 0x100b49 +#define regUMCCH6_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl3 0x100b4a +#define regUMCCH6_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr3_Lo 0x100b4b +#define regUMCCH6_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr3_Hi 0x100b4c +#define regUMCCH6_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl4 0x100b4d +#define regUMCCH6_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr4_Lo 0x100b4e +#define regUMCCH6_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr4_Hi 0x100b4f +#define regUMCCH6_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl5 0x100b50 +#define regUMCCH6_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr5_Lo 0x100b51 +#define regUMCCH6_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr5_Hi 0x100b52 +#define regUMCCH6_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl6 0x100b53 +#define regUMCCH6_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr6_Lo 0x100b54 +#define regUMCCH6_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr6_Hi 0x100b55 +#define regUMCCH6_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl7 0x100b56 +#define regUMCCH6_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr7_Lo 0x100b57 +#define regUMCCH6_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr7_Hi 0x100b58 +#define regUMCCH6_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtl8 0x100b59 +#define regUMCCH6_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr8_Lo 0x100b5a +#define regUMCCH6_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH6_2_PerfMonCtr8_Hi 0x100b5b +#define regUMCCH6_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc2_umcch7_umcchdec +// base address: 0x553000 +#define regUMCCH7_2_BaseAddrCS0 0x100c00 +#define regUMCCH7_2_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH7_2_AddrMaskCS01 0x100c08 +#define regUMCCH7_2_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH7_2_AddrSelCS01 0x100c10 +#define regUMCCH7_2_AddrSelCS01_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank0 0x100c32 +#define regUMCCH7_2_AddrHashBank0_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank1 0x100c33 +#define regUMCCH7_2_AddrHashBank1_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank2 0x100c34 +#define regUMCCH7_2_AddrHashBank2_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank3 0x100c35 +#define regUMCCH7_2_AddrHashBank3_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank4 0x100c36 +#define regUMCCH7_2_AddrHashBank4_BASE_IDX 1 +#define regUMCCH7_2_AddrHashBank5 0x100c37 +#define regUMCCH7_2_AddrHashBank5_BASE_IDX 1 +#define regUMCCH7_2_EccErrCntSel 0x100f28 +#define regUMCCH7_2_EccErrCntSel_BASE_IDX 1 +#define regUMCCH7_2_EccErrCnt 0x100f29 +#define regUMCCH7_2_EccErrCnt_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtlClk 0x100f40 +#define regUMCCH7_2_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtrClk_Lo 0x100f41 +#define regUMCCH7_2_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtrClk_Hi 0x100f42 +#define regUMCCH7_2_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl1 0x100f44 +#define regUMCCH7_2_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr1_Lo 0x100f45 +#define regUMCCH7_2_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr1_Hi 0x100f46 +#define regUMCCH7_2_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl2 0x100f47 +#define regUMCCH7_2_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr2_Lo 0x100f48 +#define regUMCCH7_2_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr2_Hi 0x100f49 +#define regUMCCH7_2_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl3 0x100f4a +#define regUMCCH7_2_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr3_Lo 0x100f4b +#define regUMCCH7_2_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr3_Hi 0x100f4c +#define regUMCCH7_2_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl4 0x100f4d +#define regUMCCH7_2_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr4_Lo 0x100f4e +#define regUMCCH7_2_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr4_Hi 0x100f4f +#define regUMCCH7_2_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl5 0x100f50 +#define regUMCCH7_2_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr5_Lo 0x100f51 +#define regUMCCH7_2_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr5_Hi 0x100f52 +#define regUMCCH7_2_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl6 0x100f53 +#define regUMCCH7_2_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr6_Lo 0x100f54 +#define regUMCCH7_2_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr6_Hi 0x100f55 +#define regUMCCH7_2_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl7 0x100f56 +#define regUMCCH7_2_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr7_Lo 0x100f57 +#define regUMCCH7_2_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr7_Hi 0x100f58 +#define regUMCCH7_2_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtl8 0x100f59 +#define regUMCCH7_2_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr8_Lo 0x100f5a +#define regUMCCH7_2_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH7_2_PerfMonCtr8_Hi 0x100f5b +#define regUMCCH7_2_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch0_umcchdec +// base address: 0x650000 +#define regUMCCH0_3_BaseAddrCS0 0x140000 +#define regUMCCH0_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH0_3_AddrMaskCS01 0x140008 +#define regUMCCH0_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH0_3_AddrSelCS01 0x140010 +#define regUMCCH0_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank0 0x140032 +#define regUMCCH0_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank1 0x140033 +#define regUMCCH0_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank2 0x140034 +#define regUMCCH0_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank3 0x140035 +#define regUMCCH0_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank4 0x140036 +#define regUMCCH0_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH0_3_AddrHashBank5 0x140037 +#define regUMCCH0_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH0_3_EccErrCntSel 0x140328 +#define regUMCCH0_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH0_3_EccErrCnt 0x140329 +#define regUMCCH0_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtlClk 0x140340 +#define regUMCCH0_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtrClk_Lo 0x140341 +#define regUMCCH0_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtrClk_Hi 0x140342 +#define regUMCCH0_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl1 0x140344 +#define regUMCCH0_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr1_Lo 0x140345 +#define regUMCCH0_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr1_Hi 0x140346 +#define regUMCCH0_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl2 0x140347 +#define regUMCCH0_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr2_Lo 0x140348 +#define regUMCCH0_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr2_Hi 0x140349 +#define regUMCCH0_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl3 0x14034a +#define regUMCCH0_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr3_Lo 0x14034b +#define regUMCCH0_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr3_Hi 0x14034c +#define regUMCCH0_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl4 0x14034d +#define regUMCCH0_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr4_Lo 0x14034e +#define regUMCCH0_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr4_Hi 0x14034f +#define regUMCCH0_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl5 0x140350 +#define regUMCCH0_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr5_Lo 0x140351 +#define regUMCCH0_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr5_Hi 0x140352 +#define regUMCCH0_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl6 0x140353 +#define regUMCCH0_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr6_Lo 0x140354 +#define regUMCCH0_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr6_Hi 0x140355 +#define regUMCCH0_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl7 0x140356 +#define regUMCCH0_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr7_Lo 0x140357 +#define regUMCCH0_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr7_Hi 0x140358 +#define regUMCCH0_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtl8 0x140359 +#define regUMCCH0_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr8_Lo 0x14035a +#define regUMCCH0_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH0_3_PerfMonCtr8_Hi 0x14035b +#define regUMCCH0_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch1_umcchdec +// base address: 0x651000 +#define regUMCCH1_3_BaseAddrCS0 0x140400 +#define regUMCCH1_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH1_3_AddrMaskCS01 0x140408 +#define regUMCCH1_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH1_3_AddrSelCS01 0x140410 +#define regUMCCH1_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank0 0x140432 +#define regUMCCH1_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank1 0x140433 +#define regUMCCH1_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank2 0x140434 +#define regUMCCH1_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank3 0x140435 +#define regUMCCH1_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank4 0x140436 +#define regUMCCH1_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH1_3_AddrHashBank5 0x140437 +#define regUMCCH1_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH1_3_EccErrCntSel 0x140728 +#define regUMCCH1_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH1_3_EccErrCnt 0x140729 +#define regUMCCH1_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtlClk 0x140740 +#define regUMCCH1_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtrClk_Lo 0x140741 +#define regUMCCH1_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtrClk_Hi 0x140742 +#define regUMCCH1_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl1 0x140744 +#define regUMCCH1_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr1_Lo 0x140745 +#define regUMCCH1_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr1_Hi 0x140746 +#define regUMCCH1_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl2 0x140747 +#define regUMCCH1_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr2_Lo 0x140748 +#define regUMCCH1_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr2_Hi 0x140749 +#define regUMCCH1_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl3 0x14074a +#define regUMCCH1_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr3_Lo 0x14074b +#define regUMCCH1_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr3_Hi 0x14074c +#define regUMCCH1_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl4 0x14074d +#define regUMCCH1_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr4_Lo 0x14074e +#define regUMCCH1_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr4_Hi 0x14074f +#define regUMCCH1_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl5 0x140750 +#define regUMCCH1_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr5_Lo 0x140751 +#define regUMCCH1_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr5_Hi 0x140752 +#define regUMCCH1_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl6 0x140753 +#define regUMCCH1_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr6_Lo 0x140754 +#define regUMCCH1_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr6_Hi 0x140755 +#define regUMCCH1_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl7 0x140756 +#define regUMCCH1_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr7_Lo 0x140757 +#define regUMCCH1_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr7_Hi 0x140758 +#define regUMCCH1_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtl8 0x140759 +#define regUMCCH1_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr8_Lo 0x14075a +#define regUMCCH1_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH1_3_PerfMonCtr8_Hi 0x14075b +#define regUMCCH1_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch2_umcchdec +// base address: 0x652000 +#define regUMCCH2_3_BaseAddrCS0 0x140800 +#define regUMCCH2_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH2_3_AddrMaskCS01 0x140808 +#define regUMCCH2_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH2_3_AddrSelCS01 0x140810 +#define regUMCCH2_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank0 0x140832 +#define regUMCCH2_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank1 0x140833 +#define regUMCCH2_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank2 0x140834 +#define regUMCCH2_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank3 0x140835 +#define regUMCCH2_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank4 0x140836 +#define regUMCCH2_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH2_3_AddrHashBank5 0x140837 +#define regUMCCH2_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH2_3_EccErrCntSel 0x140b28 +#define regUMCCH2_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH2_3_EccErrCnt 0x140b29 +#define regUMCCH2_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtlClk 0x140b40 +#define regUMCCH2_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtrClk_Lo 0x140b41 +#define regUMCCH2_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtrClk_Hi 0x140b42 +#define regUMCCH2_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl1 0x140b44 +#define regUMCCH2_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr1_Lo 0x140b45 +#define regUMCCH2_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr1_Hi 0x140b46 +#define regUMCCH2_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl2 0x140b47 +#define regUMCCH2_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr2_Lo 0x140b48 +#define regUMCCH2_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr2_Hi 0x140b49 +#define regUMCCH2_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl3 0x140b4a +#define regUMCCH2_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr3_Lo 0x140b4b +#define regUMCCH2_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr3_Hi 0x140b4c +#define regUMCCH2_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl4 0x140b4d +#define regUMCCH2_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr4_Lo 0x140b4e +#define regUMCCH2_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr4_Hi 0x140b4f +#define regUMCCH2_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl5 0x140b50 +#define regUMCCH2_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr5_Lo 0x140b51 +#define regUMCCH2_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr5_Hi 0x140b52 +#define regUMCCH2_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl6 0x140b53 +#define regUMCCH2_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr6_Lo 0x140b54 +#define regUMCCH2_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr6_Hi 0x140b55 +#define regUMCCH2_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl7 0x140b56 +#define regUMCCH2_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr7_Lo 0x140b57 +#define regUMCCH2_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr7_Hi 0x140b58 +#define regUMCCH2_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtl8 0x140b59 +#define regUMCCH2_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr8_Lo 0x140b5a +#define regUMCCH2_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH2_3_PerfMonCtr8_Hi 0x140b5b +#define regUMCCH2_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch3_umcchdec +// base address: 0x653000 +#define regUMCCH3_3_BaseAddrCS0 0x140c00 +#define regUMCCH3_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH3_3_AddrMaskCS01 0x140c08 +#define regUMCCH3_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH3_3_AddrSelCS01 0x140c10 +#define regUMCCH3_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank0 0x140c32 +#define regUMCCH3_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank1 0x140c33 +#define regUMCCH3_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank2 0x140c34 +#define regUMCCH3_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank3 0x140c35 +#define regUMCCH3_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank4 0x140c36 +#define regUMCCH3_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH3_3_AddrHashBank5 0x140c37 +#define regUMCCH3_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH3_3_EccErrCntSel 0x140f28 +#define regUMCCH3_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH3_3_EccErrCnt 0x140f29 +#define regUMCCH3_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtlClk 0x140f40 +#define regUMCCH3_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtrClk_Lo 0x140f41 +#define regUMCCH3_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtrClk_Hi 0x140f42 +#define regUMCCH3_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl1 0x140f44 +#define regUMCCH3_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr1_Lo 0x140f45 +#define regUMCCH3_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr1_Hi 0x140f46 +#define regUMCCH3_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl2 0x140f47 +#define regUMCCH3_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr2_Lo 0x140f48 +#define regUMCCH3_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr2_Hi 0x140f49 +#define regUMCCH3_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl3 0x140f4a +#define regUMCCH3_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr3_Lo 0x140f4b +#define regUMCCH3_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr3_Hi 0x140f4c +#define regUMCCH3_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl4 0x140f4d +#define regUMCCH3_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr4_Lo 0x140f4e +#define regUMCCH3_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr4_Hi 0x140f4f +#define regUMCCH3_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl5 0x140f50 +#define regUMCCH3_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr5_Lo 0x140f51 +#define regUMCCH3_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr5_Hi 0x140f52 +#define regUMCCH3_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl6 0x140f53 +#define regUMCCH3_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr6_Lo 0x140f54 +#define regUMCCH3_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr6_Hi 0x140f55 +#define regUMCCH3_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl7 0x140f56 +#define regUMCCH3_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr7_Lo 0x140f57 +#define regUMCCH3_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr7_Hi 0x140f58 +#define regUMCCH3_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtl8 0x140f59 +#define regUMCCH3_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr8_Lo 0x140f5a +#define regUMCCH3_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH3_3_PerfMonCtr8_Hi 0x140f5b +#define regUMCCH3_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch4_umcchdec +// base address: 0x750000 +#define regUMCCH4_3_BaseAddrCS0 0x180000 +#define regUMCCH4_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH4_3_AddrMaskCS01 0x180008 +#define regUMCCH4_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH4_3_AddrSelCS01 0x180010 +#define regUMCCH4_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank0 0x180032 +#define regUMCCH4_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank1 0x180033 +#define regUMCCH4_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank2 0x180034 +#define regUMCCH4_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank3 0x180035 +#define regUMCCH4_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank4 0x180036 +#define regUMCCH4_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH4_3_AddrHashBank5 0x180037 +#define regUMCCH4_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH4_3_EccErrCntSel 0x180328 +#define regUMCCH4_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH4_3_EccErrCnt 0x180329 +#define regUMCCH4_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtlClk 0x180340 +#define regUMCCH4_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtrClk_Lo 0x180341 +#define regUMCCH4_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtrClk_Hi 0x180342 +#define regUMCCH4_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl1 0x180344 +#define regUMCCH4_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr1_Lo 0x180345 +#define regUMCCH4_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr1_Hi 0x180346 +#define regUMCCH4_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl2 0x180347 +#define regUMCCH4_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr2_Lo 0x180348 +#define regUMCCH4_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr2_Hi 0x180349 +#define regUMCCH4_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl3 0x18034a +#define regUMCCH4_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr3_Lo 0x18034b +#define regUMCCH4_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr3_Hi 0x18034c +#define regUMCCH4_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl4 0x18034d +#define regUMCCH4_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr4_Lo 0x18034e +#define regUMCCH4_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr4_Hi 0x18034f +#define regUMCCH4_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl5 0x180350 +#define regUMCCH4_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr5_Lo 0x180351 +#define regUMCCH4_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr5_Hi 0x180352 +#define regUMCCH4_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl6 0x180353 +#define regUMCCH4_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr6_Lo 0x180354 +#define regUMCCH4_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr6_Hi 0x180355 +#define regUMCCH4_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl7 0x180356 +#define regUMCCH4_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr7_Lo 0x180357 +#define regUMCCH4_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr7_Hi 0x180358 +#define regUMCCH4_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtl8 0x180359 +#define regUMCCH4_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr8_Lo 0x18035a +#define regUMCCH4_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH4_3_PerfMonCtr8_Hi 0x18035b +#define regUMCCH4_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch5_umcchdec +// base address: 0x751000 +#define regUMCCH5_3_BaseAddrCS0 0x180400 +#define regUMCCH5_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH5_3_AddrMaskCS01 0x180408 +#define regUMCCH5_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH5_3_AddrSelCS01 0x180410 +#define regUMCCH5_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank0 0x180432 +#define regUMCCH5_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank1 0x180433 +#define regUMCCH5_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank2 0x180434 +#define regUMCCH5_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank3 0x180435 +#define regUMCCH5_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank4 0x180436 +#define regUMCCH5_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH5_3_AddrHashBank5 0x180437 +#define regUMCCH5_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH5_3_EccErrCntSel 0x180728 +#define regUMCCH5_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH5_3_EccErrCnt 0x180729 +#define regUMCCH5_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtlClk 0x180740 +#define regUMCCH5_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtrClk_Lo 0x180741 +#define regUMCCH5_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtrClk_Hi 0x180742 +#define regUMCCH5_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl1 0x180744 +#define regUMCCH5_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr1_Lo 0x180745 +#define regUMCCH5_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr1_Hi 0x180746 +#define regUMCCH5_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl2 0x180747 +#define regUMCCH5_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr2_Lo 0x180748 +#define regUMCCH5_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr2_Hi 0x180749 +#define regUMCCH5_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl3 0x18074a +#define regUMCCH5_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr3_Lo 0x18074b +#define regUMCCH5_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr3_Hi 0x18074c +#define regUMCCH5_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl4 0x18074d +#define regUMCCH5_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr4_Lo 0x18074e +#define regUMCCH5_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr4_Hi 0x18074f +#define regUMCCH5_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl5 0x180750 +#define regUMCCH5_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr5_Lo 0x180751 +#define regUMCCH5_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr5_Hi 0x180752 +#define regUMCCH5_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl6 0x180753 +#define regUMCCH5_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr6_Lo 0x180754 +#define regUMCCH5_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr6_Hi 0x180755 +#define regUMCCH5_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl7 0x180756 +#define regUMCCH5_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr7_Lo 0x180757 +#define regUMCCH5_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr7_Hi 0x180758 +#define regUMCCH5_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtl8 0x180759 +#define regUMCCH5_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr8_Lo 0x18075a +#define regUMCCH5_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH5_3_PerfMonCtr8_Hi 0x18075b +#define regUMCCH5_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch6_umcchdec +// base address: 0x752000 +#define regUMCCH6_3_BaseAddrCS0 0x180800 +#define regUMCCH6_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH6_3_AddrMaskCS01 0x180808 +#define regUMCCH6_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH6_3_AddrSelCS01 0x180810 +#define regUMCCH6_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank0 0x180832 +#define regUMCCH6_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank1 0x180833 +#define regUMCCH6_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank2 0x180834 +#define regUMCCH6_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank3 0x180835 +#define regUMCCH6_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank4 0x180836 +#define regUMCCH6_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH6_3_AddrHashBank5 0x180837 +#define regUMCCH6_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH6_3_EccErrCntSel 0x180b28 +#define regUMCCH6_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH6_3_EccErrCnt 0x180b29 +#define regUMCCH6_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtlClk 0x180b40 +#define regUMCCH6_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtrClk_Lo 0x180b41 +#define regUMCCH6_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtrClk_Hi 0x180b42 +#define regUMCCH6_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl1 0x180b44 +#define regUMCCH6_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr1_Lo 0x180b45 +#define regUMCCH6_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr1_Hi 0x180b46 +#define regUMCCH6_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl2 0x180b47 +#define regUMCCH6_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr2_Lo 0x180b48 +#define regUMCCH6_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr2_Hi 0x180b49 +#define regUMCCH6_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl3 0x180b4a +#define regUMCCH6_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr3_Lo 0x180b4b +#define regUMCCH6_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr3_Hi 0x180b4c +#define regUMCCH6_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl4 0x180b4d +#define regUMCCH6_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr4_Lo 0x180b4e +#define regUMCCH6_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr4_Hi 0x180b4f +#define regUMCCH6_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl5 0x180b50 +#define regUMCCH6_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr5_Lo 0x180b51 +#define regUMCCH6_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr5_Hi 0x180b52 +#define regUMCCH6_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl6 0x180b53 +#define regUMCCH6_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr6_Lo 0x180b54 +#define regUMCCH6_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr6_Hi 0x180b55 +#define regUMCCH6_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl7 0x180b56 +#define regUMCCH6_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr7_Lo 0x180b57 +#define regUMCCH6_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr7_Hi 0x180b58 +#define regUMCCH6_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtl8 0x180b59 +#define regUMCCH6_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr8_Lo 0x180b5a +#define regUMCCH6_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH6_3_PerfMonCtr8_Hi 0x180b5b +#define regUMCCH6_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +// addressBlock: umc_w_phy_umc3_umcch7_umcchdec +// base address: 0x753000 +#define regUMCCH7_3_BaseAddrCS0 0x180c00 +#define regUMCCH7_3_BaseAddrCS0_BASE_IDX 1 +#define regUMCCH7_3_AddrMaskCS01 0x180c08 +#define regUMCCH7_3_AddrMaskCS01_BASE_IDX 1 +#define regUMCCH7_3_AddrSelCS01 0x180c10 +#define regUMCCH7_3_AddrSelCS01_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank0 0x180c32 +#define regUMCCH7_3_AddrHashBank0_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank1 0x180c33 +#define regUMCCH7_3_AddrHashBank1_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank2 0x180c34 +#define regUMCCH7_3_AddrHashBank2_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank3 0x180c35 +#define regUMCCH7_3_AddrHashBank3_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank4 0x180c36 +#define regUMCCH7_3_AddrHashBank4_BASE_IDX 1 +#define regUMCCH7_3_AddrHashBank5 0x180c37 +#define regUMCCH7_3_AddrHashBank5_BASE_IDX 1 +#define regUMCCH7_3_EccErrCntSel 0x180f28 +#define regUMCCH7_3_EccErrCntSel_BASE_IDX 1 +#define regUMCCH7_3_EccErrCnt 0x180f29 +#define regUMCCH7_3_EccErrCnt_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtlClk 0x180f40 +#define regUMCCH7_3_PerfMonCtlClk_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtrClk_Lo 0x180f41 +#define regUMCCH7_3_PerfMonCtrClk_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtrClk_Hi 0x180f42 +#define regUMCCH7_3_PerfMonCtrClk_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl1 0x180f44 +#define regUMCCH7_3_PerfMonCtl1_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr1_Lo 0x180f45 +#define regUMCCH7_3_PerfMonCtr1_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr1_Hi 0x180f46 +#define regUMCCH7_3_PerfMonCtr1_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl2 0x180f47 +#define regUMCCH7_3_PerfMonCtl2_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr2_Lo 0x180f48 +#define regUMCCH7_3_PerfMonCtr2_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr2_Hi 0x180f49 +#define regUMCCH7_3_PerfMonCtr2_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl3 0x180f4a +#define regUMCCH7_3_PerfMonCtl3_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr3_Lo 0x180f4b +#define regUMCCH7_3_PerfMonCtr3_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr3_Hi 0x180f4c +#define regUMCCH7_3_PerfMonCtr3_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl4 0x180f4d +#define regUMCCH7_3_PerfMonCtl4_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr4_Lo 0x180f4e +#define regUMCCH7_3_PerfMonCtr4_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr4_Hi 0x180f4f +#define regUMCCH7_3_PerfMonCtr4_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl5 0x180f50 +#define regUMCCH7_3_PerfMonCtl5_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr5_Lo 0x180f51 +#define regUMCCH7_3_PerfMonCtr5_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr5_Hi 0x180f52 +#define regUMCCH7_3_PerfMonCtr5_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl6 0x180f53 +#define regUMCCH7_3_PerfMonCtl6_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr6_Lo 0x180f54 +#define regUMCCH7_3_PerfMonCtr6_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr6_Hi 0x180f55 +#define regUMCCH7_3_PerfMonCtr6_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl7 0x180f56 +#define regUMCCH7_3_PerfMonCtl7_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr7_Lo 0x180f57 +#define regUMCCH7_3_PerfMonCtr7_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr7_Hi 0x180f58 +#define regUMCCH7_3_PerfMonCtr7_Hi_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtl8 0x180f59 +#define regUMCCH7_3_PerfMonCtl8_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr8_Lo 0x180f5a +#define regUMCCH7_3_PerfMonCtr8_Lo_BASE_IDX 1 +#define regUMCCH7_3_PerfMonCtr8_Hi 0x180f5b +#define regUMCCH7_3_PerfMonCtr8_Hi_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..da5a0968d7cba2b0826c1a500e8960093316121f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h @@ -0,0 +1,10796 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _umc_6_7_0_SH_MASK_HEADER +#define _umc_6_7_0_SH_MASK_HEADER + + +// addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map +//MCA_UMC_UMC0_MCUMC_STATUST0 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16 +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26 +#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29 +#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b +#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c +#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d +#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f +#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34 +#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36 +#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38 +#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39 +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a +#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b +#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c +#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d +#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e +#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L +//MCA_UMC_UMC0_MCUMC_ADDRT0 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xFF00000000000000L + + +// addressBlock: umc_w_phy_umc0_umcch0_umcchdec +//UMCCH0_0_BaseAddrCS0 +#define UMCCH0_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH0_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH0_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH0_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH0_0_AddrMaskCS01 +#define UMCCH0_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH0_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH0_0_AddrSelCS01 +#define UMCCH0_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH0_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH0_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH0_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH0_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH0_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH0_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH0_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH0_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH0_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH0_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH0_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH0_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH0_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH0_0_AddrHashBank0 +#define UMCCH0_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_AddrHashBank1 +#define UMCCH0_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_AddrHashBank2 +#define UMCCH0_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_AddrHashBank3 +#define UMCCH0_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_AddrHashBank4 +#define UMCCH0_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_AddrHashBank5 +#define UMCCH0_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH0_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH0_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH0_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH0_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH0_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH0_0_UMC_CONFIG +#define UMCCH0_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0 +#define UMCCH0_0_UMC_CONFIG__BurstLength__SHIFT 0x8 +#define UMCCH0_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa +#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f +#define UMCCH0_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L +#define UMCCH0_0_UMC_CONFIG__BurstLength_MASK 0x00000300L +#define UMCCH0_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L +#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L +//UMCCH0_0_EccCtrl +#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0 +#define UMCCH0_0_EccCtrl__EccReplayEn__SHIFT 0x1 +#define UMCCH0_0_EccCtrl__UCFatalEn__SHIFT 0x8 +#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH0_0_EccCtrl__PoisonFatalDis__SHIFT 0xc +#define UMCCH0_0_EccCtrl__PoisonInhibit__SHIFT 0xd +#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH0_0_EccCtrl__EccReplayEn_MASK 0x00000002L +#define UMCCH0_0_EccCtrl__UCFatalEn_MASK 0x00000100L +#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH0_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L +#define UMCCH0_0_EccCtrl__PoisonInhibit_MASK 0x00002000L +//UMCCH0_0_UmcLocalCap +#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0 +#define UMCCH0_0_UmcLocalCap__Spare__SHIFT 0x1 +#define UMCCH0_0_UmcLocalCap__WrDis__SHIFT 0x1f +#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH0_0_UmcLocalCap__Spare_MASK 0x0000003EL +#define UMCCH0_0_UmcLocalCap__WrDis_MASK 0x80000000L +//UMCCH0_0_EccErrCntSel +#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH0_0_EccErrCnt +#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH0_0_PerfMonCtlClk +#define UMCCH0_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH0_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH0_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH0_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH0_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH0_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH0_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH0_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH0_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH0_0_PerfMonCtrClk_Lo +#define UMCCH0_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtrClk_Hi +#define UMCCH0_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH0_0_PerfMonCtl1 +#define UMCCH0_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr1_Lo +#define UMCCH0_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr1_Hi +#define UMCCH0_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl2 +#define UMCCH0_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr2_Lo +#define UMCCH0_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr2_Hi +#define UMCCH0_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl3 +#define UMCCH0_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr3_Lo +#define UMCCH0_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr3_Hi +#define UMCCH0_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl4 +#define UMCCH0_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr4_Lo +#define UMCCH0_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr4_Hi +#define UMCCH0_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl5 +#define UMCCH0_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr5_Lo +#define UMCCH0_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr5_Hi +#define UMCCH0_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl6 +#define UMCCH0_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr6_Lo +#define UMCCH0_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr6_Hi +#define UMCCH0_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl7 +#define UMCCH0_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr7_Lo +#define UMCCH0_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr7_Hi +#define UMCCH0_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_0_PerfMonCtl8 +#define UMCCH0_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH0_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH0_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH0_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH0_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH0_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH0_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH0_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH0_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH0_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH0_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH0_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH0_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH0_0_PerfMonCtr8_Lo +#define UMCCH0_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_0_PerfMonCtr8_Hi +#define UMCCH0_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH0_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch1_umcchdec +//UMCCH1_0_BaseAddrCS0 +#define UMCCH1_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH1_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH1_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH1_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH1_0_AddrMaskCS01 +#define UMCCH1_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH1_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH1_0_AddrSelCS01 +#define UMCCH1_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH1_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH1_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH1_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH1_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH1_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH1_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH1_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH1_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH1_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH1_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH1_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH1_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH1_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH1_0_AddrHashBank0 +#define UMCCH1_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_AddrHashBank1 +#define UMCCH1_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_AddrHashBank2 +#define UMCCH1_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_AddrHashBank3 +#define UMCCH1_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_AddrHashBank4 +#define UMCCH1_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_AddrHashBank5 +#define UMCCH1_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH1_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH1_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH1_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH1_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH1_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH1_0_UMC_CONFIG +#define UMCCH1_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0 +#define UMCCH1_0_UMC_CONFIG__BurstLength__SHIFT 0x8 +#define UMCCH1_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa +#define UMCCH1_0_UMC_CONFIG__DramReady__SHIFT 0x1f +#define UMCCH1_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L +#define UMCCH1_0_UMC_CONFIG__BurstLength_MASK 0x00000300L +#define UMCCH1_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L +#define UMCCH1_0_UMC_CONFIG__DramReady_MASK 0x80000000L +//UMCCH1_0_EccCtrl +#define UMCCH1_0_EccCtrl__WrEccEn__SHIFT 0x0 +#define UMCCH1_0_EccCtrl__EccReplayEn__SHIFT 0x1 +#define UMCCH1_0_EccCtrl__UCFatalEn__SHIFT 0x8 +#define UMCCH1_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH1_0_EccCtrl__PoisonFatalDis__SHIFT 0xc +#define UMCCH1_0_EccCtrl__PoisonInhibit__SHIFT 0xd +#define UMCCH1_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH1_0_EccCtrl__EccReplayEn_MASK 0x00000002L +#define UMCCH1_0_EccCtrl__UCFatalEn_MASK 0x00000100L +#define UMCCH1_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH1_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L +#define UMCCH1_0_EccCtrl__PoisonInhibit_MASK 0x00002000L +//UMCCH1_0_UmcLocalCap +#define UMCCH1_0_UmcLocalCap__EccDis__SHIFT 0x0 +#define UMCCH1_0_UmcLocalCap__Spare__SHIFT 0x1 +#define UMCCH1_0_UmcLocalCap__WrDis__SHIFT 0x1f +#define UMCCH1_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH1_0_UmcLocalCap__Spare_MASK 0x0000003EL +#define UMCCH1_0_UmcLocalCap__WrDis_MASK 0x80000000L +//UMCCH1_0_EccErrCntSel +#define UMCCH1_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH1_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH1_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH1_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH1_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH1_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH1_0_EccErrCnt +#define UMCCH1_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH1_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH1_0_PerfMonCtlClk +#define UMCCH1_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH1_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH1_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH1_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH1_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH1_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH1_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH1_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH1_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH1_0_PerfMonCtrClk_Lo +#define UMCCH1_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtrClk_Hi +#define UMCCH1_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH1_0_PerfMonCtl1 +#define UMCCH1_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr1_Lo +#define UMCCH1_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr1_Hi +#define UMCCH1_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl2 +#define UMCCH1_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr2_Lo +#define UMCCH1_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr2_Hi +#define UMCCH1_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl3 +#define UMCCH1_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr3_Lo +#define UMCCH1_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr3_Hi +#define UMCCH1_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl4 +#define UMCCH1_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr4_Lo +#define UMCCH1_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr4_Hi +#define UMCCH1_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl5 +#define UMCCH1_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr5_Lo +#define UMCCH1_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr5_Hi +#define UMCCH1_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl6 +#define UMCCH1_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr6_Lo +#define UMCCH1_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr6_Hi +#define UMCCH1_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl7 +#define UMCCH1_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr7_Lo +#define UMCCH1_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr7_Hi +#define UMCCH1_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_0_PerfMonCtl8 +#define UMCCH1_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH1_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH1_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH1_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH1_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH1_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH1_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH1_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH1_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH1_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH1_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH1_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH1_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH1_0_PerfMonCtr8_Lo +#define UMCCH1_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_0_PerfMonCtr8_Hi +#define UMCCH1_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH1_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch2_umcchdec +//UMCCH2_0_BaseAddrCS0 +#define UMCCH2_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH2_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH2_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH2_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH2_0_AddrMaskCS01 +#define UMCCH2_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH2_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH2_0_AddrSelCS01 +#define UMCCH2_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH2_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH2_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH2_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH2_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH2_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH2_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH2_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH2_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH2_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH2_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH2_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH2_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH2_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH2_0_AddrHashBank0 +#define UMCCH2_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_AddrHashBank1 +#define UMCCH2_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_AddrHashBank2 +#define UMCCH2_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_AddrHashBank3 +#define UMCCH2_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_AddrHashBank4 +#define UMCCH2_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_AddrHashBank5 +#define UMCCH2_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH2_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH2_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH2_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH2_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH2_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH2_0_UMC_CONFIG +#define UMCCH2_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0 +#define UMCCH2_0_UMC_CONFIG__BurstLength__SHIFT 0x8 +#define UMCCH2_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa +#define UMCCH2_0_UMC_CONFIG__DramReady__SHIFT 0x1f +#define UMCCH2_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L +#define UMCCH2_0_UMC_CONFIG__BurstLength_MASK 0x00000300L +#define UMCCH2_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L +#define UMCCH2_0_UMC_CONFIG__DramReady_MASK 0x80000000L +//UMCCH2_0_EccCtrl +#define UMCCH2_0_EccCtrl__WrEccEn__SHIFT 0x0 +#define UMCCH2_0_EccCtrl__EccReplayEn__SHIFT 0x1 +#define UMCCH2_0_EccCtrl__UCFatalEn__SHIFT 0x8 +#define UMCCH2_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH2_0_EccCtrl__PoisonFatalDis__SHIFT 0xc +#define UMCCH2_0_EccCtrl__PoisonInhibit__SHIFT 0xd +#define UMCCH2_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH2_0_EccCtrl__EccReplayEn_MASK 0x00000002L +#define UMCCH2_0_EccCtrl__UCFatalEn_MASK 0x00000100L +#define UMCCH2_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH2_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L +#define UMCCH2_0_EccCtrl__PoisonInhibit_MASK 0x00002000L +//UMCCH2_0_UmcLocalCap +#define UMCCH2_0_UmcLocalCap__EccDis__SHIFT 0x0 +#define UMCCH2_0_UmcLocalCap__Spare__SHIFT 0x1 +#define UMCCH2_0_UmcLocalCap__WrDis__SHIFT 0x1f +#define UMCCH2_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH2_0_UmcLocalCap__Spare_MASK 0x0000003EL +#define UMCCH2_0_UmcLocalCap__WrDis_MASK 0x80000000L +//UMCCH2_0_EccErrCntSel +#define UMCCH2_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH2_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH2_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH2_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH2_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH2_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH2_0_EccErrCnt +#define UMCCH2_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH2_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH2_0_PerfMonCtlClk +#define UMCCH2_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH2_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH2_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH2_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH2_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH2_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH2_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH2_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH2_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH2_0_PerfMonCtrClk_Lo +#define UMCCH2_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtrClk_Hi +#define UMCCH2_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH2_0_PerfMonCtl1 +#define UMCCH2_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr1_Lo +#define UMCCH2_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr1_Hi +#define UMCCH2_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl2 +#define UMCCH2_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr2_Lo +#define UMCCH2_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr2_Hi +#define UMCCH2_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl3 +#define UMCCH2_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr3_Lo +#define UMCCH2_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr3_Hi +#define UMCCH2_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl4 +#define UMCCH2_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr4_Lo +#define UMCCH2_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr4_Hi +#define UMCCH2_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl5 +#define UMCCH2_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr5_Lo +#define UMCCH2_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr5_Hi +#define UMCCH2_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl6 +#define UMCCH2_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr6_Lo +#define UMCCH2_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr6_Hi +#define UMCCH2_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl7 +#define UMCCH2_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr7_Lo +#define UMCCH2_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr7_Hi +#define UMCCH2_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_0_PerfMonCtl8 +#define UMCCH2_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH2_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH2_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH2_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH2_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH2_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH2_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH2_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH2_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH2_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH2_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH2_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH2_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH2_0_PerfMonCtr8_Lo +#define UMCCH2_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_0_PerfMonCtr8_Hi +#define UMCCH2_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH2_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch3_umcchdec +//UMCCH3_0_BaseAddrCS0 +#define UMCCH3_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH3_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH3_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH3_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH3_0_AddrMaskCS01 +#define UMCCH3_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH3_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH3_0_AddrSelCS01 +#define UMCCH3_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH3_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH3_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH3_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH3_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH3_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH3_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH3_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH3_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH3_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH3_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH3_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH3_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH3_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH3_0_AddrHashBank0 +#define UMCCH3_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_AddrHashBank1 +#define UMCCH3_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_AddrHashBank2 +#define UMCCH3_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_AddrHashBank3 +#define UMCCH3_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_AddrHashBank4 +#define UMCCH3_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_AddrHashBank5 +#define UMCCH3_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH3_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH3_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH3_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH3_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH3_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH3_0_UMC_CONFIG +#define UMCCH3_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0 +#define UMCCH3_0_UMC_CONFIG__BurstLength__SHIFT 0x8 +#define UMCCH3_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa +#define UMCCH3_0_UMC_CONFIG__DramReady__SHIFT 0x1f +#define UMCCH3_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L +#define UMCCH3_0_UMC_CONFIG__BurstLength_MASK 0x00000300L +#define UMCCH3_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L +#define UMCCH3_0_UMC_CONFIG__DramReady_MASK 0x80000000L +//UMCCH3_0_EccCtrl +#define UMCCH3_0_EccCtrl__WrEccEn__SHIFT 0x0 +#define UMCCH3_0_EccCtrl__EccReplayEn__SHIFT 0x1 +#define UMCCH3_0_EccCtrl__UCFatalEn__SHIFT 0x8 +#define UMCCH3_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH3_0_EccCtrl__PoisonFatalDis__SHIFT 0xc +#define UMCCH3_0_EccCtrl__PoisonInhibit__SHIFT 0xd +#define UMCCH3_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH3_0_EccCtrl__EccReplayEn_MASK 0x00000002L +#define UMCCH3_0_EccCtrl__UCFatalEn_MASK 0x00000100L +#define UMCCH3_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH3_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L +#define UMCCH3_0_EccCtrl__PoisonInhibit_MASK 0x00002000L +//UMCCH3_0_UmcLocalCap +#define UMCCH3_0_UmcLocalCap__EccDis__SHIFT 0x0 +#define UMCCH3_0_UmcLocalCap__Spare__SHIFT 0x1 +#define UMCCH3_0_UmcLocalCap__WrDis__SHIFT 0x1f +#define UMCCH3_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH3_0_UmcLocalCap__Spare_MASK 0x0000003EL +#define UMCCH3_0_UmcLocalCap__WrDis_MASK 0x80000000L +//UMCCH3_0_EccErrCntSel +#define UMCCH3_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH3_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH3_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH3_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH3_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH3_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH3_0_EccErrCnt +#define UMCCH3_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH3_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH3_0_PerfMonCtlClk +#define UMCCH3_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH3_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH3_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH3_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH3_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH3_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH3_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH3_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH3_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH3_0_PerfMonCtrClk_Lo +#define UMCCH3_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtrClk_Hi +#define UMCCH3_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH3_0_PerfMonCtl1 +#define UMCCH3_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr1_Lo +#define UMCCH3_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr1_Hi +#define UMCCH3_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl2 +#define UMCCH3_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr2_Lo +#define UMCCH3_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr2_Hi +#define UMCCH3_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl3 +#define UMCCH3_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr3_Lo +#define UMCCH3_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr3_Hi +#define UMCCH3_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl4 +#define UMCCH3_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr4_Lo +#define UMCCH3_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr4_Hi +#define UMCCH3_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl5 +#define UMCCH3_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr5_Lo +#define UMCCH3_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr5_Hi +#define UMCCH3_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl6 +#define UMCCH3_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr6_Lo +#define UMCCH3_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr6_Hi +#define UMCCH3_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl7 +#define UMCCH3_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr7_Lo +#define UMCCH3_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr7_Hi +#define UMCCH3_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_0_PerfMonCtl8 +#define UMCCH3_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH3_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH3_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH3_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH3_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH3_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH3_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH3_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH3_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH3_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH3_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH3_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH3_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH3_0_PerfMonCtr8_Lo +#define UMCCH3_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_0_PerfMonCtr8_Hi +#define UMCCH3_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH3_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch4_umcchdec +//UMCCH4_0_BaseAddrCS0 +#define UMCCH4_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH4_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH4_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH4_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH4_0_AddrMaskCS01 +#define UMCCH4_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH4_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH4_0_AddrSelCS01 +#define UMCCH4_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH4_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH4_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH4_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH4_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH4_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH4_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH4_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH4_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH4_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH4_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH4_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH4_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH4_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH4_0_AddrHashBank0 +#define UMCCH4_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_AddrHashBank1 +#define UMCCH4_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_AddrHashBank2 +#define UMCCH4_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_AddrHashBank3 +#define UMCCH4_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_AddrHashBank4 +#define UMCCH4_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_AddrHashBank5 +#define UMCCH4_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH4_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH4_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH4_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH4_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH4_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH4_0_EccErrCntSel +#define UMCCH4_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH4_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH4_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH4_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH4_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH4_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH4_0_EccErrCnt +#define UMCCH4_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH4_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH4_0_PerfMonCtlClk +#define UMCCH4_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH4_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH4_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH4_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH4_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH4_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH4_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH4_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH4_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH4_0_PerfMonCtrClk_Lo +#define UMCCH4_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtrClk_Hi +#define UMCCH4_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH4_0_PerfMonCtl1 +#define UMCCH4_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr1_Lo +#define UMCCH4_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr1_Hi +#define UMCCH4_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl2 +#define UMCCH4_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr2_Lo +#define UMCCH4_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr2_Hi +#define UMCCH4_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl3 +#define UMCCH4_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr3_Lo +#define UMCCH4_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr3_Hi +#define UMCCH4_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl4 +#define UMCCH4_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr4_Lo +#define UMCCH4_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr4_Hi +#define UMCCH4_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl5 +#define UMCCH4_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr5_Lo +#define UMCCH4_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr5_Hi +#define UMCCH4_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl6 +#define UMCCH4_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr6_Lo +#define UMCCH4_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr6_Hi +#define UMCCH4_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl7 +#define UMCCH4_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr7_Lo +#define UMCCH4_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr7_Hi +#define UMCCH4_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_0_PerfMonCtl8 +#define UMCCH4_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH4_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH4_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH4_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH4_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH4_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH4_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH4_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH4_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH4_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH4_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH4_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH4_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH4_0_PerfMonCtr8_Lo +#define UMCCH4_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_0_PerfMonCtr8_Hi +#define UMCCH4_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH4_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch5_umcchdec +//UMCCH5_0_BaseAddrCS0 +#define UMCCH5_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH5_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH5_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH5_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH5_0_AddrMaskCS01 +#define UMCCH5_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH5_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH5_0_AddrSelCS01 +#define UMCCH5_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH5_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH5_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH5_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH5_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH5_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH5_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH5_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH5_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH5_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH5_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH5_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH5_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH5_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH5_0_AddrHashBank0 +#define UMCCH5_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_AddrHashBank1 +#define UMCCH5_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_AddrHashBank2 +#define UMCCH5_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_AddrHashBank3 +#define UMCCH5_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_AddrHashBank4 +#define UMCCH5_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_AddrHashBank5 +#define UMCCH5_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH5_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH5_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH5_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH5_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH5_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH5_0_EccErrCntSel +#define UMCCH5_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH5_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH5_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH5_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH5_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH5_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH5_0_EccErrCnt +#define UMCCH5_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH5_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH5_0_PerfMonCtlClk +#define UMCCH5_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH5_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH5_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH5_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH5_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH5_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH5_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH5_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH5_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH5_0_PerfMonCtrClk_Lo +#define UMCCH5_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtrClk_Hi +#define UMCCH5_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH5_0_PerfMonCtl1 +#define UMCCH5_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr1_Lo +#define UMCCH5_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr1_Hi +#define UMCCH5_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl2 +#define UMCCH5_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr2_Lo +#define UMCCH5_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr2_Hi +#define UMCCH5_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl3 +#define UMCCH5_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr3_Lo +#define UMCCH5_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr3_Hi +#define UMCCH5_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl4 +#define UMCCH5_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr4_Lo +#define UMCCH5_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr4_Hi +#define UMCCH5_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl5 +#define UMCCH5_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr5_Lo +#define UMCCH5_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr5_Hi +#define UMCCH5_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl6 +#define UMCCH5_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr6_Lo +#define UMCCH5_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr6_Hi +#define UMCCH5_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl7 +#define UMCCH5_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr7_Lo +#define UMCCH5_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr7_Hi +#define UMCCH5_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_0_PerfMonCtl8 +#define UMCCH5_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH5_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH5_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH5_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH5_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH5_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH5_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH5_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH5_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH5_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH5_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH5_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH5_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH5_0_PerfMonCtr8_Lo +#define UMCCH5_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_0_PerfMonCtr8_Hi +#define UMCCH5_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH5_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch6_umcchdec +//UMCCH6_0_BaseAddrCS0 +#define UMCCH6_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH6_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH6_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH6_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH6_0_AddrMaskCS01 +#define UMCCH6_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH6_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH6_0_AddrSelCS01 +#define UMCCH6_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH6_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH6_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH6_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH6_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH6_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH6_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH6_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH6_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH6_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH6_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH6_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH6_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH6_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH6_0_AddrHashBank0 +#define UMCCH6_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_AddrHashBank1 +#define UMCCH6_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_AddrHashBank2 +#define UMCCH6_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_AddrHashBank3 +#define UMCCH6_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_AddrHashBank4 +#define UMCCH6_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_AddrHashBank5 +#define UMCCH6_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH6_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH6_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH6_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH6_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH6_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH6_0_EccErrCntSel +#define UMCCH6_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH6_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH6_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH6_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH6_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH6_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH6_0_EccErrCnt +#define UMCCH6_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH6_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH6_0_PerfMonCtlClk +#define UMCCH6_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH6_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH6_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH6_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH6_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH6_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH6_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH6_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH6_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH6_0_PerfMonCtrClk_Lo +#define UMCCH6_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtrClk_Hi +#define UMCCH6_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH6_0_PerfMonCtl1 +#define UMCCH6_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr1_Lo +#define UMCCH6_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr1_Hi +#define UMCCH6_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl2 +#define UMCCH6_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr2_Lo +#define UMCCH6_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr2_Hi +#define UMCCH6_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl3 +#define UMCCH6_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr3_Lo +#define UMCCH6_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr3_Hi +#define UMCCH6_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl4 +#define UMCCH6_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr4_Lo +#define UMCCH6_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr4_Hi +#define UMCCH6_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl5 +#define UMCCH6_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr5_Lo +#define UMCCH6_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr5_Hi +#define UMCCH6_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl6 +#define UMCCH6_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr6_Lo +#define UMCCH6_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr6_Hi +#define UMCCH6_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl7 +#define UMCCH6_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr7_Lo +#define UMCCH6_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr7_Hi +#define UMCCH6_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_0_PerfMonCtl8 +#define UMCCH6_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH6_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH6_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH6_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH6_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH6_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH6_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH6_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH6_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH6_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH6_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH6_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH6_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH6_0_PerfMonCtr8_Lo +#define UMCCH6_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_0_PerfMonCtr8_Hi +#define UMCCH6_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH6_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc0_umcch7_umcchdec +//UMCCH7_0_BaseAddrCS0 +#define UMCCH7_0_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH7_0_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH7_0_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH7_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH7_0_AddrMaskCS01 +#define UMCCH7_0_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH7_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH7_0_AddrSelCS01 +#define UMCCH7_0_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH7_0_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH7_0_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH7_0_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH7_0_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH7_0_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH7_0_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH7_0_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH7_0_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH7_0_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH7_0_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH7_0_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH7_0_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH7_0_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH7_0_AddrHashBank0 +#define UMCCH7_0_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_AddrHashBank1 +#define UMCCH7_0_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_AddrHashBank2 +#define UMCCH7_0_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_AddrHashBank3 +#define UMCCH7_0_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_AddrHashBank4 +#define UMCCH7_0_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_AddrHashBank5 +#define UMCCH7_0_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH7_0_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH7_0_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH7_0_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH7_0_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH7_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH7_0_EccErrCntSel +#define UMCCH7_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH7_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH7_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH7_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH7_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH7_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH7_0_EccErrCnt +#define UMCCH7_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH7_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH7_0_PerfMonCtlClk +#define UMCCH7_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH7_0_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH7_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH7_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH7_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH7_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH7_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH7_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH7_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH7_0_PerfMonCtrClk_Lo +#define UMCCH7_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtrClk_Hi +#define UMCCH7_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH7_0_PerfMonCtl1 +#define UMCCH7_0_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr1_Lo +#define UMCCH7_0_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr1_Hi +#define UMCCH7_0_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl2 +#define UMCCH7_0_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr2_Lo +#define UMCCH7_0_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr2_Hi +#define UMCCH7_0_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl3 +#define UMCCH7_0_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr3_Lo +#define UMCCH7_0_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr3_Hi +#define UMCCH7_0_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl4 +#define UMCCH7_0_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr4_Lo +#define UMCCH7_0_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr4_Hi +#define UMCCH7_0_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl5 +#define UMCCH7_0_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr5_Lo +#define UMCCH7_0_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr5_Hi +#define UMCCH7_0_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl6 +#define UMCCH7_0_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr6_Lo +#define UMCCH7_0_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr6_Hi +#define UMCCH7_0_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl7 +#define UMCCH7_0_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr7_Lo +#define UMCCH7_0_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr7_Hi +#define UMCCH7_0_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_0_PerfMonCtl8 +#define UMCCH7_0_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH7_0_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH7_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH7_0_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH7_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH7_0_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH7_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH7_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH7_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH7_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH7_0_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH7_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH7_0_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH7_0_PerfMonCtr8_Lo +#define UMCCH7_0_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_0_PerfMonCtr8_Hi +#define UMCCH7_0_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH7_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch0_umcchdec +//UMCCH0_1_BaseAddrCS0 +#define UMCCH0_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH0_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH0_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH0_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH0_1_AddrMaskCS01 +#define UMCCH0_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH0_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH0_1_AddrSelCS01 +#define UMCCH0_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH0_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH0_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH0_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH0_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH0_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH0_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH0_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH0_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH0_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH0_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH0_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH0_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH0_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH0_1_AddrHashBank0 +#define UMCCH0_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_AddrHashBank1 +#define UMCCH0_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_AddrHashBank2 +#define UMCCH0_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_AddrHashBank3 +#define UMCCH0_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_AddrHashBank4 +#define UMCCH0_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_AddrHashBank5 +#define UMCCH0_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH0_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH0_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH0_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH0_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH0_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH0_1_EccErrCntSel +#define UMCCH0_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH0_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH0_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH0_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH0_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH0_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH0_1_EccErrCnt +#define UMCCH0_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH0_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH0_1_PerfMonCtlClk +#define UMCCH0_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH0_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH0_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH0_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH0_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH0_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH0_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH0_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH0_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH0_1_PerfMonCtrClk_Lo +#define UMCCH0_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtrClk_Hi +#define UMCCH0_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH0_1_PerfMonCtl1 +#define UMCCH0_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr1_Lo +#define UMCCH0_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr1_Hi +#define UMCCH0_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl2 +#define UMCCH0_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr2_Lo +#define UMCCH0_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr2_Hi +#define UMCCH0_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl3 +#define UMCCH0_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr3_Lo +#define UMCCH0_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr3_Hi +#define UMCCH0_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl4 +#define UMCCH0_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr4_Lo +#define UMCCH0_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr4_Hi +#define UMCCH0_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl5 +#define UMCCH0_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr5_Lo +#define UMCCH0_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr5_Hi +#define UMCCH0_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl6 +#define UMCCH0_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr6_Lo +#define UMCCH0_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr6_Hi +#define UMCCH0_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl7 +#define UMCCH0_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr7_Lo +#define UMCCH0_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr7_Hi +#define UMCCH0_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_1_PerfMonCtl8 +#define UMCCH0_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH0_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH0_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH0_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH0_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH0_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH0_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH0_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH0_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH0_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH0_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH0_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH0_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH0_1_PerfMonCtr8_Lo +#define UMCCH0_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_1_PerfMonCtr8_Hi +#define UMCCH0_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH0_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch1_umcchdec +//UMCCH1_1_BaseAddrCS0 +#define UMCCH1_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH1_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH1_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH1_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH1_1_AddrMaskCS01 +#define UMCCH1_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH1_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH1_1_AddrSelCS01 +#define UMCCH1_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH1_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH1_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH1_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH1_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH1_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH1_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH1_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH1_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH1_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH1_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH1_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH1_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH1_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH1_1_AddrHashBank0 +#define UMCCH1_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_AddrHashBank1 +#define UMCCH1_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_AddrHashBank2 +#define UMCCH1_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_AddrHashBank3 +#define UMCCH1_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_AddrHashBank4 +#define UMCCH1_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_AddrHashBank5 +#define UMCCH1_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH1_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH1_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH1_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH1_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH1_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH1_1_EccErrCntSel +#define UMCCH1_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH1_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH1_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH1_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH1_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH1_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH1_1_EccErrCnt +#define UMCCH1_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH1_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH1_1_PerfMonCtlClk +#define UMCCH1_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH1_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH1_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH1_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH1_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH1_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH1_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH1_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH1_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH1_1_PerfMonCtrClk_Lo +#define UMCCH1_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtrClk_Hi +#define UMCCH1_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH1_1_PerfMonCtl1 +#define UMCCH1_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr1_Lo +#define UMCCH1_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr1_Hi +#define UMCCH1_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl2 +#define UMCCH1_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr2_Lo +#define UMCCH1_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr2_Hi +#define UMCCH1_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl3 +#define UMCCH1_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr3_Lo +#define UMCCH1_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr3_Hi +#define UMCCH1_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl4 +#define UMCCH1_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr4_Lo +#define UMCCH1_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr4_Hi +#define UMCCH1_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl5 +#define UMCCH1_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr5_Lo +#define UMCCH1_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr5_Hi +#define UMCCH1_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl6 +#define UMCCH1_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr6_Lo +#define UMCCH1_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr6_Hi +#define UMCCH1_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl7 +#define UMCCH1_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr7_Lo +#define UMCCH1_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr7_Hi +#define UMCCH1_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_1_PerfMonCtl8 +#define UMCCH1_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH1_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH1_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH1_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH1_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH1_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH1_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH1_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH1_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH1_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH1_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH1_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH1_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH1_1_PerfMonCtr8_Lo +#define UMCCH1_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_1_PerfMonCtr8_Hi +#define UMCCH1_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH1_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch2_umcchdec +//UMCCH2_1_BaseAddrCS0 +#define UMCCH2_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH2_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH2_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH2_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH2_1_AddrMaskCS01 +#define UMCCH2_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH2_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH2_1_AddrSelCS01 +#define UMCCH2_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH2_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH2_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH2_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH2_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH2_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH2_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH2_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH2_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH2_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH2_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH2_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH2_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH2_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH2_1_AddrHashBank0 +#define UMCCH2_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_AddrHashBank1 +#define UMCCH2_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_AddrHashBank2 +#define UMCCH2_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_AddrHashBank3 +#define UMCCH2_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_AddrHashBank4 +#define UMCCH2_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_AddrHashBank5 +#define UMCCH2_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH2_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH2_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH2_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH2_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH2_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH2_1_EccErrCntSel +#define UMCCH2_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH2_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH2_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH2_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH2_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH2_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH2_1_EccErrCnt +#define UMCCH2_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH2_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH2_1_PerfMonCtlClk +#define UMCCH2_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH2_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH2_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH2_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH2_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH2_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH2_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH2_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH2_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH2_1_PerfMonCtrClk_Lo +#define UMCCH2_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtrClk_Hi +#define UMCCH2_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH2_1_PerfMonCtl1 +#define UMCCH2_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr1_Lo +#define UMCCH2_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr1_Hi +#define UMCCH2_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl2 +#define UMCCH2_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr2_Lo +#define UMCCH2_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr2_Hi +#define UMCCH2_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl3 +#define UMCCH2_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr3_Lo +#define UMCCH2_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr3_Hi +#define UMCCH2_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl4 +#define UMCCH2_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr4_Lo +#define UMCCH2_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr4_Hi +#define UMCCH2_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl5 +#define UMCCH2_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr5_Lo +#define UMCCH2_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr5_Hi +#define UMCCH2_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl6 +#define UMCCH2_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr6_Lo +#define UMCCH2_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr6_Hi +#define UMCCH2_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl7 +#define UMCCH2_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr7_Lo +#define UMCCH2_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr7_Hi +#define UMCCH2_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_1_PerfMonCtl8 +#define UMCCH2_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH2_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH2_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH2_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH2_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH2_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH2_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH2_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH2_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH2_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH2_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH2_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH2_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH2_1_PerfMonCtr8_Lo +#define UMCCH2_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_1_PerfMonCtr8_Hi +#define UMCCH2_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH2_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch3_umcchdec +//UMCCH3_1_BaseAddrCS0 +#define UMCCH3_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH3_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH3_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH3_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH3_1_AddrMaskCS01 +#define UMCCH3_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH3_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH3_1_AddrSelCS01 +#define UMCCH3_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH3_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH3_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH3_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH3_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH3_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH3_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH3_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH3_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH3_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH3_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH3_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH3_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH3_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH3_1_AddrHashBank0 +#define UMCCH3_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_AddrHashBank1 +#define UMCCH3_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_AddrHashBank2 +#define UMCCH3_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_AddrHashBank3 +#define UMCCH3_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_AddrHashBank4 +#define UMCCH3_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_AddrHashBank5 +#define UMCCH3_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH3_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH3_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH3_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH3_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH3_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH3_1_EccErrCntSel +#define UMCCH3_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH3_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH3_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH3_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH3_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH3_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH3_1_EccErrCnt +#define UMCCH3_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH3_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH3_1_PerfMonCtlClk +#define UMCCH3_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH3_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH3_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH3_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH3_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH3_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH3_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH3_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH3_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH3_1_PerfMonCtrClk_Lo +#define UMCCH3_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtrClk_Hi +#define UMCCH3_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH3_1_PerfMonCtl1 +#define UMCCH3_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr1_Lo +#define UMCCH3_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr1_Hi +#define UMCCH3_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl2 +#define UMCCH3_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr2_Lo +#define UMCCH3_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr2_Hi +#define UMCCH3_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl3 +#define UMCCH3_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr3_Lo +#define UMCCH3_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr3_Hi +#define UMCCH3_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl4 +#define UMCCH3_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr4_Lo +#define UMCCH3_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr4_Hi +#define UMCCH3_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl5 +#define UMCCH3_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr5_Lo +#define UMCCH3_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr5_Hi +#define UMCCH3_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl6 +#define UMCCH3_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr6_Lo +#define UMCCH3_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr6_Hi +#define UMCCH3_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl7 +#define UMCCH3_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr7_Lo +#define UMCCH3_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr7_Hi +#define UMCCH3_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_1_PerfMonCtl8 +#define UMCCH3_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH3_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH3_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH3_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH3_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH3_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH3_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH3_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH3_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH3_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH3_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH3_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH3_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH3_1_PerfMonCtr8_Lo +#define UMCCH3_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_1_PerfMonCtr8_Hi +#define UMCCH3_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH3_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch4_umcchdec +//UMCCH4_1_BaseAddrCS0 +#define UMCCH4_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH4_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH4_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH4_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH4_1_AddrMaskCS01 +#define UMCCH4_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH4_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH4_1_AddrSelCS01 +#define UMCCH4_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH4_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH4_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH4_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH4_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH4_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH4_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH4_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH4_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH4_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH4_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH4_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH4_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH4_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH4_1_AddrHashBank0 +#define UMCCH4_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_AddrHashBank1 +#define UMCCH4_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_AddrHashBank2 +#define UMCCH4_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_AddrHashBank3 +#define UMCCH4_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_AddrHashBank4 +#define UMCCH4_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_AddrHashBank5 +#define UMCCH4_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH4_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH4_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH4_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH4_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH4_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH4_1_EccErrCntSel +#define UMCCH4_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH4_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH4_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH4_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH4_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH4_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH4_1_EccErrCnt +#define UMCCH4_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH4_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH4_1_PerfMonCtlClk +#define UMCCH4_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH4_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH4_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH4_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH4_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH4_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH4_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH4_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH4_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH4_1_PerfMonCtrClk_Lo +#define UMCCH4_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtrClk_Hi +#define UMCCH4_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH4_1_PerfMonCtl1 +#define UMCCH4_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr1_Lo +#define UMCCH4_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr1_Hi +#define UMCCH4_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl2 +#define UMCCH4_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr2_Lo +#define UMCCH4_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr2_Hi +#define UMCCH4_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl3 +#define UMCCH4_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr3_Lo +#define UMCCH4_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr3_Hi +#define UMCCH4_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl4 +#define UMCCH4_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr4_Lo +#define UMCCH4_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr4_Hi +#define UMCCH4_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl5 +#define UMCCH4_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr5_Lo +#define UMCCH4_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr5_Hi +#define UMCCH4_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl6 +#define UMCCH4_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr6_Lo +#define UMCCH4_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr6_Hi +#define UMCCH4_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl7 +#define UMCCH4_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr7_Lo +#define UMCCH4_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr7_Hi +#define UMCCH4_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_1_PerfMonCtl8 +#define UMCCH4_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH4_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH4_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH4_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH4_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH4_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH4_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH4_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH4_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH4_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH4_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH4_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH4_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH4_1_PerfMonCtr8_Lo +#define UMCCH4_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_1_PerfMonCtr8_Hi +#define UMCCH4_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH4_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch5_umcchdec +//UMCCH5_1_BaseAddrCS0 +#define UMCCH5_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH5_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH5_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH5_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH5_1_AddrMaskCS01 +#define UMCCH5_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH5_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH5_1_AddrSelCS01 +#define UMCCH5_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH5_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH5_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH5_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH5_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH5_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH5_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH5_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH5_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH5_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH5_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH5_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH5_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH5_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH5_1_AddrHashBank0 +#define UMCCH5_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_AddrHashBank1 +#define UMCCH5_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_AddrHashBank2 +#define UMCCH5_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_AddrHashBank3 +#define UMCCH5_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_AddrHashBank4 +#define UMCCH5_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_AddrHashBank5 +#define UMCCH5_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH5_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH5_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH5_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH5_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH5_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH5_1_EccErrCntSel +#define UMCCH5_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH5_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH5_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH5_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH5_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH5_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH5_1_EccErrCnt +#define UMCCH5_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH5_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH5_1_PerfMonCtlClk +#define UMCCH5_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH5_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH5_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH5_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH5_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH5_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH5_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH5_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH5_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH5_1_PerfMonCtrClk_Lo +#define UMCCH5_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtrClk_Hi +#define UMCCH5_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH5_1_PerfMonCtl1 +#define UMCCH5_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr1_Lo +#define UMCCH5_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr1_Hi +#define UMCCH5_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl2 +#define UMCCH5_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr2_Lo +#define UMCCH5_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr2_Hi +#define UMCCH5_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl3 +#define UMCCH5_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr3_Lo +#define UMCCH5_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr3_Hi +#define UMCCH5_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl4 +#define UMCCH5_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr4_Lo +#define UMCCH5_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr4_Hi +#define UMCCH5_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl5 +#define UMCCH5_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr5_Lo +#define UMCCH5_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr5_Hi +#define UMCCH5_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl6 +#define UMCCH5_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr6_Lo +#define UMCCH5_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr6_Hi +#define UMCCH5_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl7 +#define UMCCH5_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr7_Lo +#define UMCCH5_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr7_Hi +#define UMCCH5_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_1_PerfMonCtl8 +#define UMCCH5_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH5_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH5_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH5_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH5_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH5_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH5_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH5_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH5_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH5_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH5_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH5_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH5_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH5_1_PerfMonCtr8_Lo +#define UMCCH5_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_1_PerfMonCtr8_Hi +#define UMCCH5_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH5_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch6_umcchdec +//UMCCH6_1_BaseAddrCS0 +#define UMCCH6_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH6_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH6_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH6_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH6_1_AddrMaskCS01 +#define UMCCH6_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH6_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH6_1_AddrSelCS01 +#define UMCCH6_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH6_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH6_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH6_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH6_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH6_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH6_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH6_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH6_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH6_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH6_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH6_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH6_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH6_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH6_1_AddrHashBank0 +#define UMCCH6_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_AddrHashBank1 +#define UMCCH6_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_AddrHashBank2 +#define UMCCH6_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_AddrHashBank3 +#define UMCCH6_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_AddrHashBank4 +#define UMCCH6_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_AddrHashBank5 +#define UMCCH6_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH6_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH6_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH6_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH6_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH6_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH6_1_EccErrCntSel +#define UMCCH6_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH6_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH6_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH6_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH6_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH6_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH6_1_EccErrCnt +#define UMCCH6_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH6_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH6_1_PerfMonCtlClk +#define UMCCH6_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH6_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH6_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH6_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH6_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH6_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH6_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH6_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH6_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH6_1_PerfMonCtrClk_Lo +#define UMCCH6_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtrClk_Hi +#define UMCCH6_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH6_1_PerfMonCtl1 +#define UMCCH6_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr1_Lo +#define UMCCH6_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr1_Hi +#define UMCCH6_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl2 +#define UMCCH6_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr2_Lo +#define UMCCH6_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr2_Hi +#define UMCCH6_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl3 +#define UMCCH6_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr3_Lo +#define UMCCH6_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr3_Hi +#define UMCCH6_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl4 +#define UMCCH6_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr4_Lo +#define UMCCH6_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr4_Hi +#define UMCCH6_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl5 +#define UMCCH6_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr5_Lo +#define UMCCH6_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr5_Hi +#define UMCCH6_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl6 +#define UMCCH6_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr6_Lo +#define UMCCH6_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr6_Hi +#define UMCCH6_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl7 +#define UMCCH6_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr7_Lo +#define UMCCH6_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr7_Hi +#define UMCCH6_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_1_PerfMonCtl8 +#define UMCCH6_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH6_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH6_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH6_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH6_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH6_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH6_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH6_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH6_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH6_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH6_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH6_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH6_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH6_1_PerfMonCtr8_Lo +#define UMCCH6_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_1_PerfMonCtr8_Hi +#define UMCCH6_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH6_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc1_umcch7_umcchdec +//UMCCH7_1_BaseAddrCS0 +#define UMCCH7_1_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH7_1_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH7_1_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH7_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH7_1_AddrMaskCS01 +#define UMCCH7_1_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH7_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH7_1_AddrSelCS01 +#define UMCCH7_1_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH7_1_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH7_1_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH7_1_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH7_1_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH7_1_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH7_1_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH7_1_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH7_1_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH7_1_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH7_1_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH7_1_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH7_1_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH7_1_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH7_1_AddrHashBank0 +#define UMCCH7_1_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_AddrHashBank1 +#define UMCCH7_1_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_AddrHashBank2 +#define UMCCH7_1_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_AddrHashBank3 +#define UMCCH7_1_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_AddrHashBank4 +#define UMCCH7_1_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_AddrHashBank5 +#define UMCCH7_1_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH7_1_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH7_1_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH7_1_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH7_1_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH7_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH7_1_EccErrCntSel +#define UMCCH7_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH7_1_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH7_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH7_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH7_1_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH7_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH7_1_EccErrCnt +#define UMCCH7_1_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH7_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH7_1_PerfMonCtlClk +#define UMCCH7_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH7_1_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH7_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH7_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH7_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH7_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH7_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH7_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH7_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH7_1_PerfMonCtrClk_Lo +#define UMCCH7_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtrClk_Hi +#define UMCCH7_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH7_1_PerfMonCtl1 +#define UMCCH7_1_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr1_Lo +#define UMCCH7_1_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr1_Hi +#define UMCCH7_1_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl2 +#define UMCCH7_1_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr2_Lo +#define UMCCH7_1_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr2_Hi +#define UMCCH7_1_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl3 +#define UMCCH7_1_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr3_Lo +#define UMCCH7_1_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr3_Hi +#define UMCCH7_1_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl4 +#define UMCCH7_1_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr4_Lo +#define UMCCH7_1_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr4_Hi +#define UMCCH7_1_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl5 +#define UMCCH7_1_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr5_Lo +#define UMCCH7_1_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr5_Hi +#define UMCCH7_1_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl6 +#define UMCCH7_1_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr6_Lo +#define UMCCH7_1_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr6_Hi +#define UMCCH7_1_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl7 +#define UMCCH7_1_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr7_Lo +#define UMCCH7_1_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr7_Hi +#define UMCCH7_1_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_1_PerfMonCtl8 +#define UMCCH7_1_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH7_1_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH7_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH7_1_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH7_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH7_1_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH7_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH7_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH7_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH7_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH7_1_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH7_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH7_1_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH7_1_PerfMonCtr8_Lo +#define UMCCH7_1_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_1_PerfMonCtr8_Hi +#define UMCCH7_1_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH7_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch0_umcchdec +//UMCCH0_2_BaseAddrCS0 +#define UMCCH0_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH0_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH0_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH0_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH0_2_AddrMaskCS01 +#define UMCCH0_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH0_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH0_2_AddrSelCS01 +#define UMCCH0_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH0_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH0_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH0_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH0_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH0_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH0_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH0_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH0_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH0_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH0_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH0_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH0_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH0_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH0_2_AddrHashBank0 +#define UMCCH0_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_AddrHashBank1 +#define UMCCH0_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_AddrHashBank2 +#define UMCCH0_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_AddrHashBank3 +#define UMCCH0_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_AddrHashBank4 +#define UMCCH0_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_AddrHashBank5 +#define UMCCH0_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH0_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH0_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH0_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH0_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH0_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH0_2_EccErrCntSel +#define UMCCH0_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH0_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH0_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH0_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH0_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH0_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH0_2_EccErrCnt +#define UMCCH0_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH0_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH0_2_PerfMonCtlClk +#define UMCCH0_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH0_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH0_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH0_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH0_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH0_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH0_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH0_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH0_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH0_2_PerfMonCtrClk_Lo +#define UMCCH0_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtrClk_Hi +#define UMCCH0_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH0_2_PerfMonCtl1 +#define UMCCH0_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr1_Lo +#define UMCCH0_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr1_Hi +#define UMCCH0_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl2 +#define UMCCH0_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr2_Lo +#define UMCCH0_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr2_Hi +#define UMCCH0_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl3 +#define UMCCH0_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr3_Lo +#define UMCCH0_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr3_Hi +#define UMCCH0_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl4 +#define UMCCH0_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr4_Lo +#define UMCCH0_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr4_Hi +#define UMCCH0_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl5 +#define UMCCH0_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr5_Lo +#define UMCCH0_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr5_Hi +#define UMCCH0_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl6 +#define UMCCH0_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr6_Lo +#define UMCCH0_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr6_Hi +#define UMCCH0_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl7 +#define UMCCH0_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr7_Lo +#define UMCCH0_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr7_Hi +#define UMCCH0_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_2_PerfMonCtl8 +#define UMCCH0_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH0_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH0_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH0_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH0_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH0_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH0_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH0_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH0_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH0_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH0_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH0_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH0_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH0_2_PerfMonCtr8_Lo +#define UMCCH0_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_2_PerfMonCtr8_Hi +#define UMCCH0_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH0_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch1_umcchdec +//UMCCH1_2_BaseAddrCS0 +#define UMCCH1_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH1_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH1_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH1_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH1_2_AddrMaskCS01 +#define UMCCH1_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH1_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH1_2_AddrSelCS01 +#define UMCCH1_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH1_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH1_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH1_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH1_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH1_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH1_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH1_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH1_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH1_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH1_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH1_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH1_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH1_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH1_2_AddrHashBank0 +#define UMCCH1_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_AddrHashBank1 +#define UMCCH1_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_AddrHashBank2 +#define UMCCH1_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_AddrHashBank3 +#define UMCCH1_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_AddrHashBank4 +#define UMCCH1_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_AddrHashBank5 +#define UMCCH1_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH1_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH1_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH1_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH1_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH1_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH1_2_EccErrCntSel +#define UMCCH1_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH1_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH1_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH1_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH1_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH1_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH1_2_EccErrCnt +#define UMCCH1_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH1_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH1_2_PerfMonCtlClk +#define UMCCH1_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH1_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH1_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH1_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH1_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH1_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH1_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH1_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH1_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH1_2_PerfMonCtrClk_Lo +#define UMCCH1_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtrClk_Hi +#define UMCCH1_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH1_2_PerfMonCtl1 +#define UMCCH1_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr1_Lo +#define UMCCH1_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr1_Hi +#define UMCCH1_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl2 +#define UMCCH1_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr2_Lo +#define UMCCH1_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr2_Hi +#define UMCCH1_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl3 +#define UMCCH1_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr3_Lo +#define UMCCH1_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr3_Hi +#define UMCCH1_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl4 +#define UMCCH1_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr4_Lo +#define UMCCH1_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr4_Hi +#define UMCCH1_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl5 +#define UMCCH1_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr5_Lo +#define UMCCH1_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr5_Hi +#define UMCCH1_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl6 +#define UMCCH1_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr6_Lo +#define UMCCH1_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr6_Hi +#define UMCCH1_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl7 +#define UMCCH1_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr7_Lo +#define UMCCH1_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr7_Hi +#define UMCCH1_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_2_PerfMonCtl8 +#define UMCCH1_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH1_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH1_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH1_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH1_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH1_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH1_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH1_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH1_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH1_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH1_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH1_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH1_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH1_2_PerfMonCtr8_Lo +#define UMCCH1_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_2_PerfMonCtr8_Hi +#define UMCCH1_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH1_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch2_umcchdec +//UMCCH2_2_BaseAddrCS0 +#define UMCCH2_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH2_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH2_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH2_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH2_2_AddrMaskCS01 +#define UMCCH2_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH2_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH2_2_AddrSelCS01 +#define UMCCH2_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH2_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH2_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH2_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH2_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH2_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH2_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH2_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH2_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH2_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH2_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH2_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH2_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH2_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH2_2_AddrHashBank0 +#define UMCCH2_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_AddrHashBank1 +#define UMCCH2_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_AddrHashBank2 +#define UMCCH2_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_AddrHashBank3 +#define UMCCH2_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_AddrHashBank4 +#define UMCCH2_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_AddrHashBank5 +#define UMCCH2_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH2_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH2_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH2_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH2_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH2_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH2_2_EccErrCntSel +#define UMCCH2_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH2_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH2_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH2_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH2_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH2_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH2_2_EccErrCnt +#define UMCCH2_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH2_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH2_2_PerfMonCtlClk +#define UMCCH2_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH2_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH2_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH2_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH2_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH2_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH2_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH2_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH2_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH2_2_PerfMonCtrClk_Lo +#define UMCCH2_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtrClk_Hi +#define UMCCH2_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH2_2_PerfMonCtl1 +#define UMCCH2_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr1_Lo +#define UMCCH2_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr1_Hi +#define UMCCH2_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl2 +#define UMCCH2_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr2_Lo +#define UMCCH2_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr2_Hi +#define UMCCH2_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl3 +#define UMCCH2_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr3_Lo +#define UMCCH2_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr3_Hi +#define UMCCH2_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl4 +#define UMCCH2_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr4_Lo +#define UMCCH2_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr4_Hi +#define UMCCH2_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl5 +#define UMCCH2_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr5_Lo +#define UMCCH2_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr5_Hi +#define UMCCH2_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl6 +#define UMCCH2_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr6_Lo +#define UMCCH2_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr6_Hi +#define UMCCH2_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl7 +#define UMCCH2_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr7_Lo +#define UMCCH2_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr7_Hi +#define UMCCH2_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_2_PerfMonCtl8 +#define UMCCH2_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH2_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH2_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH2_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH2_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH2_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH2_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH2_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH2_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH2_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH2_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH2_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH2_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH2_2_PerfMonCtr8_Lo +#define UMCCH2_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_2_PerfMonCtr8_Hi +#define UMCCH2_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH2_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch3_umcchdec +//UMCCH3_2_BaseAddrCS0 +#define UMCCH3_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH3_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH3_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH3_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH3_2_AddrMaskCS01 +#define UMCCH3_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH3_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH3_2_AddrSelCS01 +#define UMCCH3_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH3_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH3_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH3_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH3_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH3_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH3_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH3_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH3_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH3_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH3_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH3_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH3_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH3_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH3_2_AddrHashBank0 +#define UMCCH3_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_AddrHashBank1 +#define UMCCH3_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_AddrHashBank2 +#define UMCCH3_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_AddrHashBank3 +#define UMCCH3_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_AddrHashBank4 +#define UMCCH3_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_AddrHashBank5 +#define UMCCH3_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH3_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH3_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH3_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH3_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH3_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH3_2_EccErrCntSel +#define UMCCH3_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH3_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH3_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH3_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH3_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH3_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH3_2_EccErrCnt +#define UMCCH3_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH3_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH3_2_PerfMonCtlClk +#define UMCCH3_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH3_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH3_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH3_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH3_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH3_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH3_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH3_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH3_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH3_2_PerfMonCtrClk_Lo +#define UMCCH3_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtrClk_Hi +#define UMCCH3_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH3_2_PerfMonCtl1 +#define UMCCH3_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr1_Lo +#define UMCCH3_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr1_Hi +#define UMCCH3_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl2 +#define UMCCH3_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr2_Lo +#define UMCCH3_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr2_Hi +#define UMCCH3_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl3 +#define UMCCH3_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr3_Lo +#define UMCCH3_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr3_Hi +#define UMCCH3_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl4 +#define UMCCH3_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr4_Lo +#define UMCCH3_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr4_Hi +#define UMCCH3_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl5 +#define UMCCH3_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr5_Lo +#define UMCCH3_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr5_Hi +#define UMCCH3_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl6 +#define UMCCH3_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr6_Lo +#define UMCCH3_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr6_Hi +#define UMCCH3_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl7 +#define UMCCH3_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr7_Lo +#define UMCCH3_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr7_Hi +#define UMCCH3_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_2_PerfMonCtl8 +#define UMCCH3_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH3_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH3_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH3_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH3_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH3_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH3_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH3_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH3_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH3_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH3_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH3_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH3_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH3_2_PerfMonCtr8_Lo +#define UMCCH3_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_2_PerfMonCtr8_Hi +#define UMCCH3_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH3_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch4_umcchdec +//UMCCH4_2_BaseAddrCS0 +#define UMCCH4_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH4_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH4_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH4_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH4_2_AddrMaskCS01 +#define UMCCH4_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH4_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH4_2_AddrSelCS01 +#define UMCCH4_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH4_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH4_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH4_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH4_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH4_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH4_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH4_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH4_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH4_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH4_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH4_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH4_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH4_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH4_2_AddrHashBank0 +#define UMCCH4_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_AddrHashBank1 +#define UMCCH4_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_AddrHashBank2 +#define UMCCH4_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_AddrHashBank3 +#define UMCCH4_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_AddrHashBank4 +#define UMCCH4_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_AddrHashBank5 +#define UMCCH4_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH4_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH4_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH4_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH4_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH4_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH4_2_EccErrCntSel +#define UMCCH4_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH4_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH4_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH4_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH4_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH4_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH4_2_EccErrCnt +#define UMCCH4_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH4_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH4_2_PerfMonCtlClk +#define UMCCH4_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH4_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH4_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH4_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH4_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH4_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH4_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH4_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH4_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH4_2_PerfMonCtrClk_Lo +#define UMCCH4_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtrClk_Hi +#define UMCCH4_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH4_2_PerfMonCtl1 +#define UMCCH4_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr1_Lo +#define UMCCH4_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr1_Hi +#define UMCCH4_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl2 +#define UMCCH4_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr2_Lo +#define UMCCH4_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr2_Hi +#define UMCCH4_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl3 +#define UMCCH4_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr3_Lo +#define UMCCH4_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr3_Hi +#define UMCCH4_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl4 +#define UMCCH4_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr4_Lo +#define UMCCH4_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr4_Hi +#define UMCCH4_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl5 +#define UMCCH4_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr5_Lo +#define UMCCH4_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr5_Hi +#define UMCCH4_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl6 +#define UMCCH4_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr6_Lo +#define UMCCH4_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr6_Hi +#define UMCCH4_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl7 +#define UMCCH4_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr7_Lo +#define UMCCH4_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr7_Hi +#define UMCCH4_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_2_PerfMonCtl8 +#define UMCCH4_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH4_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH4_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH4_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH4_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH4_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH4_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH4_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH4_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH4_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH4_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH4_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH4_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH4_2_PerfMonCtr8_Lo +#define UMCCH4_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_2_PerfMonCtr8_Hi +#define UMCCH4_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH4_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch5_umcchdec +//UMCCH5_2_BaseAddrCS0 +#define UMCCH5_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH5_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH5_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH5_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH5_2_AddrMaskCS01 +#define UMCCH5_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH5_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH5_2_AddrSelCS01 +#define UMCCH5_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH5_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH5_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH5_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH5_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH5_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH5_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH5_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH5_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH5_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH5_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH5_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH5_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH5_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH5_2_AddrHashBank0 +#define UMCCH5_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_AddrHashBank1 +#define UMCCH5_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_AddrHashBank2 +#define UMCCH5_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_AddrHashBank3 +#define UMCCH5_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_AddrHashBank4 +#define UMCCH5_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_AddrHashBank5 +#define UMCCH5_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH5_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH5_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH5_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH5_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH5_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH5_2_EccErrCntSel +#define UMCCH5_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH5_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH5_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH5_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH5_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH5_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH5_2_EccErrCnt +#define UMCCH5_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH5_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH5_2_PerfMonCtlClk +#define UMCCH5_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH5_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH5_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH5_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH5_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH5_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH5_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH5_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH5_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH5_2_PerfMonCtrClk_Lo +#define UMCCH5_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtrClk_Hi +#define UMCCH5_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH5_2_PerfMonCtl1 +#define UMCCH5_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr1_Lo +#define UMCCH5_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr1_Hi +#define UMCCH5_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl2 +#define UMCCH5_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr2_Lo +#define UMCCH5_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr2_Hi +#define UMCCH5_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl3 +#define UMCCH5_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr3_Lo +#define UMCCH5_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr3_Hi +#define UMCCH5_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl4 +#define UMCCH5_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr4_Lo +#define UMCCH5_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr4_Hi +#define UMCCH5_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl5 +#define UMCCH5_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr5_Lo +#define UMCCH5_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr5_Hi +#define UMCCH5_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl6 +#define UMCCH5_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr6_Lo +#define UMCCH5_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr6_Hi +#define UMCCH5_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl7 +#define UMCCH5_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr7_Lo +#define UMCCH5_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr7_Hi +#define UMCCH5_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_2_PerfMonCtl8 +#define UMCCH5_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH5_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH5_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH5_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH5_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH5_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH5_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH5_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH5_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH5_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH5_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH5_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH5_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH5_2_PerfMonCtr8_Lo +#define UMCCH5_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_2_PerfMonCtr8_Hi +#define UMCCH5_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH5_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch6_umcchdec +//UMCCH6_2_BaseAddrCS0 +#define UMCCH6_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH6_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH6_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH6_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH6_2_AddrMaskCS01 +#define UMCCH6_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH6_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH6_2_AddrSelCS01 +#define UMCCH6_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH6_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH6_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH6_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH6_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH6_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH6_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH6_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH6_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH6_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH6_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH6_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH6_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH6_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH6_2_AddrHashBank0 +#define UMCCH6_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_AddrHashBank1 +#define UMCCH6_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_AddrHashBank2 +#define UMCCH6_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_AddrHashBank3 +#define UMCCH6_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_AddrHashBank4 +#define UMCCH6_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_AddrHashBank5 +#define UMCCH6_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH6_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH6_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH6_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH6_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH6_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH6_2_EccErrCntSel +#define UMCCH6_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH6_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH6_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH6_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH6_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH6_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH6_2_EccErrCnt +#define UMCCH6_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH6_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH6_2_PerfMonCtlClk +#define UMCCH6_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH6_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH6_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH6_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH6_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH6_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH6_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH6_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH6_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH6_2_PerfMonCtrClk_Lo +#define UMCCH6_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtrClk_Hi +#define UMCCH6_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH6_2_PerfMonCtl1 +#define UMCCH6_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr1_Lo +#define UMCCH6_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr1_Hi +#define UMCCH6_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl2 +#define UMCCH6_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr2_Lo +#define UMCCH6_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr2_Hi +#define UMCCH6_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl3 +#define UMCCH6_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr3_Lo +#define UMCCH6_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr3_Hi +#define UMCCH6_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl4 +#define UMCCH6_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr4_Lo +#define UMCCH6_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr4_Hi +#define UMCCH6_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl5 +#define UMCCH6_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr5_Lo +#define UMCCH6_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr5_Hi +#define UMCCH6_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl6 +#define UMCCH6_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr6_Lo +#define UMCCH6_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr6_Hi +#define UMCCH6_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl7 +#define UMCCH6_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr7_Lo +#define UMCCH6_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr7_Hi +#define UMCCH6_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_2_PerfMonCtl8 +#define UMCCH6_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH6_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH6_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH6_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH6_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH6_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH6_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH6_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH6_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH6_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH6_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH6_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH6_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH6_2_PerfMonCtr8_Lo +#define UMCCH6_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_2_PerfMonCtr8_Hi +#define UMCCH6_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH6_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc2_umcch7_umcchdec +//UMCCH7_2_BaseAddrCS0 +#define UMCCH7_2_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH7_2_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH7_2_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH7_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH7_2_AddrMaskCS01 +#define UMCCH7_2_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH7_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH7_2_AddrSelCS01 +#define UMCCH7_2_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH7_2_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH7_2_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH7_2_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH7_2_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH7_2_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH7_2_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH7_2_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH7_2_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH7_2_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH7_2_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH7_2_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH7_2_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH7_2_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH7_2_AddrHashBank0 +#define UMCCH7_2_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_AddrHashBank1 +#define UMCCH7_2_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_AddrHashBank2 +#define UMCCH7_2_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_AddrHashBank3 +#define UMCCH7_2_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_AddrHashBank4 +#define UMCCH7_2_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_AddrHashBank5 +#define UMCCH7_2_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH7_2_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH7_2_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH7_2_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH7_2_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH7_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH7_2_EccErrCntSel +#define UMCCH7_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH7_2_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH7_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH7_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH7_2_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH7_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH7_2_EccErrCnt +#define UMCCH7_2_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH7_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH7_2_PerfMonCtlClk +#define UMCCH7_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH7_2_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH7_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH7_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH7_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH7_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH7_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH7_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH7_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH7_2_PerfMonCtrClk_Lo +#define UMCCH7_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtrClk_Hi +#define UMCCH7_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH7_2_PerfMonCtl1 +#define UMCCH7_2_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr1_Lo +#define UMCCH7_2_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr1_Hi +#define UMCCH7_2_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl2 +#define UMCCH7_2_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr2_Lo +#define UMCCH7_2_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr2_Hi +#define UMCCH7_2_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl3 +#define UMCCH7_2_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr3_Lo +#define UMCCH7_2_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr3_Hi +#define UMCCH7_2_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl4 +#define UMCCH7_2_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr4_Lo +#define UMCCH7_2_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr4_Hi +#define UMCCH7_2_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl5 +#define UMCCH7_2_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr5_Lo +#define UMCCH7_2_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr5_Hi +#define UMCCH7_2_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl6 +#define UMCCH7_2_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr6_Lo +#define UMCCH7_2_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr6_Hi +#define UMCCH7_2_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl7 +#define UMCCH7_2_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr7_Lo +#define UMCCH7_2_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr7_Hi +#define UMCCH7_2_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_2_PerfMonCtl8 +#define UMCCH7_2_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH7_2_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH7_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH7_2_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH7_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH7_2_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH7_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH7_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH7_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH7_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH7_2_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH7_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH7_2_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH7_2_PerfMonCtr8_Lo +#define UMCCH7_2_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_2_PerfMonCtr8_Hi +#define UMCCH7_2_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH7_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch0_umcchdec +//UMCCH0_3_BaseAddrCS0 +#define UMCCH0_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH0_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH0_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH0_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH0_3_AddrMaskCS01 +#define UMCCH0_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH0_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH0_3_AddrSelCS01 +#define UMCCH0_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH0_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH0_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH0_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH0_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH0_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH0_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH0_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH0_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH0_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH0_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH0_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH0_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH0_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH0_3_AddrHashBank0 +#define UMCCH0_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_AddrHashBank1 +#define UMCCH0_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_AddrHashBank2 +#define UMCCH0_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_AddrHashBank3 +#define UMCCH0_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_AddrHashBank4 +#define UMCCH0_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_AddrHashBank5 +#define UMCCH0_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH0_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH0_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH0_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH0_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH0_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH0_3_EccErrCntSel +#define UMCCH0_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH0_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH0_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH0_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH0_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH0_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH0_3_EccErrCnt +#define UMCCH0_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH0_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH0_3_PerfMonCtlClk +#define UMCCH0_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH0_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH0_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH0_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH0_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH0_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH0_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH0_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH0_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH0_3_PerfMonCtrClk_Lo +#define UMCCH0_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtrClk_Hi +#define UMCCH0_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH0_3_PerfMonCtl1 +#define UMCCH0_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr1_Lo +#define UMCCH0_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr1_Hi +#define UMCCH0_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl2 +#define UMCCH0_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr2_Lo +#define UMCCH0_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr2_Hi +#define UMCCH0_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl3 +#define UMCCH0_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr3_Lo +#define UMCCH0_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr3_Hi +#define UMCCH0_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl4 +#define UMCCH0_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr4_Lo +#define UMCCH0_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr4_Hi +#define UMCCH0_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl5 +#define UMCCH0_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr5_Lo +#define UMCCH0_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr5_Hi +#define UMCCH0_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl6 +#define UMCCH0_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr6_Lo +#define UMCCH0_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr6_Hi +#define UMCCH0_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl7 +#define UMCCH0_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr7_Lo +#define UMCCH0_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr7_Hi +#define UMCCH0_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH0_3_PerfMonCtl8 +#define UMCCH0_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH0_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH0_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH0_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH0_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH0_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH0_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH0_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH0_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH0_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH0_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH0_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH0_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH0_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH0_3_PerfMonCtr8_Lo +#define UMCCH0_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH0_3_PerfMonCtr8_Hi +#define UMCCH0_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH0_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH0_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH0_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch1_umcchdec +//UMCCH1_3_BaseAddrCS0 +#define UMCCH1_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH1_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH1_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH1_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH1_3_AddrMaskCS01 +#define UMCCH1_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH1_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH1_3_AddrSelCS01 +#define UMCCH1_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH1_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH1_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH1_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH1_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH1_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH1_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH1_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH1_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH1_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH1_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH1_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH1_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH1_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH1_3_AddrHashBank0 +#define UMCCH1_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_AddrHashBank1 +#define UMCCH1_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_AddrHashBank2 +#define UMCCH1_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_AddrHashBank3 +#define UMCCH1_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_AddrHashBank4 +#define UMCCH1_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_AddrHashBank5 +#define UMCCH1_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH1_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH1_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH1_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH1_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH1_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH1_3_EccErrCntSel +#define UMCCH1_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH1_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH1_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH1_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH1_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH1_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH1_3_EccErrCnt +#define UMCCH1_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH1_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH1_3_PerfMonCtlClk +#define UMCCH1_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH1_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH1_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH1_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH1_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH1_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH1_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH1_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH1_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH1_3_PerfMonCtrClk_Lo +#define UMCCH1_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtrClk_Hi +#define UMCCH1_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH1_3_PerfMonCtl1 +#define UMCCH1_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr1_Lo +#define UMCCH1_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr1_Hi +#define UMCCH1_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl2 +#define UMCCH1_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr2_Lo +#define UMCCH1_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr2_Hi +#define UMCCH1_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl3 +#define UMCCH1_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr3_Lo +#define UMCCH1_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr3_Hi +#define UMCCH1_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl4 +#define UMCCH1_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr4_Lo +#define UMCCH1_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr4_Hi +#define UMCCH1_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl5 +#define UMCCH1_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr5_Lo +#define UMCCH1_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr5_Hi +#define UMCCH1_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl6 +#define UMCCH1_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr6_Lo +#define UMCCH1_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr6_Hi +#define UMCCH1_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl7 +#define UMCCH1_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr7_Lo +#define UMCCH1_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr7_Hi +#define UMCCH1_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH1_3_PerfMonCtl8 +#define UMCCH1_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH1_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH1_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH1_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH1_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH1_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH1_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH1_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH1_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH1_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH1_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH1_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH1_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH1_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH1_3_PerfMonCtr8_Lo +#define UMCCH1_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH1_3_PerfMonCtr8_Hi +#define UMCCH1_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH1_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH1_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH1_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch2_umcchdec +//UMCCH2_3_BaseAddrCS0 +#define UMCCH2_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH2_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH2_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH2_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH2_3_AddrMaskCS01 +#define UMCCH2_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH2_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH2_3_AddrSelCS01 +#define UMCCH2_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH2_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH2_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH2_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH2_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH2_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH2_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH2_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH2_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH2_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH2_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH2_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH2_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH2_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH2_3_AddrHashBank0 +#define UMCCH2_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_AddrHashBank1 +#define UMCCH2_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_AddrHashBank2 +#define UMCCH2_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_AddrHashBank3 +#define UMCCH2_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_AddrHashBank4 +#define UMCCH2_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_AddrHashBank5 +#define UMCCH2_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH2_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH2_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH2_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH2_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH2_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH2_3_EccErrCntSel +#define UMCCH2_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH2_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH2_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH2_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH2_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH2_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH2_3_EccErrCnt +#define UMCCH2_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH2_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH2_3_PerfMonCtlClk +#define UMCCH2_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH2_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH2_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH2_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH2_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH2_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH2_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH2_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH2_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH2_3_PerfMonCtrClk_Lo +#define UMCCH2_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtrClk_Hi +#define UMCCH2_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH2_3_PerfMonCtl1 +#define UMCCH2_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr1_Lo +#define UMCCH2_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr1_Hi +#define UMCCH2_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl2 +#define UMCCH2_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr2_Lo +#define UMCCH2_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr2_Hi +#define UMCCH2_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl3 +#define UMCCH2_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr3_Lo +#define UMCCH2_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr3_Hi +#define UMCCH2_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl4 +#define UMCCH2_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr4_Lo +#define UMCCH2_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr4_Hi +#define UMCCH2_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl5 +#define UMCCH2_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr5_Lo +#define UMCCH2_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr5_Hi +#define UMCCH2_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl6 +#define UMCCH2_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr6_Lo +#define UMCCH2_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr6_Hi +#define UMCCH2_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl7 +#define UMCCH2_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr7_Lo +#define UMCCH2_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr7_Hi +#define UMCCH2_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH2_3_PerfMonCtl8 +#define UMCCH2_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH2_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH2_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH2_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH2_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH2_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH2_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH2_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH2_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH2_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH2_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH2_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH2_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH2_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH2_3_PerfMonCtr8_Lo +#define UMCCH2_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH2_3_PerfMonCtr8_Hi +#define UMCCH2_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH2_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH2_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH2_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch3_umcchdec +//UMCCH3_3_BaseAddrCS0 +#define UMCCH3_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH3_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH3_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH3_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH3_3_AddrMaskCS01 +#define UMCCH3_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH3_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH3_3_AddrSelCS01 +#define UMCCH3_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH3_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH3_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH3_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH3_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH3_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH3_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH3_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH3_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH3_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH3_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH3_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH3_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH3_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH3_3_AddrHashBank0 +#define UMCCH3_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_AddrHashBank1 +#define UMCCH3_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_AddrHashBank2 +#define UMCCH3_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_AddrHashBank3 +#define UMCCH3_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_AddrHashBank4 +#define UMCCH3_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_AddrHashBank5 +#define UMCCH3_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH3_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH3_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH3_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH3_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH3_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH3_3_EccErrCntSel +#define UMCCH3_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH3_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH3_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH3_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH3_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH3_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH3_3_EccErrCnt +#define UMCCH3_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH3_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH3_3_PerfMonCtlClk +#define UMCCH3_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH3_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH3_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH3_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH3_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH3_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH3_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH3_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH3_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH3_3_PerfMonCtrClk_Lo +#define UMCCH3_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtrClk_Hi +#define UMCCH3_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH3_3_PerfMonCtl1 +#define UMCCH3_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr1_Lo +#define UMCCH3_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr1_Hi +#define UMCCH3_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl2 +#define UMCCH3_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr2_Lo +#define UMCCH3_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr2_Hi +#define UMCCH3_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl3 +#define UMCCH3_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr3_Lo +#define UMCCH3_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr3_Hi +#define UMCCH3_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl4 +#define UMCCH3_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr4_Lo +#define UMCCH3_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr4_Hi +#define UMCCH3_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl5 +#define UMCCH3_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr5_Lo +#define UMCCH3_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr5_Hi +#define UMCCH3_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl6 +#define UMCCH3_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr6_Lo +#define UMCCH3_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr6_Hi +#define UMCCH3_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl7 +#define UMCCH3_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr7_Lo +#define UMCCH3_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr7_Hi +#define UMCCH3_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH3_3_PerfMonCtl8 +#define UMCCH3_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH3_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH3_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH3_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH3_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH3_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH3_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH3_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH3_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH3_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH3_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH3_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH3_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH3_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH3_3_PerfMonCtr8_Lo +#define UMCCH3_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH3_3_PerfMonCtr8_Hi +#define UMCCH3_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH3_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH3_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH3_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch4_umcchdec +//UMCCH4_3_BaseAddrCS0 +#define UMCCH4_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH4_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH4_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH4_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH4_3_AddrMaskCS01 +#define UMCCH4_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH4_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH4_3_AddrSelCS01 +#define UMCCH4_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH4_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH4_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH4_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH4_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH4_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH4_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH4_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH4_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH4_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH4_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH4_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH4_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH4_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH4_3_AddrHashBank0 +#define UMCCH4_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_AddrHashBank1 +#define UMCCH4_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_AddrHashBank2 +#define UMCCH4_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_AddrHashBank3 +#define UMCCH4_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_AddrHashBank4 +#define UMCCH4_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_AddrHashBank5 +#define UMCCH4_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH4_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH4_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH4_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH4_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH4_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH4_3_EccErrCntSel +#define UMCCH4_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH4_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH4_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH4_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH4_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH4_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH4_3_EccErrCnt +#define UMCCH4_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH4_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH4_3_PerfMonCtlClk +#define UMCCH4_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH4_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH4_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH4_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH4_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH4_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH4_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH4_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH4_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH4_3_PerfMonCtrClk_Lo +#define UMCCH4_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtrClk_Hi +#define UMCCH4_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH4_3_PerfMonCtl1 +#define UMCCH4_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr1_Lo +#define UMCCH4_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr1_Hi +#define UMCCH4_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl2 +#define UMCCH4_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr2_Lo +#define UMCCH4_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr2_Hi +#define UMCCH4_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl3 +#define UMCCH4_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr3_Lo +#define UMCCH4_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr3_Hi +#define UMCCH4_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl4 +#define UMCCH4_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr4_Lo +#define UMCCH4_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr4_Hi +#define UMCCH4_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl5 +#define UMCCH4_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr5_Lo +#define UMCCH4_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr5_Hi +#define UMCCH4_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl6 +#define UMCCH4_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr6_Lo +#define UMCCH4_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr6_Hi +#define UMCCH4_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl7 +#define UMCCH4_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr7_Lo +#define UMCCH4_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr7_Hi +#define UMCCH4_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH4_3_PerfMonCtl8 +#define UMCCH4_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH4_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH4_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH4_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH4_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH4_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH4_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH4_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH4_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH4_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH4_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH4_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH4_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH4_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH4_3_PerfMonCtr8_Lo +#define UMCCH4_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH4_3_PerfMonCtr8_Hi +#define UMCCH4_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH4_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH4_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH4_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch5_umcchdec +//UMCCH5_3_BaseAddrCS0 +#define UMCCH5_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH5_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH5_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH5_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH5_3_AddrMaskCS01 +#define UMCCH5_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH5_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH5_3_AddrSelCS01 +#define UMCCH5_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH5_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH5_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH5_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH5_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH5_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH5_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH5_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH5_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH5_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH5_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH5_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH5_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH5_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH5_3_AddrHashBank0 +#define UMCCH5_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_AddrHashBank1 +#define UMCCH5_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_AddrHashBank2 +#define UMCCH5_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_AddrHashBank3 +#define UMCCH5_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_AddrHashBank4 +#define UMCCH5_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_AddrHashBank5 +#define UMCCH5_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH5_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH5_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH5_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH5_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH5_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH5_3_EccErrCntSel +#define UMCCH5_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH5_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH5_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH5_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH5_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH5_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH5_3_EccErrCnt +#define UMCCH5_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH5_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH5_3_PerfMonCtlClk +#define UMCCH5_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH5_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH5_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH5_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH5_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH5_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH5_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH5_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH5_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH5_3_PerfMonCtrClk_Lo +#define UMCCH5_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtrClk_Hi +#define UMCCH5_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH5_3_PerfMonCtl1 +#define UMCCH5_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr1_Lo +#define UMCCH5_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr1_Hi +#define UMCCH5_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl2 +#define UMCCH5_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr2_Lo +#define UMCCH5_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr2_Hi +#define UMCCH5_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl3 +#define UMCCH5_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr3_Lo +#define UMCCH5_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr3_Hi +#define UMCCH5_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl4 +#define UMCCH5_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr4_Lo +#define UMCCH5_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr4_Hi +#define UMCCH5_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl5 +#define UMCCH5_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr5_Lo +#define UMCCH5_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr5_Hi +#define UMCCH5_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl6 +#define UMCCH5_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr6_Lo +#define UMCCH5_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr6_Hi +#define UMCCH5_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl7 +#define UMCCH5_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr7_Lo +#define UMCCH5_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr7_Hi +#define UMCCH5_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH5_3_PerfMonCtl8 +#define UMCCH5_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH5_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH5_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH5_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH5_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH5_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH5_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH5_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH5_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH5_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH5_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH5_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH5_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH5_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH5_3_PerfMonCtr8_Lo +#define UMCCH5_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH5_3_PerfMonCtr8_Hi +#define UMCCH5_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH5_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH5_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH5_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch6_umcchdec +//UMCCH6_3_BaseAddrCS0 +#define UMCCH6_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH6_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH6_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH6_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH6_3_AddrMaskCS01 +#define UMCCH6_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH6_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH6_3_AddrSelCS01 +#define UMCCH6_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH6_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH6_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH6_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH6_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH6_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH6_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH6_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH6_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH6_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH6_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH6_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH6_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH6_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH6_3_AddrHashBank0 +#define UMCCH6_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_AddrHashBank1 +#define UMCCH6_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_AddrHashBank2 +#define UMCCH6_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_AddrHashBank3 +#define UMCCH6_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_AddrHashBank4 +#define UMCCH6_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_AddrHashBank5 +#define UMCCH6_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH6_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH6_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH6_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH6_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH6_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH6_3_EccErrCntSel +#define UMCCH6_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH6_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH6_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH6_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH6_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH6_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH6_3_EccErrCnt +#define UMCCH6_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH6_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH6_3_PerfMonCtlClk +#define UMCCH6_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH6_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH6_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH6_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH6_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH6_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH6_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH6_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH6_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH6_3_PerfMonCtrClk_Lo +#define UMCCH6_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtrClk_Hi +#define UMCCH6_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH6_3_PerfMonCtl1 +#define UMCCH6_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr1_Lo +#define UMCCH6_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr1_Hi +#define UMCCH6_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl2 +#define UMCCH6_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr2_Lo +#define UMCCH6_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr2_Hi +#define UMCCH6_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl3 +#define UMCCH6_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr3_Lo +#define UMCCH6_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr3_Hi +#define UMCCH6_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl4 +#define UMCCH6_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr4_Lo +#define UMCCH6_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr4_Hi +#define UMCCH6_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl5 +#define UMCCH6_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr5_Lo +#define UMCCH6_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr5_Hi +#define UMCCH6_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl6 +#define UMCCH6_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr6_Lo +#define UMCCH6_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr6_Hi +#define UMCCH6_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl7 +#define UMCCH6_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr7_Lo +#define UMCCH6_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr7_Hi +#define UMCCH6_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH6_3_PerfMonCtl8 +#define UMCCH6_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH6_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH6_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH6_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH6_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH6_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH6_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH6_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH6_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH6_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH6_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH6_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH6_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH6_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH6_3_PerfMonCtr8_Lo +#define UMCCH6_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH6_3_PerfMonCtr8_Hi +#define UMCCH6_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH6_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH6_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH6_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +// addressBlock: umc_w_phy_umc3_umcch7_umcchdec +//UMCCH7_3_BaseAddrCS0 +#define UMCCH7_3_BaseAddrCS0__CSEnable__SHIFT 0x0 +#define UMCCH7_3_BaseAddrCS0__BaseAddr__SHIFT 0x1 +#define UMCCH7_3_BaseAddrCS0__CSEnable_MASK 0x00000001L +#define UMCCH7_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL +//UMCCH7_3_AddrMaskCS01 +#define UMCCH7_3_AddrMaskCS01__AddrMask__SHIFT 0x1 +#define UMCCH7_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL +//UMCCH7_3_AddrSelCS01 +#define UMCCH7_3_AddrSelCS01__BankBit0__SHIFT 0x0 +#define UMCCH7_3_AddrSelCS01__BankBit1__SHIFT 0x4 +#define UMCCH7_3_AddrSelCS01__BankBit2__SHIFT 0x8 +#define UMCCH7_3_AddrSelCS01__BankBit3__SHIFT 0xc +#define UMCCH7_3_AddrSelCS01__BankBit4__SHIFT 0x10 +#define UMCCH7_3_AddrSelCS01__RowLo__SHIFT 0x18 +#define UMCCH7_3_AddrSelCS01__RowHi__SHIFT 0x1c +#define UMCCH7_3_AddrSelCS01__BankBit0_MASK 0x0000000FL +#define UMCCH7_3_AddrSelCS01__BankBit1_MASK 0x000000F0L +#define UMCCH7_3_AddrSelCS01__BankBit2_MASK 0x00000F00L +#define UMCCH7_3_AddrSelCS01__BankBit3_MASK 0x0000F000L +#define UMCCH7_3_AddrSelCS01__BankBit4_MASK 0x001F0000L +#define UMCCH7_3_AddrSelCS01__RowLo_MASK 0x0F000000L +#define UMCCH7_3_AddrSelCS01__RowHi_MASK 0xF0000000L +//UMCCH7_3_AddrHashBank0 +#define UMCCH7_3_AddrHashBank0__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank0__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank0__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank0__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank0__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_AddrHashBank1 +#define UMCCH7_3_AddrHashBank1__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank1__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank1__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank1__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank1__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_AddrHashBank2 +#define UMCCH7_3_AddrHashBank2__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank2__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank2__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank2__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank2__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_AddrHashBank3 +#define UMCCH7_3_AddrHashBank3__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank3__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank3__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank3__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank3__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_AddrHashBank4 +#define UMCCH7_3_AddrHashBank4__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank4__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank4__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank4__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank4__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_AddrHashBank5 +#define UMCCH7_3_AddrHashBank5__XorEnable__SHIFT 0x0 +#define UMCCH7_3_AddrHashBank5__ColXor__SHIFT 0x1 +#define UMCCH7_3_AddrHashBank5__RowXor__SHIFT 0xe +#define UMCCH7_3_AddrHashBank5__XorEnable_MASK 0x00000001L +#define UMCCH7_3_AddrHashBank5__ColXor_MASK 0x00003FFEL +#define UMCCH7_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L +//UMCCH7_3_EccErrCntSel +#define UMCCH7_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH7_3_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH7_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH7_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH7_3_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH7_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH7_3_EccErrCnt +#define UMCCH7_3_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH7_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//UMCCH7_3_PerfMonCtlClk +#define UMCCH7_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtlClk__ClkGate__SHIFT 0x16 +#define UMCCH7_3_PerfMonCtlClk__GlblReset__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19 +#define UMCCH7_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a +#define UMCCH7_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL +#define UMCCH7_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L +#define UMCCH7_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L +#define UMCCH7_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L +#define UMCCH7_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L +#define UMCCH7_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L +//UMCCH7_3_PerfMonCtrClk_Lo +#define UMCCH7_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtrClk_Hi +#define UMCCH7_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L +//UMCCH7_3_PerfMonCtl1 +#define UMCCH7_3_PerfMonCtl1__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl1__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl1__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl1__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl1__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl1__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl1__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl1__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr1_Lo +#define UMCCH7_3_PerfMonCtr1_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr1_Hi +#define UMCCH7_3_PerfMonCtr1_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl2 +#define UMCCH7_3_PerfMonCtl2__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl2__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl2__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl2__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl2__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl2__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl2__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl2__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr2_Lo +#define UMCCH7_3_PerfMonCtr2_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr2_Hi +#define UMCCH7_3_PerfMonCtr2_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl3 +#define UMCCH7_3_PerfMonCtl3__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl3__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl3__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl3__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl3__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl3__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl3__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl3__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr3_Lo +#define UMCCH7_3_PerfMonCtr3_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr3_Hi +#define UMCCH7_3_PerfMonCtr3_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl4 +#define UMCCH7_3_PerfMonCtl4__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl4__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl4__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl4__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl4__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl4__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl4__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl4__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr4_Lo +#define UMCCH7_3_PerfMonCtr4_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr4_Hi +#define UMCCH7_3_PerfMonCtr4_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl5 +#define UMCCH7_3_PerfMonCtl5__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl5__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl5__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl5__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl5__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl5__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl5__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl5__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr5_Lo +#define UMCCH7_3_PerfMonCtr5_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr5_Hi +#define UMCCH7_3_PerfMonCtr5_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl6 +#define UMCCH7_3_PerfMonCtl6__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl6__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl6__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl6__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl6__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl6__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl6__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl6__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr6_Lo +#define UMCCH7_3_PerfMonCtr6_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr6_Hi +#define UMCCH7_3_PerfMonCtr6_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl7 +#define UMCCH7_3_PerfMonCtl7__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl7__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl7__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl7__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl7__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl7__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl7__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl7__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr7_Lo +#define UMCCH7_3_PerfMonCtr7_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr7_Hi +#define UMCCH7_3_PerfMonCtr7_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L +//UMCCH7_3_PerfMonCtl8 +#define UMCCH7_3_PerfMonCtl8__EventSelect__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtl8__RdWrMask__SHIFT 0x8 +#define UMCCH7_3_PerfMonCtl8__PriorityMask__SHIFT 0xa +#define UMCCH7_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe +#define UMCCH7_3_PerfMonCtl8__BankSel__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtl8__VCSel__SHIFT 0x18 +#define UMCCH7_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d +#define UMCCH7_3_PerfMonCtl8__Enable__SHIFT 0x1f +#define UMCCH7_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL +#define UMCCH7_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L +#define UMCCH7_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L +#define UMCCH7_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L +#define UMCCH7_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L +#define UMCCH7_3_PerfMonCtl8__VCSel_MASK 0x1F000000L +#define UMCCH7_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L +#define UMCCH7_3_PerfMonCtl8__Enable_MASK 0x80000000L +//UMCCH7_3_PerfMonCtr8_Lo +#define UMCCH7_3_PerfMonCtr8_Lo__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL +//UMCCH7_3_PerfMonCtr8_Hi +#define UMCCH7_3_PerfMonCtr8_Hi__Data__SHIFT 0x0 +#define UMCCH7_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10 +#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12 +#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14 +#define UMCCH7_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL +#define UMCCH7_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L +#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L +#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h new file mode 100644 index 0000000000000000000000000000000000000000..98d22bd5b30481c8f5f39df3c565ae93ff9a760c --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h @@ -0,0 +1,1462 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _vcn_2_6_0_OFFSET_HEADER +#define _vcn_2_6_0_OFFSET_HEADER + + + +// addressBlock: uvd0_ecpudec +// base address: 0x1fd00 +#define regUVD_VCPU_CACHE_OFFSET0 0x0140 +#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE0 0x0141 +#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET1 0x0142 +#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE1 0x0143 +#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET2 0x0144 +#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE2 0x0145 +#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET3 0x0146 +#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE3 0x0147 +#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET4 0x0148 +#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE4 0x0149 +#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET5 0x014a +#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE5 0x014b +#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET6 0x014c +#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE6 0x014d +#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET7 0x014e +#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE7 0x014f +#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET8 0x0150 +#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE8 0x0151 +#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_OFFSET0 0x0152 +#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_SIZE0 0x0153 +#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_OFFSET1 0x0154 +#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_SIZE1 0x0155 +#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 +#define regUVD_VCPU_CNTL 0x0156 +#define regUVD_VCPU_CNTL_BASE_IDX 1 +#define regUVD_VCPU_PRID 0x0157 +#define regUVD_VCPU_PRID_BASE_IDX 1 +#define regUVD_VCPU_TRCE 0x0158 +#define regUVD_VCPU_TRCE_BASE_IDX 1 +#define regUVD_VCPU_TRCE_RD 0x0159 +#define regUVD_VCPU_TRCE_RD_BASE_IDX 1 +#define regUVD_VCPU_IND_INDEX 0x015b +#define regUVD_VCPU_IND_INDEX_BASE_IDX 1 +#define regUVD_VCPU_IND_DATA 0x015c +#define regUVD_VCPU_IND_DATA_BASE_IDX 1 + + +// addressBlock: uvd0_jpegnpdec +// base address: 0x1e200 +#define regUVD_JPEG_CNTL 0x0080 +#define regUVD_JPEG_CNTL_BASE_IDX 0 +#define regUVD_JPEG_RB_BASE 0x0081 +#define regUVD_JPEG_RB_BASE_BASE_IDX 0 +#define regUVD_JPEG_RB_WPTR 0x0082 +#define regUVD_JPEG_RB_WPTR_BASE_IDX 0 +#define regUVD_JPEG_RB_RPTR 0x0083 +#define regUVD_JPEG_RB_RPTR_BASE_IDX 0 +#define regUVD_JPEG_RB_SIZE 0x0084 +#define regUVD_JPEG_RB_SIZE_BASE_IDX 0 +#define regUVD_JPEG_DEC_CNT 0x0085 +#define regUVD_JPEG_DEC_CNT_BASE_IDX 0 +#define regUVD_JPEG_SPS_INFO 0x0086 +#define regUVD_JPEG_SPS_INFO_BASE_IDX 0 +#define regUVD_JPEG_SPS1_INFO 0x0087 +#define regUVD_JPEG_SPS1_INFO_BASE_IDX 0 +#define regUVD_JPEG_RE_TIMER 0x0088 +#define regUVD_JPEG_RE_TIMER_BASE_IDX 0 +#define regUVD_JPEG_DEC_SCRATCH0 0x0089 +#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 +#define regUVD_JPEG_INT_EN 0x008a +#define regUVD_JPEG_INT_EN_BASE_IDX 0 +#define regUVD_JPEG_INT_STAT 0x008b +#define regUVD_JPEG_INT_STAT_BASE_IDX 0 +#define regUVD_JPEG_TIER_CNTL0 0x008d +#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 0 +#define regUVD_JPEG_TIER_CNTL1 0x008e +#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 0 +#define regUVD_JPEG_TIER_CNTL2 0x008f +#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 0 +#define regUVD_JPEG_TIER_STATUS 0x0090 +#define regUVD_JPEG_TIER_STATUS_BASE_IDX 0 +#define regUVD_JPEG_OUTBUF_CNTL 0x009c +#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 0 +#define regUVD_JPEG_OUTBUF_WPTR 0x009d +#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 0 +#define regUVD_JPEG_OUTBUF_RPTR 0x009e +#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 0 +#define regUVD_JPEG_PITCH 0x009f +#define regUVD_JPEG_PITCH_BASE_IDX 0 +#define regUVD_JPEG_UV_PITCH 0x00a0 +#define regUVD_JPEG_UV_PITCH_BASE_IDX 0 +#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 +#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 +#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 +#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 +#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 +#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 +#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 +#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 +#define regJPEG_DEC_ADDR_MODE 0x00a7 +#define regJPEG_DEC_ADDR_MODE_BASE_IDX 0 +#define regUVD_JPEG_OUTPUT_XY 0x00a8 +#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 0 +#define regUVD_JPEG_GPCOM_CMD 0x00a9 +#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 0 +#define regUVD_JPEG_GPCOM_DATA0 0x00aa +#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 +#define regUVD_JPEG_GPCOM_DATA1 0x00ab +#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 +#define regUVD_JPEG_INDEX 0x00ac +#define regUVD_JPEG_INDEX_BASE_IDX 0 +#define regUVD_JPEG_DATA 0x00ad +#define regUVD_JPEG_DATA_BASE_IDX 0 +#define regUVD_JPEG_SCRATCH1 0x00ae +#define regUVD_JPEG_SCRATCH1_BASE_IDX 0 +#define regUVD_JPEG_DEC_SOFT_RST 0x00af +#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 + + +// addressBlock: uvd0_lmi_adpdec +// base address: 0x20870 +#define regUVD_LMI_RE_64BIT_BAR_LOW 0x041c +#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x041d +#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_IT_64BIT_BAR_LOW 0x041e +#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x041f +#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0420 +#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0421 +#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_CM_64BIT_BAR_LOW 0x0422 +#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x0423 +#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_DB_64BIT_BAR_LOW 0x0424 +#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x0425 +#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x0426 +#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x0427 +#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0428 +#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0429 +#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x042a +#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x042b +#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x042c +#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x042d +#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x042e +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x042f +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0430 +#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0431 +#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 +#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 +#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 +#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 +#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x0436 +#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x0437 +#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x043e +#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x043f +#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0440 +#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0441 +#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x0442 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x0443 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x0444 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x0445 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x0446 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x0447 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0448 +#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0449 +#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x044a +#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x044b +#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x044c +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x044d +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x044e +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x044f +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0450 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0451 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x0452 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x0453 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x0454 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x0455 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x0456 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x0457 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0458 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0459 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x045a +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x045b +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x045c +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x045d +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x045e +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x045f +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0478 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0479 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x047a +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x047b +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c +#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC_VMID 0x048d +#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 +#define regUVD_LMI_MMSCH_CTRL 0x048e +#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 +#define regUVD_MMSCH_LMI_STATUS 0x048f +#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0490 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0491 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x0492 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x0493 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x0494 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x0495 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x0496 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x0497 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_ADP_ATOMIC_CONFIG 0x0499 +#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 +#define regUVD_LMI_ARB_CTRL2 0x049a +#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f +#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 +#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 +#define regUVD_LMI_LAT_CTRL 0x04a1 +#define regUVD_LMI_LAT_CTRL_BASE_IDX 1 +#define regUVD_LMI_LAT_CNTR 0x04a2 +#define regUVD_LMI_LAT_CNTR_BASE_IDX 1 +#define regUVD_LMI_AVG_LAT_CNTR 0x04a3 +#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 +#define regUVD_LMI_SPH 0x04a4 +#define regUVD_LMI_SPH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_VMID 0x04a5 +#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define regUVD_LMI_CTRL2 0x04a6 +#define regUVD_LMI_CTRL2_BASE_IDX 1 +#define regUVD_LMI_URGENT_CTRL 0x04a7 +#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 +#define regUVD_LMI_CTRL 0x04a8 +#define regUVD_LMI_CTRL_BASE_IDX 1 +#define regUVD_LMI_STATUS 0x04a9 +#define regUVD_LMI_STATUS_BASE_IDX 1 +#define regUVD_LMI_PERFMON_CTRL 0x04ac +#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 +#define regUVD_LMI_PERFMON_COUNT_LO 0x04ad +#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 +#define regUVD_LMI_PERFMON_COUNT_HI 0x04ae +#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 +#define regUVD_LMI_ADP_SWAP_CNTL 0x04af +#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_VMID 0x04b0 +#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_VMID 0x04b1 +#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 +#define regUVD_LMI_MC_CREDITS 0x04b2 +#define regUVD_LMI_MC_CREDITS_BASE_IDX 1 +#define regUVD_LMI_ADP_IND_INDEX 0x04b6 +#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 +#define regUVD_LMI_ADP_IND_DATA 0x04b7 +#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 +#define regVCN_RAS_CNTL 0x04b9 +#define regVCN_RAS_CNTL_BASE_IDX 1 + + +// addressBlock: uvd0_mmsch_dec +// base address: 0x1e000 +#define regMMSCH_UCODE_ADDR 0x0000 +#define regMMSCH_UCODE_ADDR_BASE_IDX 0 +#define regMMSCH_UCODE_DATA 0x0001 +#define regMMSCH_UCODE_DATA_BASE_IDX 0 +#define regMMSCH_SRAM_ADDR 0x0002 +#define regMMSCH_SRAM_ADDR_BASE_IDX 0 +#define regMMSCH_SRAM_DATA 0x0003 +#define regMMSCH_SRAM_DATA_BASE_IDX 0 +#define regMMSCH_VF_SRAM_OFFSET 0x0004 +#define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 0 +#define regMMSCH_DB_SRAM_OFFSET 0x0005 +#define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 0 +#define regMMSCH_CTX_SRAM_OFFSET 0x0006 +#define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0 +#define regMMSCH_INTR 0x0008 +#define regMMSCH_INTR_BASE_IDX 0 +#define regMMSCH_INTR_ACK 0x0009 +#define regMMSCH_INTR_ACK_BASE_IDX 0 +#define regMMSCH_INTR_STATUS 0x000a +#define regMMSCH_INTR_STATUS_BASE_IDX 0 +#define regMMSCH_VF_VMID 0x000b +#define regMMSCH_VF_VMID_BASE_IDX 0 +#define regMMSCH_VF_CTX_ADDR_LO 0x000c +#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 +#define regMMSCH_VF_CTX_ADDR_HI 0x000d +#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 +#define regMMSCH_VF_CTX_SIZE 0x000e +#define regMMSCH_VF_CTX_SIZE_BASE_IDX 0 +#define regMMSCH_VF_GPCOM_ADDR_LO 0x000f +#define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 +#define regMMSCH_VF_GPCOM_ADDR_HI 0x0010 +#define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 +#define regMMSCH_VF_GPCOM_SIZE 0x0011 +#define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_HOST 0x0012 +#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_RESP 0x0013 +#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_0 0x0014 +#define regMMSCH_VF_MAILBOX_0_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_0_RESP 0x0015 +#define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_1 0x0016 +#define regMMSCH_VF_MAILBOX_1_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX_1_RESP 0x0017 +#define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0 +#define regMMSCH_CNTL 0x001c +#define regMMSCH_CNTL_BASE_IDX 0 +#define regMMSCH_NONCACHE_OFFSET0 0x001d +#define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 0 +#define regMMSCH_NONCACHE_SIZE0 0x001e +#define regMMSCH_NONCACHE_SIZE0_BASE_IDX 0 +#define regMMSCH_NONCACHE_OFFSET1 0x001f +#define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 0 +#define regMMSCH_NONCACHE_SIZE1 0x0020 +#define regMMSCH_NONCACHE_SIZE1_BASE_IDX 0 +#define regMMSCH_PROC_STATE1 0x0026 +#define regMMSCH_PROC_STATE1_BASE_IDX 0 +#define regMMSCH_LAST_MC_ADDR 0x0027 +#define regMMSCH_LAST_MC_ADDR_BASE_IDX 0 +#define regMMSCH_LAST_MEM_ACCESS_HI 0x0028 +#define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0 +#define regMMSCH_LAST_MEM_ACCESS_LO 0x0029 +#define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0 +#define regMMSCH_SCRATCH_0 0x002b +#define regMMSCH_SCRATCH_0_BASE_IDX 0 +#define regMMSCH_SCRATCH_1 0x002c +#define regMMSCH_SCRATCH_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_0 0x002d +#define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_CONTROL_0 0x002e +#define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_0 0x002f +#define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031 +#define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW6_0 0x0033 +#define regMMSCH_GPUIOV_DW6_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW7_0 0x0034 +#define regMMSCH_GPUIOV_DW7_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW8_0 0x0035 +#define regMMSCH_GPUIOV_DW8_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0036 +#define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0037 +#define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_1 0x0038 +#define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a +#define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW6_1 0x003c +#define regMMSCH_GPUIOV_DW6_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW7_1 0x003d +#define regMMSCH_GPUIOV_DW7_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW8_1 0x003e +#define regMMSCH_GPUIOV_DW8_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_CNTXT 0x003f +#define regMMSCH_GPUIOV_CNTXT_BASE_IDX 0 +#define regMMSCH_SCRATCH_2 0x0040 +#define regMMSCH_SCRATCH_2_BASE_IDX 0 +#define regMMSCH_SCRATCH_3 0x0041 +#define regMMSCH_SCRATCH_3_BASE_IDX 0 +#define regMMSCH_SCRATCH_4 0x0042 +#define regMMSCH_SCRATCH_4_BASE_IDX 0 +#define regMMSCH_SCRATCH_5 0x0043 +#define regMMSCH_SCRATCH_5_BASE_IDX 0 +#define regMMSCH_SCRATCH_6 0x0044 +#define regMMSCH_SCRATCH_6_BASE_IDX 0 +#define regMMSCH_SCRATCH_7 0x0045 +#define regMMSCH_SCRATCH_7_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_HEAD_0 0x0046 +#define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_TAIL_0 0x0047 +#define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_HEAD_1 0x0048 +#define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_TAIL_1 0x0049 +#define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0 +#define regMMSCH_NACK_STATUS 0x004a +#define regMMSCH_NACK_STATUS_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX0_DATA 0x004b +#define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0 +#define regMMSCH_VF_MAILBOX1_DATA 0x004c +#define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e +#define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050 +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051 +#define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0 +#define regMMSCH_GPUIOV_CNTXT_IP 0x0053 +#define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0054 +#define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0055 +#define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_2 0x0056 +#define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057 +#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058 +#define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW6_2 0x005a +#define regMMSCH_GPUIOV_DW6_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW7_2 0x005b +#define regMMSCH_GPUIOV_DW7_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_DW8_2 0x005c +#define regMMSCH_GPUIOV_DW8_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d +#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e +#define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0 +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f +#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_HEAD_2 0x0060 +#define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0 +#define regMMSCH_VFID_FIFO_TAIL_2 0x0061 +#define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0 +#define regMMSCH_VM_BUSY_STATUS_0 0x0062 +#define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0 +#define regMMSCH_VM_BUSY_STATUS_1 0x0063 +#define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0 +#define regMMSCH_VM_BUSY_STATUS_2 0x0064 +#define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jmi_dec +// base address: 0x1e500 +#define regUVD_JADP_MCIF_URGENT_CTRL 0x0141 +#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 0 +#define regUVD_JMI_URGENT_CTRL 0x0142 +#define regUVD_JMI_URGENT_CTRL_BASE_IDX 0 +#define regUVD_JPEG_DEC_PF_CTRL 0x0143 +#define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 +#define regUVD_JPEG_ENC_PF_CTRL 0x0144 +#define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 0 +#define regUVD_JMI_CTRL 0x0145 +#define regUVD_JMI_CTRL_BASE_IDX 0 +#define regUVD_LMI_JRBC_CTRL 0x0146 +#define regUVD_LMI_JRBC_CTRL_BASE_IDX 0 +#define regUVD_LMI_JPEG_CTRL 0x0147 +#define regUVD_LMI_JPEG_CTRL_BASE_IDX 0 +#define regUVD_JMI_EJRBC_CTRL 0x0148 +#define regUVD_JMI_EJRBC_CTRL_BASE_IDX 0 +#define regUVD_LMI_EJPEG_CTRL 0x0149 +#define regUVD_LMI_EJPEG_CTRL_BASE_IDX 0 +#define regUVD_JMI_SCALER_CTRL 0x014a +#define regUVD_JMI_SCALER_CTRL_BASE_IDX 0 +#define regJPEG_LMI_DROP 0x014b +#define regJPEG_LMI_DROP_BASE_IDX 0 +#define regUVD_JMI_EJPEG_DROP 0x014c +#define regUVD_JMI_EJPEG_DROP_BASE_IDX 0 +#define regJPEG_MEMCHECK_CLAMPING 0x014d +#define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 0 +#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x014e +#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_VMID 0x014f +#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_VMID 0x0150 +#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 +#define regUVD_LMI_JPEG_VMID 0x0151 +#define regUVD_LMI_JPEG_VMID_BASE_IDX 0 +#define regUVD_JMI_ENC_JRBC_IB_VMID 0x0152 +#define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 +#define regUVD_JMI_ENC_JRBC_RB_VMID 0x0153 +#define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 +#define regUVD_JMI_ENC_JPEG_VMID 0x0154 +#define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 +#define regUVD_JMI_EJPEG_RAS_CNTL 0x0156 +#define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 0 +#define regJPEG_MEMCHECK_SAFE_ADDR 0x0157 +#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 0 +#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0158 +#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 0 +#define regUVD_JMI_LAT_CTRL 0x0159 +#define regUVD_JMI_LAT_CTRL_BASE_IDX 0 +#define regUVD_JMI_LAT_CNTR 0x015a +#define regUVD_JMI_LAT_CNTR_BASE_IDX 0 +#define regUVD_JMI_AVG_LAT_CNTR 0x015b +#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 0 +#define regUVD_JMI_PERFMON_CTRL 0x015c +#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 0 +#define regUVD_JMI_PERFMON_COUNT_LO 0x015d +#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 +#define regUVD_JMI_PERFMON_COUNT_HI 0x015e +#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 +#define regUVD_JMI_CLEAN_STATUS 0x015f +#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 0 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c +#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d +#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 +#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 +#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x0172 +#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x0173 +#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x0174 +#define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x0175 +#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x0176 +#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x0177 +#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x0178 +#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x0179 +#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a +#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b +#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c +#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d +#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e +#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f +#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 +#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 +#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 +#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 +#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 +#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 +#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 +#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 +#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JPEG_PREEMPT_VMID 0x0188 +#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 +#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 +#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 +#define regUVD_LMI_JPEG2_VMID 0x018a +#define regUVD_LMI_JPEG2_VMID_BASE_IDX 0 +#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b +#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c +#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d +#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e +#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_LMI_JPEG_CTRL2 0x018f +#define regUVD_LMI_JPEG_CTRL2_BASE_IDX 0 +#define regUVD_JMI_DEC_SWAP_CNTL 0x0190 +#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 +#define regUVD_JMI_ENC_SWAP_CNTL 0x0191 +#define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 +#define regUVD_JMI_CNTL 0x0192 +#define regUVD_JMI_CNTL_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_CNTL 0x0193 +#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_CNTL2 0x0194 +#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0195 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0196 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x0197 +#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x0198 +#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regJPEG2_LMI_DROP 0x0199 +#define regJPEG2_LMI_DROP_BASE_IDX 0 +#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a +#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b +#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define regUVD_JMI_DEC_SWAP_CNTL2 0x019c +#define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 +#define regUVD_JMI_DJPEG_RAS_CNTL 0x019f +#define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_common_dec +// base address: 0x1e700 +#define regJPEG_SOFT_RESET_STATUS 0x01c0 +#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 0 +#define regJPEG_SYS_INT_EN 0x01c1 +#define regJPEG_SYS_INT_EN_BASE_IDX 0 +#define regJPEG_SYS_INT_STATUS 0x01c2 +#define regJPEG_SYS_INT_STATUS_BASE_IDX 0 +#define regJPEG_SYS_INT_ACK 0x01c3 +#define regJPEG_SYS_INT_ACK_BASE_IDX 0 +#define regJPEG_MEMCHECK_SYS_INT_EN 0x01c4 +#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 0 +#define regJPEG_MEMCHECK_SYS_INT_STAT 0x01c5 +#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 0 +#define regJPEG_MEMCHECK_SYS_INT_ACK 0x01c6 +#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 0 +#define regJPEG_MASTINT_EN 0x01c8 +#define regJPEG_MASTINT_EN_BASE_IDX 0 +#define regJPEG_IH_CTRL 0x01c9 +#define regJPEG_IH_CTRL_BASE_IDX 0 +#define regJRBBM_ARB_CTRL 0x01cb +#define regJRBBM_ARB_CTRL_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_common_sclk_dec +// base address: 0x1e780 +#define regJPEG_CGC_GATE 0x01e0 +#define regJPEG_CGC_GATE_BASE_IDX 0 +#define regJPEG_CGC_CTRL 0x01e1 +#define regJPEG_CGC_CTRL_BASE_IDX 0 +#define regJPEG_CGC_STATUS 0x01e2 +#define regJPEG_CGC_STATUS_BASE_IDX 0 +#define regJPEG_COMN_CGC_MEM_CTRL 0x01e3 +#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 +#define regJPEG_DEC_CGC_MEM_CTRL 0x01e4 +#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 +#define regJPEG2_DEC_CGC_MEM_CTRL 0x01e5 +#define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 +#define regJPEG_ENC_CGC_MEM_CTRL 0x01e6 +#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 +#define regJPEG_SOFT_RESET2 0x01e7 +#define regJPEG_SOFT_RESET2_BASE_IDX 0 +#define regJPEG_PERF_BANK_CONF 0x01e8 +#define regJPEG_PERF_BANK_CONF_BASE_IDX 0 +#define regJPEG_PERF_BANK_EVENT_SEL 0x01e9 +#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 +#define regJPEG_PERF_BANK_COUNT0 0x01ea +#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 0 +#define regJPEG_PERF_BANK_COUNT1 0x01eb +#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 0 +#define regJPEG_PERF_BANK_COUNT2 0x01ec +#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 0 +#define regJPEG_PERF_BANK_COUNT3 0x01ed +#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_enc_dec +// base address: 0x1e300 +#define regUVD_JPEG_ENC_INT_EN 0x00c1 +#define regUVD_JPEG_ENC_INT_EN_BASE_IDX 0 +#define regUVD_JPEG_ENC_INT_STATUS 0x00c2 +#define regUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 +#define regUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 +#define regUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 +#define regUVD_JPEG_ENC_SCRATCH1 0x00ce +#define regUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec +// base address: 0x1e380 +#define regUVD_JPEG_ENC_SPS_INFO 0x00e0 +#define regUVD_JPEG_ENC_SPS_INFO_BASE_IDX 0 +#define regUVD_JPEG_ENC_SPS_INFO1 0x00e1 +#define regUVD_JPEG_ENC_SPS_INFO1_BASE_IDX 0 +#define regUVD_JPEG_ENC_TBL_SIZE 0x00e2 +#define regUVD_JPEG_ENC_TBL_SIZE_BASE_IDX 0 +#define regUVD_JPEG_ENC_TBL_CNTL 0x00e3 +#define regUVD_JPEG_ENC_TBL_CNTL_BASE_IDX 0 +#define regUVD_JPEG_ENC_MC_REQ_CNTL 0x00e4 +#define regUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX 0 +#define regUVD_JPEG_ENC_STATUS 0x00e5 +#define regUVD_JPEG_ENC_STATUS_BASE_IDX 0 +#define regUVD_JPEG_ENC_PITCH 0x00e6 +#define regUVD_JPEG_ENC_PITCH_BASE_IDX 0 +#define regUVD_JPEG_ENC_LUMA_BASE 0x00e7 +#define regUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 +#define regUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 +#define regUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 +#define regUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 +#define regUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 +#define regJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea +#define regJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb +#define regJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 +#define regJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec +#define regJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 +#define regJPEG_ENC_ADDR_MODE 0x00ed +#define regJPEG_ENC_ADDR_MODE_BASE_IDX 0 +#define regUVD_JPEG_ENC_GPCOM_CMD 0x00ee +#define regUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 +#define regUVD_JPEG_ENC_GPCOM_DATA0 0x00ef +#define regUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 +#define regUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 +#define regUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 +#define regUVD_JPEG_TBL_DAT0 0x00f1 +#define regUVD_JPEG_TBL_DAT0_BASE_IDX 0 +#define regUVD_JPEG_TBL_DAT1 0x00f2 +#define regUVD_JPEG_TBL_DAT1_BASE_IDX 0 +#define regUVD_JPEG_TBL_IDX 0x00f3 +#define regUVD_JPEG_TBL_IDX_BASE_IDX 0 +#define regUVD_JPEG_ENC_CGC_CNTL 0x00f5 +#define regUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 +#define regUVD_JPEG_ENC_SCRATCH0 0x00f6 +#define regUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 +#define regUVD_JPEG_ENC_SOFT_RST 0x00f7 +#define regUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jrbc_dec +// base address: 0x1e400 +#define regUVD_JRBC_RB_WPTR 0x0100 +#define regUVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC_RB_CNTL 0x0101 +#define regUVD_JRBC_RB_CNTL_BASE_IDX 0 +#define regUVD_JRBC_IB_SIZE 0x0102 +#define regUVD_JRBC_IB_SIZE_BASE_IDX 0 +#define regUVD_JRBC_URGENT_CNTL 0x0103 +#define regUVD_JRBC_URGENT_CNTL_BASE_IDX 0 +#define regUVD_JRBC_RB_REF_DATA 0x0104 +#define regUVD_JRBC_RB_REF_DATA_BASE_IDX 0 +#define regUVD_JRBC_RB_COND_RD_TIMER 0x0105 +#define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 +#define regUVD_JRBC_SOFT_RESET 0x0108 +#define regUVD_JRBC_SOFT_RESET_BASE_IDX 0 +#define regUVD_JRBC_STATUS 0x0109 +#define regUVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC_RB_RPTR 0x010a +#define regUVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC_RB_BUF_STATUS 0x010b +#define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 +#define regUVD_JRBC_IB_BUF_STATUS 0x010c +#define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 +#define regUVD_JRBC_IB_SIZE_UPDATE 0x010d +#define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 +#define regUVD_JRBC_IB_COND_RD_TIMER 0x010e +#define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 +#define regUVD_JRBC_IB_REF_DATA 0x010f +#define regUVD_JRBC_IB_REF_DATA_BASE_IDX 0 +#define regUVD_JPEG_PREEMPT_CMD 0x0110 +#define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 +#define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 +#define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 +#define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 +#define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 +#define regUVD_JRBC_RB_SIZE 0x0113 +#define regUVD_JRBC_RB_SIZE_BASE_IDX 0 +#define regUVD_JRBC_SCRATCH0 0x0114 +#define regUVD_JRBC_SCRATCH0_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jrbc_enc_dec +// base address: 0x1e480 +#define regUVD_JRBC_ENC_RB_WPTR 0x0120 +#define regUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_CNTL 0x0121 +#define regUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 +#define regUVD_JRBC_ENC_IB_SIZE 0x0122 +#define regUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 +#define regUVD_JRBC_ENC_URGENT_CNTL 0x0123 +#define regUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_REF_DATA 0x0124 +#define regUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 +#define regUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 +#define regUVD_JRBC_ENC_SOFT_RESET 0x0128 +#define regUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 +#define regUVD_JRBC_ENC_STATUS 0x0129 +#define regUVD_JRBC_ENC_STATUS_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_RPTR 0x012a +#define regUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_BUF_STATUS 0x012b +#define regUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 +#define regUVD_JRBC_ENC_IB_BUF_STATUS 0x012c +#define regUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 +#define regUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d +#define regUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 +#define regUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e +#define regUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 +#define regUVD_JRBC_ENC_IB_REF_DATA 0x012f +#define regUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 +#define regUVD_JPEG_ENC_PREEMPT_CMD 0x0130 +#define regUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 +#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 +#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 +#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 +#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 +#define regUVD_JRBC_ENC_RB_SIZE 0x0133 +#define regUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 +#define regUVD_JRBC_ENC_SCRATCH0 0x0134 +#define regUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_mpcdec +// base address: 0x20310 +#define regUVD_MP_SWAP_CNTL 0x02c4 +#define regUVD_MP_SWAP_CNTL_BASE_IDX 1 +#define regUVD_MP_SWAP_CNTL2 0x02c5 +#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1 +#define regUVD_MPC_LUMA_SRCH 0x02c6 +#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1 +#define regUVD_MPC_LUMA_HIT 0x02c7 +#define regUVD_MPC_LUMA_HIT_BASE_IDX 1 +#define regUVD_MPC_LUMA_HITPEND 0x02c8 +#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1 +#define regUVD_MPC_CHROMA_SRCH 0x02c9 +#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 +#define regUVD_MPC_CHROMA_HIT 0x02ca +#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1 +#define regUVD_MPC_CHROMA_HITPEND 0x02cb +#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 +#define regUVD_MPC_CNTL 0x02cc +#define regUVD_MPC_CNTL_BASE_IDX 1 +#define regUVD_MPC_PITCH 0x02cd +#define regUVD_MPC_PITCH_BASE_IDX 1 +#define regUVD_MPC_SET_MUXA0 0x02ce +#define regUVD_MPC_SET_MUXA0_BASE_IDX 1 +#define regUVD_MPC_SET_MUXA1 0x02cf +#define regUVD_MPC_SET_MUXA1_BASE_IDX 1 +#define regUVD_MPC_SET_MUXB0 0x02d0 +#define regUVD_MPC_SET_MUXB0_BASE_IDX 1 +#define regUVD_MPC_SET_MUXB1 0x02d1 +#define regUVD_MPC_SET_MUXB1_BASE_IDX 1 +#define regUVD_MPC_SET_MUX 0x02d2 +#define regUVD_MPC_SET_MUX_BASE_IDX 1 +#define regUVD_MPC_SET_ALU 0x02d3 +#define regUVD_MPC_SET_ALU_BASE_IDX 1 +#define regUVD_MPC_PERF0 0x02d4 +#define regUVD_MPC_PERF0_BASE_IDX 1 +#define regUVD_MPC_PERF1 0x02d5 +#define regUVD_MPC_PERF1_BASE_IDX 1 +#define regUVD_MPC_IND_INDEX 0x02d6 +#define regUVD_MPC_IND_INDEX_BASE_IDX 1 +#define regUVD_MPC_IND_DATA 0x02d7 +#define regUVD_MPC_IND_DATA_BASE_IDX 1 + + +// addressBlock: uvd0_uvd_pg_dec +// base address: 0x1f800 +#define regUVD_PGFSM_CONFIG 0x0000 +#define regUVD_PGFSM_CONFIG_BASE_IDX 1 +#define regUVD_PGFSM_STATUS 0x0001 +#define regUVD_PGFSM_STATUS_BASE_IDX 1 +#define regUVD_POWER_STATUS 0x0004 +#define regUVD_POWER_STATUS_BASE_IDX 1 +#define regUVD_PG_IND_INDEX 0x0005 +#define regUVD_PG_IND_INDEX_BASE_IDX 1 +#define regUVD_PG_IND_DATA 0x0006 +#define regUVD_PG_IND_DATA_BASE_IDX 1 +#define regCC_UVD_HARVESTING 0x0007 +#define regCC_UVD_HARVESTING_BASE_IDX 1 +#define regUVD_JPEG_POWER_STATUS 0x000a +#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 +#define regUVD_DPG_LMA_CTL 0x0011 +#define regUVD_DPG_LMA_CTL_BASE_IDX 1 +#define regUVD_DPG_LMA_DATA 0x0012 +#define regUVD_DPG_LMA_DATA_BASE_IDX 1 +#define regUVD_DPG_LMA_MASK 0x0013 +#define regUVD_DPG_LMA_MASK_BASE_IDX 1 +#define regUVD_DPG_PAUSE 0x0014 +#define regUVD_DPG_PAUSE_BASE_IDX 1 +#define regUVD_SCRATCH1 0x0015 +#define regUVD_SCRATCH1_BASE_IDX 1 +#define regUVD_SCRATCH2 0x0016 +#define regUVD_SCRATCH2_BASE_IDX 1 +#define regUVD_SCRATCH3 0x0017 +#define regUVD_SCRATCH3_BASE_IDX 1 +#define regUVD_SCRATCH4 0x0018 +#define regUVD_SCRATCH4_BASE_IDX 1 +#define regUVD_SCRATCH5 0x0019 +#define regUVD_SCRATCH5_BASE_IDX 1 +#define regUVD_SCRATCH6 0x001a +#define regUVD_SCRATCH6_BASE_IDX 1 +#define regUVD_SCRATCH7 0x001b +#define regUVD_SCRATCH7_BASE_IDX 1 +#define regUVD_SCRATCH8 0x001c +#define regUVD_SCRATCH8_BASE_IDX 1 +#define regUVD_SCRATCH9 0x001d +#define regUVD_SCRATCH9_BASE_IDX 1 +#define regUVD_SCRATCH10 0x001e +#define regUVD_SCRATCH10_BASE_IDX 1 +#define regUVD_SCRATCH11 0x001f +#define regUVD_SCRATCH11_BASE_IDX 1 +#define regUVD_SCRATCH12 0x0020 +#define regUVD_SCRATCH12_BASE_IDX 1 +#define regUVD_SCRATCH13 0x0021 +#define regUVD_SCRATCH13_BASE_IDX 1 +#define regUVD_SCRATCH14 0x0022 +#define regUVD_SCRATCH14_BASE_IDX 1 +#define regUVD_FREE_COUNTER_REG 0x0024 +#define regUVD_FREE_COUNTER_REG_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 +#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 +#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define regUVD_PF_STATUS 0x0039 +#define regUVD_PF_STATUS_BASE_IDX 1 +#define regUVD_FW_VERSION 0x003a +#define regUVD_FW_VERSION_BASE_IDX 1 +#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x003c +#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 +#define regUVD_GFX8_ADDR_CONFIG 0x0049 +#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 +#define regUVD_GFX10_ADDR_CONFIG 0x004a +#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 +#define regUVD_GPCNT2_CNTL 0x004b +#define regUVD_GPCNT2_CNTL_BASE_IDX 1 +#define regUVD_GPCNT2_TARGET_LOWER 0x004c +#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 +#define regUVD_GPCNT2_STATUS_LOWER 0x004d +#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 +#define regUVD_GPCNT2_TARGET_UPPER 0x004e +#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 +#define regUVD_GPCNT2_STATUS_UPPER 0x004f +#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 +#define regUVD_GPCNT3_CNTL 0x0050 +#define regUVD_GPCNT3_CNTL_BASE_IDX 1 +#define regUVD_GPCNT3_TARGET_LOWER 0x0051 +#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 +#define regUVD_GPCNT3_STATUS_LOWER 0x0052 +#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 +#define regUVD_GPCNT3_TARGET_UPPER 0x0053 +#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 +#define regUVD_GPCNT3_STATUS_UPPER 0x0054 +#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 +#define regUVD_VCLK_DS_CNTL 0x0055 +#define regUVD_VCLK_DS_CNTL_BASE_IDX 1 +#define regUVD_DCLK_DS_CNTL 0x0056 +#define regUVD_DCLK_DS_CNTL_BASE_IDX 1 +#define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057 +#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 +#define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058 +#define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 +#define regUVD_RAS_JPEG0_STATUS 0x0059 +#define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1 +#define regUVD_RAS_JPEG1_STATUS 0x005a +#define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1 +#define regUVD_RAS_CNTL_PMI_ARB 0x005b +#define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1 + + +// addressBlock: uvd0_uvd_rbcdec +// base address: 0x20370 +#define regUVD_RBC_IB_SIZE 0x02dc +#define regUVD_RBC_IB_SIZE_BASE_IDX 1 +#define regUVD_RBC_IB_SIZE_UPDATE 0x02dd +#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define regUVD_RBC_RB_CNTL 0x02de +#define regUVD_RBC_RB_CNTL_BASE_IDX 1 +#define regUVD_RBC_RB_RPTR_ADDR 0x02df +#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 +#define regUVD_RBC_RB_RPTR 0x02e0 +#define regUVD_RBC_RB_RPTR_BASE_IDX 1 +#define regUVD_RBC_RB_WPTR 0x02e1 +#define regUVD_RBC_RB_WPTR_BASE_IDX 1 +#define regUVD_RBC_VCPU_ACCESS 0x02e2 +#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1 +#define regUVD_FW_SEMAPHORE_CNTL 0x02e3 +#define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1 +#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 +#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 +#define regUVD_RBC_RB_WPTR_CNTL 0x02e6 +#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 +#define regUVD_RBC_WPTR_STATUS 0x02e7 +#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1 +#define regUVD_RBC_WPTR_POLL_CNTL 0x02e8 +#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 +#define regUVD_RBC_WPTR_POLL_ADDR 0x02e9 +#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 +#define regUVD_SEMA_CMD 0x02ea +#define regUVD_SEMA_CMD_BASE_IDX 1 +#define regUVD_SEMA_ADDR_LOW 0x02eb +#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1 +#define regUVD_SEMA_ADDR_HIGH 0x02ec +#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1 +#define regUVD_ENGINE_CNTL 0x02ed +#define regUVD_ENGINE_CNTL_BASE_IDX 1 +#define regUVD_SEMA_TIMEOUT_STATUS 0x02ee +#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 +#define regUVD_SEMA_CNTL 0x02ef +#define regUVD_SEMA_CNTL_BASE_IDX 1 +#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 +#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 +#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 +#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 +#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define regUVD_JOB_START 0x02f3 +#define regUVD_JOB_START_BASE_IDX 1 +#define regUVD_RBC_BUF_STATUS 0x02f4 +#define regUVD_RBC_BUF_STATUS_BASE_IDX 1 +#define regUVD_RBC_SWAP_CNTL 0x02f5 +#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1 + + +// addressBlock: uvd0_uvddec +// base address: 0x1fa00 +#define regUVD_STATUS 0x0080 +#define regUVD_STATUS_BASE_IDX 1 +#define regUVD_ENC_PIPE_BUSY 0x0081 +#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 +#define regUVD_FW_POWER_STATUS 0x0082 +#define regUVD_FW_POWER_STATUS_BASE_IDX 1 +#define regUVD_CNTL 0x0083 +#define regUVD_CNTL_BASE_IDX 1 +#define regUVD_SOFT_RESET 0x0084 +#define regUVD_SOFT_RESET_BASE_IDX 1 +#define regUVD_SOFT_RESET2 0x0085 +#define regUVD_SOFT_RESET2_BASE_IDX 1 +#define regUVD_MMSCH_SOFT_RESET 0x0086 +#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 +#define regUVD_WIG_CTRL 0x0087 +#define regUVD_WIG_CTRL_BASE_IDX 1 +#define regUVD_CGC_GATE 0x0088 +#define regUVD_CGC_GATE_BASE_IDX 1 +#define regUVD_CGC_STATUS 0x0089 +#define regUVD_CGC_STATUS_BASE_IDX 1 +#define regUVD_CGC_CTRL 0x008a +#define regUVD_CGC_CTRL_BASE_IDX 1 +#define regUVD_CGC_UDEC_STATUS 0x008b +#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 +#define regUVD_SUVD_CGC_GATE 0x008c +#define regUVD_SUVD_CGC_GATE_BASE_IDX 1 +#define regUVD_SUVD_CGC_STATUS 0x008d +#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 +#define regUVD_SUVD_CGC_CTRL 0x008e +#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_CMD 0x008f +#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_DATA0 0x0090 +#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_DATA1 0x0091 +#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define regUVD_GPCOM_SYS_CMD 0x0092 +#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 +#define regUVD_GPCOM_SYS_DATA0 0x0093 +#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 +#define regUVD_GPCOM_SYS_DATA1 0x0094 +#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 +#define regUVD_VCPU_INT_EN 0x0095 +#define regUVD_VCPU_INT_EN_BASE_IDX 1 +#define regUVD_VCPU_INT_STATUS 0x0096 +#define regUVD_VCPU_INT_STATUS_BASE_IDX 1 +#define regUVD_VCPU_INT_ACK 0x0097 +#define regUVD_VCPU_INT_ACK_BASE_IDX 1 +#define regUVD_VCPU_INT_ROUTE 0x0098 +#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 +#define regUVD_DRV_FW_MSG 0x0099 +#define regUVD_DRV_FW_MSG_BASE_IDX 1 +#define regUVD_FW_DRV_MSG_ACK 0x009a +#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 +#define regUVD_SUVD_INT_EN 0x009b +#define regUVD_SUVD_INT_EN_BASE_IDX 1 +#define regUVD_SUVD_INT_STATUS 0x009c +#define regUVD_SUVD_INT_STATUS_BASE_IDX 1 +#define regUVD_SUVD_INT_ACK 0x009d +#define regUVD_SUVD_INT_ACK_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_EN 0x009e +#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_STATUS 0x009f +#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_ACK 0x00a0 +#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 +#define regUVD_MASTINT_EN 0x00a1 +#define regUVD_MASTINT_EN_BASE_IDX 1 +#define regUVD_SYS_INT_EN 0x00a2 +#define regUVD_SYS_INT_EN_BASE_IDX 1 +#define regUVD_SYS_INT_STATUS 0x00a3 +#define regUVD_SYS_INT_STATUS_BASE_IDX 1 +#define regUVD_SYS_INT_ACK 0x00a4 +#define regUVD_SYS_INT_ACK_BASE_IDX 1 +#define regUVD_JOB_DONE 0x00a5 +#define regUVD_JOB_DONE_BASE_IDX 1 +#define regUVD_CBUF_ID 0x00a6 +#define regUVD_CBUF_ID_BASE_IDX 1 +#define regUVD_CONTEXT_ID 0x00a7 +#define regUVD_CONTEXT_ID_BASE_IDX 1 +#define regUVD_CONTEXT_ID2 0x00a8 +#define regUVD_CONTEXT_ID2_BASE_IDX 1 +#define regUVD_NO_OP 0x00a9 +#define regUVD_NO_OP_BASE_IDX 1 +#define regUVD_RB_BASE_LO 0x00aa +#define regUVD_RB_BASE_LO_BASE_IDX 1 +#define regUVD_RB_BASE_HI 0x00ab +#define regUVD_RB_BASE_HI_BASE_IDX 1 +#define regUVD_RB_SIZE 0x00ac +#define regUVD_RB_SIZE_BASE_IDX 1 +#define regUVD_RB_RPTR 0x00ad +#define regUVD_RB_RPTR_BASE_IDX 1 +#define regUVD_RB_WPTR 0x00ae +#define regUVD_RB_WPTR_BASE_IDX 1 +#define regUVD_RB_BASE_LO2 0x00af +#define regUVD_RB_BASE_LO2_BASE_IDX 1 +#define regUVD_RB_BASE_HI2 0x00b0 +#define regUVD_RB_BASE_HI2_BASE_IDX 1 +#define regUVD_RB_SIZE2 0x00b1 +#define regUVD_RB_SIZE2_BASE_IDX 1 +#define regUVD_RB_RPTR2 0x00b2 +#define regUVD_RB_RPTR2_BASE_IDX 1 +#define regUVD_RB_WPTR2 0x00b3 +#define regUVD_RB_WPTR2_BASE_IDX 1 +#define regUVD_RB_BASE_LO3 0x00b4 +#define regUVD_RB_BASE_LO3_BASE_IDX 1 +#define regUVD_RB_BASE_HI3 0x00b5 +#define regUVD_RB_BASE_HI3_BASE_IDX 1 +#define regUVD_RB_SIZE3 0x00b6 +#define regUVD_RB_SIZE3_BASE_IDX 1 +#define regUVD_RB_RPTR3 0x00b7 +#define regUVD_RB_RPTR3_BASE_IDX 1 +#define regUVD_RB_WPTR3 0x00b8 +#define regUVD_RB_WPTR3_BASE_IDX 1 +#define regUVD_RB_BASE_LO4 0x00b9 +#define regUVD_RB_BASE_LO4_BASE_IDX 1 +#define regUVD_RB_BASE_HI4 0x00ba +#define regUVD_RB_BASE_HI4_BASE_IDX 1 +#define regUVD_RB_SIZE4 0x00bb +#define regUVD_RB_SIZE4_BASE_IDX 1 +#define regUVD_RB_RPTR4 0x00bc +#define regUVD_RB_RPTR4_BASE_IDX 1 +#define regUVD_RB_WPTR4 0x00bd +#define regUVD_RB_WPTR4_BASE_IDX 1 +#define regUVD_OUT_RB_BASE_LO 0x00be +#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 +#define regUVD_OUT_RB_BASE_HI 0x00bf +#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 +#define regUVD_OUT_RB_SIZE 0x00c0 +#define regUVD_OUT_RB_SIZE_BASE_IDX 1 +#define regUVD_OUT_RB_RPTR 0x00c1 +#define regUVD_OUT_RB_RPTR_BASE_IDX 1 +#define regUVD_OUT_RB_WPTR 0x00c2 +#define regUVD_OUT_RB_WPTR_BASE_IDX 1 +#define regUVD_IOV_MAILBOX 0x00c4 +#define regUVD_IOV_MAILBOX_BASE_IDX 1 +#define regUVD_IOV_MAILBOX_RESP 0x00c5 +#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 +#define regUVD_RB_ARB_CTRL 0x00c6 +#define regUVD_RB_ARB_CTRL_BASE_IDX 1 +#define regUVD_CTX_INDEX 0x00c7 +#define regUVD_CTX_INDEX_BASE_IDX 1 +#define regUVD_CTX_DATA 0x00c8 +#define regUVD_CTX_DATA_BASE_IDX 1 +#define regUVD_CXW_WR 0x00c9 +#define regUVD_CXW_WR_BASE_IDX 1 +#define regUVD_CXW_WR_INT_ID 0x00ca +#define regUVD_CXW_WR_INT_ID_BASE_IDX 1 +#define regUVD_CXW_WR_INT_CTX_ID 0x00cb +#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 +#define regUVD_CXW_INT_ID 0x00cc +#define regUVD_CXW_INT_ID_BASE_IDX 1 +#define regUVD_MPEG2_ERROR 0x00cd +#define regUVD_MPEG2_ERROR_BASE_IDX 1 +#define regUVD_TOP_CTRL 0x00cf +#define regUVD_TOP_CTRL_BASE_IDX 1 +#define regUVD_YBASE 0x00d0 +#define regUVD_YBASE_BASE_IDX 1 +#define regUVD_UVBASE 0x00d1 +#define regUVD_UVBASE_BASE_IDX 1 +#define regUVD_PITCH 0x00d2 +#define regUVD_PITCH_BASE_IDX 1 +#define regUVD_WIDTH 0x00d3 +#define regUVD_WIDTH_BASE_IDX 1 +#define regUVD_HEIGHT 0x00d4 +#define regUVD_HEIGHT_BASE_IDX 1 +#define regUVD_PICCOUNT 0x00d5 +#define regUVD_PICCOUNT_BASE_IDX 1 +#define regUVD_MPRD_INITIAL_XY 0x00d6 +#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 +#define regUVD_MPEG2_CTRL 0x00d7 +#define regUVD_MPEG2_CTRL_BASE_IDX 1 +#define regUVD_MB_CTL_BUF_BASE 0x00d8 +#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 +#define regUVD_PIC_CTL_BUF_BASE 0x00d9 +#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 +#define regUVD_DXVA_BUF_SIZE 0x00da +#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 +#define regUVD_SCRATCH_NP 0x00db +#define regUVD_SCRATCH_NP_BASE_IDX 1 +#define regUVD_CLK_SWT_HANDSHAKE 0x00dc +#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 +#define regUVD_VERSION 0x00dd +#define regUVD_VERSION_BASE_IDX 1 +#define regUVD_GP_SCRATCH0 0x00de +#define regUVD_GP_SCRATCH0_BASE_IDX 1 +#define regUVD_GP_SCRATCH1 0x00df +#define regUVD_GP_SCRATCH1_BASE_IDX 1 +#define regUVD_GP_SCRATCH2 0x00e0 +#define regUVD_GP_SCRATCH2_BASE_IDX 1 +#define regUVD_GP_SCRATCH3 0x00e1 +#define regUVD_GP_SCRATCH3_BASE_IDX 1 +#define regUVD_GP_SCRATCH4 0x00e2 +#define regUVD_GP_SCRATCH4_BASE_IDX 1 +#define regUVD_GP_SCRATCH5 0x00e3 +#define regUVD_GP_SCRATCH5_BASE_IDX 1 +#define regUVD_GP_SCRATCH6 0x00e4 +#define regUVD_GP_SCRATCH6_BASE_IDX 1 +#define regUVD_GP_SCRATCH7 0x00e5 +#define regUVD_GP_SCRATCH7_BASE_IDX 1 +#define regUVD_GP_SCRATCH8 0x00e6 +#define regUVD_GP_SCRATCH8_BASE_IDX 1 +#define regUVD_GP_SCRATCH9 0x00e7 +#define regUVD_GP_SCRATCH9_BASE_IDX 1 +#define regUVD_GP_SCRATCH10 0x00e8 +#define regUVD_GP_SCRATCH10_BASE_IDX 1 +#define regUVD_GP_SCRATCH11 0x00e9 +#define regUVD_GP_SCRATCH11_BASE_IDX 1 +#define regUVD_GP_SCRATCH12 0x00ea +#define regUVD_GP_SCRATCH12_BASE_IDX 1 +#define regUVD_GP_SCRATCH13 0x00eb +#define regUVD_GP_SCRATCH13_BASE_IDX 1 +#define regUVD_GP_SCRATCH14 0x00ec +#define regUVD_GP_SCRATCH14_BASE_IDX 1 +#define regUVD_GP_SCRATCH15 0x00ed +#define regUVD_GP_SCRATCH15_BASE_IDX 1 +#define regUVD_GP_SCRATCH16 0x00ee +#define regUVD_GP_SCRATCH16_BASE_IDX 1 +#define regUVD_GP_SCRATCH17 0x00ef +#define regUVD_GP_SCRATCH17_BASE_IDX 1 +#define regUVD_GP_SCRATCH18 0x00f0 +#define regUVD_GP_SCRATCH18_BASE_IDX 1 +#define regUVD_GP_SCRATCH19 0x00f1 +#define regUVD_GP_SCRATCH19_BASE_IDX 1 +#define regUVD_GP_SCRATCH20 0x00f2 +#define regUVD_GP_SCRATCH20_BASE_IDX 1 +#define regUVD_GP_SCRATCH21 0x00f3 +#define regUVD_GP_SCRATCH21_BASE_IDX 1 +#define regUVD_GP_SCRATCH22 0x00f4 +#define regUVD_GP_SCRATCH22_BASE_IDX 1 +#define regUVD_GP_SCRATCH23 0x00f5 +#define regUVD_GP_SCRATCH23_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h new file mode 100644 index 0000000000000000000000000000000000000000..f61a5bbb1973ebba8e1945f285a9559eabec929d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h @@ -0,0 +1,4535 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _vcn_2_6_0_SH_MASK_HEADER +#define _vcn_2_6_0_SH_MASK_HEADER + + +// addressBlock: uvd0_ecpudec +//UVD_VCPU_CACHE_OFFSET0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET1 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE1 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET2 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE2 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET3 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE3 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET4 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE4 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET5 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE5 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET6 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE6 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET7 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE7 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET8 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE8 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET1 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE1 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CNTL +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L +#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L +//UVD_VCPU_PRID +#define UVD_VCPU_PRID__PRID__SHIFT 0x0 +#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL +//UVD_VCPU_TRCE +#define UVD_VCPU_TRCE__PC__SHIFT 0x0 +#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL +//UVD_VCPU_TRCE_RD +#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 +#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL +//UVD_VCPU_IND_INDEX +#define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL +//UVD_VCPU_IND_DATA +#define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 +#define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_jpegnpdec +//UVD_JPEG_CNTL +#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 +#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 +#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 +#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L +#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L +#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L +//UVD_JPEG_RB_BASE +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 +#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL +#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L +//UVD_JPEG_RB_WPTR +#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_RPTR +#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_SIZE +#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L +//UVD_JPEG_DEC_CNT +#define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 +#define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL +//UVD_JPEG_SPS_INFO +#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 +#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 +#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL +#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L +//UVD_JPEG_SPS1_INFO +#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 +#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 +#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 +#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L +#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L +#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L +//UVD_JPEG_RE_TIMER +#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 +#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 +#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL +#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L +//UVD_JPEG_DEC_SCRATCH0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL +//UVD_JPEG_INT_EN +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 +#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 +#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 +#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 +#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc +#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd +#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L +#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L +#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L +#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L +#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L +#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L +#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L +//UVD_JPEG_INT_STAT +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 +#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 +#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 +#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd +#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L +#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L +#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L +#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L +#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L +//UVD_JPEG_TIER_CNTL0 +#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 +#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 +#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 +#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 +#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb +#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe +#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 +#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 +#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 +#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a +#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c +#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e +#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L +#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL +#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L +#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L +#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L +#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L +#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L +#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L +#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L +#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L +#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L +#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L +#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L +//UVD_JPEG_TIER_CNTL1 +#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 +#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL +#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L +//UVD_JPEG_TIER_CNTL2 +#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 +#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 +#define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 +#define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 +#define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 +#define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa +#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe +#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 +#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L +#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L +#define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL +#define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L +#define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L +#define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L +#define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L +#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L +#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L +//UVD_JPEG_TIER_STATUS +#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 +#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 +#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L +#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L +//UVD_JPEG_OUTBUF_CNTL +#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 +#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L +#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L +//UVD_JPEG_OUTBUF_WPTR +#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL +//UVD_JPEG_OUTBUF_RPTR +#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL +//UVD_JPEG_PITCH +#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 +#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL +//UVD_JPEG_UV_PITCH +#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 +#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL +//JPEG_DEC_Y_GFX8_TILING_SURFACE +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_UV_GFX8_TILING_SURFACE +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_GFX8_ADDR_CONFIG +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//JPEG_DEC_Y_GFX10_TILING_SURFACE +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_UV_GFX10_TILING_SURFACE +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_GFX10_ADDR_CONFIG +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//JPEG_DEC_ADDR_MODE +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L +//UVD_JPEG_OUTPUT_XY +#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 +#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 +#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL +#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L +//UVD_JPEG_GPCOM_CMD +#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL +//UVD_JPEG_GPCOM_DATA0 +#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_GPCOM_DATA1 +#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_INDEX +#define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 +#define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL +//UVD_JPEG_DATA +#define UVD_JPEG_DATA__DATA__SHIFT 0x0 +#define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_JPEG_SCRATCH1 +#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 +#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL +//UVD_JPEG_DEC_SOFT_RST +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L + + +// addressBlock: uvd0_lmi_adpdec +//UVD_LMI_RE_64BIT_BAR_LOW +#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RE_64BIT_BAR_HIGH +#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_IT_64BIT_BAR_LOW +#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_IT_64BIT_BAR_HIGH +#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MP_64BIT_BAR_LOW +#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MP_64BIT_BAR_HIGH +#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_CM_64BIT_BAR_LOW +#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_CM_64BIT_BAR_HIGH +#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_DB_64BIT_BAR_LOW +#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_DB_64BIT_BAR_HIGH +#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_DBW_64BIT_BAR_LOW +#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_DBW_64BIT_BAR_HIGH +#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_IDCT_64BIT_BAR_LOW +#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_IDCT_64BIT_BAR_HIGH +#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S0_64BIT_BAR_LOW +#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S0_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S1_64BIT_BAR_LOW +#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S1_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_DBW_64BIT_BAR_LOW +#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPC_64BIT_BAR_LOW +#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPC_64BIT_BAR_HIGH +#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_LOW +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_LOW +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_LOW +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_HIGH +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_CENC_64BIT_BAR_LOW +#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_CENC_64BIT_BAR_HIGH +#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_SRE_64BIT_BAR_LOW +#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_SRE_64BIT_BAR_HIGH +#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_REF_64BIT_BAR_LOW +#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_REF_64BIT_BAR_HIGH +#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_DBW_64BIT_BAR_LOW +#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_DBW_64BIT_BAR_HIGH +#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP0_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP1_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP2_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP3_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD0_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD1_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD2_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD3_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD4_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR_64BIT_BAR_LOW +#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH +#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_SPH_64BIT_BAR_HIGH +#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC_VMID +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L +//UVD_LMI_MMSCH_CTRL +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 +#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L +#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L +//UVD_MMSCH_LMI_STATUS +#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 +#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd +#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe +#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L +#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L +#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L +//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_ADP_ATOMIC_CONFIG +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L +//UVD_LMI_ARB_CTRL2 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L +//UVD_LMI_VCPU_CACHE_VMIDS_MULTI +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L +//UVD_LMI_VCPU_NC_VMIDS_MULTI +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L +//UVD_LMI_LAT_CTRL +#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 +#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 +#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 +#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb +#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 +#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL +#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L +#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L +#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L +#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L +//UVD_LMI_LAT_CNTR +#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 +#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 +#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL +#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L +//UVD_LMI_AVG_LAT_CNTR +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L +//UVD_LMI_SPH +#define UVD_LMI_SPH__ADDR__SHIFT 0x0 +#define UVD_LMI_SPH__STS__SHIFT 0x1c +#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e +#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f +#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL +#define UVD_LMI_SPH__STS_MASK 0x30000000L +#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L +#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L +//UVD_LMI_VCPU_CACHE_VMID +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_LMI_CTRL2 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 +#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a +#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L +#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L +#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L +//UVD_LMI_URGENT_CTRL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L +//UVD_LMI_CTRL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b +#define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c +#define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d +#define UVD_LMI_CTRL__RFU__SHIFT 0x1e +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L +#define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L +#define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L +#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L +//UVD_LMI_STATUS +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 +#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L +#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L +//UVD_LMI_PERFMON_CTRL +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L +//UVD_LMI_PERFMON_COUNT_LO +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_LMI_PERFMON_COUNT_HI +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_LMI_ADP_SWAP_CNTL +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 +#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L +#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L +#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L +#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L +#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L +#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L +#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L +#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L +#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L +//UVD_LMI_RBC_RB_VMID +#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL +//UVD_LMI_RBC_IB_VMID +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL +//UVD_LMI_MC_CREDITS +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L +//UVD_LMI_ADP_IND_INDEX +#define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL +//UVD_LMI_ADP_IND_DATA +#define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 +#define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL +//VCN_RAS_CNTL +#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 +#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 +#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 +#define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5 +#define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 +#define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9 +#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc +#define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 +#define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11 +#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L +#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L +#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L +#define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L +#define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L +#define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L +#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L +#define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L +#define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L + + +// addressBlock: uvd0_mmsch_dec +//MMSCH_UCODE_ADDR +#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 +#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f +#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL +#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L +//MMSCH_UCODE_DATA +#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//MMSCH_SRAM_ADDR +#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 +#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f +#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL +#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L +//MMSCH_SRAM_DATA +#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 +#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_SRAM_OFFSET +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L +//MMSCH_DB_SRAM_OFFSET +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L +//MMSCH_CTX_SRAM_OFFSET +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L +//MMSCH_INTR +#define MMSCH_INTR__INTR__SHIFT 0x0 +#define MMSCH_INTR__INTR_MASK 0x00001FFFL +//MMSCH_INTR_ACK +#define MMSCH_INTR_ACK__INTR__SHIFT 0x0 +#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL +//MMSCH_INTR_STATUS +#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 +#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL +//MMSCH_VF_VMID +#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 +#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 +#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL +#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L +//MMSCH_VF_CTX_ADDR_LO +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L +//MMSCH_VF_CTX_ADDR_HI +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL +//MMSCH_VF_CTX_SIZE +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL +//MMSCH_VF_GPCOM_ADDR_LO +#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 +#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L +//MMSCH_VF_GPCOM_ADDR_HI +#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 +#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL +//MMSCH_VF_GPCOM_SIZE +#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 +#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_HOST +#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_RESP +#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_0 +#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_0_RESP +#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_1 +#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_1_RESP +#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_CNTL +#define MMSCH_CNTL__CLK_EN__SHIFT 0x0 +#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 +#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 +#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 +#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa +#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c +#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L +#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L +#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L +#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L +#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L +#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L +#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L +//MMSCH_NONCACHE_OFFSET0 +#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 +#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL +//MMSCH_NONCACHE_SIZE0 +#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 +#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL +//MMSCH_NONCACHE_OFFSET1 +#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 +#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL +//MMSCH_NONCACHE_SIZE1 +#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 +#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL +//MMSCH_PROC_STATE1 +#define MMSCH_PROC_STATE1__PC__SHIFT 0x0 +#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL +//MMSCH_LAST_MC_ADDR +#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 +#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f +#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL +#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L +//MMSCH_LAST_MEM_ACCESS_HI +#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc +#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L +//MMSCH_LAST_MEM_ACCESS_LO +#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 +#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_0 +#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_1 +#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_0 +#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_0 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_0 +#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_0 +#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_0 +#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_0 +#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_1 +#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_1 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_1 +#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_1 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_1 +#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_1 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_1 +#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_1 +#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_1 +#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_CNTXT +#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 +#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 +#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa +#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL +#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L +#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L +//MMSCH_SCRATCH_2 +#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 +#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_3 +#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 +#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_4 +#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 +#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_5 +#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 +#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_6 +#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 +#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_7 +#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 +#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL +//MMSCH_VFID_FIFO_HEAD_0 +#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_0 +#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL +//MMSCH_VFID_FIFO_HEAD_1 +#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_1 +#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL +//MMSCH_NACK_STATUS +#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 +#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 +#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L +#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL +//MMSCH_VF_MAILBOX0_DATA +#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX1_DATA +#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_IP_0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_SCH_BLOCK_IP_1 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_1 +#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_CNTXT_IP +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L +//MMSCH_GPUIOV_SCH_BLOCK_2 +#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_2 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_2 +#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_2 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_2 +#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_2 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_2 +#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_2 +#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_2 +#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_IP_2 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_2 +#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L +//MMSCH_VFID_FIFO_HEAD_2 +#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_2 +#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL +//MMSCH_VM_BUSY_STATUS_0 +#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL +//MMSCH_VM_BUSY_STATUS_1 +#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL +//MMSCH_VM_BUSY_STATUS_2 +#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jmi_dec +//UVD_JADP_MCIF_URGENT_CTRL +#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 +#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb +#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 +#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a +#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL +#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L +#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L +#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L +//UVD_JMI_URGENT_CTRL +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L +//UVD_JPEG_DEC_PF_CTRL +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L +//UVD_JPEG_ENC_PF_CTRL +#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 +#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 +#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L +#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L +//UVD_JMI_CTRL +#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 +#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 +#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 +#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 +#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 +#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L +#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L +#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L +#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L +#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L +//UVD_LMI_JRBC_CTRL +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_JPEG_CTRL +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_JMI_EJRBC_CTRL +#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_EJPEG_CTRL +#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_JMI_SCALER_CTRL +#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L +//JPEG_LMI_DROP +#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 +#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 +#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 +#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 +#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L +#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L +#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L +#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L +//UVD_JMI_EJPEG_DROP +#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 +#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 +#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 +#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 +#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 +#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 +#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L +#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L +#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L +#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L +#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L +#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L +//JPEG_MEMCHECK_CLAMPING +#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd +#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe +#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 +#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 +#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 +#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a +#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f +#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L +#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L +#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L +#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L +#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L +#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L +#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L +//UVD_JMI_EJPEG_MEMCHECK_CLAMPING +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L +#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L +//UVD_LMI_JRBC_IB_VMID +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JRBC_RB_VMID +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JPEG_VMID +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JRBC_IB_VMID +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JRBC_RB_VMID +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 +#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L +#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JPEG_VMID +#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf +#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 +#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 +#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L +#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L +#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L +//UVD_JMI_EJPEG_RAS_CNTL +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0 +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1 +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2 +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3 +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4 +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L +#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L +//JPEG_MEMCHECK_SAFE_ADDR +#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 +#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL +//JPEG_MEMCHECK_SAFE_ADDR_64BIT +#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 +#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL +//UVD_JMI_LAT_CTRL +#define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 +#define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 +#define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 +#define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa +#define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb +#define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 +#define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL +#define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L +#define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L +#define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L +#define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L +#define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L +//UVD_JMI_LAT_CNTR +#define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 +#define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 +#define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL +#define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L +//UVD_JMI_AVG_LAT_CNTR +#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 +#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L +//UVD_JMI_PERFMON_CTRL +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L +//UVD_JMI_PERFMON_COUNT_LO +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_JMI_PERFMON_COUNT_HI +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_JMI_CLEAN_STATUS +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 +#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 +#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 +#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 +#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 +#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 +#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 +#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa +#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb +#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc +#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd +#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe +#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf +#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L +#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L +#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L +#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L +#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L +#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L +#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L +#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L +#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L +#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L +#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L +#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L +#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L +#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L +//UVD_LMI_JPEG_READ_64BIT_BAR_LOW +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_PEL_RD_64BIT_BAR_LOW +#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_PEL_RD_64BIT_BAR_HIGH +#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_BS_WR_64BIT_BAR_LOW +#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_BS_WR_64BIT_BAR_HIGH +#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_SCALAR_RD_64BIT_BAR_LOW +#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH +#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_SCALAR_WR_64BIT_BAR_LOW +#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH +#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_VMID +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL +//UVD_LMI_ENC_JPEG_PREEMPT_VMID +#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 +#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL +//UVD_LMI_JPEG2_VMID +#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 +#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 +#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL +#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L +//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW +#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH +#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_CTRL2 +#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L +//UVD_JMI_DEC_SWAP_CNTL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L +//UVD_JMI_ENC_SWAP_CNTL +#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa +#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc +#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe +#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 +#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L +#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L +#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L +#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L +#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L +//UVD_JMI_CNTL +#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 +#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L +//UVD_JMI_ATOMIC_CNTL +#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 +#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb +#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L +#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L +//UVD_JMI_ATOMIC_CNTL2 +#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 +#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 +#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L +#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L +//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW +#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH +#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//JPEG2_LMI_DROP +#define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 +#define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 +#define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L +#define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L +//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_DEC_SWAP_CNTL2 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL +//UVD_JMI_DJPEG_RAS_CNTL +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0 +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1 +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2 +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3 +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4 +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L +#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L + + +// addressBlock: uvd0_uvd_jpeg_common_dec +//JPEG_SOFT_RESET_STATUS +#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 +#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 +#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 +#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L +#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L +#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L +//JPEG_SYS_INT_EN +#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x7 +#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x8 +#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L +#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000080L +#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000100L +//JPEG_SYS_INT_STATUS +#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x7 +#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x8 +#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L +#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000080L +#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000100L +//JPEG_SYS_INT_ACK +#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x7 +#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x8 +#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L +#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000080L +#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000100L +//JPEG_MEMCHECK_SYS_INT_EN +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 +#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 +#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L +#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L +#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L +//JPEG_MEMCHECK_SYS_INT_STAT +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 +#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf +#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L +#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L +#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L +#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L +#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L +#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L +#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L +#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L +//JPEG_MEMCHECK_SYS_INT_ACK +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 +#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf +#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L +#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L +#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L +#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L +#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L +#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L +#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L +#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L +//JPEG_MASTINT_EN +#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//JPEG_IH_CTRL +#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 +#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 +#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 +#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 +#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 +#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 +#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L +#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L +#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L +#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L +#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L +#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L +//JRBBM_ARB_CTRL +#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 +#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 +#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 +#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L +#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L +#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L + + +// addressBlock: uvd0_uvd_jpeg_common_sclk_dec +//JPEG_CGC_GATE +#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 +#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 +#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 +#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 +#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 +#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L +#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L +#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L +#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L +#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L +//JPEG_CGC_CTRL +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 +#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 +#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa +#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb +#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc +#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 +#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 +#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 +#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 +#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL +#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L +#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L +#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L +#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L +#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L +#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L +#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L +#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L +#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L +//JPEG_CGC_STATUS +#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 +#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 +#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 +#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 +#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L +#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L +#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L +#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L +//JPEG_COMN_CGC_MEM_CTRL +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 +#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L +#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L +#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L +//JPEG_DEC_CGC_MEM_CTRL +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L +//JPEG2_DEC_CGC_MEM_CTRL +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L +//JPEG_ENC_CGC_MEM_CTRL +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L +//JPEG_SOFT_RESET2 +#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 +#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L +//JPEG_PERF_BANK_CONF +#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 +#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 +#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 +#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL +#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L +#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L +//JPEG_PERF_BANK_EVENT_SEL +#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 +#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 +#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 +#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 +#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL +#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L +#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L +#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L +//JPEG_PERF_BANK_COUNT0 +#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT1 +#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT2 +#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT3 +#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jpeg_enc_dec +//UVD_JPEG_ENC_INT_EN +#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 +#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 +#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 +#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 +#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 +#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 +#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L +#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L +#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L +#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L +#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L +#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L +#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L +//UVD_JPEG_ENC_INT_STATUS +#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 +#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 +#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 +#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 +#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 +#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 +#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 +#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L +#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L +#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L +#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L +#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L +#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L +#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L +//UVD_JPEG_ENC_ENGINE_CNTL +#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 +#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 +#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 +#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 +#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 +#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 +#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L +#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L +#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L +#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L +#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L +#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L +//UVD_JPEG_ENC_SCRATCH1 +#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 +#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec +//UVD_JPEG_ENC_SPS_INFO +#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0 +#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3 +#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4 +#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L +#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L +#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L +//UVD_JPEG_ENC_SPS_INFO1 +#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0 +#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10 +#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL +#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L +//UVD_JPEG_ENC_TBL_SIZE +#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6 +#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L +//UVD_JPEG_ENC_TBL_CNTL +#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0 +#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1 +#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2 +#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4 +#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L +#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L +#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL +#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L +//UVD_JPEG_ENC_MC_REQ_CNTL +#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL +//UVD_JPEG_ENC_STATUS +#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 +#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 +#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 +#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 +#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L +#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L +#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L +#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L +//UVD_JPEG_ENC_PITCH +#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 +#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 +#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL +#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L +//UVD_JPEG_ENC_LUMA_BASE +#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_CHROMAU_BASE +#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_CHROMAV_BASE +#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL +//JPEG_ENC_Y_GFX10_TILING_SURFACE +#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_ENC_UV_GFX10_TILING_SURFACE +#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_ENC_GFX10_ADDR_CONFIG +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//JPEG_ENC_ADDR_MODE +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 +#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL +#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L +//UVD_JPEG_ENC_GPCOM_CMD +#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL +//UVD_JPEG_ENC_GPCOM_DATA0 +#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_GPCOM_DATA1 +#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_TBL_DAT0 +#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0 +#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL +//UVD_JPEG_TBL_DAT1 +#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0 +#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL +//UVD_JPEG_TBL_IDX +#define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0 +#define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL +//UVD_JPEG_ENC_CGC_CNTL +#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L +//UVD_JPEG_ENC_SCRATCH0 +#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_SOFT_RST +#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 +#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 +#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L +#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L + + +// addressBlock: uvd0_uvd_jrbc_dec +//UVD_JRBC_RB_WPTR +#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_CNTL +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC_IB_SIZE +#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_URGENT_CNTL +#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC_RB_REF_DATA +#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_SOFT_RESET +#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC_STATUS +#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC_RB_RPTR +#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_IB_REF_DATA +#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JPEG_PREEMPT_CMD +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC_RB_SIZE +#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC_SCRATCH0 +#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jrbc_enc_dec +//UVD_JRBC_ENC_RB_WPTR +#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_ENC_RB_CNTL +#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC_ENC_IB_SIZE +#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_ENC_URGENT_CNTL +#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC_ENC_RB_REF_DATA +#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC_ENC_RB_COND_RD_TIMER +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_ENC_SOFT_RESET +#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC_ENC_STATUS +#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC_ENC_RB_RPTR +#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC_ENC_RB_BUF_STATUS +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_ENC_IB_BUF_STATUS +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_ENC_IB_SIZE_UPDATE +#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_ENC_IB_COND_RD_TIMER +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_ENC_IB_REF_DATA +#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_PREEMPT_CMD +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC_ENC_RB_SIZE +#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC_ENC_SCRATCH0 +#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_mpcdec +//UVD_MP_SWAP_CNTL +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L +//UVD_MP_SWAP_CNTL2 +#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L +//UVD_MPC_LUMA_SRCH +#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_LUMA_HIT +#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_LUMA_HITPEND +#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_SRCH +#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_HIT +#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_HITPEND +#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CNTL +#define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 +#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 +#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 +#define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L +#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L +#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L +#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L +//UVD_MPC_PITCH +#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 +#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL +//UVD_MPC_SET_MUXA0 +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXA1 +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L +//UVD_MPC_SET_MUXB0 +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXB1 +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L +//UVD_MPC_SET_MUX +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L +#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L +#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L +//UVD_MPC_SET_ALU +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L +#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L +//UVD_MPC_PERF0 +#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 +#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL +//UVD_MPC_PERF1 +#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 +#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL +//UVD_MPC_IND_INDEX +#define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL +//UVD_MPC_IND_DATA +#define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 +#define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_pg_dec +//UVD_PGFSM_CONFIG +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 +#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L +#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L +//UVD_PGFSM_STATUS +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 +#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L +#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L +//UVD_POWER_STATUS +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L +#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L +#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L +//UVD_PG_IND_INDEX +#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL +//UVD_PG_IND_DATA +#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 +#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL +//CC_UVD_HARVESTING +#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 +#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 +#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L +#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L +//UVD_JPEG_POWER_STATUS +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L +//UVD_DPG_LMA_CTL +#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 +#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 +#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 +#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L +#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L +#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L +//UVD_DPG_LMA_DATA +#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 +#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL +//UVD_DPG_LMA_MASK +#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 +#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL +//UVD_DPG_PAUSE +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L +//UVD_SCRATCH1 +#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 +#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH2 +#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 +#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH3 +#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 +#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH4 +#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 +#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH5 +#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 +#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH6 +#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 +#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH7 +#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 +#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH8 +#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 +#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH9 +#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 +#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH10 +#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 +#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH11 +#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 +#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH12 +#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 +#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH13 +#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 +#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH14 +#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 +#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL +//UVD_FREE_COUNTER_REG +#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 +#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_DPG_VCPU_CACHE_OFFSET0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_VMID +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_PF_STATUS +#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 +#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 +#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 +#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 +#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe +#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 +#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L +#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L +#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L +#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L +#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L +#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L +//UVD_FW_VERSION +#define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 +#define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL +//UVD_DPG_CLK_EN_VCPU_REPORT +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL +//UVD_GFX8_ADDR_CONFIG +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//UVD_GFX10_ADDR_CONFIG +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//UVD_GPCNT2_CNTL +#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L +//UVD_GPCNT2_TARGET_LOWER +#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT2_STATUS_LOWER +#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT2_TARGET_UPPER +#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT2_STATUS_UPPER +#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL +//UVD_GPCNT3_CNTL +#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 +#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa +#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L +#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L +#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L +//UVD_GPCNT3_TARGET_LOWER +#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT3_STATUS_LOWER +#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT3_TARGET_UPPER +#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT3_STATUS_UPPER +#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL +//UVD_VCLK_DS_CNTL +#define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 +#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 +#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 +#define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L +#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L +#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L +//UVD_DCLK_DS_CNTL +#define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 +#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 +#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 +#define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L +#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L +#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L +//UVD_RAS_VCPU_VCODEC_STATUS +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L +//UVD_RAS_MMSCH_FATAL_ERROR +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L +//UVD_RAS_JPEG0_STATUS +#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL +#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L +//UVD_RAS_JPEG1_STATUS +#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL +#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L +//UVD_RAS_CNTL_PMI_ARB +#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0 +#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1 +#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2 +#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3 +#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4 +#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5 +#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6 +#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7 +#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L +#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L +#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L +#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L +#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L +#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L +#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L +#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L + + +// addressBlock: uvd0_uvd_rbcdec +//UVD_RBC_IB_SIZE +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_RBC_IB_SIZE_UPDATE +#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_RBC_RB_CNTL +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L +#define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L +//UVD_RBC_RB_RPTR_ADDR +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL +//UVD_RBC_RB_RPTR +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_WPTR +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RBC_VCPU_ACCESS +#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 +#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L +//UVD_FW_SEMAPHORE_CNTL +#define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 +#define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 +#define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 +#define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L +#define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L +#define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L +//UVD_RBC_READ_REQ_URGENT_CNTL +#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_RBC_RB_WPTR_CNTL +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL +//UVD_RBC_WPTR_STATUS +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L +//UVD_RBC_WPTR_POLL_CNTL +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//UVD_RBC_WPTR_POLL_ADDR +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL +//UVD_SEMA_CMD +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L +#define UVD_SEMA_CMD__MODE_MASK 0x00000040L +#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L +#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L +//UVD_SEMA_ADDR_LOW +#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL +//UVD_SEMA_ADDR_HIGH +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL +//UVD_ENGINE_CNTL +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 +#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L +#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L +//UVD_SEMA_TIMEOUT_STATUS +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L +//UVD_SEMA_CNTL +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L +//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_JOB_START +#define UVD_JOB_START__JOB_START__SHIFT 0x0 +#define UVD_JOB_START__JOB_START_MASK 0x00000001L +//UVD_RBC_BUF_STATUS +#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 +#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 +#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 +#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 +#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL +#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L +#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L +#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L +#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L +#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L +//UVD_RBC_SWAP_CNTL +#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 +#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a +#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L +#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L + + +// addressBlock: uvd0_uvddec +//UVD_STATUS +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 +#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL +#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L +#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L +//UVD_ENC_PIPE_BUSY +#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 +#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 +#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 +#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 +#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 +#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e +#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L +#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L +#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L +#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L +#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L +#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L +//UVD_FW_POWER_STATUS +#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 +#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1 +#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 +#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF__SHIFT 0x3 +#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF__SHIFT 0x4 +#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x5 +#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x6 +#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x7 +#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF__SHIFT 0x8 +#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L +#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L +#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L +#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF_MASK 0x00000008L +#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF_MASK 0x00000010L +#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000020L +#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000040L +#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000080L +#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF_MASK 0x00000100L +//UVD_CNTL +#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 +#define UVD_CNTL__SUVD_EN__SHIFT 0x13 +#define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c +#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f +#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L +#define UVD_CNTL__SUVD_EN_MASK 0x00080000L +#define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L +#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L +//UVD_SOFT_RESET +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L +//UVD_SOFT_RESET2 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_MMSCH_SOFT_RESET +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L +//UVD_WIG_CTRL +#define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 +#define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 +#define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 +#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 +#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 +#define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L +#define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L +#define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L +#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L +#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L +//UVD_CGC_GATE +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L +//UVD_CGC_STATUS +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L +//UVD_CGC_CTRL +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L +//UVD_CGC_UDEC_STATUS +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L +//UVD_SUVD_CGC_GATE +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L +//UVD_SUVD_CGC_STATUS +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf +#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 +#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 +#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b +#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L +#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L +#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L +#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L +#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L +#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L +//UVD_SUVD_CGC_CTRL +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +//UVD_GPCOM_VCPU_CMD +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_VCPU_DATA0 +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_VCPU_DATA1 +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_CMD +#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_SYS_DATA0 +#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_DATA1 +#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_VCPU_INT_EN +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa +#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf +#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 +#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 +#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 +#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a +#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L +#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L +#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L +#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L +#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L +#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L +#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L +//UVD_VCPU_INT_STATUS +#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 +#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 +#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 +#define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 +#define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 +#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 +#define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 +#define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 +#define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa +#define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb +#define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc +#define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf +#define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 +#define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 +#define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 +#define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 +#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15 +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 +#define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 +#define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 +#define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a +#define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b +#define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c +#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d +#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e +#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f +#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L +#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L +#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L +#define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L +#define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L +#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L +#define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L +#define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L +#define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L +#define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L +#define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L +#define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L +#define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L +#define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L +#define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L +#define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L +#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L +#define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L +#define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L +#define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L +#define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L +#define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L +#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L +#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L +#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L +//UVD_VCPU_INT_ACK +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa +#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 +#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 +#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 +#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L +#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L +#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L +#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L +#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L +//UVD_VCPU_INT_ROUTE +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L +//UVD_DRV_FW_MSG +#define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 +#define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL +//UVD_FW_DRV_MSG_ACK +#define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 +#define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L +//UVD_SUVD_INT_EN +#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 +#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 +#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 +#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb +#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc +#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 +#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 +#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 +#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 +#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d +#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL +#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L +#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L +#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L +#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L +#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L +#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L +#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L +#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L +#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L +//UVD_SUVD_INT_STATUS +#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 +#define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 +#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 +#define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb +#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc +#define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 +#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 +#define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 +#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 +#define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d +#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL +#define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L +#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L +#define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L +#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L +#define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L +#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L +#define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L +#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L +#define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L +//UVD_SUVD_INT_ACK +#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 +#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 +#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 +#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb +#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc +#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 +#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 +#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 +#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 +#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d +#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL +#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L +#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L +#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L +#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L +#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L +#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L +#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L +#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L +#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L +//UVD_ENC_VCPU_INT_EN +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L +//UVD_ENC_VCPU_INT_STATUS +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L +//UVD_ENC_VCPU_INT_ACK +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L +//UVD_MASTINT_EN +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L +//UVD_SYS_INT_EN +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf +#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a +#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L +#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L +#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L +//UVD_SYS_INT_STATUS +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 +#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 +#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb +#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc +#define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf +#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 +#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 +#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 +#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 +#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b +#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d +#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e +#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L +#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L +#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L +#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L +#define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L +#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L +#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L +#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L +#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L +#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L +#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L +#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L +#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L +//UVD_SYS_INT_ACK +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf +#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e +#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L +#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L +#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L +//UVD_JOB_DONE +#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 +#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L +//UVD_CBUF_ID +#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 +#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID2 +#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 +#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL +//UVD_NO_OP +#define UVD_NO_OP__NO_OP__SHIFT 0x0 +#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL +//UVD_RB_BASE_LO +#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI +#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE +#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR +#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR +#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO2 +#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI2 +#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE2 +#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR2 +#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR2 +#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO3 +#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI3 +#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE3 +#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR3 +#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR3 +#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO4 +#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI4 +#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE4 +#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR4 +#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR4 +#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_BASE_LO +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_OUT_RB_BASE_HI +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_OUT_RB_SIZE +#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_OUT_RB_RPTR +#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_WPTR +#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_IOV_MAILBOX +#define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 +#define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL +//UVD_IOV_MAILBOX_RESP +#define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 +#define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL +//UVD_RB_ARB_CTRL +#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 +#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 +#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 +#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 +#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 +#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 +#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 +#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 +#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 +#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L +#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L +#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L +#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L +#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L +#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L +#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L +#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L +#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L +//UVD_CTX_INDEX +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL +//UVD_CTX_DATA +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_CXW_WR +#define UVD_CXW_WR__DAT__SHIFT 0x0 +#define UVD_CXW_WR__STAT__SHIFT 0x1f +#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL +#define UVD_CXW_WR__STAT_MASK 0x80000000L +//UVD_CXW_WR_INT_ID +#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL +//UVD_CXW_WR_INT_CTX_ID +#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL +//UVD_CXW_INT_ID +#define UVD_CXW_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL +//UVD_MPEG2_ERROR +#define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 +#define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL +//UVD_TOP_CTRL +#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 +#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 +#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL +#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L +//UVD_YBASE +#define UVD_YBASE__DUM__SHIFT 0x0 +#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL +//UVD_UVBASE +#define UVD_UVBASE__DUM__SHIFT 0x0 +#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL +//UVD_PITCH +#define UVD_PITCH__DUM__SHIFT 0x0 +#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL +//UVD_WIDTH +#define UVD_WIDTH__DUM__SHIFT 0x0 +#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL +//UVD_HEIGHT +#define UVD_HEIGHT__DUM__SHIFT 0x0 +#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL +//UVD_PICCOUNT +#define UVD_PICCOUNT__DUM__SHIFT 0x0 +#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL +//UVD_MPRD_INITIAL_XY +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L +//UVD_MPEG2_CTRL +#define UVD_MPEG2_CTRL__EN__SHIFT 0x0 +#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 +#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 +#define UVD_MPEG2_CTRL__EN_MASK 0x00000001L +#define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L +#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L +//UVD_MB_CTL_BUF_BASE +#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 +#define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//UVD_PIC_CTL_BUF_BASE +#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 +#define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//UVD_DXVA_BUF_SIZE +#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 +#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 +#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL +#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L +//UVD_SCRATCH_NP +#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 +#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL +//UVD_CLK_SWT_HANDSHAKE +#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 +#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 +#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L +#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L +//UVD_VERSION +#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 +#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 +#define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c +#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL +#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L +#define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L +//UVD_GP_SCRATCH0 +#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH1 +#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH2 +#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH3 +#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH4 +#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH5 +#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH6 +#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH7 +#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH8 +#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH9 +#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH10 +#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH11 +#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH12 +#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH13 +#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH14 +#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH15 +#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH16 +#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH17 +#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH18 +#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH19 +#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH20 +#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH21 +#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH22 +#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH23 +#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 3cb8d4c5c1a31f24df1ffee4e145de2b4042c043..58364a8eb1f3e5e3902cc94842d5eceab48699a1 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -180,6 +180,7 @@ enum atom_voltage_type enum atom_dgpu_vram_type { ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, + ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, }; @@ -596,7 +597,10 @@ struct atom_firmware_info_v3_4 { uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. - uint32_t reserved[5]; + uint32_t pspbl_init_done_reg_addr; + uint32_t pspbl_init_done_value; + uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done + uint32_t reserved[2]; }; /* @@ -1528,6 +1532,47 @@ struct atom_gfx_info_v2_4 uint32_t sram_custom_rm_fuses_val; }; +struct atom_gfx_info_v2_7 { + struct atom_common_table_header table_header; + uint8_t gfxip_min_ver; + uint8_t gfxip_max_ver; + uint8_t max_shader_engines; + uint8_t reserved; + uint8_t max_cu_per_sh; + uint8_t max_sh_per_se; + uint8_t max_backends_per_se; + uint8_t max_texture_channel_caches; + uint32_t regaddr_cp_dma_src_addr; + uint32_t regaddr_cp_dma_src_addr_hi; + uint32_t regaddr_cp_dma_dst_addr; + uint32_t regaddr_cp_dma_dst_addr_hi; + uint32_t regaddr_cp_dma_command; + uint32_t regaddr_cp_status; + uint32_t regaddr_rlc_gpu_clock_32; + uint32_t rlc_gpu_timer_refclk; + uint8_t active_cu_per_sh; + uint8_t active_rb_per_se; + uint16_t gcgoldenoffset; + uint16_t gc_num_gprs; + uint16_t gc_gsprim_buff_depth; + uint16_t gc_parameter_cache_depth; + uint16_t gc_wave_size; + uint16_t gc_max_waves_per_simd; + uint16_t gc_lds_size; + uint8_t gc_num_max_gs_thds; + uint8_t gc_gs_table_depth; + uint8_t gc_double_offchip_lds_buffer; + uint8_t gc_max_scratch_slots_per_cu; + uint32_t sram_rm_fuses_val; + uint32_t sram_custom_rm_fuses_val; + uint8_t cut_cu; + uint8_t active_cu_total; + uint8_t cu_reserved[2]; + uint32_t gc_config; + uint8_t inactive_cu_per_se[8]; + uint32_t reserved2[6]; +}; + /* *************************************************************************** Data Table smu_info structure @@ -2332,6 +2377,59 @@ struct atom_smc_dpm_info_v4_9 }; +struct atom_smc_dpm_info_v4_10 +{ + struct atom_common_table_header table_header; + + // SECTION: BOARD PARAMETERS + // Telemetry Settings + uint16_t GfxMaxCurrent; // in Amps + uint8_t GfxOffset; // in Amps + uint8_t Padding_TelemetryGfx; + + uint16_t SocMaxCurrent; // in Amps + uint8_t SocOffset; // in Amps + uint8_t Padding_TelemetrySoc; + + uint16_t MemMaxCurrent; // in Amps + uint8_t MemOffset; // in Amps + uint8_t Padding_TelemetryMem; + + uint16_t BoardMaxCurrent; // in Amps + uint8_t BoardOffset; // in Amps + uint8_t Padding_TelemetryBoardInput; + + // Platform input telemetry voltage coefficient + uint32_t BoardVoltageCoeffA; // decode by /1000 + uint32_t BoardVoltageCoeffB; // decode by /1000 + + // GPIO Settings + uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event + uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + + // UCLK Spread Spectrum + uint8_t UclkSpreadEnabled; // on or off + uint8_t UclkSpreadPercent; // Q4.4 + uint16_t UclkSpreadFreq; // kHz + + // FCLK Spread Spectrum + uint8_t FclkSpreadEnabled; // on or off + uint8_t FclkSpreadPercent; // Q4.4 + uint16_t FclkSpreadFreq; // kHz + + // I2C Controller Structure + struct smudpm_i2c_controller_config_v3 I2cControllers[8]; + + // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence + uint8_t GpioI2cScl; // Serial Clock + uint8_t GpioI2cSda; // Serial Data + uint16_t spare5; + + uint32_t reserved[16]; +}; + /* *************************************************************************** Data Table asic_profiling_info structure @@ -2537,7 +2635,18 @@ struct atom_umc_info_v3_3 uint32_t pstate_uclk_10khz[4]; uint16_t umcgoldenoffset; uint16_t densitygoldenoffset; - uint32_t reserved[4]; + uint32_t umc_config1; + uint32_t bist_data_startaddr; + uint32_t reserved[2]; +}; + +enum atom_umc_config1_def { + UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, + UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, + UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, + UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, + UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, + UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, }; /* @@ -2789,6 +2898,22 @@ struct atom_vram_info_header_v2_5 { struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; }; +struct atom_vram_info_header_v2_6 { + struct atom_common_table_header table_header; + uint16_t mem_adjust_tbloffset; + uint16_t mem_clk_patch_tbloffset; + uint16_t mc_adjust_pertile_tbloffset; + uint16_t mc_phyinit_tbloffset; + uint16_t dram_data_remap_tbloffset; + uint16_t tmrs_seq_offset; + uint16_t post_ucode_init_offset; + uint16_t vram_rsd2; + uint8_t vram_module_num; + uint8_t umcip_min_ver; + uint8_t umcip_max_ver; + uint8_t mc_phy_tile_num; + struct atom_vram_module_v9 vram_module[16]; +}; /* *************************************************************************** Data Table voltageobject_info structure diff --git a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h index ac9fa3a9bd07fac7a30748a9ec3733f462280e62..e2bffcae273a5f255c10f5c2e412c005437258a6 100644 --- a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h +++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h @@ -1130,5 +1130,7 @@ #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68 +#define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6 #endif // __IRQSRCS_DCN_1_0_H__ diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index a41875ac5dfbdaca9564db8a0679f610b870f438..dd695817c4816db75ded18253df2713cba6afec6 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -48,6 +48,7 @@ enum amd_dpm_forced_level { AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, + AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, }; enum amd_pm_state_type { @@ -95,10 +96,14 @@ enum pp_clock_type { PP_SOCCLK, PP_FCLK, PP_DCEFCLK, + PP_VCLK, + PP_DCLK, OD_SCLK, OD_MCLK, OD_VDDC_CURVE, OD_RANGE, + OD_VDDGFX_OFFSET, + OD_CCLK, }; enum amd_pp_sensors { @@ -226,6 +231,8 @@ enum pp_df_cstate { #define XGMI_MODE_PSTATE_D3 0 #define XGMI_MODE_PSTATE_D0 1 +#define NUM_HBM_INSTANCES 4 + struct seq_file; enum amd_pp_clock_type; struct amd_pp_simple_clock_info; @@ -281,7 +288,8 @@ struct amd_pm_funcs { uint32_t block_type, bool gate); int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); int (*set_power_limit)(void *handle, uint32_t n); - int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit); + int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit, + bool default_limit); int (*get_power_profile_mode)(void *handle, char *buf); int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); @@ -336,6 +344,10 @@ struct metrics_table_header { uint8_t content_revision; }; +/* + * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. + * Use gpu_metrics_v1_1 or later instead. + */ struct gpu_metrics_v1_0 { struct metrics_table_header common_header; @@ -388,6 +400,69 @@ struct gpu_metrics_v1_0 { uint8_t pcie_link_speed; // in 0.1 GT/s }; +struct gpu_metrics_v1_1 { + struct metrics_table_header common_header; + + /* Temperature */ + uint16_t temperature_edge; + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrgfx; + uint16_t temperature_vrsoc; + uint16_t temperature_vrmem; + + /* Utilization */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + uint16_t average_mm_activity; // UVD or VCN + + /* Power/Energy */ + uint16_t average_socket_power; + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_uclk_frequency; + uint16_t average_vclk0_frequency; + uint16_t average_dclk0_frequency; + uint16_t average_vclk1_frequency; + uint16_t average_dclk1_frequency; + + /* Current clocks */ + uint16_t current_gfxclk; + uint16_t current_socclk; + uint16_t current_uclk; + uint16_t current_vclk0; + uint16_t current_dclk0; + uint16_t current_vclk1; + uint16_t current_dclk1; + + /* Throttle status */ + uint32_t throttle_status; + + /* Fans */ + uint16_t current_fan_speed; + + /* Link width/speed */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; // in 0.1 GT/s + + uint16_t padding; + + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + uint16_t temperature_hbm[NUM_HBM_INSTANCES]; +}; + +/* + * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. + * Use gpu_metrics_v2_1 or later instead. + */ struct gpu_metrics_v2_0 { struct metrics_table_header common_header; @@ -438,4 +513,54 @@ struct gpu_metrics_v2_0 { uint16_t padding; }; +struct gpu_metrics_v2_1 { + struct metrics_table_header common_header; + + /* Temperature */ + uint16_t temperature_gfx; // gfx temperature on APUs + uint16_t temperature_soc; // soc temperature on APUs + uint16_t temperature_core[8]; // CPU core temperature on APUs + uint16_t temperature_l3[2]; + + /* Utilization */ + uint16_t average_gfx_activity; + uint16_t average_mm_activity; // UVD or VCN + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Power/Energy */ + uint16_t average_socket_power; // dGPU + APU power on A + A platform + uint16_t average_cpu_power; + uint16_t average_soc_power; + uint16_t average_gfx_power; + uint16_t average_core_power[8]; // CPU core power on APUs + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_uclk_frequency; + uint16_t average_fclk_frequency; + uint16_t average_vclk_frequency; + uint16_t average_dclk_frequency; + + /* Current clocks */ + uint16_t current_gfxclk; + uint16_t current_socclk; + uint16_t current_uclk; + uint16_t current_fclk; + uint16_t current_vclk; + uint16_t current_dclk; + uint16_t current_coreclk[8]; // CPU core clocks + uint16_t current_l3clk[2]; + + /* Throttle status */ + uint32_t throttle_status; + + /* Fans */ + uint16_t fan_pwm; + + uint16_t padding[3]; +}; + #endif diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h index fb67bb55ed79334f5cce3ac30878f8b6cb419990..1ace2cff088394c5c0d385dba69535cb6fa944fc 100644 --- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h +++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h @@ -24,8 +24,10 @@ #ifndef __SOC15_IH_CLIENTID_H__ #define __SOC15_IH_CLIENTID_H__ - /* - * vega10+ IH clients +/* + * Vega10+ IH clients + * Whenever this structure is updated, which should not happen, make sure + * soc15_ih_clientid_name in the below is also updated accordingly. */ enum soc15_ih_clientid { SOC15_IH_CLIENTID_IH = 0x00, @@ -54,6 +56,7 @@ enum soc15_ih_clientid { SOC15_IH_CLIENTID_DF = 0x17, SOC15_IH_CLIENTID_VCE1 = 0x18, SOC15_IH_CLIENTID_PWR = 0x19, + SOC15_IH_CLIENTID_RESERVED = 0x1a, SOC15_IH_CLIENTID_UTCL2 = 0x1b, SOC15_IH_CLIENTID_EA = 0x1c, SOC15_IH_CLIENTID_UTCL2LOG = 0x1d, @@ -74,6 +77,8 @@ enum soc15_ih_clientid { SOC15_IH_CLIENTID_VMC1 = SOC15_IH_CLIENTID_PCIE0, }; +extern const char *soc15_ih_clientid_name[]; + #endif diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h index c17613287cd0c67b01374d6b3a55f65f1a36426c..50ebf885fa7c517d91e264f803574dc432a1991e 100644 --- a/drivers/gpu/drm/amd/include/vi_structs.h +++ b/drivers/gpu/drm/amd/include/vi_structs.h @@ -397,22 +397,22 @@ struct vi_mqd { uint32_t reserved60; uint32_t reserved61; uint32_t reserved62; - uint32_t reserved63; - uint32_t reserved64; - uint32_t reserved65; - uint32_t reserved66; - uint32_t reserved67; - uint32_t reserved68; - uint32_t reserved69; - uint32_t reserved70; - uint32_t reserved71; - uint32_t reserved72; - uint32_t reserved73; - uint32_t reserved74; - uint32_t reserved75; - uint32_t reserved76; - uint32_t reserved77; - uint32_t reserved78; + uint32_t queue_doorbell_id0; + uint32_t queue_doorbell_id1; + uint32_t queue_doorbell_id2; + uint32_t queue_doorbell_id3; + uint32_t queue_doorbell_id4; + uint32_t queue_doorbell_id5; + uint32_t queue_doorbell_id6; + uint32_t queue_doorbell_id7; + uint32_t queue_doorbell_id8; + uint32_t queue_doorbell_id9; + uint32_t queue_doorbell_id10; + uint32_t queue_doorbell_id11; + uint32_t queue_doorbell_id12; + uint32_t queue_doorbell_id13; + uint32_t queue_doorbell_id14; + uint32_t queue_doorbell_id15; uint32_t reserved_t[256]; }; diff --git a/drivers/gpu/drm/amd/pm/Makefile b/drivers/gpu/drm/amd/pm/Makefile index f01e86030cd1607b4406234e49711f2136148eaa..8cf6eff1ea93ddf3c84e365196ad00e56ee58b52 100644 --- a/drivers/gpu/drm/amd/pm/Makefile +++ b/drivers/gpu/drm/amd/pm/Makefile @@ -27,6 +27,7 @@ subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/pm/swsmu \ -I$(FULL_AMD_PATH)/pm/swsmu/smu11 \ -I$(FULL_AMD_PATH)/pm/swsmu/smu12 \ + -I$(FULL_AMD_PATH)/pm/swsmu/smu13 \ -I$(FULL_AMD_PATH)/pm/powerplay \ -I$(FULL_AMD_PATH)/pm/powerplay/smumgr\ -I$(FULL_AMD_PATH)/pm/powerplay/hwmgr diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 8fb12afe3c96ad6994c6a4dc6b8ad1ad6cad7e9a..0a6bb3311f0fc88cf8d487b7584d82ae5a48753d 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -911,50 +911,28 @@ amdgpu_get_vce_clock_state(void *handle, u32 idx) int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { - uint32_t clk_freq; - int ret = 0; - if (is_support_sw_smu(adev)) { - ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK, - low ? &clk_freq : NULL, - !low ? &clk_freq : NULL); - if (ret) - return 0; - return clk_freq * 100; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - } else { - return (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); - } + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { - uint32_t clk_freq; - int ret = 0; - if (is_support_sw_smu(adev)) { - ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK, - low ? &clk_freq : NULL, - !low ? &clk_freq : NULL); - if (ret) - return 0; - return clk_freq * 100; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - } else { - return (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); - } + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) { int ret = 0; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; bool swsmu = is_support_sw_smu(adev); switch (block_type) { case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_VCE: - if (swsmu) { - ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); - } else if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_powergating_by_smu) { + if (pp_funcs && pp_funcs->set_powergating_by_smu) { /* * TODO: need a better lock mechanism * @@ -982,7 +960,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block * amdgpu_set_dpm_forced_performance_level+0x129/0x330 [amdgpu] */ mutex_lock(&adev->pm.mutex); - ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( + ret = (pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); mutex_unlock(&adev->pm.mutex); } @@ -990,12 +968,10 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block case AMD_IP_BLOCK_TYPE_GFX: case AMD_IP_BLOCK_TYPE_VCN: case AMD_IP_BLOCK_TYPE_SDMA: - if (swsmu) - ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); - else if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_powergating_by_smu) - ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( + if (pp_funcs && pp_funcs->set_powergating_by_smu) { + ret = (pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); + } break; case AMD_IP_BLOCK_TYPE_JPEG: if (swsmu) @@ -1003,10 +979,10 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block break; case AMD_IP_BLOCK_TYPE_GMC: case AMD_IP_BLOCK_TYPE_ACP: - if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_powergating_by_smu) - ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( + if (pp_funcs && pp_funcs->set_powergating_by_smu) { + ret = (pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); + } break; default: break; @@ -1019,18 +995,13 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; int ret = 0; - if (is_support_sw_smu(adev)) { - ret = smu_baco_enter(smu); - } else { - if (!pp_funcs || !pp_funcs->set_asic_baco_state) - return -ENOENT; + if (!pp_funcs || !pp_funcs->set_asic_baco_state) + return -ENOENT; - /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - } + /* enter BACO state */ + ret = pp_funcs->set_asic_baco_state(pp_handle, 1); return ret; } @@ -1039,18 +1010,13 @@ int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; int ret = 0; - if (is_support_sw_smu(adev)) { - ret = smu_baco_exit(smu); - } else { - if (!pp_funcs || !pp_funcs->set_asic_baco_state) - return -ENOENT; + if (!pp_funcs || !pp_funcs->set_asic_baco_state) + return -ENOENT; - /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - } + /* exit BACO state */ + ret = pp_funcs->set_asic_baco_state(pp_handle, 0); return ret; } @@ -1059,12 +1025,10 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { int ret = 0; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - if (is_support_sw_smu(adev)) { - ret = smu_set_mp1_state(&adev->smu, mp1_state); - } else if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_mp1_state) { - ret = adev->powerplay.pp_funcs->set_mp1_state( + if (pp_funcs && pp_funcs->set_mp1_state) { + ret = pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); } @@ -1076,68 +1040,46 @@ bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; bool baco_cap; - if (is_support_sw_smu(adev)) { - return smu_baco_is_support(smu); - } else { - if (!pp_funcs || !pp_funcs->get_asic_baco_capability) - return false; + if (!pp_funcs || !pp_funcs->get_asic_baco_capability) + return false; - if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap)) - return false; + if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap)) + return false; - return baco_cap ? true : false; - } + return baco_cap; } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; - if (is_support_sw_smu(adev)) { - return smu_mode2_reset(smu); - } else { - if (!pp_funcs || !pp_funcs->asic_reset_mode_2) - return -ENOENT; + if (!pp_funcs || !pp_funcs->asic_reset_mode_2) + return -ENOENT; - return pp_funcs->asic_reset_mode_2(pp_handle); - } + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; int ret = 0; - if (is_support_sw_smu(adev)) { - ret = smu_baco_enter(smu); - if (ret) - return ret; - - ret = smu_baco_exit(smu); - if (ret) - return ret; - } else { - if (!pp_funcs - || !pp_funcs->set_asic_baco_state) - return -ENOENT; + if (!pp_funcs || !pp_funcs->set_asic_baco_state) + return -ENOENT; - /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - if (ret) - return ret; + /* enter BACO state */ + ret = pp_funcs->set_asic_baco_state(pp_handle, 1); + if (ret) + return ret; - /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - if (ret) - return ret; - } + /* exit BACO state */ + ret = pp_funcs->set_asic_baco_state(pp_handle, 0); + if (ret) + return ret; return 0; } @@ -1166,16 +1108,14 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, enum PP_SMC_POWER_PROFILE type, bool en) { + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (is_support_sw_smu(adev)) - ret = smu_switch_power_profile(&adev->smu, type, en); - else if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->switch_power_profile) - ret = adev->powerplay.pp_funcs->switch_power_profile( + if (pp_funcs && pp_funcs->switch_power_profile) + ret = pp_funcs->switch_power_profile( adev->powerplay.pp_handle, type, en); return ret; @@ -1184,13 +1124,11 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int ret = 0; - if (is_support_sw_smu(adev)) - ret = smu_set_xgmi_pstate(&adev->smu, pstate); - else if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_xgmi_pstate) - ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + if (pp_funcs && pp_funcs->set_xgmi_pstate) + ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, pstate); return ret; @@ -1202,12 +1140,8 @@ int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - struct smu_context *smu = &adev->smu; - if (is_support_sw_smu(adev)) - ret = smu_set_df_cstate(smu, cstate); - else if (pp_funcs && - pp_funcs->set_df_cstate) + if (pp_funcs && pp_funcs->set_df_cstate) ret = pp_funcs->set_df_cstate(pp_handle, cstate); return ret; @@ -1228,12 +1162,9 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - struct smu_context *smu = &adev->smu; int ret = 0; - if (is_support_sw_smu(adev)) - ret = smu_enable_mgpu_fan_boost(smu); - else if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) + if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); return ret; @@ -1290,20 +1221,17 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, void *data, uint32_t *size) { + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int ret = 0; if (!data || !size) return -EINVAL; - if (is_support_sw_smu(adev)) - ret = smu_read_sensor(&adev->smu, sensor, data, size); - else { - if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) - ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, + if (pp_funcs && pp_funcs->read_sensor) + ret = pp_funcs->read_sensor((adev)->powerplay.pp_handle, sensor, data, size); - else - ret = -EINVAL; - } + else + ret = -EINVAL; return ret; } @@ -1560,36 +1488,30 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - if (is_support_sw_smu(adev)) { - struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm; - smu_handle_task(&adev->smu, - smu_dpm->dpm_level, - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, - true); - } else { - if (adev->powerplay.pp_funcs->dispatch_tasks) { - if (!amdgpu_device_has_dc_support(adev)) { - mutex_lock(&adev->pm.mutex); - amdgpu_dpm_get_active_displays(adev); - adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; - adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); - adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); - /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */ - if (adev->pm.pm_display_cfg.vrefresh > 120) - adev->pm.pm_display_cfg.min_vblank_time = 0; - if (adev->powerplay.pp_funcs->display_configuration_change) - adev->powerplay.pp_funcs->display_configuration_change( - adev->powerplay.pp_handle, - &adev->pm.pm_display_cfg); - mutex_unlock(&adev->pm.mutex); - } - amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL); - } else { + if (adev->powerplay.pp_funcs->dispatch_tasks) { + if (!amdgpu_device_has_dc_support(adev)) { mutex_lock(&adev->pm.mutex); amdgpu_dpm_get_active_displays(adev); - amdgpu_dpm_change_power_state_locked(adev); + adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; + adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); + adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); + /* we have issues with mclk switching with + * refresh rates over 120 hz on the non-DC code. + */ + if (adev->pm.pm_display_cfg.vrefresh > 120) + adev->pm.pm_display_cfg.min_vblank_time = 0; + if (adev->powerplay.pp_funcs->display_configuration_change) + adev->powerplay.pp_funcs->display_configuration_change( + adev->powerplay.pp_handle, + &adev->pm.pm_display_cfg); mutex_unlock(&adev->pm.mutex); } + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL); + } else { + mutex_lock(&adev->pm.mutex); + amdgpu_dpm_get_active_displays(adev); + amdgpu_dpm_change_power_state_locked(adev); + mutex_unlock(&adev->pm.mutex); } } diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 5fa65f191a3790071d8b2de786ede25c1bfcabc1..2627870a786ed0e4cbd19f0c264d7da48b321679 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -23,8 +23,6 @@ * Alex Deucher */ -#include - #include "amdgpu.h" #include "amdgpu_drv.h" #include "amdgpu_pm.h" @@ -125,6 +123,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; enum amd_pm_state_type pm; int ret; @@ -137,12 +136,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - if (adev->smu.ppt_funcs->get_current_power_state) - pm = smu_get_current_power_state(&adev->smu); - else - pm = adev->pm.dpm.user_state; - } else if (adev->powerplay.pp_funcs->get_current_power_state) { + if (pp_funcs->get_current_power_state) { pm = amdgpu_dpm_get_current_power_state(adev); } else { pm = adev->pm.dpm.user_state; @@ -281,9 +275,7 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - level = smu_get_performance_level(&adev->smu); - else if (adev->powerplay.pp_funcs->get_performance_level) + if (adev->powerplay.pp_funcs->get_performance_level) level = amdgpu_dpm_get_performance_level(adev); else level = adev->pm.dpm.forced_level; @@ -300,6 +292,7 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : + (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : "unknown"); } @@ -310,6 +303,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; enum amd_dpm_forced_level level; enum amd_dpm_forced_level current_level = 0xff; int ret = 0; @@ -335,6 +329,8 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; + } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { + level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; } else { return -EINVAL; } @@ -345,9 +341,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - current_level = smu_get_performance_level(&adev->smu); - else if (adev->powerplay.pp_funcs->get_performance_level) + if (pp_funcs->get_performance_level) current_level = amdgpu_dpm_get_performance_level(adev); if (current_level == level) { @@ -377,14 +371,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, return -EINVAL; } - if (is_support_sw_smu(adev)) { - ret = smu_force_performance_level(&adev->smu, level); - if (ret) { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return -EINVAL; - } - } else if (adev->powerplay.pp_funcs->force_performance_level) { + if (pp_funcs->force_performance_level) { mutex_lock(&adev->pm.mutex); if (adev->pm.dpm.thermal_active) { mutex_unlock(&adev->pm.mutex); @@ -415,6 +402,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; struct pp_states_info data; int i, buf_len, ret; @@ -427,11 +415,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - ret = smu_get_power_num_states(&adev->smu, &data); - if (ret) - return ret; - } else if (adev->powerplay.pp_funcs->get_pp_num_states) { + if (pp_funcs->get_pp_num_states) { amdgpu_dpm_get_pp_num_states(adev, &data); } else { memset(&data, 0, sizeof(data)); @@ -457,8 +441,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; struct pp_states_info data; - struct smu_context *smu = &adev->smu; enum amd_pm_state_type pm = 0; int i = 0, ret = 0; @@ -471,13 +455,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - pm = smu_get_current_power_state(smu); - ret = smu_get_power_num_states(smu, &data); - if (ret) - return ret; - } else if (adev->powerplay.pp_funcs->get_current_power_state - && adev->powerplay.pp_funcs->get_pp_num_states) { + if (pp_funcs->get_current_power_state + && pp_funcs->get_pp_num_states) { pm = amdgpu_dpm_get_current_power_state(adev); amdgpu_dpm_get_pp_num_states(adev, &data); } @@ -592,13 +571,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - size = smu_sys_get_pp_table(&adev->smu, (void **)&table); - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - if (size < 0) - return size; - } else if (adev->powerplay.pp_funcs->get_pp_table) { + if (adev->powerplay.pp_funcs->get_pp_table) { size = amdgpu_dpm_get_pp_table(adev, &table); pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -636,15 +609,12 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count); - if (ret) { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - } else if (adev->powerplay.pp_funcs->set_pp_table) - amdgpu_dpm_set_pp_table(adev, buf, count); + ret = amdgpu_dpm_set_pp_table(adev, buf, count); + if (ret) { + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -842,53 +812,42 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - ret = smu_od_edit_dpm_table(&adev->smu, type, - parameter, parameter_size); - + if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) { + ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type, + parameter, + parameter_size); if (ret) { pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); return -EINVAL; } - } else { - - if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) { - ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type, - parameter, - parameter_size); - if (ret) { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return -EINVAL; - } - } + } - if (adev->powerplay.pp_funcs->odn_edit_dpm_table) { - ret = amdgpu_dpm_odn_edit_dpm_table(adev, type, - parameter, parameter_size); - if (ret) { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return -EINVAL; - } + if (adev->powerplay.pp_funcs->odn_edit_dpm_table) { + ret = amdgpu_dpm_odn_edit_dpm_table(adev, type, + parameter, parameter_size); + if (ret) { + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return -EINVAL; } + } - if (type == PP_OD_COMMIT_DPM_TABLE) { - if (adev->powerplay.pp_funcs->dispatch_tasks) { - amdgpu_dpm_dispatch_task(adev, - AMD_PP_TASK_READJUST_POWER_STATE, - NULL); - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return count; - } else { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return -EINVAL; - } + if (type == PP_OD_COMMIT_DPM_TABLE) { + if (adev->powerplay.pp_funcs->dispatch_tasks) { + amdgpu_dpm_dispatch_task(adev, + AMD_PP_TASK_READJUST_POWER_STATE, + NULL); + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return count; + } else { + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return -EINVAL; } } + pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -913,18 +872,13 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf); - size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size); - size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size); - size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size); - size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size); - size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size); - } else if (adev->powerplay.pp_funcs->print_clock_levels) { + if (adev->powerplay.pp_funcs->print_clock_levels) { size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size); size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size); + size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size); size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size); + size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size); } else { size = snprintf(buf, PAGE_SIZE, "\n"); } @@ -1012,9 +966,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - size = smu_sys_get_pp_feature_mask(&adev->smu, buf); - else if (adev->powerplay.pp_funcs->get_ppfeature_status) + if (adev->powerplay.pp_funcs->get_ppfeature_status) size = amdgpu_dpm_get_ppfeature_status(adev, buf); else size = snprintf(buf, PAGE_SIZE, "\n"); @@ -1045,461 +997,18 @@ static ssize_t amdgpu_get_pp_features(struct device *dev, * Secondly, enter a new value for each level by inputing a string that * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" * E.g., - * - * .. code-block:: bash - * - * echo "4 5 6" > pp_dpm_sclk - * - * will enable sclk levels 4, 5, and 6. - * - * NOTE: change to the dcefclk max dpm level is not supported now - */ - -static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -/* - * Worst case: 32 bits individually specified, in octal at 12 characters - * per line (+1 for \n). - */ -#define AMDGPU_MASK_BUF_MAX (32 * 13) - -static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) -{ - int ret; - unsigned long level; - char *sub_str = NULL; - char *tmp; - char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; - const char delimiter[3] = {' ', '\n', '\0'}; - size_t bytes; - - *mask = 0; - - bytes = min(count, sizeof(buf_cpy) - 1); - memcpy(buf_cpy, buf, bytes); - buf_cpy[bytes] = '\0'; - tmp = buf_cpy; - while ((sub_str = strsep(&tmp, delimiter)) != NULL) { - if (strlen(sub_str)) { - ret = kstrtoul(sub_str, 0, &level); - if (ret || level > 31) - return -EINVAL; - *mask |= 1 << level; - } else - break; - } - - return 0; -} - -static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} - -static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - uint32_t mask = 0; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} - -static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask); - else - ret = 0; - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} - -static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask); - else - ret = 0; - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} - -static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_VCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_VCLK, mask); - else - ret = 0; - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} - -static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_DCLK, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - return size; -} - -static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; - - if (amdgpu_in_reset(adev)) - return -EPERM; - - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; - - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } - - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_DCLK, mask); - else - ret = 0; - - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - - if (ret) - return -EINVAL; - - return count; -} + * + * .. code-block:: bash + * + * echo "4 5 6" > pp_dpm_sclk + * + * will enable sclk levels 4, 5, and 6. + * + * NOTE: change to the dcefclk max dpm level is not supported now + */ -static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, - struct device_attribute *attr, +static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, + enum pp_clock_type type, char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); @@ -1516,10 +1025,8 @@ static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf); + if (adev->powerplay.pp_funcs->print_clock_levels) + size = amdgpu_dpm_print_clock_levels(adev, type, buf); else size = snprintf(buf, PAGE_SIZE, "\n"); @@ -1529,8 +1036,43 @@ static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, return size; } -static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, - struct device_attribute *attr, +/* + * Worst case: 32 bits individually specified, in octal at 12 characters + * per line (+1 for \n). + */ +#define AMDGPU_MASK_BUF_MAX (32 * 13) + +static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) +{ + int ret; + unsigned long level; + char *sub_str = NULL; + char *tmp; + char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; + const char delimiter[3] = {' ', '\n', '\0'}; + size_t bytes; + + *mask = 0; + + bytes = min(count, sizeof(buf_cpy) - 1); + memcpy(buf_cpy, buf, bytes); + buf_cpy[bytes] = '\0'; + tmp = buf_cpy; + while ((sub_str = strsep(&tmp, delimiter)) != NULL) { + if (strlen(sub_str)) { + ret = kstrtoul(sub_str, 0, &level); + if (ret || level > 31) + return -EINVAL; + *mask |= 1 << level; + } else + break; + } + + return 0; +} + +static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, + enum pp_clock_type type, const char *buf, size_t count) { @@ -1552,10 +1094,8 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask); + if (adev->powerplay.pp_funcs->force_clock_level) + ret = amdgpu_dpm_force_clock_level(adev, type, mask); else ret = 0; @@ -1568,74 +1108,124 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, return count; } -static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, +static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, struct device_attribute *attr, char *buf) { - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - ssize_t size; - int ret; + return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); +} - if (amdgpu_in_reset(adev)) - return -EPERM; +static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); +} - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } +static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); +} - if (is_support_sw_smu(adev)) - size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf); - else if (adev->powerplay.pp_funcs->print_clock_levels) - size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); - else - size = snprintf(buf, PAGE_SIZE, "\n"); +static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); +} - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); +static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); +} - return size; +static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); } -static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, +static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); +} + +static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct drm_device *ddev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(ddev); - int ret; - uint32_t mask = 0; + return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); +} - if (amdgpu_in_reset(adev)) - return -EPERM; +static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); +} - ret = amdgpu_read_mask(buf, count, &mask); - if (ret) - return ret; +static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); +} - ret = pm_runtime_get_sync(ddev->dev); - if (ret < 0) { - pm_runtime_put_autosuspend(ddev->dev); - return ret; - } +static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); +} - if (is_support_sw_smu(adev)) - ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask); - else if (adev->powerplay.pp_funcs->force_clock_level) - ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); - else - ret = 0; +static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); +} - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); +static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); +} - if (ret) - return -EINVAL; +static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); +} - return count; +static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); +} + +static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); } static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, @@ -1822,9 +1412,7 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - size = smu_get_power_profile_mode(&adev->smu, buf); - else if (adev->powerplay.pp_funcs->get_power_profile_mode) + if (adev->powerplay.pp_funcs->get_power_profile_mode) size = amdgpu_dpm_get_power_profile_mode(adev, buf); else size = snprintf(buf, PAGE_SIZE, "\n"); @@ -1888,9 +1476,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true); - else if (adev->powerplay.pp_funcs->set_power_profile_mode) + if (adev->powerplay.pp_funcs->set_power_profile_mode) ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); pm_runtime_mark_last_busy(ddev->dev); @@ -2147,9 +1733,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) - size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics); - else if (adev->powerplay.pp_funcs->get_gpu_metrics) + if (adev->powerplay.pp_funcs->get_gpu_metrics) size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); if (size <= 0) @@ -2169,7 +1753,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev, static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), - AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), @@ -2513,22 +2097,18 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - pwm_mode = smu_get_fan_control_mode(&adev->smu); - } else { - if (!adev->powerplay.pp_funcs->get_fan_control_mode) { - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); - return -EINVAL; - } - - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + if (!adev->powerplay.pp_funcs->get_fan_control_mode) { + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return -EINVAL; } + pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); - return sprintf(buf, "%i\n", pwm_mode); + return sprintf(buf, "%u\n", pwm_mode); } static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, @@ -2553,18 +2133,14 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - smu_set_fan_control_mode(&adev->smu, value); - } else { - if (!adev->powerplay.pp_funcs->set_fan_control_mode) { - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); - return -EINVAL; - } - - amdgpu_dpm_set_fan_control_mode(adev, value); + if (!adev->powerplay.pp_funcs->set_fan_control_mode) { + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return -EINVAL; } + amdgpu_dpm_set_fan_control_mode(adev, value); + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -2603,11 +2179,7 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - pwm_mode = smu_get_fan_control_mode(&adev->smu); - else - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); - + pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); if (pwm_mode != AMD_FAN_CTRL_MANUAL) { pr_info("manual fan speed control should be enabled first\n"); pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); @@ -2624,9 +2196,7 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, value = (value * 100) / 255; - if (is_support_sw_smu(adev)) - err = smu_set_fan_speed_percent(&adev->smu, value); - else if (adev->powerplay.pp_funcs->set_fan_speed_percent) + if (adev->powerplay.pp_funcs->set_fan_speed_percent) err = amdgpu_dpm_set_fan_speed_percent(adev, value); else err = -EINVAL; @@ -2657,9 +2227,7 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - err = smu_get_fan_speed_percent(&adev->smu, &speed); - else if (adev->powerplay.pp_funcs->get_fan_speed_percent) + if (adev->powerplay.pp_funcs->get_fan_speed_percent) err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); else err = -EINVAL; @@ -2692,9 +2260,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - err = smu_get_fan_speed_rpm(&adev->smu, &speed); - else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) + if (adev->powerplay.pp_funcs->get_fan_speed_rpm) err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); else err = -EINVAL; @@ -2785,9 +2351,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - err = smu_get_fan_speed_rpm(&adev->smu, &rpm); - else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) + if (adev->powerplay.pp_funcs->get_fan_speed_rpm) err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); else err = -EINVAL; @@ -2819,10 +2383,7 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - pwm_mode = smu_get_fan_control_mode(&adev->smu); - else - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); if (pwm_mode != AMD_FAN_CTRL_MANUAL) { pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); @@ -2837,9 +2398,7 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - err = smu_set_fan_speed_rpm(&adev->smu, value); - else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) + if (adev->powerplay.pp_funcs->set_fan_speed_rpm) err = amdgpu_dpm_set_fan_speed_rpm(adev, value); else err = -EINVAL; @@ -2870,18 +2429,14 @@ static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - pwm_mode = smu_get_fan_control_mode(&adev->smu); - } else { - if (!adev->powerplay.pp_funcs->get_fan_control_mode) { - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); - return -EINVAL; - } - - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + if (!adev->powerplay.pp_funcs->get_fan_control_mode) { + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return -EINVAL; } + pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -2918,16 +2473,12 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, return err; } - if (is_support_sw_smu(adev)) { - smu_set_fan_control_mode(&adev->smu, pwm_mode); - } else { - if (!adev->powerplay.pp_funcs->set_fan_control_mode) { - pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); - pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); - return -EINVAL; - } - amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); + if (!adev->powerplay.pp_funcs->set_fan_control_mode) { + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return -EINVAL; } + amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -3059,8 +2610,10 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, char *buf) { struct amdgpu_device *adev = dev_get_drvdata(dev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int limit_type = to_sensor_dev_attr(attr)->index; uint32_t limit = limit_type << 24; + uint32_t max_limit = 0; ssize_t size; int r; @@ -3076,9 +2629,10 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, if (is_support_sw_smu(adev)) { smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX); size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { - adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); + } else if (pp_funcs && pp_funcs->get_power_limit) { + pp_funcs->get_power_limit(adev->powerplay.pp_handle, + &limit, &max_limit, true); + size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000); } else { size = snprintf(buf, PAGE_SIZE, "\n"); } @@ -3094,6 +2648,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, char *buf) { struct amdgpu_device *adev = dev_get_drvdata(dev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int limit_type = to_sensor_dev_attr(attr)->index; uint32_t limit = limit_type << 24; ssize_t size; @@ -3111,8 +2666,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, if (is_support_sw_smu(adev)) { smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT); size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { - adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); + } else if (pp_funcs && pp_funcs->get_power_limit) { + pp_funcs->get_power_limit(adev->powerplay.pp_handle, + &limit, NULL, false); size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); } else { size = snprintf(buf, PAGE_SIZE, "\n"); @@ -3124,6 +2680,42 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, return size; } +static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; + ssize_t size; + int r; + + if (amdgpu_in_reset(adev)) + return -EPERM; + + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + if (is_support_sw_smu(adev)) { + smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT); + size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); + } else if (pp_funcs && pp_funcs->get_power_limit) { + pp_funcs->get_power_limit(adev->powerplay.pp_handle, + &limit, NULL, true); + size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); + } else { + size = snprintf(buf, PAGE_SIZE, "\n"); + } + + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + + return size; +} static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, struct device_attribute *attr, char *buf) @@ -3140,6 +2732,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, size_t count) { struct amdgpu_device *adev = dev_get_drvdata(dev); + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; int limit_type = to_sensor_dev_attr(attr)->index; int err; u32 value; @@ -3163,10 +2756,8 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, return err; } - if (is_support_sw_smu(adev)) - err = smu_set_power_limit(&adev->smu, value); - else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) - err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); + if (pp_funcs && pp_funcs->set_power_limit) + err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); else err = -EINVAL; @@ -3315,9 +2906,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, * * - pwm1_max: pulse width modulation fan control maximum level (255) * - * - fan1_min: an minimum value Unit: revolution/min (RPM) + * - fan1_min: a minimum value Unit: revolution/min (RPM) * - * - fan1_max: an maxmum value Unit: revolution/max (RPM) + * - fan1_max: a maximum value Unit: revolution/max (RPM) * * - fan1_input: fan speed in RPM * @@ -3367,11 +2958,13 @@ static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); +static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); +static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); @@ -3411,11 +3004,13 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_power1_cap_max.dev_attr.attr, &sensor_dev_attr_power1_cap_min.dev_attr.attr, &sensor_dev_attr_power1_cap.dev_attr.attr, + &sensor_dev_attr_power1_cap_default.dev_attr.attr, &sensor_dev_attr_power1_label.dev_attr.attr, &sensor_dev_attr_power2_average.dev_attr.attr, &sensor_dev_attr_power2_cap_max.dev_attr.attr, &sensor_dev_attr_power2_cap_min.dev_attr.attr, &sensor_dev_attr_power2_cap.dev_attr.attr, + &sensor_dev_attr_power2_cap_default.dev_attr.attr, &sensor_dev_attr_power2_label.dev_attr.attr, &sensor_dev_attr_freq1_input.dev_attr.attr, &sensor_dev_attr_freq1_label.dev_attr.attr, @@ -3514,7 +3109,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, (adev->asic_type != CHIP_VANGOGH))) && /* not implemented yet */ (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| - attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) + attr == &sensor_dev_attr_power1_cap.dev_attr.attr || + attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) return 0; if (((adev->family == AMDGPU_FAMILY_SI) || @@ -3580,6 +3176,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || attr == &sensor_dev_attr_power2_cap.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || attr == &sensor_dev_attr_power2_label.dev_attr.attr || attr == &sensor_dev_attr_power1_label.dev_attr.attr)) return 0; @@ -3784,11 +3381,10 @@ static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) (flags & clocks[i].flag) ? "On" : "Off"); } -static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) +static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) { - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct drm_device *dev = adev_to_drm(adev); u32 flags = 0; int r; @@ -3836,16 +3432,18 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) return r; } -static const struct drm_info_list amdgpu_pm_info_list[] = { - {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, -}; +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); + #endif -int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) +void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) - return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); -#else - return 0; + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + + debugfs_create_file("amdgpu_pm_info", 0444, root, adev, + &amdgpu_debugfs_pm_info_fops); + #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h new file mode 100644 index 0000000000000000000000000000000000000000..433dd1e9ec4f819a7da73fac7f4d7c609ab7ff0d --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h @@ -0,0 +1,126 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef ALDEBARAN_PP_SMC_H +#define ALDEBARAN_PP_SMC_H + +#pragma pack(push, 1) + +// SMU Response Codes: +#define PPSMC_Result_OK 0x1 +#define PPSMC_Result_Failed 0xFF +#define PPSMC_Result_UnknownCmd 0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +// Message Definitions: +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GfxDriverReset 0x3 +#define PPSMC_MSG_GetDriverIfVersion 0x4 +#define PPSMC_MSG_spare1 0x5 +#define PPSMC_MSG_spare2 0x6 +#define PPSMC_MSG_EnableAllSmuFeatures 0x7 +#define PPSMC_MSG_DisableAllSmuFeatures 0x8 +#define PPSMC_MSG_spare3 0x9 +#define PPSMC_MSG_spare4 0xA +#define PPSMC_MSG_spare5 0xB +#define PPSMC_MSG_spare6 0xC +#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xD +#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xE +#define PPSMC_MSG_SetDriverDramAddrHigh 0xF +#define PPSMC_MSG_SetDriverDramAddrLow 0x10 +#define PPSMC_MSG_SetToolsDramAddrHigh 0x11 +#define PPSMC_MSG_SetToolsDramAddrLow 0x12 +#define PPSMC_MSG_TransferTableSmu2Dram 0x13 +#define PPSMC_MSG_TransferTableDram2Smu 0x14 +#define PPSMC_MSG_UseDefaultPPTable 0x15 +#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x16 +#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x17 +#define PPSMC_MSG_SetSoftMinByFreq 0x18 +#define PPSMC_MSG_SetSoftMaxByFreq 0x19 +#define PPSMC_MSG_SetHardMinByFreq 0x1A +#define PPSMC_MSG_SetHardMaxByFreq 0x1B +#define PPSMC_MSG_GetMinDpmFreq 0x1C +#define PPSMC_MSG_GetMaxDpmFreq 0x1D +#define PPSMC_MSG_GetDpmFreqByIndex 0x1E +#define PPSMC_MSG_SetWorkloadMask 0x1F +#define PPSMC_MSG_GetVoltageByDpm 0x20 +#define PPSMC_MSG_GetVoltageByDpmOverdrive 0x21 +#define PPSMC_MSG_SetPptLimit 0x22 +#define PPSMC_MSG_GetPptLimit 0x23 +#define PPSMC_MSG_PrepareMp1ForUnload 0x24 +#define PPSMC_MSG_PrepareMp1ForReset 0x25 //retired in 68.07 +#define PPSMC_MSG_SoftReset 0x26 //retired in 68.07 +#define PPSMC_MSG_RunDcBtc 0x27 +#define PPSMC_MSG_DramLogSetDramAddrHigh 0x28 +#define PPSMC_MSG_DramLogSetDramAddrLow 0x29 +#define PPSMC_MSG_DramLogSetDramSize 0x2A +#define PPSMC_MSG_GetDebugData 0x2B +#define PPSMC_MSG_WaflTest 0x2C +#define PPSMC_MSG_spare7 0x2D +#define PPSMC_MSG_SetMemoryChannelEnable 0x2E +#define PPSMC_MSG_SetNumBadHbmPagesRetired 0x2F +#define PPSMC_MSG_DFCstateControl 0x32 +#define PPSMC_MSG_GetGmiPwrDnHyst 0x33 +#define PPSMC_MSG_SetGmiPwrDnHyst 0x34 +#define PPSMC_MSG_GmiPwrDnControl 0x35 +#define PPSMC_MSG_EnterGfxoff 0x36 +#define PPSMC_MSG_ExitGfxoff 0x37 +#define PPSMC_MSG_SetExecuteDMATest 0x38 +#define PPSMC_MSG_EnableDeterminism 0x39 +#define PPSMC_MSG_DisableDeterminism 0x3A +#define PPSMC_MSG_SetUclkDpmMode 0x3B + +//STB to dram log +#define PPSMC_MSG_DumpSTBtoDram 0x3C +#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3D +#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3E +#define PPSMC_MSG_STBtoDramLogSetDramSize 0x3F +#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40 +#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41 + +#define PPSMC_Message_Count 0x42 + +//PPSMC Reset Types +#define PPSMC_RESET_TYPE_WARM_RESET 0x00 +#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x01 //driver msg argument should be 1 for mode-1 +#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x02 //and 2 for mode-2 +#define PPSMC_RESET_TYPE_PCIE_LINK_RESET 0x03 +#define PPSMC_RESET_TYPE_BIF_LINK_RESET 0x04 +#define PPSMC_RESET_TYPE_PF0_FLR_RESET 0x05 + + +typedef enum { + GFXOFF_ERROR_NO_ERROR, + GFXOFF_ERROR_DISALLOWED, + GFXOFF_ERROR_GFX_BUSY, + GFXOFF_ERROR_GFX_OFF, + GFXOFF_ERROR_GFX_ON, +} GFXOFF_ERROR_e; + +typedef uint32_t PPSMC_Result; +typedef uint32_t PPSMC_Msg; +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h index 45a22e101d1593e065aea7a56c230e7b4170e448..a920515e22744279700b09d32edce2ed91c91761 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h @@ -84,6 +84,6 @@ int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev); void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev); void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev); -int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); +void amdgpu_debugfs_pm_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 10b0624ade651eaa0d5ae30d4d8426cc7323f0c6..25d5f03aaa679a4b94d049bfe84691d1ca3e22ae 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -171,6 +171,7 @@ enum smu_ppt_limit_level { SMU_PPT_LIMIT_MIN = -1, SMU_PPT_LIMIT_CURRENT, + SMU_PPT_LIMIT_DEFAULT, SMU_PPT_LIMIT_MAX, }; @@ -439,9 +440,6 @@ struct smu_context struct smu_baco_context smu_baco; struct smu_temperature_range thermal_range; void *od_settings; -#if defined(CONFIG_DEBUG_FS) - struct dentry *debugfs_sclk; -#endif struct smu_umd_pstate_table pstate_table; uint32_t pstate_sclk; @@ -449,6 +447,7 @@ struct smu_context bool od_enabled; uint32_t current_power_limit; + uint32_t default_power_limit; uint32_t max_power_limit; /* soft pptable */ @@ -1047,6 +1046,10 @@ struct pptable_funcs { * @mode1_reset_is_support: Check if GPU supports mode1 reset. */ bool (*mode1_reset_is_support)(struct smu_context *smu); + /** + * @mode2_reset_is_support: Check if GPU supports mode2 reset. + */ + bool (*mode2_reset_is_support)(struct smu_context *smu); /** * @mode1_reset: Perform mode1 reset. @@ -1152,6 +1155,11 @@ struct pptable_funcs { * parameters to defaults. */ int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); + + /** + * @set_light_sbr: Set light sbr mode for the SMU. + */ + int (*set_light_sbr)(struct smu_context *smu, bool enable); }; typedef enum { @@ -1233,33 +1241,28 @@ int smu_check_fw_status(struct smu_context *smu); int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); -int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed); +int smu_set_fan_speed_rpm(void *handle, uint32_t speed); int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, enum smu_ppt_limit_level limit_level); -int smu_set_power_limit(struct smu_context *smu, uint32_t limit); -int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); +int smu_set_power_limit(void *handle, uint32_t limit); +int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf); -int smu_od_edit_dpm_table(struct smu_context *smu, +int smu_od_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, long *input, uint32_t size); -int smu_read_sensor(struct smu_context *smu, - enum amd_pp_sensors sensor, - void *data, uint32_t *size); -int smu_get_power_profile_mode(struct smu_context *smu, char *buf); - -int smu_set_power_profile_mode(struct smu_context *smu, - long *param, - uint32_t param_size, - bool lock_needed); -int smu_get_fan_control_mode(struct smu_context *smu); +int smu_read_sensor(void *handle, int sensor, void *data, int *size); +int smu_get_power_profile_mode(void *handle, char *buf); +int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size); +u32 smu_get_fan_control_mode(void *handle); int smu_set_fan_control_mode(struct smu_context *smu, int value); -int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed); -int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); -int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed); +void smu_pp_set_fan_control_mode(void *handle, u32 value); +int smu_get_fan_speed_percent(void *handle, u32 *speed); +int smu_set_fan_speed_percent(void *handle, u32 speed); +int smu_get_fan_speed_rpm(void *handle, uint32_t *speed); int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk); @@ -1271,34 +1274,39 @@ int smu_display_clock_voltage_request(struct smu_context *smu, struct pp_display_clock_request *clock_req); int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch); -int smu_set_xgmi_pstate(struct smu_context *smu, +int smu_set_xgmi_pstate(void *handle, uint32_t pstate); int smu_set_azalia_d3_pme(struct smu_context *smu); bool smu_baco_is_support(struct smu_context *smu); +int smu_get_baco_capability(void *handle, bool *cap); int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state); int smu_baco_enter(struct smu_context *smu); int smu_baco_exit(struct smu_context *smu); +int smu_baco_set_state(void *handle, int state); + bool smu_mode1_reset_is_support(struct smu_context *smu); +bool smu_mode2_reset_is_support(struct smu_context *smu); int smu_mode1_reset(struct smu_context *smu); -int smu_mode2_reset(struct smu_context *smu); +int smu_mode2_reset(void *handle); extern const struct amd_ip_funcs smu_ip_funcs; extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; +extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; bool is_support_sw_smu(struct amdgpu_device *adev); bool is_support_cclk_dpm(struct amdgpu_device *adev); int smu_reset(struct smu_context *smu); -int smu_sys_get_pp_table(struct smu_context *smu, void **table); -int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size); -int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info); -enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu); +int smu_sys_get_pp_table(void *handle, char **table); +int smu_sys_set_pp_table(void *handle, const char *buf, size_t size); +int smu_get_power_num_states(void *handle, struct pp_states_info *state_info); +enum amd_pm_state_type smu_get_current_power_state(void *handle); int smu_write_watermarks_table(struct smu_context *smu); int smu_set_watermarks_for_clock_ranges( struct smu_context *smu, @@ -1308,30 +1316,33 @@ int smu_set_watermarks_for_clock_ranges( extern int smu_display_configuration_change(struct smu_context *smu, const struct amd_pp_display_configuration *display_config); -extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate); +extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate); extern int smu_handle_task(struct smu_context *smu, enum amd_dpm_forced_level level, enum amd_pp_task task_id, bool lock_needed); -int smu_switch_power_profile(struct smu_context *smu, +extern int smu_handle_dpm_task(void *handle, + enum amd_pp_task task_id, + enum amd_pm_state_type *user_state); +int smu_switch_power_profile(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); +u32 smu_get_mclk(void *handle, bool low); +u32 smu_get_sclk(void *handle, bool low); int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); -enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); -int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); +enum amd_dpm_forced_level smu_get_performance_level(void *handle); +int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level); int smu_set_display_count(struct smu_context *smu, uint32_t count); int smu_set_ac_dc(struct smu_context *smu); -size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); -int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); -int smu_force_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, - uint32_t mask); -int smu_set_mp1_state(struct smu_context *smu, +int smu_sys_get_pp_feature_mask(void *handle, char *buf); +int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask); +int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask); +int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); -int smu_set_df_cstate(struct smu_context *smu, +int smu_set_df_cstate(void *handle, enum pp_df_cstate state); int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); @@ -1347,10 +1358,12 @@ int smu_get_dpm_clock_table(struct smu_context *smu, int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); -ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table); +ssize_t smu_sys_get_gpu_metrics(void *handle, void **table); -int smu_enable_mgpu_fan_boost(struct smu_context *smu); +int smu_enable_mgpu_fan_boost(void *handle); int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state); +int smu_set_light_sbr(struct smu_context *smu, bool enable); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h index 79afb132164ead8ef485028b4abb931689090d4e..45f5d29bc70574662c1380c15ab2a16049396335 100644 --- a/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h @@ -120,6 +120,13 @@ #define PPSMC_MSG_ReadSerialNumTop32 0x40 #define PPSMC_MSG_ReadSerialNumBottom32 0x41 +/* paramater for MSG_LightSBR + * 1 -- Enable light secondary bus reset, only do nbio respond without further handling, + * leave driver to handle the real reset + * 0 -- Disable LightSBR, default behavior, SMU will pass the reset to PSP + */ +#define PPSMC_MSG_LightSBR 0x42 + typedef uint32_t PPSMC_Result; typedef uint32_t PPSMC_Msg; #pragma pack(pop) diff --git a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h index 4c7e08ba5fa4b96735615611f3804c9d138ca98c..171f12b8271650d7e9b7963b0b83fbbdfde45bc4 100644 --- a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h @@ -84,6 +84,7 @@ #define PPSMC_MSG_PowerGateMmHub 0x35 #define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36 #define PPSMC_MSG_GpuChangeState 0x37 +#define PPSMC_MSG_GetGfxBusy 0x3D #define PPSMC_Message_Count 0x42 typedef uint16_t PPSMC_Result; diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h index 246d3951a78ab471bc7cc9f7bdc293a020755337..04752ade10165f3e23ac1e9b31e665072ad05e36 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h +++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h @@ -843,11 +843,15 @@ typedef struct { uint16_t FanMaximumRpm; uint16_t FanMinimumPwm; uint16_t FanTargetTemperature; // Degree Celcius + uint16_t FanMode; + uint16_t FanMaxPwm; + uint16_t FanMinPwm; + uint16_t FanMaxTemp; // Degree Celcius + uint16_t FanMinTemp; // Degree Celcius uint16_t MaxOpTemp; // Degree Celcius uint16_t FanZeroRpmEnable; - uint16_t Padding; - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[6]; // SMU internal use } OverDriveTable_t; @@ -880,6 +884,45 @@ typedef struct { uint8_t Padding8_2; uint16_t CurrFanSpeed; + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} SmuMetrics_legacy_t; + +typedef struct { + uint16_t CurrClock[PPCLK_COUNT]; + uint16_t AverageGfxclkFrequencyPostDs; + uint16_t AverageSocclkFrequency; + uint16_t AverageUclkFrequencyPostDs; + uint16_t AverageGfxActivity ; + uint16_t AverageUclkActivity ; + uint8_t CurrSocVoltageOffset ; + uint8_t CurrGfxVoltageOffset ; + uint8_t CurrMemVidOffset ; + uint8_t Padding8 ; + uint16_t AverageSocketPower ; + uint16_t TemperatureEdge ; + uint16_t TemperatureHotspot ; + uint16_t TemperatureMem ; + uint16_t TemperatureVrGfx ; + uint16_t TemperatureVrMem0 ; + uint16_t TemperatureVrMem1 ; + uint16_t TemperatureVrSoc ; + uint16_t TemperatureLiquid0 ; + uint16_t TemperatureLiquid1 ; + uint16_t TemperaturePlx ; + uint16_t Padding16 ; + uint32_t ThrottlerStatus ; + + uint8_t LinkDpmLevel; + uint8_t Padding8_2; + uint16_t CurrFanSpeed; + + uint16_t AverageGfxclkFrequencyPreDs; + uint16_t AverageUclkFrequencyPreDs; + uint8_t PcieRate; + uint8_t PcieWidth; + uint8_t Padding8_3[2]; + // Padding - ignore uint32_t MmHubPadding[8]; // SMU internal use } SmuMetrics_t; @@ -919,10 +962,61 @@ typedef struct { uint16_t VcnActivityPercentage ; uint16_t padding16_2; + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} SmuMetrics_NV12_legacy_t; + +typedef struct { + uint16_t CurrClock[PPCLK_COUNT]; + uint16_t AverageGfxclkFrequencyPostDs; + uint16_t AverageSocclkFrequency; + uint16_t AverageUclkFrequencyPostDs; + uint16_t AverageGfxActivity ; + uint16_t AverageUclkActivity ; + uint8_t CurrSocVoltageOffset ; + uint8_t CurrGfxVoltageOffset ; + uint8_t CurrMemVidOffset ; + uint8_t Padding8 ; + uint16_t AverageSocketPower ; + uint16_t TemperatureEdge ; + uint16_t TemperatureHotspot ; + uint16_t TemperatureMem ; + uint16_t TemperatureVrGfx ; + uint16_t TemperatureVrMem0 ; + uint16_t TemperatureVrMem1 ; + uint16_t TemperatureVrSoc ; + uint16_t TemperatureLiquid0 ; + uint16_t TemperatureLiquid1 ; + uint16_t TemperaturePlx ; + uint16_t Padding16 ; + uint32_t ThrottlerStatus ; + + uint8_t LinkDpmLevel; + uint8_t Padding8_2; + uint16_t CurrFanSpeed; + + uint16_t AverageVclkFrequency ; + uint16_t AverageDclkFrequency ; + uint16_t VcnActivityPercentage ; + uint16_t AverageGfxclkFrequencyPreDs; + uint16_t AverageUclkFrequencyPreDs; + uint8_t PcieRate; + uint8_t PcieWidth; + + uint32_t Padding32_1; + uint64_t EnergyAccumulator; + // Padding - ignore uint32_t MmHubPadding[8]; // SMU internal use } SmuMetrics_NV12_t; +typedef union SmuMetrics { + SmuMetrics_legacy_t nv10_legacy_metrics; + SmuMetrics_t nv10_metrics; + SmuMetrics_NV12_legacy_t nv12_legacy_metrics; + SmuMetrics_NV12_t nv12_metrics; +} SmuMetrics_NV1X_t; + typedef struct { uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h new file mode 100644 index 0000000000000000000000000000000000000000..df2ead254f37e4ecad14d67b4ee0921ca13f6fbd --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h @@ -0,0 +1,512 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU13_DRIVER_IF_ALDEBARAN_H +#define SMU13_DRIVER_IF_ALDEBARAN_H + +#define NUM_VCLK_DPM_LEVELS 8 +#define NUM_DCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_LCLK_DPM_LEVELS 8 +#define NUM_UCLK_DPM_LEVELS 4 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_XGMI_DPM_LEVELS 4 + +// Feature Control Defines +#define FEATURE_DATA_CALCULATIONS 0 +#define FEATURE_DPM_GFXCLK_BIT 1 +#define FEATURE_DPM_UCLK_BIT 2 +#define FEATURE_DPM_SOCCLK_BIT 3 +#define FEATURE_DPM_FCLK_BIT 4 +#define FEATURE_DPM_LCLK_BIT 5 +#define FEATURE_DPM_XGMI_BIT 6 +#define FEATURE_DS_GFXCLK_BIT 7 +#define FEATURE_DS_SOCCLK_BIT 8 +#define FEATURE_DS_LCLK_BIT 9 +#define FEATURE_DS_FCLK_BIT 10 +#define FEATURE_DS_UCLK_BIT 11 +#define FEATURE_GFX_SS_BIT 12 +#define FEATURE_DPM_VCN_BIT 13 +#define FEATURE_RSMU_SMN_CG_BIT 14 +#define FEATURE_WAFL_CG_BIT 15 +#define FEATURE_PPT_BIT 16 +#define FEATURE_TDC_BIT 17 +#define FEATURE_APCC_PLUS_BIT 18 +#define FEATURE_APCC_DFLL_BIT 19 +#define FEATURE_FW_CTF_BIT 20 +#define FEATURE_THERMAL_BIT 21 +#define FEATURE_OUT_OF_BAND_MONITOR_BIT 22 +#define FEATURE_SPARE_23_BIT 23 +#define FEATURE_XGMI_PER_LINK_PWR_DWN 24 +#define FEATURE_DF_CSTATE 25 +#define FEATURE_FUSE_CG_BIT 26 +#define FEATURE_MP1_CG_BIT 27 +#define FEATURE_SMUIO_CG_BIT 28 +#define FEATURE_THM_CG_BIT 29 +#define FEATURE_CLK_CG_BIT 30 +#define FEATURE_SPARE_31_BIT 31 +#define FEATURE_SPARE_32_BIT 32 +#define FEATURE_SPARE_33_BIT 33 +#define FEATURE_SPARE_34_BIT 34 +#define FEATURE_SPARE_35_BIT 35 +#define FEATURE_SPARE_36_BIT 36 +#define FEATURE_SPARE_37_BIT 37 +#define FEATURE_SPARE_38_BIT 38 +#define FEATURE_SPARE_39_BIT 39 +#define FEATURE_SPARE_40_BIT 40 +#define FEATURE_SPARE_41_BIT 41 +#define FEATURE_SPARE_42_BIT 42 +#define FEATURE_SPARE_43_BIT 43 +#define FEATURE_SPARE_44_BIT 44 +#define FEATURE_SPARE_45_BIT 45 +#define FEATURE_SPARE_46_BIT 46 +#define FEATURE_SPARE_47_BIT 47 +#define FEATURE_SPARE_48_BIT 48 +#define FEATURE_SPARE_49_BIT 49 +#define FEATURE_SPARE_50_BIT 50 +#define FEATURE_SPARE_51_BIT 51 +#define FEATURE_SPARE_52_BIT 52 +#define FEATURE_SPARE_53_BIT 53 +#define FEATURE_SPARE_54_BIT 54 +#define FEATURE_SPARE_55_BIT 55 +#define FEATURE_SPARE_56_BIT 56 +#define FEATURE_SPARE_57_BIT 57 +#define FEATURE_SPARE_58_BIT 58 +#define FEATURE_SPARE_59_BIT 59 +#define FEATURE_SPARE_60_BIT 60 +#define FEATURE_SPARE_61_BIT 61 +#define FEATURE_SPARE_62_BIT 62 +#define FEATURE_SPARE_63_BIT 63 + +#define NUM_FEATURES 64 + +// I2C Config Bit Defines +#define I2C_CONTROLLER_ENABLED 1 +#define I2C_CONTROLLER_DISABLED 0 + +// Throttler Status Bits. +// These are aligned with the out of band monitor alarm bits for common throttlers +#define THROTTLER_PPT0_BIT 0 +#define THROTTLER_PPT1_BIT 1 +#define THROTTLER_TDC_GFX_BIT 2 +#define THROTTLER_TDC_SOC_BIT 3 +#define THROTTLER_TDC_HBM_BIT 4 +#define THROTTLER_SPARE_5 5 +#define THROTTLER_TEMP_GPU_BIT 6 +#define THROTTLER_TEMP_MEM_BIT 7 +#define THORTTLER_SPARE_8 8 +#define THORTTLER_SPARE_9 9 +#define THORTTLER_SPARE_10 10 +#define THROTTLER_TEMP_VR_GFX_BIT 11 +#define THROTTLER_TEMP_VR_SOC_BIT 12 +#define THROTTLER_TEMP_VR_MEM_BIT 13 +#define THORTTLER_SPARE_14 14 +#define THORTTLER_SPARE_15 15 +#define THORTTLER_SPARE_16 16 +#define THORTTLER_SPARE_17 17 +#define THORTTLER_SPARE_18 18 +#define THROTTLER_APCC_BIT 19 + +// Table transfer status +#define TABLE_TRANSFER_OK 0x0 +#define TABLE_TRANSFER_FAILED 0xFF +#define TABLE_TRANSFER_PENDING 0xAB + +//I2C Interface +#define NUM_I2C_CONTROLLERS 8 + +#define I2C_CONTROLLER_ENABLED 1 +#define I2C_CONTROLLER_DISABLED 0 + +#define MAX_SW_I2C_COMMANDS 24 + +typedef enum { + I2C_CONTROLLER_PORT_0, //CKSVII2C0 + I2C_CONTROLLER_PORT_1, //CKSVII2C1 + I2C_CONTROLLER_PORT_COUNT, +} I2cControllerPort_e; + +typedef enum { + I2C_CONTROLLER_THROTTLER_TYPE_NONE, + I2C_CONTROLLER_THROTTLER_VR_GFX0, + I2C_CONTROLLER_THROTTLER_VR_GFX1, + I2C_CONTROLLER_THROTTLER_VR_SOC, + I2C_CONTROLLER_THROTTLER_VR_MEM, + I2C_CONTROLLER_THROTTLER_COUNT, +} I2cControllerThrottler_e; + +typedef enum { + I2C_CONTROLLER_PROTOCOL_VR_MP2855, + I2C_CONTROLLER_PROTOCOL_COUNT, +} I2cControllerProtocol_e; + +typedef struct { + uint8_t Enabled; + uint8_t Speed; + uint8_t SlaveAddress; + uint8_t ControllerPort; + uint8_t ThermalThrotter; + uint8_t I2cProtocol; + uint8_t PaddingConfig[2]; +} I2cControllerConfig_t; + +typedef enum { + I2C_PORT_SVD_SCL, + I2C_PORT_GPIO, +} I2cPort_e; + +typedef enum { + I2C_SPEED_FAST_50K, //50 Kbits/s + I2C_SPEED_FAST_100K, //100 Kbits/s + I2C_SPEED_FAST_400K, //400 Kbits/s + I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) + I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) + I2C_SPEED_HIGH_2M, //2.3 Mbits/s + I2C_SPEED_COUNT, +} I2cSpeed_e; + +typedef enum { + I2C_CMD_READ, + I2C_CMD_WRITE, + I2C_CMD_COUNT, +} I2cCmdType_e; + +#define CMDCONFIG_STOP_BIT 0 +#define CMDCONFIG_RESTART_BIT 1 +#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write + +#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) +#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) +#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) + +typedef struct { + uint8_t ReadWriteData; //Return data for read. Data to send for write + uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write +} SwI2cCmd_t; //SW I2C Command Table + +typedef struct { + uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) + uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select + uint8_t SlaveAddress; //Slave address of device + uint8_t NumCmds; //Number of commands + SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; +} SwI2cRequest_t; // SW I2C Request Table + +typedef struct { + SwI2cRequest_t SwI2cRequest; + uint32_t Spare[8]; + uint32_t MmHubPadding[8]; // SMU internal use +} SwI2cRequestExternal_t; + +typedef struct { + uint32_t a; // store in IEEE float format in this variable + uint32_t b; // store in IEEE float format in this variable + uint32_t c; // store in IEEE float format in this variable +} QuadraticInt_t; + +typedef struct { + uint32_t m; // store in IEEE float format in this variable + uint32_t b; // store in IEEE float format in this variable +} LinearInt_t; + +typedef enum { + GFXCLK_SOURCE_PLL, + GFXCLK_SOURCE_DFLL, + GFXCLK_SOURCE_COUNT, +} GfxclkSrc_e; + +typedef enum { + PPCLK_GFXCLK, + PPCLK_VCLK, + PPCLK_DCLK, + PPCLK_SOCCLK, + PPCLK_UCLK, + PPCLK_FCLK, + PPCLK_LCLK, + PPCLK_COUNT, +} PPCLK_e; + +typedef enum { + GPIO_INT_POLARITY_ACTIVE_LOW, + GPIO_INT_POLARITY_ACTIVE_HIGH, +} GpioIntPolarity_e; + +//PPSMC_MSG_SetUclkDpmMode +typedef enum { + UCLK_DPM_MODE_BANDWIDTH, + UCLK_DPM_MODE_LATENCY, +} UCLK_DPM_MODE_e; + +typedef struct { + uint8_t StartupLevel; + uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used + uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin + LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) + QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) +} DpmDescriptor_t; + +typedef struct { + uint32_t Version; + + // SECTION: Feature Enablement + uint32_t FeaturesToRun[2]; + + // SECTION: Infrastructure Limits + uint16_t PptLimit; // Watts + uint16_t TdcLimitGfx; // Amps + uint16_t TdcLimitSoc; // Amps + uint16_t TdcLimitHbm; // Amps + uint16_t ThotspotLimit; // Celcius + uint16_t TmemLimit; // Celcius + uint16_t Tvr_gfxLimit; // Celcius + uint16_t Tvr_memLimit; // Celcius + uint16_t Tvr_socLimit; // Celcius + uint16_t PaddingLimit; + + // SECTION: Voltage Control Parameters + uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX + uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC + + //SECTION: DPM Config 1 + DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; + + uint8_t DidTableVclk[NUM_VCLK_DPM_LEVELS]; //PPCLK_VCLK + uint8_t DidTableDclk[NUM_DCLK_DPM_LEVELS]; //PPCLK_DCLK + uint8_t DidTableSocclk[NUM_SOCCLK_DPM_LEVELS]; //PPCLK_SOCCLK + uint8_t DidTableLclk[NUM_LCLK_DPM_LEVELS]; //PPCLK_LCLK + uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK + uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK + uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK + uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK + + uint32_t StartupFidPll0; //GFXAVFSCLK, SOCCLK, MP0CLK, MPIOCLK, DXIOCLK + uint32_t StartupFidPll4; //VCLK, DCLK, WAFLCLK + uint32_t StartupFidPll5; //SMNCLK, MP1CLK, LCLK + + uint8_t StartupSmnclkDid; + uint8_t StartupMp0clkDid; + uint8_t StartupMp1clkDid; + uint8_t StartupWaflclkDid; + uint8_t StartupGfxavfsclkDid; + uint8_t StartupMpioclkDid; + uint8_t StartupDxioclkDid; + uint8_t spare123; + + uint8_t StartupVidGpu0Svi0Plane0; //VDDCR_GFX0 + uint8_t StartupVidGpu0Svi0Plane1; //VDDCR_SOC + uint8_t StartupVidGpu0Svi1Plane0; //VDDCR_HBM + uint8_t StartupVidGpu0Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] + + uint8_t StartupVidGpu1Svi0Plane0; //VDDCR_GFX1 + uint8_t StartupVidGpu1Svi0Plane1; //UNUSED [0 = plane is not used and should not be programmed] + uint8_t StartupVidGpu1Svi1Plane0; //UNUSED [0 = plane is not used and should not be programmed] + uint8_t StartupVidGpu1Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] + + // GFXCLK DPM + uint16_t GfxclkFmax; // In MHz + uint16_t GfxclkFmin; // In MHz + uint16_t GfxclkFidle; // In MHz + uint16_t GfxclkFinit; // In MHz + uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL] + uint8_t spare1[2]; + uint8_t StartupGfxclkDid; + uint32_t StartupGfxclkFid; + + // SECTION: AVFS + uint16_t GFX_Guardband_Freq[8]; // MHz [unsigned] + int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed] + int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed] + int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed] + + uint16_t SOC_Guardband_Freq[8]; // MHz [unsigned] + int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed] + int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed] + int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed] + + // VDDCR_GFX BTC + uint16_t DcBtcEnabled; + int16_t DcBtcMin; // mV [signed] + int16_t DcBtcMax; // mV [signed] + int16_t DcBtcGb; // mV [signed] + + // SECTION: XGMI + uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps] + uint8_t XgmiLinkWidth[NUM_XGMI_DPM_LEVELS]; //Width [EX: 16 = x16] + uint8_t XgmiStartupLevel; + uint8_t spare12[3]; + + // GFX Vmin + uint16_t GFX_PPVmin_Enabled; + uint16_t GFX_Vmin_Plat_Offset_Hot; // mV + uint16_t GFX_Vmin_Plat_Offset_Cold; // mV + uint16_t GFX_Vmin_Hot_T0; // mV + uint16_t GFX_Vmin_Cold_T0; // mV + uint16_t GFX_Vmin_Hot_Eol; // mV + uint16_t GFX_Vmin_Cold_Eol; // mV + uint16_t GFX_Vmin_Aging_Offset; // mV + uint16_t GFX_Vmin_Temperature_Hot; // 'C + uint16_t GFX_Vmin_Temperature_Cold; // 'C + + // SOC Vmin + uint16_t SOC_PPVmin_Enabled; + uint16_t SOC_Vmin_Plat_Offset_Hot; // mV + uint16_t SOC_Vmin_Plat_Offset_Cold; // mV + uint16_t SOC_Vmin_Hot_T0; // mV + uint16_t SOC_Vmin_Cold_T0; // mV + uint16_t SOC_Vmin_Hot_Eol; // mV + uint16_t SOC_Vmin_Cold_Eol; // mV + uint16_t SOC_Vmin_Aging_Offset; // mV + uint16_t SOC_Vmin_Temperature_Hot; // 'C + uint16_t SOC_Vmin_Temperature_Cold; // 'C + + // APCC Settings + uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100) + + // Determinism + uint16_t DeterminismVoltageOffset; //mV + uint16_t spare22; + + // reserved + uint32_t spare3[14]; + + // SECTION: BOARD PARAMETERS + // Telemetry Settings + uint16_t GfxMaxCurrent; // in Amps + int8_t GfxOffset; // in Amps + uint8_t Padding_TelemetryGfx; + + uint16_t SocMaxCurrent; // in Amps + int8_t SocOffset; // in Amps + uint8_t Padding_TelemetrySoc; + + uint16_t MemMaxCurrent; // in Amps + int8_t MemOffset; // in Amps + uint8_t Padding_TelemetryMem; + + uint16_t BoardMaxCurrent; // in Amps + int8_t BoardOffset; // in Amps + uint8_t Padding_TelemetryBoardInput; + + // Platform input telemetry voltage coefficient + uint32_t BoardVoltageCoeffA; // decode by /1000 + uint32_t BoardVoltageCoeffB; // decode by /1000 + + // GPIO Settings + uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event + uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + + // UCLK Spread Spectrum + uint8_t UclkSpreadEnabled; // on or off + uint8_t UclkSpreadPercent; // Q4.4 + uint16_t UclkSpreadFreq; // kHz + + // FCLK Spread Spectrum + uint8_t FclkSpreadEnabled; // on or off + uint8_t FclkSpreadPercent; // Q4.4 + uint16_t FclkSpreadFreq; // kHz + + // I2C Controller Structure + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + + // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence + uint8_t GpioI2cScl; // Serial Clock + uint8_t GpioI2cSda; // Serial Data + uint16_t spare5; + + //reserved + uint32_t reserved[16]; + +} PPTable_t; + +typedef struct { + // Time constant parameters for clock averages in ms + uint16_t GfxclkAverageLpfTau; + uint16_t SocclkAverageLpfTau; + uint16_t UclkAverageLpfTau; + uint16_t GfxActivityLpfTau; + uint16_t UclkActivityLpfTau; + + uint16_t SocketPowerLpfTau; + + uint32_t Spare[8]; + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} DriverSmuConfig_t; + +typedef struct { + uint16_t CurrClock[PPCLK_COUNT]; + uint16_t Padding1 ; + uint16_t AverageGfxclkFrequency; + uint16_t AverageSocclkFrequency; + uint16_t AverageUclkFrequency ; + uint16_t AverageGfxActivity ; + uint16_t AverageUclkActivity ; + uint8_t CurrSocVoltageOffset ; + uint8_t CurrGfxVoltageOffset ; + uint8_t CurrMemVidOffset ; + uint8_t Padding8 ; + uint16_t AverageSocketPower ; + uint16_t TemperatureEdge ; + uint16_t TemperatureHotspot ; + uint16_t TemperatureHBM ; // Max + uint16_t TemperatureVrGfx ; + uint16_t TemperatureVrSoc ; + uint16_t TemperatureVrMem ; + uint32_t ThrottlerStatus ; + + uint32_t PublicSerialNumLower32; + uint32_t PublicSerialNumUpper32; + uint16_t TemperatureAllHBM[4] ; + uint32_t GfxBusyAcc ; + uint32_t DramBusyAcc ; + uint32_t Spare[4]; + + // Padding - ignore + uint32_t MmHubPadding[8]; // SMU internal use +} SmuMetrics_t; + + +typedef struct { + uint16_t avgPsmCount[76]; + uint16_t minPsmCount[76]; + float avgPsmVoltage[76]; + float minPsmVoltage[76]; + + uint32_t MmHubPadding[8]; // SMU internal use +} AvfsDebugTable_t; + +// These defines are used with the following messages: +// SMC_MSG_TransferTableDram2Smu +// SMC_MSG_TransferTableSmu2Dram +#define TABLE_PPTABLE 0 +#define TABLE_AVFS_PSM_DEBUG 1 +#define TABLE_AVFS_FUSE_OVERRIDE 2 +#define TABLE_PMSTATUSLOG 3 +#define TABLE_SMU_METRICS 4 +#define TABLE_DRIVER_SMU_CONFIG 5 +#define TABLE_I2C_COMMANDS 6 +#define TABLE_COUNT 7 + +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index aa4822202587f327e06b96ad3d5a988cf528e0cc..5bfb60f41dd422b92d685aea3db2c0a2df1f0c73 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -168,9 +168,16 @@ __SMU_DUMMY_MAP(PowerGateAtHub), \ __SMU_DUMMY_MAP(SetSoftMinJpeg), \ __SMU_DUMMY_MAP(SetHardMinFclkByFreq), \ - __SMU_DUMMY_MAP(DFCstateControl), \ - __SMU_DUMMY_MAP(GmiPwrDnControl), \ - __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\ + __SMU_DUMMY_MAP(DFCstateControl), \ + __SMU_DUMMY_MAP(GmiPwrDnControl), \ + __SMU_DUMMY_MAP(spare), \ + __SMU_DUMMY_MAP(SetNumBadHbmPagesRetired), \ + __SMU_DUMMY_MAP(GetGmiPwrDnHyst), \ + __SMU_DUMMY_MAP(SetGmiPwrDnHyst), \ + __SMU_DUMMY_MAP(EnterGfxoff), \ + __SMU_DUMMY_MAP(ExitGfxoff), \ + __SMU_DUMMY_MAP(SetExecuteDMATest), \ + __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \ __SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \ __SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \ __SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \ @@ -214,6 +221,10 @@ __SMU_DUMMY_MAP(SetSlowPPTLimit), \ __SMU_DUMMY_MAP(GetFastPPTLimit), \ __SMU_DUMMY_MAP(GetSlowPPTLimit), \ + __SMU_DUMMY_MAP(EnableDeterminism), \ + __SMU_DUMMY_MAP(DisableDeterminism), \ + __SMU_DUMMY_MAP(SetUclkDpmMode), \ + __SMU_DUMMY_MAP(LightSBR), \ #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type @@ -239,6 +250,7 @@ enum smu_clk_type { SMU_SCLK, SMU_MCLK, SMU_PCIE, + SMU_LCLK, SMU_OD_CCLK, SMU_OD_SCLK, SMU_OD_MCLK, @@ -255,6 +267,7 @@ enum smu_clk_type { __SMU_DUMMY_MAP(DPM_SOCCLK), \ __SMU_DUMMY_MAP(DPM_UVD), \ __SMU_DUMMY_MAP(DPM_VCE), \ + __SMU_DUMMY_MAP(DPM_LCLK), \ __SMU_DUMMY_MAP(ULV), \ __SMU_DUMMY_MAP(DPM_MP0CLK), \ __SMU_DUMMY_MAP(DPM_LINK), \ @@ -283,6 +296,7 @@ enum smu_clk_type { __SMU_DUMMY_MAP(DS_MP1CLK), \ __SMU_DUMMY_MAP(DS_MP0CLK), \ __SMU_DUMMY_MAP(XGMI), \ + __SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN), \ __SMU_DUMMY_MAP(DPM_GFX_PACE), \ __SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \ __SMU_DUMMY_MAP(MEM_MVDD_SCALING), \ @@ -304,6 +318,7 @@ enum smu_clk_type { __SMU_DUMMY_MAP(MMHUB_PG), \ __SMU_DUMMY_MAP(ATHUB_PG), \ __SMU_DUMMY_MAP(APCC_DFLL), \ + __SMU_DUMMY_MAP(DF_CSTATE), \ __SMU_DUMMY_MAP(DPM_GFX_GPO), \ __SMU_DUMMY_MAP(WAFL_CG), \ __SMU_DUMMY_MAP(CCLK_DPM), \ @@ -335,7 +350,12 @@ enum smu_clk_type { __SMU_DUMMY_MAP(ISP_DPM), \ __SMU_DUMMY_MAP(A55_DPM), \ __SMU_DUMMY_MAP(CVIP_DSP_DPM), \ - __SMU_DUMMY_MAP(MSMU_LOW_POWER), + __SMU_DUMMY_MAP(MSMU_LOW_POWER), \ + __SMU_DUMMY_MAP(FUSE_CG), \ + __SMU_DUMMY_MAP(MP1_CG), \ + __SMU_DUMMY_MAP(SMUIO_CG), \ + __SMU_DUMMY_MAP(THM_CG), \ + __SMU_DUMMY_MAP(CLK_CG), \ #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index d4cddd2390a29d1d54f6003714321791f9bc516f..ad4db2edf1fb2d140a650d3bd6a12b230830fa80 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -27,9 +27,9 @@ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF #define SMU11_DRIVER_IF_VERSION_ARCT 0x17 -#define SMU11_DRIVER_IF_VERSION_NV10 0x36 -#define SMU11_DRIVER_IF_VERSION_NV12 0x36 -#define SMU11_DRIVER_IF_VERSION_NV14 0x36 +#define SMU11_DRIVER_IF_VERSION_NV10 0x37 +#define SMU11_DRIVER_IF_VERSION_NV12 0x38 +#define SMU11_DRIVER_IF_VERSION_NV14 0x38 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3D #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02 @@ -58,6 +58,12 @@ #define CTF_OFFSET_HOTSPOT 5 #define CTF_OFFSET_MEM 5 +#define LINK_WIDTH_MAX 6 +#define LINK_SPEED_MAX 3 + +static __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16}; +static __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160}; + static const struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = { @@ -135,6 +141,7 @@ struct smu_11_5_power_context { enum smu_11_0_power_state power_state; uint32_t current_fast_ppt_limit; + uint32_t default_fast_ppt_limit; uint32_t max_fast_ppt_limit; }; @@ -275,11 +282,11 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu, int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu); -int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); +uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu); -int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); +uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement); @@ -289,5 +296,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu, void smu_v11_0_interrupt_work(struct smu_context *smu); +int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h new file mode 100644 index 0000000000000000000000000000000000000000..80208e1eefc95b82c9852e730c1d322c37bd8f6d --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h @@ -0,0 +1,272 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_V13_0_H__ +#define __SMU_V13_0_H__ + +#include "amdgpu_smu.h" + +#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF +#define SMU13_DRIVER_IF_VERSION_ALDE 0x5 + +/* MP Apertures */ +#define MP0_Public 0x03800000 +#define MP0_SRAM 0x03900000 +#define MP1_Public 0x03b00000 +#define MP1_SRAM 0x03c00004 + +/* address block */ +#define smnMP1_FIRMWARE_FLAGS 0x3010024 +#define smnMP0_FW_INTF 0x30101c0 +#define smnMP1_PUB_CTRL 0x3010b14 + +#define TEMP_RANGE_MIN (0) +#define TEMP_RANGE_MAX (80 * 1000) + +#define SMU13_TOOL_SIZE 0x19000 + +#define MAX_DPM_LEVELS 16 +#define MAX_PCIE_CONF 2 + +#define CTF_OFFSET_EDGE 5 +#define CTF_OFFSET_HOTSPOT 5 +#define CTF_OFFSET_MEM 5 + +static const struct smu_temperature_range smu13_thermal_policy[] = +{ + {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, + { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, +}; + +struct smu_13_0_max_sustainable_clocks { + uint32_t display_clock; + uint32_t phy_clock; + uint32_t pixel_clock; + uint32_t uclock; + uint32_t dcef_clock; + uint32_t soc_clock; +}; + +struct smu_13_0_dpm_clk_level { + bool enabled; + uint32_t value; +}; + +struct smu_13_0_dpm_table { + uint32_t min; /* MHz */ + uint32_t max; /* MHz */ + uint32_t count; + struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; +}; + +struct smu_13_0_pcie_table { + uint8_t pcie_gen[MAX_PCIE_CONF]; + uint8_t pcie_lane[MAX_PCIE_CONF]; +}; + +struct smu_13_0_dpm_tables { + struct smu_13_0_dpm_table soc_table; + struct smu_13_0_dpm_table gfx_table; + struct smu_13_0_dpm_table uclk_table; + struct smu_13_0_dpm_table eclk_table; + struct smu_13_0_dpm_table vclk_table; + struct smu_13_0_dpm_table dclk_table; + struct smu_13_0_dpm_table dcef_table; + struct smu_13_0_dpm_table pixel_table; + struct smu_13_0_dpm_table display_table; + struct smu_13_0_dpm_table phy_table; + struct smu_13_0_dpm_table fclk_table; + struct smu_13_0_pcie_table pcie_table; +}; + +struct smu_13_0_dpm_context { + struct smu_13_0_dpm_tables dpm_tables; + uint32_t workload_policy_mask; + uint32_t dcef_min_ds_clk; +}; + +enum smu_13_0_power_state { + SMU_13_0_POWER_STATE__D0 = 0, + SMU_13_0_POWER_STATE__D1, + SMU_13_0_POWER_STATE__D3, /* Sleep*/ + SMU_13_0_POWER_STATE__D4, /* Hibernate*/ + SMU_13_0_POWER_STATE__D5, /* Power off*/ +}; + +struct smu_13_0_power_context { + uint32_t power_source; + uint8_t in_power_limit_boost_mode; + enum smu_13_0_power_state power_state; +}; + +enum smu_v13_0_baco_seq { + BACO_SEQ_BACO = 0, + BACO_SEQ_MSR, + BACO_SEQ_BAMACO, + BACO_SEQ_ULPS, + BACO_SEQ_COUNT, +}; + +#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) + +int smu_v13_0_init_microcode(struct smu_context *smu); + +void smu_v13_0_fini_microcode(struct smu_context *smu); + +int smu_v13_0_load_microcode(struct smu_context *smu); + +int smu_v13_0_init_smc_tables(struct smu_context *smu); + +int smu_v13_0_fini_smc_tables(struct smu_context *smu); + +int smu_v13_0_init_power(struct smu_context *smu); + +int smu_v13_0_fini_power(struct smu_context *smu); + +int smu_v13_0_check_fw_status(struct smu_context *smu); + +int smu_v13_0_setup_pptable(struct smu_context *smu); + +int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); + +int smu_v13_0_check_fw_version(struct smu_context *smu); + +int smu_v13_0_set_driver_table_location(struct smu_context *smu); + +int smu_v13_0_set_tool_table_location(struct smu_context *smu); + +int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); + +int smu_v13_0_system_features_control(struct smu_context *smu, + bool en); + +int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); + +int smu_v13_0_set_allowed_mask(struct smu_context *smu); + +int smu_v13_0_notify_display_change(struct smu_context *smu); + +int smu_v13_0_get_current_power_limit(struct smu_context *smu, + uint32_t *power_limit); + +int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n); + +int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); + +int smu_v13_0_enable_thermal_alert(struct smu_context *smu); + +int smu_v13_0_disable_thermal_alert(struct smu_context *smu); + +int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); + +int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); + +int +smu_v13_0_display_clock_voltage_request(struct smu_context *smu, + struct pp_display_clock_request + *clock_req); + +uint32_t +smu_v13_0_get_fan_control_mode(struct smu_context *smu); + +int +smu_v13_0_set_fan_control_mode(struct smu_context *smu, + uint32_t mode); + +int +smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); + +int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, + uint32_t speed); + +int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, + uint32_t pstate); + +int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); + +int smu_v13_0_register_irq_handler(struct smu_context *smu); + +int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); + +int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, + struct pp_smu_nv_clock_table *max_clocks); + +bool smu_v13_0_baco_is_support(struct smu_context *smu); + +enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); + +int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); + +int smu_v13_0_baco_enter(struct smu_context *smu); +int smu_v13_0_baco_exit(struct smu_context *smu); + +int smu_v13_0_mode1_reset(struct smu_context *smu); +int smu_v13_0_mode2_reset(struct smu_context *smu); + +int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t *min, uint32_t *max); + +int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t min, uint32_t max); + +int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max); + +int smu_v13_0_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level); + +int smu_v13_0_set_power_source(struct smu_context *smu, + enum smu_power_src_type power_src); + +int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint16_t level, + uint32_t *value); + +int smu_v13_0_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value); + +int smu_v13_0_set_single_dpm_table(struct smu_context *smu, + enum smu_clk_type clk_type, + struct smu_13_0_dpm_table *single_dpm_table); + +int smu_v13_0_get_dpm_level_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min_value, + uint32_t *max_value); + +int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); + +int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); + +int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); + +int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); + +int smu_v13_0_gfx_ulv_control(struct smu_context *smu, + bool enablement); + +#endif +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_pptable.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_pptable.h new file mode 100644 index 0000000000000000000000000000000000000000..1f311396b706700f5dba36c4bc4934bac348f662 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_pptable.h @@ -0,0 +1,165 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef SMU_13_0_PPTABLE_H +#define SMU_13_0_PPTABLE_H + +#define SMU_13_0_TABLE_FORMAT_REVISION 1 + +//// POWERPLAYTABLE::ulPlatformCaps +#define SMU_13_0_PP_PLATFORM_CAP_POWERPLAY 0x1 +#define SMU_13_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 +#define SMU_13_0_PP_PLATFORM_CAP_HARDWAREDC 0x4 +#define SMU_13_0_PP_PLATFORM_CAP_BACO 0x8 +#define SMU_13_0_PP_PLATFORM_CAP_MACO 0x10 +#define SMU_13_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 + +// SMU_13_0_PP_THERMALCONTROLLER - Thermal Controller Type +#define SMU_13_0_PP_THERMALCONTROLLER_NONE 0 + +#define SMU_13_0_PP_OVERDRIVE_VERSION 0x0800 +#define SMU_13_0_PP_POWERSAVINGCLOCK_VERSION 0x0100 + +enum SMU_13_0_ODFEATURE_CAP { + SMU_13_0_ODCAP_GFXCLK_LIMITS = 0, + SMU_13_0_ODCAP_GFXCLK_CURVE, + SMU_13_0_ODCAP_UCLK_MAX, + SMU_13_0_ODCAP_POWER_LIMIT, + SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT, + SMU_13_0_ODCAP_FAN_SPEED_MIN, + SMU_13_0_ODCAP_TEMPERATURE_FAN, + SMU_13_0_ODCAP_TEMPERATURE_SYSTEM, + SMU_13_0_ODCAP_MEMORY_TIMING_TUNE, + SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL, + SMU_13_0_ODCAP_AUTO_UV_ENGINE, + SMU_13_0_ODCAP_AUTO_OC_ENGINE, + SMU_13_0_ODCAP_AUTO_OC_MEMORY, + SMU_13_0_ODCAP_FAN_CURVE, + SMU_13_0_ODCAP_COUNT, +}; + +enum SMU_13_0_ODFEATURE_ID { + SMU_13_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature + SMU_13_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_13_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature + SMU_13_0_ODFEATURE_UCLK_MAX = 1 << SMU_13_0_ODCAP_UCLK_MAX, //UCLK Limit feature + SMU_13_0_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_ODCAP_POWER_LIMIT, //Power Limit feature + SMU_13_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature + SMU_13_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_13_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature + SMU_13_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_13_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature + SMU_13_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_13_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature + SMU_13_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_13_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature + SMU_13_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature + SMU_13_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_13_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature + SMU_13_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_13_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature + SMU_13_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_13_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature + SMU_13_0_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_ODCAP_FAN_CURVE, //Fan Curve feature + SMU_13_0_ODFEATURE_COUNT = 14, +}; + +#define SMU_13_0_MAX_ODFEATURE 32 //Maximum Number of OD Features + +enum SMU_13_0_ODSETTING_ID { + SMU_13_0_ODSETTING_GFXCLKFMAX = 0, + SMU_13_0_ODSETTING_GFXCLKFMIN, + SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P1, + SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, + SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P2, + SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, + SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P3, + SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, + SMU_13_0_ODSETTING_UCLKFMAX, + SMU_13_0_ODSETTING_POWERPERCENTAGE, + SMU_13_0_ODSETTING_FANRPMMIN, + SMU_13_0_ODSETTING_FANRPMACOUSTICLIMIT, + SMU_13_0_ODSETTING_FANTARGETTEMPERATURE, + SMU_13_0_ODSETTING_OPERATINGTEMPMAX, + SMU_13_0_ODSETTING_ACTIMING, + SMU_13_0_ODSETTING_FAN_ZERO_RPM_CONTROL, + SMU_13_0_ODSETTING_AUTOUVENGINE, + SMU_13_0_ODSETTING_AUTOOCENGINE, + SMU_13_0_ODSETTING_AUTOOCMEMORY, + SMU_13_0_ODSETTING_COUNT, +}; + +#define SMU_13_0_MAX_ODSETTING 32 //Maximum Number of ODSettings + +struct smu_13_0_overdrive_table { + uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION + uint8_t reserve[3]; //Zero filled field reserved for future use + uint32_t feature_count; //Total number of supported features + uint32_t setting_count; //Total number of supported settings + uint8_t cap[SMU_13_0_MAX_ODFEATURE]; //OD feature support flags + uint32_t max[SMU_13_0_MAX_ODSETTING]; //default maximum settings + uint32_t min[SMU_13_0_MAX_ODSETTING]; //default minimum settings +} __attribute__((packed)); + +enum SMU_13_0_PPCLOCK_ID { + SMU_13_0_PPCLOCK_GFXCLK = 0, + SMU_13_0_PPCLOCK_VCLK, + SMU_13_0_PPCLOCK_DCLK, + SMU_13_0_PPCLOCK_ECLK, + SMU_13_0_PPCLOCK_SOCCLK, + SMU_13_0_PPCLOCK_UCLK, + SMU_13_0_PPCLOCK_DCEFCLK, + SMU_13_0_PPCLOCK_DISPCLK, + SMU_13_0_PPCLOCK_PIXCLK, + SMU_13_0_PPCLOCK_PHYCLK, + SMU_13_0_PPCLOCK_COUNT, +}; +#define SMU_13_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks + +struct smu_13_0_power_saving_clock_table { + uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION + uint8_t reserve[3]; //Zero filled field reserved for future use + uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT + uint32_t max[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz + uint32_t min[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz +} __attribute__((packed)); + +struct smu_13_0_powerplay_table { + struct atom_common_table_header header; + uint8_t table_revision; + uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size + uint32_t golden_pp_id; + uint32_t golden_revision; + uint16_t format_id; + uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps + + uint8_t thermal_controller_type; //one of SMU_13_0_PP_THERMALCONTROLLER + + uint16_t small_power_limit1; + uint16_t small_power_limit2; + uint16_t boost_power_limit; + uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning. + uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning. + uint16_t software_shutdown_temp; + + uint16_t reserve[6]; //Zero filled field reserved for future use + + struct smu_13_0_power_saving_clock_table power_saving_clock; + struct smu_13_0_overdrive_table overdrive_table; + +#ifndef SMU_13_0_PARTIAL_PPTABLE + PPTable_t smc_pptable; //PPTable_t in driver_if.h +#endif +} __attribute__((packed)); + +#endif diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index e0d28820822090d729db5d41c7af07498bce75d2..ee6340c6f921e51f89db050ddfe9fab1f70c4502 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -1034,7 +1034,8 @@ static int pp_set_power_limit(void *handle, uint32_t limit) return 0; } -static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit) +static int pp_get_power_limit(void *handle, uint32_t *limit, + uint32_t *max_limit, bool default_limit) { struct pp_hwmgr *hwmgr = handle; @@ -1045,9 +1046,12 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit) if (default_limit) { *limit = hwmgr->default_power_limit; - if (hwmgr->od_enabled) { - *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); - *limit /= 100; + if (max_limit) { + *max_limit = *limit; + if (hwmgr->od_enabled) { + *max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); + *max_limit /= 100; + } } } else diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index ed05a30d1139dc5488e3541c7420f33cce81f3c2..f5d59fa3a0308693063ed141aa7f5c74ddc7dc7a 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1261,9 +1261,21 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - uint32_t sclk, mclk; + struct amdgpu_device *adev = hwmgr->adev; + uint32_t sclk, mclk, activity_percent; + bool has_gfx_busy; int ret = 0; + /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */ + if ((adev->apu_flags & AMD_APU_IS_PICASSO) && + (hwmgr->smu_version >= 0x41e3b)) + has_gfx_busy = true; + else if ((adev->apu_flags & AMD_APU_IS_RAVEN) && + (hwmgr->smu_version >= 0x1e5500)) + has_gfx_busy = true; + else + has_gfx_busy = false; + switch (idx) { case AMDGPU_PP_SENSOR_GFX_SCLK: smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); @@ -1284,8 +1296,22 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; *size = 4; break; + case AMDGPU_PP_SENSOR_GPU_LOAD: + if (has_gfx_busy) { + ret = smum_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetGfxBusy, + &activity_percent); + if (!ret) + activity_percent = activity_percent > 100 ? 100 : activity_percent; + else + return -EIO; + *((uint32_t *)value) = activity_percent; + return 0; + } else { + return -EOPNOTSUPP; + } default: - ret = -EINVAL; + ret = -EOPNOTSUPP; break; } @@ -1487,7 +1513,7 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, } if (!smu10_data->fine_grain_enabled) { - pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); + pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); return -EINVAL; } @@ -1526,20 +1552,6 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, smu10_data->gfx_actual_soft_min_freq = min_freq; smu10_data->gfx_actual_soft_max_freq = max_freq; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - min_freq, - NULL); - if (ret) - return ret; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - max_freq, - NULL); - if (ret) - return ret; } else if (type == PP_OD_COMMIT_DPM_TABLE) { if (size != 0) { pr_err("Input parameter number not correct\n"); diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index c57dc9ae81f2f4e7af3dc1dd3d9537cca3c18eb3..7edafef095a3a3c0874a9bbe43ccbc96a62bd3bd 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -587,6 +587,48 @@ static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) tmp, MC_CG_ARB_FREQ_F0); } +static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + uint16_t pcie_gen = 0; + + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 && + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4) + pcie_gen = 3; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 && + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) + pcie_gen = 2; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 && + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2) + pcie_gen = 1; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 && + adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1) + pcie_gen = 0; + + return pcie_gen; +} + +static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + uint16_t pcie_width = 0; + + if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) + pcie_width = 16; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) + pcie_width = 12; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) + pcie_width = 8; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) + pcie_width = 4; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) + pcie_width = 2; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) + pcie_width = 1; + + return pcie_width; +} + static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -683,6 +725,11 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) PP_Min_PCIEGen), get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); + + if (data->pcie_dpm_key_disabled) + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, + data->dpm_table.pcie_speed_table.count, + smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr)); } return 0; } @@ -1248,6 +1295,13 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) NULL)), "Failed to enable pcie DPM during DPM Start Function!", return -EINVAL); + } else { + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr, + PPSMC_MSG_PCIeDPM_Disable, + NULL)), + "Failed to disable pcie DPM during DPM Start Function!", + return -EINVAL); } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -3945,7 +3999,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); return 0; default: - return -EINVAL; + return -EOPNOTSUPP; } } @@ -5216,10 +5270,10 @@ static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, for (j = 0; j < dep_sclk_table->count; j++) { valid_entry = false; for (k = 0; k < watermarks->num_wm_sets; k++) { - if (dep_sclk_table->entries[i].clk / 10 >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz && - dep_sclk_table->entries[i].clk / 10 < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz && - dep_mclk_table->entries[i].clk / 10 >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz && - dep_mclk_table->entries[i].clk / 10 < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz) { + if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && + dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && + dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && + dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { valid_entry = true; table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; break; diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c index ed9b89980184821bdc8f53e776a7668a827da5f2..d425b02b1418f5fedbdd0b421d206edeb4120a11 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c @@ -1788,11 +1788,10 @@ static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity, &activity_percent); - if (0 == result) { + if (0 == result) activity_percent = activity_percent > 100 ? 100 : activity_percent; - } else { - activity_percent = 50; - } + else + return -EIO; *((uint32_t *)value) = activity_percent; return 0; case AMDGPU_PP_SENSOR_UVD_POWER: @@ -1805,7 +1804,7 @@ static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); return 0; default: - return -EINVAL; + return -EOPNOTSUPP; } } diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 29c99642d22d407e5613aef1f1264efb9cc30f86..31c61ac3bd5e1eaaf5ea0b94059c134f96c012a0 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -54,6 +54,9 @@ #include "smuio/smuio_9_0_offset.h" #include "smuio/smuio_9_0_sh_mask.h" +#define smnPCIE_LC_SPEED_CNTL 0x11140290 +#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 + #define HBM_MEMORY_CHANNEL_WIDTH 128 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; @@ -443,8 +446,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (PP_CAP(PHM_PlatformCaps_VCEDPM)) data->smu_features[GNLD_DPM_VCE].supported = true; - if (!data->registry_data.pcie_dpm_key_disabled) - data->smu_features[GNLD_DPM_LINK].supported = true; + data->smu_features[GNLD_DPM_LINK].supported = true; if (!data->registry_data.dcefclk_dpm_key_disabled) data->smu_features[GNLD_DPM_DCEFCLK].supported = true; @@ -1505,6 +1507,55 @@ static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, return 0; } +static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + uint32_t pcie_gen = 0, pcie_width = 0; + PPTable_t *pp_table = &(data->smc_state_table.pp_table); + int i; + + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) + pcie_gen = 3; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) + pcie_gen = 2; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) + pcie_gen = 1; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) + pcie_gen = 0; + + if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) + pcie_width = 6; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) + pcie_width = 5; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) + pcie_width = 4; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) + pcie_width = 3; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) + pcie_width = 2; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) + pcie_width = 1; + + for (i = 0; i < NUM_LINK_LEVELS; i++) { + if (pp_table->PcieGenSpeed[i] > pcie_gen) + pp_table->PcieGenSpeed[i] = pcie_gen; + + if (pp_table->PcieLaneCount[i] > pcie_width) + pp_table->PcieLaneCount[i] = pcie_width; + } + + if (data->registry_data.pcie_dpm_key_disabled) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { + pp_table->PcieGenSpeed[i] = pcie_gen; + pp_table->PcieLaneCount[i] = pcie_width; + } + } + + return 0; +} + static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) { int result = -1; @@ -2556,6 +2607,11 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) "Failed to initialize Link Level!", return result); + result = vega10_override_pcie_parameters(hwmgr); + PP_ASSERT_WITH_CODE(!result, + "Failed to override pcie parameters!", + return result); + result = vega10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, "Failed to initialize Graphics Level!", @@ -2919,9 +2975,18 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) } } + if (data->registry_data.pcie_dpm_key_disabled) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, + false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), + "Attempt to Disable Link DPM feature Failed!", return -EINVAL); + data->smu_features[GNLD_DPM_LINK].enabled = false; + data->smu_features[GNLD_DPM_LINK].supported = false; + } + return 0; } + static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) { struct vega10_hwmgr *data = hwmgr->backend; @@ -3890,7 +3955,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *size = 8; break; default: - ret = -EINVAL; + ret = -EOPNOTSUPP; break; } @@ -4536,6 +4601,24 @@ static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfe return 0; } +static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = hwmgr->adev; + + return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & + PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) + >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; +} + +static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = hwmgr->adev; + + return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & + PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) + >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; +} + static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf) { @@ -4544,8 +4627,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); - struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; + uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; + PPTable_t *pptable = &(data->smc_state_table.pp_table); int i, now, size = 0, count = 0; @@ -4602,15 +4686,31 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, "*" : ""); break; case PP_PCIE: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex, &now); - - for (i = 0; i < pcie_table->count; i++) - size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "", - (i == now) ? "*" : ""); + current_gen_speed = + vega10_get_current_pcie_link_speed_level(hwmgr); + current_lane_width = + vega10_get_current_pcie_link_width_level(hwmgr); + for (i = 0; i < NUM_LINK_LEVELS; i++) { + gen_speed = pptable->PcieGenSpeed[i]; + lane_width = pptable->PcieLaneCount[i]; + + size += sprintf(buf + size, "%d: %s %s %s\n", i, + (gen_speed == 0) ? "2.5GT/s," : + (gen_speed == 1) ? "5.0GT/s," : + (gen_speed == 2) ? "8.0GT/s," : + (gen_speed == 3) ? "16.0GT/s," : "", + (lane_width == 1) ? "x1" : + (lane_width == 2) ? "x2" : + (lane_width == 3) ? "x4" : + (lane_width == 4) ? "x8" : + (lane_width == 5) ? "x12" : + (lane_width == 6) ? "x16" : "", + (current_gen_speed == gen_speed) && + (current_lane_width == lane_width) ? + "*" : ""); + } break; + case OD_SCLK: if (hwmgr->od_enabled) { size = sprintf(buf, "%s:\n", "OD_SCLK"); @@ -5060,7 +5160,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui out: smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, - 1 << power_profile_mode, + (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), NULL); hwmgr->power_profile_mode = power_profile_mode; diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h index c934e9612c1b56e6002c9724df88b116175a50d2..9c479bd9a786b1e7da35b2996a9e7d5ee880d14f 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h @@ -161,9 +161,9 @@ typedef struct _ATOM_Vega10_MCLK_Dependency_Record { } ATOM_Vega10_MCLK_Dependency_Record; typedef struct _ATOM_Vega10_GFXCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_GFXCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + UCHAR ucRevId; + UCHAR ucNumEntries; /* Number of entries. */ + ATOM_Vega10_GFXCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Vega10_GFXCLK_Dependency_Table; typedef struct _ATOM_Vega10_MCLK_Dependency_Table { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c index c0753029a8e2a9f6b1039ab906a2d354b047a463..b6d7b7b224a9057016b6659ea4755b2bec024dd4 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c @@ -133,6 +133,7 @@ static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) data->registry_data.auto_wattman_debug = 0; data->registry_data.auto_wattman_sample_period = 100; data->registry_data.auto_wattman_threshold = 50; + data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); } static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) @@ -481,6 +482,90 @@ static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) dpm_state->hard_max_level = 0xffff; } +static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + struct vega12_hwmgr *data = + (struct vega12_hwmgr *)(hwmgr->backend); + uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; + PPTable_t *pp_table = &(data->smc_state_table.pp_table); + int i; + int ret; + + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) + pcie_gen = 3; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) + pcie_gen = 2; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) + pcie_gen = 1; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) + pcie_gen = 0; + + if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) + pcie_width = 6; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) + pcie_width = 5; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) + pcie_width = 4; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) + pcie_width = 3; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) + pcie_width = 2; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) + pcie_width = 1; + + /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 + * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 + * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 + */ + for (i = 0; i < NUM_LINK_LEVELS; i++) { + pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : + pp_table->PcieGenSpeed[i]; + pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : + pp_table->PcieLaneCount[i]; + + if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != + pp_table->PcieLaneCount[i]) { + smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, + NULL); + PP_ASSERT_WITH_CODE(!ret, + "[OverridePcieParameters] Attempt to override pcie params failed!", + return ret); + } + + /* update the pptable */ + pp_table->PcieGenSpeed[i] = pcie_gen_arg; + pp_table->PcieLaneCount[i] = pcie_width_arg; + } + + /* override to the highest if it's disabled from ppfeaturmask */ + if (data->registry_data.pcie_dpm_key_disabled) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { + smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, + NULL); + PP_ASSERT_WITH_CODE(!ret, + "[OverridePcieParameters] Attempt to override pcie params failed!", + return ret); + + pp_table->PcieGenSpeed[i] = pcie_gen; + pp_table->PcieLaneCount[i] = pcie_width; + } + ret = vega12_enable_smc_features(hwmgr, + false, + data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); + PP_ASSERT_WITH_CODE(!ret, + "Attempt to Disable DPM LINK Failed!", + return ret); + data->smu_features[GNLD_DPM_LINK].enabled = false; + data->smu_features[GNLD_DPM_LINK].supported = false; + } + return 0; +} + static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, PPCLK_e clk_id, uint32_t *num_of_levels) { @@ -968,6 +1053,11 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to enable all smu features!", return result); + result = vega12_override_pcie_parameters(hwmgr); + PP_ASSERT_WITH_CODE(!result, + "[EnableDPMTasks] Failed to override pcie parameters!", + return result); + tmp_result = vega12_power_control_set_level(hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to power control set level!", @@ -1429,7 +1519,7 @@ static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, *size = 8; break; default: - ret = -EINVAL; + ret = -EOPNOTSUPP; break; } return ret; diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c index 87811b005b85f314c3c9491533a6867fc3123791..213c9c6b446238566d99e3fa0b341e45510201d8 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c @@ -171,6 +171,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) data->registry_data.gfxoff_controlled_by_driver = 1; data->gfxoff_allowed = false; data->counter_gfxoff = 0; + data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); } static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) @@ -831,7 +832,9 @@ static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; + uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; + PPTable_t *pp_table = &(data->smc_state_table.pp_table); + int i; int ret; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) @@ -860,17 +863,51 @@ static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */ - smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width; - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, - NULL); - PP_ASSERT_WITH_CODE(!ret, - "[OverridePcieParameters] Attempt to override pcie params failed!", - return ret); + for (i = 0; i < NUM_LINK_LEVELS; i++) { + pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : + pp_table->PcieGenSpeed[i]; + pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : + pp_table->PcieLaneCount[i]; + + if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != + pp_table->PcieLaneCount[i]) { + smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, + NULL); + PP_ASSERT_WITH_CODE(!ret, + "[OverridePcieParameters] Attempt to override pcie params failed!", + return ret); + } + + /* update the pptable */ + pp_table->PcieGenSpeed[i] = pcie_gen_arg; + pp_table->PcieLaneCount[i] = pcie_width_arg; + } + + /* override to the highest if it's disabled from ppfeaturmask */ + if (data->registry_data.pcie_dpm_key_disabled) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { + smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, + NULL); + PP_ASSERT_WITH_CODE(!ret, + "[OverridePcieParameters] Attempt to override pcie params failed!", + return ret); - data->pcie_parameters_override = true; - data->pcie_gen_level1 = pcie_gen; - data->pcie_width_level1 = pcie_width; + pp_table->PcieGenSpeed[i] = pcie_gen; + pp_table->PcieLaneCount[i] = pcie_width; + } + ret = vega20_enable_smc_features(hwmgr, + false, + data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); + PP_ASSERT_WITH_CODE(!ret, + "Attempt to Disable DPM LINK Failed!", + return ret); + data->smu_features[GNLD_DPM_LINK].enabled = false; + data->smu_features[GNLD_DPM_LINK].supported = false; + } return 0; } @@ -2240,7 +2277,7 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, *size = 8; break; default: - ret = -EINVAL; + ret = -EOPNOTSUPP; break; } return ret; @@ -3319,9 +3356,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, data->od8_settings.od8_settings_array; OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable; + PPTable_t *pptable = &(data->smc_state_table.pp_table); struct pp_clock_levels_with_latency clocks; struct vega20_single_dpm_table *fclk_dpm_table = &(data->dpm_table.fclk_table); @@ -3420,13 +3455,9 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, current_lane_width = vega20_get_current_pcie_link_width_level(hwmgr); for (i = 0; i < NUM_LINK_LEVELS; i++) { - if (i == 1 && data->pcie_parameters_override) { - gen_speed = data->pcie_gen_level1; - lane_width = data->pcie_width_level1; - } else { - gen_speed = pptable->PcieGenSpeed[i]; - lane_width = pptable->PcieLaneCount[i]; - } + gen_speed = pptable->PcieGenSpeed[i]; + lane_width = pptable->PcieLaneCount[i]; + size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, (gen_speed == 0) ? "2.5GT/s," : (gen_speed == 1) ? "5.0GT/s," : diff --git a/drivers/gpu/drm/amd/pm/powerplay/kv_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/kv_dpm.c index 66daabebee358ef47832f4898da386dca3a368eb..bcae42cef37434de0c1840c85d0916c873c77788 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/powerplay/kv_dpm.c @@ -3305,7 +3305,7 @@ static int kv_dpm_read_sensor(void *handle, int idx, *size = 4; return 0; default: - return -EINVAL; + return -EOPNOTSUPP; } } diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c index afa1711c96203bcc1acb3791635da81152ab45cf..26a5321e621bfea0259fd6f1a31fc1371da2a94c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c @@ -5715,11 +5715,9 @@ static int si_upload_sw_state(struct amdgpu_device *adev, int ret; u32 address = si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, driverState); - u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + - ((new_state->performance_level_count - 1) * - sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; - + size_t state_size = struct_size(smc_state, levels, + new_state->performance_level_count); memset(smc_state, 0, state_size); ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); @@ -8016,7 +8014,7 @@ static int si_dpm_read_sensor(void *handle, int idx, *size = 4; return 0; default: - return -EINVAL; + return -EOPNOTSUPP; } } diff --git a/drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h b/drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h index d2930eceaf3c846c8cd52f1d9d2ec85fcbee4231..0f7554052c9062a8ce88f5ad0750fde01227dd2b 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h +++ b/drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h @@ -182,11 +182,11 @@ typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEV struct SISLANDS_SMC_SWSTATE { - uint8_t flags; - uint8_t levelCount; - uint8_t padding2; - uint8_t padding3; - SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; + uint8_t flags; + uint8_t levelCount; + uint8_t padding2; + uint8_t padding3; + SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; }; typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; diff --git a/drivers/gpu/drm/amd/pm/swsmu/Makefile b/drivers/gpu/drm/amd/pm/swsmu/Makefile index 6f281990b7b4b0e1949497c486a099ead245be8e..7987c6cf849d23de916b3724eed6557822accf27 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/Makefile @@ -22,7 +22,7 @@ AMD_SWSMU_PATH = ../pm/swsmu -SWSMU_LIBS = smu11 smu12 +SWSMU_LIBS = smu11 smu12 smu13 AMD_SWSMU = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/swsmu/,$(SWSMU_LIBS))) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index d143ef1b460bf6f887d0aaf49c97150f8a604445..e722adcf2f534321295bacf37e6d6075a2981eb6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -34,6 +34,7 @@ #include "sienna_cichlid_ppt.h" #include "renoir_ppt.h" #include "vangogh_ppt.h" +#include "aldebaran_ppt.h" #include "amd_pcie.h" /* @@ -46,9 +47,15 @@ #undef pr_info #undef pr_debug -size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) +static const struct amd_pm_funcs swsmu_pm_funcs; +static int smu_force_smuclk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t mask); + +int smu_sys_get_pp_feature_mask(void *handle, char *buf) { - size_t size = 0; + struct smu_context *smu = handle; + int size = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; @@ -62,8 +69,9 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) return size; } -int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) +int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -134,6 +142,34 @@ int smu_get_dpm_freq_range(struct smu_context *smu, return ret; } +u32 smu_get_mclk(void *handle, bool low) +{ + struct smu_context *smu = handle; + uint32_t clk_freq; + int ret = 0; + + ret = smu_get_dpm_freq_range(smu, SMU_UCLK, + low ? &clk_freq : NULL, + !low ? &clk_freq : NULL); + if (ret) + return 0; + return clk_freq * 100; +} + +u32 smu_get_sclk(void *handle, bool low) +{ + struct smu_context *smu = handle; + uint32_t clk_freq; + int ret = 0; + + ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, + low ? &clk_freq : NULL, + !low ? &clk_freq : NULL); + if (ret) + return 0; + return clk_freq * 100; +} + static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, bool enable) { @@ -209,7 +245,7 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu, /** * smu_dpm_set_power_gate - power gate/ungate the specific IP block * - * @smu: smu_context pointer + * @handle: smu_context pointer * @block_type: the IP block to power gate/ungate * @gate: to power gate if true, ungate otherwise * @@ -220,9 +256,10 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu, * Under this case, the smu->mutex lock protection is already enforced on * the parent API smu_force_performance_level of the call path. */ -int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, +int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -279,35 +316,25 @@ static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_ if (smu->adev->in_suspend) return; - /* - * mclk, fclk and socclk are interdependent - * on each other - */ if (clk == SMU_MCLK) { - /* reset clock dependency */ smu->user_dpm_profile.clk_dependency = 0; - /* set mclk dependent clocks(fclk and socclk) */ smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); } else if (clk == SMU_FCLK) { - /* give priority to mclk, if mclk dependent clocks are set */ + /* MCLK takes precedence over FCLK */ if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) return; - /* reset clock dependency */ smu->user_dpm_profile.clk_dependency = 0; - /* set fclk dependent clocks(mclk and socclk) */ smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); } else if (clk == SMU_SOCCLK) { - /* give priority to mclk, if mclk dependent clocks are set */ + /* MCLK takes precedence over SOCCLK */ if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) return; - /* reset clock dependency */ smu->user_dpm_profile.clk_dependency = 0; - /* set socclk dependent clocks(mclk and fclk) */ smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); } else - /* add clk dependencies here, if any */ + /* Add clk dependencies here, if any */ return; } @@ -331,7 +358,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) return; /* Enable restore flag */ - smu->user_dpm_profile.flags = SMU_DPM_USER_PROFILE_RESTORE; + smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; /* set the user dpm power limit */ if (smu->user_dpm_profile.power_limit) { @@ -351,11 +378,11 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) */ if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && smu->user_dpm_profile.clk_mask[clk_type]) { - ret = smu_force_clk_levels(smu, clk_type, + ret = smu_force_smuclk_levels(smu, clk_type, smu->user_dpm_profile.clk_mask[clk_type]); if (ret) - dev_err(smu->adev->dev, "Failed to set clock type = %d\n", - clk_type); + dev_err(smu->adev->dev, + "Failed to set clock type = %d\n", clk_type); } } } @@ -379,7 +406,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; } -int smu_get_power_num_states(struct smu_context *smu, +int smu_get_power_num_states(void *handle, struct pp_states_info *state_info) { if (!state_info) @@ -415,8 +442,9 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev) } -int smu_sys_get_pp_table(struct smu_context *smu, void **table) +int smu_sys_get_pp_table(void *handle, char **table) { + struct smu_context *smu = handle; struct smu_table_context *smu_table = &smu->smu_table; uint32_t powerplay_table_size; @@ -440,8 +468,9 @@ int smu_sys_get_pp_table(struct smu_context *smu, void **table) return powerplay_table_size; } -int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) +int smu_sys_set_pp_table(void *handle, const char *buf, size_t size) { + struct smu_context *smu = handle; struct smu_table_context *smu_table = &smu->smu_table; ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; int ret = 0; @@ -527,6 +556,11 @@ static int smu_set_funcs(struct amdgpu_device *adev) case CHIP_DIMGREY_CAVEFISH: sienna_cichlid_set_ppt_funcs(smu); break; + case CHIP_ALDEBARAN: + aldebaran_set_ppt_funcs(smu); + /* Enable pp_od_clk_voltage node */ + smu->od_enabled = true; + break; case CHIP_RENOIR: renoir_set_ppt_funcs(smu); break; @@ -553,6 +587,9 @@ static int smu_early_init(void *handle) smu->smu_baco.state = SMU_BACO_STATE_EXIT; smu->smu_baco.platform_support = false; + adev->powerplay.pp_handle = smu; + adev->powerplay.pp_funcs = &swsmu_pm_funcs; + return smu_set_funcs(adev); } @@ -612,10 +649,12 @@ static int smu_late_init(void *handle) return ret; } - ret = smu_set_default_od_settings(smu); - if (ret) { - dev_err(adev->dev, "Failed to setup default OD settings!\n"); - return ret; + if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { + ret = smu_set_default_od_settings(smu); + if (ret) { + dev_err(adev->dev, "Failed to setup default OD settings!\n"); + return ret; + } } ret = smu_populate_umd_state_clk(smu); @@ -989,6 +1028,10 @@ static int smu_sw_init(void *handle) return ret; } + /* If there is no way to query fan control mode, fan control is not supported */ + if (!smu->ppt_funcs->get_fan_control_mode) + smu->adev->pm.no_fan = true; + return 0; } @@ -1566,6 +1609,18 @@ static int smu_enable_umd_pstate(void *handle, return 0; } +static int smu_bump_power_profile_mode(struct smu_context *smu, + long *param, + uint32_t param_size) +{ + int ret = 0; + + if (smu->ppt_funcs->set_power_profile_mode) + ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); + + return ret; +} + static int smu_adjust_power_state_dynamic(struct smu_context *smu, enum amd_dpm_forced_level level, bool skip_display_settings) @@ -1608,13 +1663,14 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, smu_dpm_ctx->dpm_level = level; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && + smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { index = fls(smu->workload_mask); index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload = smu->workload_setting[index]; if (smu->power_profile_mode != workload) - smu_set_power_profile_mode(smu, &workload, 0, false); + smu_bump_power_profile_mode(smu, &workload, 0); } return ret; @@ -1655,10 +1711,23 @@ int smu_handle_task(struct smu_context *smu, return ret; } -int smu_switch_power_profile(struct smu_context *smu, +int smu_handle_dpm_task(void *handle, + enum amd_pp_task task_id, + enum amd_pm_state_type *user_state) +{ + struct smu_context *smu = handle; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); + +} + + +int smu_switch_power_profile(void *handle, enum PP_SMC_POWER_PROFILE type, bool en) { + struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); long workload; uint32_t index; @@ -1683,16 +1752,18 @@ int smu_switch_power_profile(struct smu_context *smu, workload = smu->workload_setting[index]; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) - smu_set_power_profile_mode(smu, &workload, 0, false); + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && + smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) + smu_bump_power_profile_mode(smu, &workload, 0); mutex_unlock(&smu->mutex); return 0; } -enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) +enum amd_dpm_forced_level smu_get_performance_level(void *handle) { + struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); enum amd_dpm_forced_level level; @@ -1709,8 +1780,9 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) return level; } -int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) +int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level) { + struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); int ret = 0; @@ -1757,7 +1829,7 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count) return ret; } -int smu_force_clk_levels(struct smu_context *smu, +static int smu_force_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) { @@ -1776,7 +1848,7 @@ int smu_force_clk_levels(struct smu_context *smu, if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); - if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) { + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { smu->user_dpm_profile.clk_mask[clk_type] = mask; smu_set_user_clk_dependencies(smu, clk_type); } @@ -1787,6 +1859,43 @@ int smu_force_clk_levels(struct smu_context *smu, return ret; } +int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask) +{ + struct smu_context *smu = handle; + enum smu_clk_type clk_type; + + switch (type) { + case PP_SCLK: + clk_type = SMU_SCLK; break; + case PP_MCLK: + clk_type = SMU_MCLK; break; + case PP_PCIE: + clk_type = SMU_PCIE; break; + case PP_SOCCLK: + clk_type = SMU_SOCCLK; break; + case PP_FCLK: + clk_type = SMU_FCLK; break; + case PP_DCEFCLK: + clk_type = SMU_DCEFCLK; break; + case PP_VCLK: + clk_type = SMU_VCLK; break; + case PP_DCLK: + clk_type = SMU_DCLK; break; + case OD_SCLK: + clk_type = SMU_OD_SCLK; break; + case OD_MCLK: + clk_type = SMU_OD_MCLK; break; + case OD_VDDC_CURVE: + clk_type = SMU_OD_VDDC_CURVE; break; + case OD_RANGE: + clk_type = SMU_OD_RANGE; break; + default: + return -EINVAL; + } + + return smu_force_smuclk_levels(smu, clk_type, mask); +} + /* * On system suspending or resetting, the dpm_enabled * flag will be cleared. So that those SMU services which @@ -1794,9 +1903,10 @@ int smu_force_clk_levels(struct smu_context *smu, * However, the mp1 state setting should still be granted * even if the dpm_enabled cleared. */ -int smu_set_mp1_state(struct smu_context *smu, +int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) { + struct smu_context *smu = handle; uint16_t msg; int ret; @@ -1833,9 +1943,10 @@ int smu_set_mp1_state(struct smu_context *smu, return ret; } -int smu_set_df_cstate(struct smu_context *smu, +int smu_set_df_cstate(void *handle, enum pp_df_cstate state) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -1972,6 +2083,15 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block = .funcs = &smu_ip_funcs, }; +const struct amdgpu_ip_block_version smu_v13_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 13, + .minor = 0, + .rev = 0, + .funcs = &smu_ip_funcs, +}; + int smu_load_microcode(struct smu_context *smu) { int ret = 0; @@ -2020,8 +2140,9 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) return ret; } -int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) +int smu_set_fan_speed_rpm(void *handle, uint32_t speed) { + struct smu_context *smu = handle; u32 percent; int ret = 0; @@ -2033,7 +2154,7 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) if (smu->ppt_funcs->set_fan_speed_percent) { percent = speed * 100 / smu->fan_max_rpm; ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); - if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) smu->user_dpm_profile.fan_speed_percent = percent; } @@ -2062,6 +2183,9 @@ int smu_get_power_limit(struct smu_context *smu, case SMU_PPT_LIMIT_CURRENT: *limit = smu->current_power_limit; break; + case SMU_PPT_LIMIT_DEFAULT: + *limit = smu->default_power_limit; + break; case SMU_PPT_LIMIT_MAX: *limit = smu->max_power_limit; break; @@ -2075,8 +2199,9 @@ int smu_get_power_limit(struct smu_context *smu, return ret; } -int smu_set_power_limit(struct smu_context *smu, uint32_t limit) +int smu_set_power_limit(void *handle, uint32_t limit) { + struct smu_context *smu = handle; uint32_t limit_type = limit >> 24; int ret = 0; @@ -2103,7 +2228,7 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit) if (smu->ppt_funcs->set_power_limit) { ret = smu->ppt_funcs->set_power_limit(smu, limit); - if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) smu->user_dpm_profile.power_limit = limit; } @@ -2113,7 +2238,7 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit) return ret; } -int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) +static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { int ret = 0; @@ -2130,10 +2255,52 @@ int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, ch return ret; } -int smu_od_edit_dpm_table(struct smu_context *smu, +int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf) +{ + struct smu_context *smu = handle; + enum smu_clk_type clk_type; + + switch (type) { + case PP_SCLK: + clk_type = SMU_SCLK; break; + case PP_MCLK: + clk_type = SMU_MCLK; break; + case PP_PCIE: + clk_type = SMU_PCIE; break; + case PP_SOCCLK: + clk_type = SMU_SOCCLK; break; + case PP_FCLK: + clk_type = SMU_FCLK; break; + case PP_DCEFCLK: + clk_type = SMU_DCEFCLK; break; + case PP_VCLK: + clk_type = SMU_VCLK; break; + case PP_DCLK: + clk_type = SMU_DCLK; break; + case OD_SCLK: + clk_type = SMU_OD_SCLK; break; + case OD_MCLK: + clk_type = SMU_OD_MCLK; break; + case OD_VDDC_CURVE: + clk_type = SMU_OD_VDDC_CURVE; break; + case OD_RANGE: + clk_type = SMU_OD_RANGE; break; + case OD_VDDGFX_OFFSET: + clk_type = SMU_OD_VDDGFX_OFFSET; break; + case OD_CCLK: + clk_type = SMU_OD_CCLK; break; + default: + return -EINVAL; + } + + return smu_print_smuclk_levels(smu, clk_type, buf); +} + +int smu_od_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, long *input, uint32_t size) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2143,11 +2310,6 @@ int smu_od_edit_dpm_table(struct smu_context *smu, if (smu->ppt_funcs->od_edit_dpm_table) { ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); - if (!ret && (type == PP_OD_COMMIT_DPM_TABLE)) - ret = smu_handle_task(smu, - smu->smu_dpm.dpm_level, - AMD_PP_TASK_READJUST_POWER_STATE, - false); } mutex_unlock(&smu->mutex); @@ -2155,20 +2317,23 @@ int smu_od_edit_dpm_table(struct smu_context *smu, return ret; } -int smu_read_sensor(struct smu_context *smu, - enum amd_pp_sensors sensor, - void *data, uint32_t *size) +int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg) { + struct smu_context *smu = handle; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; int ret = 0; + uint32_t *size, size_val; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; - if (!data || !size) + if (!data || !size_arg) return -EINVAL; + size_val = *size_arg; + size = &size_val; + mutex_lock(&smu->mutex); if (smu->ppt_funcs->read_sensor) @@ -2213,11 +2378,15 @@ int smu_read_sensor(struct smu_context *smu, unlock: mutex_unlock(&smu->mutex); + // assign uint32_t to int + *size_arg = size_val; + return ret; } -int smu_get_power_profile_mode(struct smu_context *smu, char *buf) +int smu_get_power_profile_mode(void *handle, char *buf) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2233,35 +2402,31 @@ int smu_get_power_profile_mode(struct smu_context *smu, char *buf) return ret; } -int smu_set_power_profile_mode(struct smu_context *smu, - long *param, - uint32_t param_size, - bool lock_needed) +int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; - if (lock_needed) - mutex_lock(&smu->mutex); + mutex_lock(&smu->mutex); - if (smu->ppt_funcs->set_power_profile_mode) - ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); + smu_bump_power_profile_mode(smu, param, param_size); - if (lock_needed) - mutex_unlock(&smu->mutex); + mutex_unlock(&smu->mutex); return ret; } -int smu_get_fan_control_mode(struct smu_context *smu) +u32 smu_get_fan_control_mode(void *handle) { - int ret = 0; + struct smu_context *smu = handle; + u32 ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) - return -EOPNOTSUPP; + return AMD_FAN_CTRL_NONE; mutex_lock(&smu->mutex); @@ -2278,13 +2443,13 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value) int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) - return -EOPNOTSUPP; + return -EOPNOTSUPP; mutex_lock(&smu->mutex); if (smu->ppt_funcs->set_fan_control_mode) { ret = smu->ppt_funcs->set_fan_control_mode(smu, value); - if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) smu->user_dpm_profile.fan_mode = value; } @@ -2292,14 +2457,22 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value) /* reset user dpm fan speed */ if (!ret && value != AMD_FAN_CTRL_MANUAL && - smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) + !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) smu->user_dpm_profile.fan_speed_percent = 0; return ret; } -int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) +void smu_pp_set_fan_control_mode(void *handle, u32 value) { + struct smu_context *smu = handle; + + smu_set_fan_control_mode(smu, value); +} + + +int smu_get_fan_speed_percent(void *handle, u32 *speed) { + struct smu_context *smu = handle; int ret = 0; uint32_t percent; @@ -2321,8 +2494,9 @@ int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) return ret; } -int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) +int smu_set_fan_speed_percent(void *handle, u32 speed) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2334,7 +2508,7 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) if (speed > 100) speed = 100; ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); - if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) smu->user_dpm_profile.fan_speed_percent = speed; } @@ -2343,8 +2517,9 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) return ret; } -int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) +int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) { + struct smu_context *smu = handle; int ret = 0; u32 percent; @@ -2434,9 +2609,10 @@ int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disabl return ret; } -int smu_set_xgmi_pstate(struct smu_context *smu, +int smu_set_xgmi_pstate(void *handle, uint32_t pstate) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2497,6 +2673,27 @@ bool smu_baco_is_support(struct smu_context *smu) return ret; } +int smu_get_baco_capability(void *handle, bool *cap) +{ + struct smu_context *smu = handle; + int ret = 0; + + *cap = false; + + if (!smu->pm_enabled) + return 0; + + mutex_lock(&smu->mutex); + + if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) + *cap = smu->ppt_funcs->baco_is_support(smu); + + mutex_unlock(&smu->mutex); + + return ret; +} + + int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) { if (smu->ppt_funcs->baco_get_state) @@ -2549,6 +2746,40 @@ int smu_baco_exit(struct smu_context *smu) return ret; } +int smu_baco_set_state(void *handle, int state) +{ + struct smu_context *smu = handle; + int ret = 0; + + if (!smu->pm_enabled) + return -EOPNOTSUPP; + + if (state == 0) { + mutex_lock(&smu->mutex); + + if (smu->ppt_funcs->baco_exit) + ret = smu->ppt_funcs->baco_exit(smu); + + mutex_unlock(&smu->mutex); + } else if (state == 1) { + mutex_lock(&smu->mutex); + + if (smu->ppt_funcs->baco_enter) + ret = smu->ppt_funcs->baco_enter(smu); + + mutex_unlock(&smu->mutex); + + } else { + return -EINVAL; + } + + if (ret) + dev_err(smu->adev->dev, "Failed to %s BACO state!\n", + (state)?"enter":"exit"); + + return ret; +} + bool smu_mode1_reset_is_support(struct smu_context *smu) { bool ret = false; @@ -2566,6 +2797,23 @@ bool smu_mode1_reset_is_support(struct smu_context *smu) return ret; } +bool smu_mode2_reset_is_support(struct smu_context *smu) +{ + bool ret = false; + + if (!smu->pm_enabled) + return false; + + mutex_lock(&smu->mutex); + + if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) + ret = smu->ppt_funcs->mode2_reset_is_support(smu); + + mutex_unlock(&smu->mutex); + + return ret; +} + int smu_mode1_reset(struct smu_context *smu) { int ret = 0; @@ -2583,8 +2831,9 @@ int smu_mode1_reset(struct smu_context *smu) return ret; } -int smu_mode2_reset(struct smu_context *smu) +int smu_mode2_reset(void *handle) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled) @@ -2640,8 +2889,9 @@ int smu_get_uclk_dpm_states(struct smu_context *smu, return ret; } -enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu) +enum amd_pm_state_type smu_get_current_power_state(void *handle) { + struct smu_context *smu = handle; enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2675,9 +2925,9 @@ int smu_get_dpm_clock_table(struct smu_context *smu, return ret; } -ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, - void **table) +ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) { + struct smu_context *smu = handle; ssize_t size; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2695,8 +2945,9 @@ ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, return size; } -int smu_enable_mgpu_fan_boost(struct smu_context *smu) +int smu_enable_mgpu_fan_boost(void *handle) { + struct smu_context *smu = handle; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2723,3 +2974,56 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state) return ret; } + +int smu_set_light_sbr(struct smu_context *smu, bool enable) +{ + int ret = 0; + + mutex_lock(&smu->mutex); + if (smu->ppt_funcs->set_light_sbr) + ret = smu->ppt_funcs->set_light_sbr(smu, enable); + mutex_unlock(&smu->mutex); + + return ret; +} + + +static const struct amd_pm_funcs swsmu_pm_funcs = { + /* export for sysfs */ + .set_fan_control_mode = smu_pp_set_fan_control_mode, + .get_fan_control_mode = smu_get_fan_control_mode, + .set_fan_speed_percent = smu_set_fan_speed_percent, + .get_fan_speed_percent = smu_get_fan_speed_percent, + .force_performance_level = smu_force_performance_level, + .read_sensor = smu_read_sensor, + .get_performance_level = smu_get_performance_level, + .get_current_power_state = smu_get_current_power_state, + .get_fan_speed_rpm = smu_get_fan_speed_rpm, + .set_fan_speed_rpm = smu_set_fan_speed_rpm, + .get_pp_num_states = smu_get_power_num_states, + .get_pp_table = smu_sys_get_pp_table, + .set_pp_table = smu_sys_set_pp_table, + .switch_power_profile = smu_switch_power_profile, + /* export to amdgpu */ + .dispatch_tasks = smu_handle_dpm_task, + .set_powergating_by_smu = smu_dpm_set_power_gate, + .set_power_limit = smu_set_power_limit, + .odn_edit_dpm_table = smu_od_edit_dpm_table, + .set_mp1_state = smu_set_mp1_state, + /* export to DC */ + .get_sclk = smu_get_sclk, + .get_mclk = smu_get_mclk, + .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, + .get_asic_baco_capability = smu_get_baco_capability, + .set_asic_baco_state = smu_baco_set_state, + .get_ppfeature_status = smu_sys_get_pp_feature_mask, + .set_ppfeature_status = smu_sys_set_pp_feature_mask, + .asic_reset_mode_2 = smu_mode2_reset, + .set_df_cstate = smu_set_df_cstate, + .set_xgmi_pstate = smu_set_xgmi_pstate, + .get_gpu_metrics = smu_sys_get_gpu_metrics, + .set_power_profile_mode = smu_set_power_profile_mode, + .get_power_profile_mode = smu_get_power_profile_mode, + .force_clock_level = smu_force_ppclk_levels, + .print_clock_levels = smu_print_ppclk_levels, +}; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 9f0d03ae310924be9a919327a8ea33e1be943e6a..bbc03092b0a9ba57580f0afe68c12b6e8c9e3f03 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -142,6 +142,7 @@ static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1), MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1), + MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0), }; static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = { @@ -236,7 +237,7 @@ static int arcturus_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { kfree(smu_table->metrics_table); @@ -1128,7 +1129,7 @@ static int arcturus_get_power_limit(struct smu_context *smu) power_limit = pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = power_limit; + smu->current_power_limit = smu->default_power_limit = power_limit; if (smu->od_enabled) { od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); @@ -2211,7 +2212,7 @@ static void arcturus_log_thermal_throttling_event(struct smu_context *smu) kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status); } -static int arcturus_get_current_pcie_link_speed(struct smu_context *smu) +static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; uint32_t esm_ctrl; @@ -2219,7 +2220,7 @@ static int arcturus_get_current_pcie_link_speed(struct smu_context *smu) /* TODO: confirm this on real target */ esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); if ((esm_ctrl >> 15) & 0x1FFFF) - return (((esm_ctrl >> 8) & 0x3F) + 128); + return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128); return smu_v11_0_get_current_pcie_link_speed(smu); } @@ -2228,8 +2229,8 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_0 *gpu_metrics = - (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -2239,7 +2240,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2280,7 +2281,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_0); + return sizeof(struct gpu_metrics_v1_1); } static const struct pptable_funcs arcturus_ppt_funcs = { @@ -2363,6 +2364,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { .deep_sleep_control = smu_v11_0_deep_sleep_control, .get_fan_parameters = arcturus_get_fan_parameters, .interrupt_work = smu_v11_0_interrupt_work, + .set_light_sbr = smu_v11_0_set_light_sbr, }; void arcturus_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 6e641f1513d80b0b48a2fce00dfb9485c79ae5a7..3d0de2c958fa8a7e1d120f2406618ffeeca4101c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -70,6 +70,8 @@ FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) +#define SMU_11_0_GFX_BUSY_THRESHOLD 15 + static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), @@ -456,18 +458,13 @@ static int navi10_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; - struct amdgpu_device *adev = smu->adev; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); - if (adev->asic_type == CHIP_NAVI12) - SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV12_t), - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); - else - SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), @@ -478,14 +475,13 @@ static int navi10_tables_init(struct smu_context *smu) sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); - smu_table->metrics_table = kzalloc(adev->asic_type == CHIP_NAVI12 ? - sizeof(SmuMetrics_NV12_t) : - sizeof(SmuMetrics_t), GFP_KERNEL); + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), + GFP_KERNEL); if (!smu_table->metrics_table) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -504,17 +500,200 @@ static int navi10_tables_init(struct smu_context *smu) return -ENOMEM; } +static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table= &smu->smu_table; + SmuMetrics_legacy_t *metrics = + (SmuMetrics_legacy_t *)smu_table->metrics_table; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + false); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + switch (member) { + case METRICS_CURR_GFXCLK: + *value = metrics->CurrClock[PPCLK_GFXCLK]; + break; + case METRICS_CURR_SOCCLK: + *value = metrics->CurrClock[PPCLK_SOCCLK]; + break; + case METRICS_CURR_UCLK: + *value = metrics->CurrClock[PPCLK_UCLK]; + break; + case METRICS_CURR_VCLK: + *value = metrics->CurrClock[PPCLK_VCLK]; + break; + case METRICS_CURR_DCLK: + *value = metrics->CurrClock[PPCLK_DCLK]; + break; + case METRICS_CURR_DCEFCLK: + *value = metrics->CurrClock[PPCLK_DCEFCLK]; + break; + case METRICS_AVERAGE_GFXCLK: + *value = metrics->AverageGfxclkFrequency; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->AverageSocclkFrequency; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->AverageUclkFrequency; + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = metrics->AverageGfxActivity; + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = metrics->AverageUclkActivity; + break; + case METRICS_AVERAGE_SOCKETPOWER: + *value = metrics->AverageSocketPower << 8; + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->TemperatureEdge * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->TemperatureHotspot * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + *value = metrics->TemperatureMem * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRGFX: + *value = metrics->TemperatureVrGfx * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRSOC: + *value = metrics->TemperatureVrSoc * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_STATUS: + *value = metrics->ThrottlerStatus; + break; + case METRICS_CURR_FANSPEED: + *value = metrics->CurrFanSpeed; + break; + default: + *value = UINT_MAX; + break; + } + + mutex_unlock(&smu->metrics_lock); + + return ret; +} + static int navi10_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) { struct smu_table_context *smu_table= &smu->smu_table; - /* - * This works for NV12 also. As although NV12 uses a different - * SmuMetrics structure from other NV1X ASICs, they share the - * same offsets for the heading parts(those members used here). - */ - SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; + SmuMetrics_t *metrics = + (SmuMetrics_t *)smu_table->metrics_table; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + false); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + switch (member) { + case METRICS_CURR_GFXCLK: + *value = metrics->CurrClock[PPCLK_GFXCLK]; + break; + case METRICS_CURR_SOCCLK: + *value = metrics->CurrClock[PPCLK_SOCCLK]; + break; + case METRICS_CURR_UCLK: + *value = metrics->CurrClock[PPCLK_UCLK]; + break; + case METRICS_CURR_VCLK: + *value = metrics->CurrClock[PPCLK_VCLK]; + break; + case METRICS_CURR_DCLK: + *value = metrics->CurrClock[PPCLK_DCLK]; + break; + case METRICS_CURR_DCEFCLK: + *value = metrics->CurrClock[PPCLK_DCEFCLK]; + break; + case METRICS_AVERAGE_GFXCLK: + if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) + *value = metrics->AverageGfxclkFrequencyPreDs; + else + *value = metrics->AverageGfxclkFrequencyPostDs; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->AverageSocclkFrequency; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->AverageUclkFrequencyPostDs; + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = metrics->AverageGfxActivity; + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = metrics->AverageUclkActivity; + break; + case METRICS_AVERAGE_SOCKETPOWER: + *value = metrics->AverageSocketPower << 8; + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->TemperatureEdge * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->TemperatureHotspot * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + *value = metrics->TemperatureMem * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRGFX: + *value = metrics->TemperatureVrGfx * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRSOC: + *value = metrics->TemperatureVrSoc * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_STATUS: + *value = metrics->ThrottlerStatus; + break; + case METRICS_CURR_FANSPEED: + *value = metrics->CurrFanSpeed; + break; + default: + *value = UINT_MAX; + break; + } + + mutex_unlock(&smu->metrics_lock); + + return ret; +} + +static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table= &smu->smu_table; + SmuMetrics_NV12_legacy_t *metrics = + (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; int ret = 0; mutex_lock(&smu->metrics_lock); @@ -600,6 +779,136 @@ static int navi10_get_smu_metrics_data(struct smu_context *smu, return ret; } +static int navi12_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table= &smu->smu_table; + SmuMetrics_NV12_t *metrics = + (SmuMetrics_NV12_t *)smu_table->metrics_table; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + false); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + switch (member) { + case METRICS_CURR_GFXCLK: + *value = metrics->CurrClock[PPCLK_GFXCLK]; + break; + case METRICS_CURR_SOCCLK: + *value = metrics->CurrClock[PPCLK_SOCCLK]; + break; + case METRICS_CURR_UCLK: + *value = metrics->CurrClock[PPCLK_UCLK]; + break; + case METRICS_CURR_VCLK: + *value = metrics->CurrClock[PPCLK_VCLK]; + break; + case METRICS_CURR_DCLK: + *value = metrics->CurrClock[PPCLK_DCLK]; + break; + case METRICS_CURR_DCEFCLK: + *value = metrics->CurrClock[PPCLK_DCEFCLK]; + break; + case METRICS_AVERAGE_GFXCLK: + if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) + *value = metrics->AverageGfxclkFrequencyPreDs; + else + *value = metrics->AverageGfxclkFrequencyPostDs; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->AverageSocclkFrequency; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->AverageUclkFrequencyPostDs; + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = metrics->AverageGfxActivity; + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = metrics->AverageUclkActivity; + break; + case METRICS_AVERAGE_SOCKETPOWER: + *value = metrics->AverageSocketPower << 8; + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->TemperatureEdge * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->TemperatureHotspot * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + *value = metrics->TemperatureMem * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRGFX: + *value = metrics->TemperatureVrGfx * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRSOC: + *value = metrics->TemperatureVrSoc * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_STATUS: + *value = metrics->ThrottlerStatus; + break; + case METRICS_CURR_FANSPEED: + *value = metrics->CurrFanSpeed; + break; + default: + *value = UINT_MAX; + break; + } + + mutex_unlock(&smu->metrics_lock); + + return ret; +} + +static int navi1x_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + int ret = 0; + + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (ret) { + dev_err(adev->dev, "Failed to get smu version!\n"); + return ret; + } + + switch (adev->asic_type) { + case CHIP_NAVI12: + if (smu_version > 0x00341C00) + ret = navi12_get_smu_metrics_data(smu, member, value); + else + ret = navi12_get_legacy_smu_metrics_data(smu, member, value); + break; + case CHIP_NAVI10: + case CHIP_NAVI14: + default: + if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || + ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) + ret = navi10_get_smu_metrics_data(smu, member, value); + else + ret = navi10_get_legacy_smu_metrics_data(smu, member, value); + break; + } + + return ret; +} + static int navi10_allocate_dpm_context(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -880,7 +1189,7 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, return -EINVAL; } - return navi10_get_smu_metrics_data(smu, + return navi1x_get_smu_metrics_data(smu, member_type, value); } @@ -897,7 +1206,7 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ - return dpm_desc->SnapToDiscrete == 0 ? true : false; + return dpm_desc->SnapToDiscrete == 0; } static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) @@ -1328,7 +1637,7 @@ static int navi10_get_fan_speed_percent(struct smu_context *smu, switch (smu_v11_0_get_fan_control_mode(smu)) { case AMD_FAN_CTRL_AUTO: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_CURR_FANSPEED, &rpm); if (!ret && smu->fan_max_rpm) @@ -1644,37 +1953,37 @@ static int navi10_read_sensor(struct smu_context *smu, *size = 4; break; case AMDGPU_PP_SENSOR_MEM_LOAD: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_MEMACTIVITY, (uint32_t *)data); *size = 4; break; case AMDGPU_PP_SENSOR_GPU_LOAD: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXACTIVITY, (uint32_t *)data); *size = 4; break; case AMDGPU_PP_SENSOR_GPU_POWER: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_SOCKETPOWER, (uint32_t *)data); *size = 4; break; case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_TEMPERATURE_HOTSPOT, (uint32_t *)data); *size = 4; break; case AMDGPU_PP_SENSOR_EDGE_TEMP: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_TEMPERATURE_EDGE, (uint32_t *)data); *size = 4; break; case AMDGPU_PP_SENSOR_MEM_TEMP: - ret = navi10_get_smu_metrics_data(smu, + ret = navi1x_get_smu_metrics_data(smu, METRICS_TEMPERATURE_MEM, (uint32_t *)data); *size = 4; @@ -1685,7 +1994,7 @@ static int navi10_read_sensor(struct smu_context *smu, *size = 4; break; case AMDGPU_PP_SENSOR_GFX_SCLK: - ret = navi10_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); + ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); *(uint32_t *)data *= 100; *size = 4; break; @@ -1802,7 +2111,7 @@ static int navi10_get_power_limit(struct smu_context *smu) power_limit = pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = power_limit; + smu->current_power_limit = smu->default_power_limit = power_limit; if (smu->od_enabled && navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { @@ -2287,14 +2596,75 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu) return 0; } +static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + SmuMetrics_legacy_t metrics; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + true); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); + + mutex_unlock(&smu->metrics_lock); + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + + gpu_metrics->temperature_edge = metrics.TemperatureEdge; + gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; + gpu_metrics->temperature_mem = metrics.TemperatureMem; + gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; + gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; + gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; + + gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; + gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; + + gpu_metrics->average_socket_power = metrics.AverageSocketPower; + + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; + gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; + + gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; + gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; + gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; + + gpu_metrics->throttle_status = metrics.ThrottlerStatus; + + gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; + + gpu_metrics->pcie_link_width = + smu_v11_0_get_current_pcie_link_width(smu); + gpu_metrics->pcie_link_speed = + smu_v11_0_get_current_pcie_link_speed(smu); + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + *table = (void *)gpu_metrics; + + return sizeof(struct gpu_metrics_v1_1); +} + static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_0 *gpu_metrics = - (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; - struct amdgpu_device *adev = smu->adev; - SmuMetrics_NV12_t nv12_metrics = { 0 }; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -2309,12 +2679,75 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, } memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); - if (adev->asic_type == CHIP_NAVI12) - memcpy(&nv12_metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + + gpu_metrics->temperature_edge = metrics.TemperatureEdge; + gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; + gpu_metrics->temperature_mem = metrics.TemperatureMem; + gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; + gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; + gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; + + gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; + gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; + + gpu_metrics->average_socket_power = metrics.AverageSocketPower; + + if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; + else + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; + + gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; + + gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; + gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; + gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; + + gpu_metrics->throttle_status = metrics.ThrottlerStatus; + + gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; + + gpu_metrics->pcie_link_width = metrics.PcieWidth; + gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + *table = (void *)gpu_metrics; + + return sizeof(struct gpu_metrics_v1_1); +} + +static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + SmuMetrics_NV12_legacy_t metrics; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + true); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); + + mutex_unlock(&smu->metrics_lock); + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2332,12 +2765,10 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; - if (adev->asic_type == CHIP_NAVI12) { - gpu_metrics->energy_accumulator = nv12_metrics.EnergyAccumulator; - gpu_metrics->average_vclk0_frequency = nv12_metrics.AverageVclkFrequency; - gpu_metrics->average_dclk0_frequency = nv12_metrics.AverageDclkFrequency; - gpu_metrics->average_mm_activity = nv12_metrics.VcnActivityPercentage; - } + gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; + gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; + gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; + gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; @@ -2358,7 +2789,111 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_0); + return sizeof(struct gpu_metrics_v1_1); +} + +static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + SmuMetrics_NV12_t metrics; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + true); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); + + mutex_unlock(&smu->metrics_lock); + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + + gpu_metrics->temperature_edge = metrics.TemperatureEdge; + gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; + gpu_metrics->temperature_mem = metrics.TemperatureMem; + gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; + gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; + gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; + + gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; + gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; + + gpu_metrics->average_socket_power = metrics.AverageSocketPower; + + if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; + else + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; + + gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; + + gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; + gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; + gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; + gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; + + gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; + gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; + gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; + + gpu_metrics->throttle_status = metrics.ThrottlerStatus; + + gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; + + gpu_metrics->pcie_link_width = metrics.PcieWidth; + gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + *table = (void *)gpu_metrics; + + return sizeof(struct gpu_metrics_v1_1); +} + +static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + int ret = 0; + + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (ret) { + dev_err(adev->dev, "Failed to get smu version!\n"); + return ret; + } + + switch (adev->asic_type) { + case CHIP_NAVI12: + if (smu_version > 0x00341C00) + ret = navi12_get_gpu_metrics(smu, table); + else + ret = navi12_get_legacy_gpu_metrics(smu, table); + break; + case CHIP_NAVI10: + case CHIP_NAVI14: + default: + if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || + ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) + ret = navi10_get_gpu_metrics(smu, table); + else + ret =navi10_get_legacy_gpu_metrics(smu, table); + break; + } + + return ret; } static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) @@ -2489,7 +3024,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { .set_power_source = smu_v11_0_set_power_source, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, - .get_gpu_metrics = navi10_get_gpu_metrics, + .get_gpu_metrics = navi1x_get_gpu_metrics, .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, .gfx_ulv_control = smu_v11_0_gfx_ulv_control, .deep_sleep_control = smu_v11_0_deep_sleep_control, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index af73e1430af535beefff194d4140c8a3af4ca042..3621884c32935d4ac72919af701629e4934a0094 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -89,17 +89,17 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), - MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), - MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), + MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), + MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), - MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), + MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), - MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), - MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), + MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), + MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), @@ -416,7 +416,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -921,7 +921,7 @@ static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ - return dpm_desc->SnapToDiscrete == 0 ? true : false; + return dpm_desc->SnapToDiscrete == 0; } static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, @@ -1736,7 +1736,7 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu) power_limit = pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = power_limit; + smu->current_power_limit = smu->default_power_limit = power_limit; if (smu->od_enabled) { od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); @@ -2948,11 +2948,13 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_0 *gpu_metrics = - (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; SmuMetricsExternal_t metrics_external; SmuMetrics_t *metrics = &(metrics_external.SmuMetrics); + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; int ret = 0; ret = smu_cmn_get_metrics_table(smu, @@ -2961,7 +2963,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); gpu_metrics->temperature_edge = metrics->TemperatureEdge; gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; @@ -2999,16 +3001,26 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_fan_speed = metrics->CurrFanSpeed; - gpu_metrics->pcie_link_width = - smu_v11_0_get_current_pcie_link_width(smu); - gpu_metrics->pcie_link_speed = - smu_v11_0_get_current_pcie_link_speed(smu); + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (ret) + return ret; + + if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) || + ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) { + gpu_metrics->pcie_link_width = metrics->PcieWidth; + gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate]; + } else { + gpu_metrics->pcie_link_width = + smu_v11_0_get_current_pcie_link_width(smu); + gpu_metrics->pcie_link_speed = + smu_v11_0_get_current_pcie_link_speed(smu); + } gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_0); + return sizeof(struct gpu_metrics_v1_1); } static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index a6211858ead457d9a88fc10fee85df4b58cdeec3..0d137af1a78aca4360809f4519736e19cd52fb9d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -68,9 +68,6 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms -#define LINK_WIDTH_MAX 6 -#define LINK_SPEED_MAX 3 - #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 @@ -81,9 +78,6 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); #define mmTHM_BACO_CNTL_ARCT 0xA7 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 -static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; -static int link_speed[] = {25, 50, 80, 160}; - int smu_v11_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -750,8 +744,10 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) + if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { + ret = -EINVAL; goto failed; + } bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); @@ -1534,7 +1530,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) NULL); break; default: - if (!ras || !ras->supported) { + if (!ras || !ras->supported || adev->gmc.xgmi.pending_reset) { if (adev->asic_type == CHIP_ARCTURUS) { data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); data |= 0x80000000; @@ -1607,6 +1603,16 @@ int smu_v11_0_mode1_reset(struct smu_context *smu) return ret; } +int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable) +{ + int ret = 0; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL); + + return ret; +} + + int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) { @@ -2001,7 +2007,7 @@ int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; } -int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) +uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) { uint32_t width_level; @@ -2021,7 +2027,7 @@ int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; } -int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) +uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) { uint32_t speed_level; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 7ddbaecb11c2dcd83b20b81101882b7ec794c1b7..c5b387360f019cff9d6c2f43e77e46d6d06e8b8d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -210,7 +210,7 @@ static int vangogh_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -442,7 +442,7 @@ static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_typ return 0; } -static int vangogh_print_fine_grain_clk(struct smu_context *smu, +static int vangogh_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { DpmClocks_t *clk_table = smu->smu_table.clocks_table; @@ -1401,8 +1401,8 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v2_0 *gpu_metrics = - (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v2_1 *gpu_metrics = + (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -1410,7 +1410,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1450,19 +1450,18 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v2_0); + return sizeof(struct gpu_metrics_v2_1); } static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { int ret = 0; - int i; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { dev_warn(smu->adev->dev, - "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); + "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); return -EINVAL; } @@ -1530,43 +1529,6 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; - - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, - smu->gfx_actual_hard_min_freq, NULL); - if (ret) { - dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); - return ret; - } - - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, - smu->gfx_actual_soft_max_freq, NULL); - if (ret) { - dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); - return ret; - } - - if (smu->adev->pm.fw_version < 0x43f1b00) { - dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); - break; - } - - for (i = 0; i < smu->cpu_core_num; i++) { - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, - (i << 20) | smu->cpu_actual_soft_min_freq, - NULL); - if (ret) { - dev_err(smu->adev->dev, "Set hard min cclk failed!"); - return ret; - } - - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, - (i << 20) | smu->cpu_actual_soft_max_freq, - NULL); - if (ret) { - dev_err(smu->adev->dev, "Set soft max cclk failed!"); - return ret; - } - } } break; case PP_OD_COMMIT_DPM_TABLE: @@ -1794,7 +1756,7 @@ static int vangogh_get_power_limit(struct smu_context *smu) return ret; } /* convert from milliwatt to watt */ - smu->current_power_limit = ppt_limit / 1000; + smu->current_power_limit = smu->default_power_limit = ppt_limit / 1000; smu->max_power_limit = 29; ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); @@ -1803,7 +1765,8 @@ static int vangogh_get_power_limit(struct smu_context *smu) return ret; } /* convert from milliwatt to watt */ - power_context->current_fast_ppt_limit = ppt_limit / 1000; + power_context->current_fast_ppt_limit = + power_context->default_fast_ppt_limit = ppt_limit / 1000; power_context->max_fast_ppt_limit = 30; return ret; @@ -1828,6 +1791,9 @@ static int vangogh_get_ppt_limit(struct smu_context *smu, case SMU_PPT_LIMIT_CURRENT: *ppt_limit = power_context->current_fast_ppt_limit; break; + case SMU_PPT_LIMIT_DEFAULT: + *ppt_limit = power_context->default_fast_ppt_limit; + break; default: break; } @@ -1907,7 +1873,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .interrupt_work = smu_v11_0_interrupt_work, .get_gpu_metrics = vangogh_get_gpu_metrics, .od_edit_dpm_table = vangogh_od_edit_dpm_table, - .print_clk_levels = vangogh_print_fine_grain_clk, + .print_clk_levels = vangogh_print_clk_levels, .set_default_dpm_table = vangogh_set_default_dpm_tables, .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, .system_features_control = vangogh_system_features_control, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 5493388fcb10c88507812db76a1e81cfa67b75b4..e3232295f2bf798e92b9328a92607c2e1e9b1d52 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -151,7 +151,7 @@ static int renoir_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err3_out; @@ -351,7 +351,7 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu, if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { dev_warn(smu->adev->dev, - "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); + "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); return -EINVAL; } @@ -389,24 +389,6 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu, } smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; - - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetHardMinGfxClk, - smu->gfx_actual_hard_min_freq, - NULL); - if (ret) { - dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); - return ret; - } - - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetSoftMaxGfxClk, - smu->gfx_actual_soft_max_freq, - NULL); - if (ret) { - dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); - return ret; - } break; case PP_OD_COMMIT_DPM_TABLE: if (size != 0) { @@ -1249,8 +1231,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v2_0 *gpu_metrics = - (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v2_1 *gpu_metrics = + (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -1258,7 +1240,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1303,7 +1285,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v2_0); + return sizeof(struct gpu_metrics_v2_1); } static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..652b4e554378be45d54722965b026ac895109e1b --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile @@ -0,0 +1,30 @@ +# +# Copyright 2020 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# +# Makefile for the 'smu manager' sub-component of powerplay. +# It provides the smu management services for the driver. + +SMU13_MGR = smu_v13_0.o aldebaran_ppt.o + +AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR)) + +AMD_POWERPLAY_FILES += $(AMD_SWSMU_SMU13MGR) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c new file mode 100644 index 0000000000000000000000000000000000000000..9813a86ca31a79530b876df2dbbc574857d17eb8 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -0,0 +1,1530 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#define SWSMU_CODE_LAYER_L2 + +#include +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "atomfirmware.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_atombios.h" +#include "smu_v13_0.h" +#include "smu13_driver_if_aldebaran.h" +#include "soc15_common.h" +#include "atom.h" +#include "power_state.h" +#include "aldebaran_ppt.h" +#include "smu_v13_0_pptable.h" +#include "aldebaran_ppsmc.h" +#include "nbio/nbio_7_4_offset.h" +#include "nbio/nbio_7_4_sh_mask.h" +#include "thm/thm_11_0_2_offset.h" +#include "thm/thm_11_0_2_sh_mask.h" +#include "amdgpu_xgmi.h" +#include +#include "amdgpu_ras.h" +#include "smu_cmn.h" +#include "mp/mp_13_0_2_offset.h" + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) + +#define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ + [smu_feature] = {1, (aldebaran_feature)} + +#define FEATURE_MASK(feature) (1ULL << feature) +#define SMC_DPM_FEATURE ( \ + FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ + FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ + FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ + FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ + FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ + FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ + FEATURE_MASK(FEATURE_DPM_VCN_BIT)) + +/* possible frequency drift (1Mhz) */ +#define EPSILON 1 + +#define smnPCIE_ESM_CTRL 0x111003D0 + +static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), + MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), + MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), + MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), + MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), + MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), + MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), + MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), + MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), + MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), + MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), + MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), + MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), + MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), + MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), + MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), + MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), + MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), + MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), + MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), + MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), + MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), + MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), + MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), + MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), + MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), + MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), + MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), + MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), + MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), + MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), + MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), + MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), + MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), + MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), + MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), + MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), + MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), + MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), + MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), + MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), + MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), + MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), + MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), + MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), +}; + +static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { + CLK_MAP(GFXCLK, PPCLK_GFXCLK), + CLK_MAP(SCLK, PPCLK_GFXCLK), + CLK_MAP(SOCCLK, PPCLK_SOCCLK), + CLK_MAP(FCLK, PPCLK_FCLK), + CLK_MAP(UCLK, PPCLK_UCLK), + CLK_MAP(MCLK, PPCLK_UCLK), + CLK_MAP(DCLK, PPCLK_DCLK), + CLK_MAP(VCLK, PPCLK_VCLK), + CLK_MAP(LCLK, PPCLK_LCLK), +}; + +static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT, FEATURE_DATA_CALCULATIONS), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), + ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), + ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), +}; + +static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { + TAB_MAP(PPTABLE), + TAB_MAP(AVFS_PSM_DEBUG), + TAB_MAP(AVFS_FUSE_OVERRIDE), + TAB_MAP(PMSTATUSLOG), + TAB_MAP(SMU_METRICS), + TAB_MAP(DRIVER_SMU_CONFIG), + TAB_MAP(I2C_COMMANDS), +}; + +static int aldebaran_tables_init(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + + SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); + if (!smu_table->metrics_table) + return -ENOMEM; + smu_table->metrics_time = 0; + + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); + smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); + if (!smu_table->gpu_metrics_table) { + kfree(smu_table->metrics_table); + return -ENOMEM; + } + + return 0; +} + +static int aldebaran_allocate_dpm_context(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), + GFP_KERNEL); + if (!smu_dpm->dpm_context) + return -ENOMEM; + smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); + + smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state), + GFP_KERNEL); + if (!smu_dpm->dpm_current_power_state) + return -ENOMEM; + + smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state), + GFP_KERNEL); + if (!smu_dpm->dpm_request_power_state) + return -ENOMEM; + + return 0; +} + +static int aldebaran_init_smc_tables(struct smu_context *smu) +{ + int ret = 0; + + ret = aldebaran_tables_init(smu); + if (ret) + return ret; + + ret = aldebaran_allocate_dpm_context(smu); + if (ret) + return ret; + + return smu_v13_0_init_smc_tables(smu); +} + +static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, + uint32_t *feature_mask, uint32_t num) +{ + if (num > 2) + return -EINVAL; + + /* pptable will handle the features to enable */ + memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + + return 0; +} + +static int aldebaran_set_default_dpm_table(struct smu_context *smu) +{ + struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_13_0_dpm_table *dpm_table = NULL; + PPTable_t *pptable = smu->smu_table.driver_pptable; + int ret = 0; + + /* socclk dpm table setup */ + dpm_table = &dpm_context->dpm_tables.soc_table; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { + ret = smu_v13_0_set_single_dpm_table(smu, + SMU_SOCCLK, + dpm_table); + if (ret) + return ret; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->min = dpm_table->dpm_levels[0].value; + dpm_table->max = dpm_table->dpm_levels[0].value; + } + + /* gfxclk dpm table setup */ + dpm_table = &dpm_context->dpm_tables.gfx_table; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { + /* in the case of gfxclk, only fine-grained dpm is honored */ + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; + dpm_table->dpm_levels[1].enabled = true; + dpm_table->min = dpm_table->dpm_levels[0].value; + dpm_table->max = dpm_table->dpm_levels[1].value; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->min = dpm_table->dpm_levels[0].value; + dpm_table->max = dpm_table->dpm_levels[0].value; + } + + /* memclk dpm table setup */ + dpm_table = &dpm_context->dpm_tables.uclk_table; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + ret = smu_v13_0_set_single_dpm_table(smu, + SMU_UCLK, + dpm_table); + if (ret) + return ret; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->min = dpm_table->dpm_levels[0].value; + dpm_table->max = dpm_table->dpm_levels[0].value; + } + + /* fclk dpm table setup */ + dpm_table = &dpm_context->dpm_tables.fclk_table; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { + ret = smu_v13_0_set_single_dpm_table(smu, + SMU_FCLK, + dpm_table); + if (ret) + return ret; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->min = dpm_table->dpm_levels[0].value; + dpm_table->max = dpm_table->dpm_levels[0].value; + } + + return 0; +} + +static int aldebaran_check_powerplay_table(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_13_0_powerplay_table *powerplay_table = + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; + + mutex_lock(&smu_baco->mutex); + if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO || + powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO) + smu_baco->platform_support = true; + mutex_unlock(&smu_baco->mutex); + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; + + return 0; +} + +static int aldebaran_store_powerplay_table(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_13_0_powerplay_table *powerplay_table = + table_context->power_play_table; + memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, + sizeof(PPTable_t)); + + return 0; +} + +static int aldebaran_append_powerplay_table(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + PPTable_t *smc_pptable = table_context->driver_pptable; + struct atom_smc_dpm_info_v4_10 *smc_dpm_table; + int index, ret; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + smc_dpm_info); + + ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, + (uint8_t **)&smc_dpm_table); + if (ret) + return ret; + + dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", + smc_dpm_table->table_header.format_revision, + smc_dpm_table->table_header.content_revision); + + if ((smc_dpm_table->table_header.format_revision == 4) && + (smc_dpm_table->table_header.content_revision == 10)) + memcpy(&smc_pptable->GfxMaxCurrent, + &smc_dpm_table->GfxMaxCurrent, + sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent)); + return 0; +} + +static int aldebaran_setup_pptable(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_v13_0_setup_pptable(smu); + if (ret) + return ret; + + ret = aldebaran_store_powerplay_table(smu); + if (ret) + return ret; + + ret = aldebaran_append_powerplay_table(smu); + if (ret) + return ret; + + ret = aldebaran_check_powerplay_table(smu); + if (ret) + return ret; + + return ret; +} + +static int aldebaran_run_btc(struct smu_context *smu) +{ + int ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); + if (ret) + dev_err(smu->adev->dev, "RunDcBtc failed!\n"); + + return ret; +} + +static int aldebaran_populate_umd_state_clk(struct smu_context *smu) +{ + struct smu_13_0_dpm_context *dpm_context = + smu->smu_dpm.dpm_context; + struct smu_13_0_dpm_table *gfx_table = + &dpm_context->dpm_tables.gfx_table; + struct smu_13_0_dpm_table *mem_table = + &dpm_context->dpm_tables.uclk_table; + struct smu_13_0_dpm_table *soc_table = + &dpm_context->dpm_tables.soc_table; + struct smu_umd_pstate_table *pstate_table = + &smu->pstate_table; + + pstate_table->gfxclk_pstate.min = gfx_table->min; + pstate_table->gfxclk_pstate.peak = gfx_table->max; + + pstate_table->uclk_pstate.min = mem_table->min; + pstate_table->uclk_pstate.peak = mem_table->max; + + pstate_table->socclk_pstate.min = soc_table->min; + pstate_table->socclk_pstate.peak = soc_table->max; + + if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && + mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && + soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { + pstate_table->gfxclk_pstate.standard = + gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; + pstate_table->uclk_pstate.standard = + mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; + pstate_table->socclk_pstate.standard = + soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; + } else { + pstate_table->gfxclk_pstate.standard = + pstate_table->gfxclk_pstate.min; + pstate_table->uclk_pstate.standard = + pstate_table->uclk_pstate.min; + pstate_table->socclk_pstate.standard = + pstate_table->socclk_pstate.min; + } + + return 0; +} + +static int aldebaran_get_clk_table(struct smu_context *smu, + struct pp_clock_levels_with_latency *clocks, + struct smu_13_0_dpm_table *dpm_table) +{ + int i, count; + + count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; + clocks->num_levels = count; + + for (i = 0; i < count; i++) { + clocks->data[i].clocks_in_khz = + dpm_table->dpm_levels[i].value * 1000; + clocks->data[i].latency_in_us = 0; + } + + return 0; +} + +static int aldebaran_freqs_in_same_level(int32_t frequency1, + int32_t frequency2) +{ + return (abs(frequency1 - frequency2) <= EPSILON); +} + +static int aldebaran_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table= &smu->smu_table; + SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, + NULL, + false); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + switch (member) { + case METRICS_CURR_GFXCLK: + *value = metrics->CurrClock[PPCLK_GFXCLK]; + break; + case METRICS_CURR_SOCCLK: + *value = metrics->CurrClock[PPCLK_SOCCLK]; + break; + case METRICS_CURR_UCLK: + *value = metrics->CurrClock[PPCLK_UCLK]; + break; + case METRICS_CURR_VCLK: + *value = metrics->CurrClock[PPCLK_VCLK]; + break; + case METRICS_CURR_DCLK: + *value = metrics->CurrClock[PPCLK_DCLK]; + break; + case METRICS_CURR_FCLK: + *value = metrics->CurrClock[PPCLK_FCLK]; + break; + case METRICS_AVERAGE_GFXCLK: + *value = metrics->AverageGfxclkFrequency; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->AverageSocclkFrequency; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->AverageUclkFrequency; + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = metrics->AverageGfxActivity; + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = metrics->AverageUclkActivity; + break; + case METRICS_AVERAGE_SOCKETPOWER: + *value = metrics->AverageSocketPower << 8; + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->TemperatureEdge * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->TemperatureHotspot * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + *value = metrics->TemperatureHBM * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRGFX: + *value = metrics->TemperatureVrGfx * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRSOC: + *value = metrics->TemperatureVrSoc * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_VRMEM: + *value = metrics->TemperatureVrMem * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_STATUS: + *value = metrics->ThrottlerStatus; + break; + default: + *value = UINT_MAX; + break; + } + + mutex_unlock(&smu->metrics_lock); + + return ret; +} + +static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + MetricsMember_t member_type; + int clk_id = 0; + + if (!value) + return -EINVAL; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return -EINVAL; + + switch (clk_id) { + case PPCLK_GFXCLK: + /* + * CurrClock[clk_id] can provide accurate + * output only when the dpm feature is enabled. + * We can use Average_* for dpm disabled case. + * But this is available for gfxclk/uclk/socclk/vclk/dclk. + */ + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) + member_type = METRICS_CURR_GFXCLK; + else + member_type = METRICS_AVERAGE_GFXCLK; + break; + case PPCLK_UCLK: + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) + member_type = METRICS_CURR_UCLK; + else + member_type = METRICS_AVERAGE_UCLK; + break; + case PPCLK_SOCCLK: + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) + member_type = METRICS_CURR_SOCCLK; + else + member_type = METRICS_AVERAGE_SOCCLK; + break; + case PPCLK_VCLK: + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) + member_type = METRICS_CURR_VCLK; + else + member_type = METRICS_AVERAGE_VCLK; + break; + case PPCLK_DCLK: + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) + member_type = METRICS_CURR_DCLK; + else + member_type = METRICS_AVERAGE_DCLK; + break; + case PPCLK_FCLK: + member_type = METRICS_CURR_FCLK; + break; + default: + return -EINVAL; + } + + return aldebaran_get_smu_metrics_data(smu, + member_type, + value); +} + +static int aldebaran_print_clk_levels(struct smu_context *smu, + enum smu_clk_type type, char *buf) +{ + int i, now, size = 0; + int ret = 0; + struct pp_clock_levels_with_latency clocks; + struct smu_13_0_dpm_table *single_dpm_table; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_13_0_dpm_context *dpm_context = NULL; + uint32_t display_levels; + uint32_t freq_values[3] = {0}; + + if (amdgpu_ras_intr_triggered()) + return snprintf(buf, PAGE_SIZE, "unavailable\n"); + + dpm_context = smu_dpm->dpm_context; + + switch (type) { + + case SMU_OD_SCLK: + size = sprintf(buf, "%s:\n", "GFXCLK"); + fallthrough; + case SMU_SCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); + return ret; + } + + display_levels = clocks.num_levels; + + /* fine-grained dpm has only 2 levels */ + if (now > single_dpm_table->dpm_levels[0].value && + now < single_dpm_table->dpm_levels[1].value) { + display_levels = clocks.num_levels + 1; + freq_values[0] = single_dpm_table->dpm_levels[0].value; + freq_values[2] = single_dpm_table->dpm_levels[1].value; + freq_values[1] = now; + } + + /* + * For DPM disabled case, there will be only one clock level. + * And it's safe to assume that is always the current clock. + */ + if (display_levels == clocks.num_levels) { + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + } else { + for (i = 0; i < display_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", i, + freq_values[i], i == 1 ? "*" : ""); + } + + break; + + case SMU_OD_MCLK: + size = sprintf(buf, "%s:\n", "MCLK"); + fallthrough; + case SMU_MCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.uclk_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); + return ret; + } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, clocks.data[i].clocks_in_khz / 1000, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + + case SMU_SOCCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.soc_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); + return ret; + } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, clocks.data[i].clocks_in_khz / 1000, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + + case SMU_FCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.fclk_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, single_dpm_table->dpm_levels[i].value, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + + default: + break; + } + + return size; +} + +static int aldebaran_upload_dpm_level(struct smu_context *smu, + bool max, + uint32_t feature_mask, + uint32_t level) +{ + struct smu_13_0_dpm_context *dpm_context = + smu->smu_dpm.dpm_context; + uint32_t freq; + int ret = 0; + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && + (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { + freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; + ret = smu_cmn_send_smc_msg_with_param(smu, + (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), + (PPCLK_GFXCLK << 16) | (freq & 0xffff), + NULL); + if (ret) { + dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", + max ? "max" : "min"); + return ret; + } + } + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && + (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { + freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; + ret = smu_cmn_send_smc_msg_with_param(smu, + (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), + (PPCLK_UCLK << 16) | (freq & 0xffff), + NULL); + if (ret) { + dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", + max ? "max" : "min"); + return ret; + } + } + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && + (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { + freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; + ret = smu_cmn_send_smc_msg_with_param(smu, + (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), + (PPCLK_SOCCLK << 16) | (freq & 0xffff), + NULL); + if (ret) { + dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", + max ? "max" : "min"); + return ret; + } + } + + return ret; +} + +static int aldebaran_force_clk_levels(struct smu_context *smu, + enum smu_clk_type type, uint32_t mask) +{ + struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_13_0_dpm_table *single_dpm_table = NULL; + uint32_t soft_min_level, soft_max_level; + int ret = 0; + + soft_min_level = mask ? (ffs(mask) - 1) : 0; + soft_max_level = mask ? (fls(mask) - 1) : 0; + + switch (type) { + case SMU_SCLK: + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + if (soft_max_level >= single_dpm_table->count) { + dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", + soft_max_level, single_dpm_table->count - 1); + ret = -EINVAL; + break; + } + + ret = aldebaran_upload_dpm_level(smu, + false, + FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), + soft_min_level); + if (ret) { + dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); + break; + } + + ret = aldebaran_upload_dpm_level(smu, + true, + FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), + soft_max_level); + if (ret) + dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); + + break; + + case SMU_MCLK: + case SMU_SOCCLK: + case SMU_FCLK: + /* + * Should not arrive here since aldebaran does not + * support mclk/socclk/fclk softmin/softmax settings + */ + ret = -EINVAL; + break; + + default: + break; + } + + return ret; +} + +static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, + struct smu_temperature_range *range) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_13_0_powerplay_table *powerplay_table = + table_context->power_play_table; + PPTable_t *pptable = smu->smu_table.driver_pptable; + + if (!range) + return -EINVAL; + + memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); + + range->hotspot_crit_max = pptable->ThotspotLimit * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->mem_crit_max = pptable->TmemLimit * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; + + return 0; +} + +static int aldebaran_get_current_activity_percent(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXACTIVITY, + value); + break; + case AMDGPU_PP_SENSOR_MEM_LOAD: + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_AVERAGE_MEMACTIVITY, + value); + break; + default: + dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); + return -EINVAL; + } + + return ret; +} + +static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) +{ + if (!value) + return -EINVAL; + + return aldebaran_get_smu_metrics_data(smu, + METRICS_AVERAGE_SOCKETPOWER, + value); +} + +static int aldebaran_thermal_get_temperature(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_HOTSPOT, + value); + break; + case AMDGPU_PP_SENSOR_EDGE_TEMP: + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_EDGE, + value); + break; + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_MEM, + value); + break; + default: + dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); + return -EINVAL; + } + + return ret; +} + +static int aldebaran_read_sensor(struct smu_context *smu, + enum amd_pp_sensors sensor, + void *data, uint32_t *size) +{ + int ret = 0; + + if (amdgpu_ras_intr_triggered()) + return 0; + + if (!data || !size) + return -EINVAL; + + mutex_lock(&smu->sensor_lock); + switch (sensor) { + case AMDGPU_PP_SENSOR_MEM_LOAD: + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = aldebaran_get_current_activity_percent(smu, + sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_POWER: + ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + case AMDGPU_PP_SENSOR_EDGE_TEMP: + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = aldebaran_thermal_get_temperature(smu, sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); + /* the output clock frequency in 10K unit */ + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDGFX: + ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); + *size = 4; + break; + default: + ret = -EOPNOTSUPP; + break; + } + mutex_unlock(&smu->sensor_lock); + + return ret; +} + +static int aldebaran_get_power_limit(struct smu_context *smu) +{ + PPTable_t *pptable = smu->smu_table.driver_pptable; + uint32_t power_limit = 0; + int ret; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) + return -EINVAL; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); + + if (ret) { + /* the last hope to figure out the ppt limit */ + if (!pptable) { + dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); + return -EINVAL; + } + power_limit = pptable->PptLimit; + } + + smu->current_power_limit = smu->default_power_limit = power_limit; + if (pptable) + smu->max_power_limit = pptable->PptLimit; + + return 0; +} + +static int aldebaran_system_features_control(struct smu_context *smu, bool enable) +{ + int ret; + + ret = smu_v13_0_system_features_control(smu, enable); + if (!ret && enable) + ret = aldebaran_run_btc(smu); + + return ret; +} + +static int aldebaran_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + + /* Disable determinism if switching to another mode */ + if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) + && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) + smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); + + + switch (level) { + + case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: + return 0; + + case AMD_DPM_FORCED_LEVEL_HIGH: + case AMD_DPM_FORCED_LEVEL_LOW: + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + default: + break; + } + + return smu_v13_0_set_performance_level(smu, level); +} + +static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct amdgpu_device *adev = smu->adev; + uint32_t min_clk; + uint32_t max_clk; + int ret = 0; + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) + return -EINVAL; + + if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) + return -EINVAL; + + if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { + min_clk = max(min, dpm_context->dpm_tables.gfx_table.min); + max_clk = min(max, dpm_context->dpm_tables.gfx_table.max); + return smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); + } + + if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { + if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || + (max > dpm_context->dpm_tables.gfx_table.max)) { + dev_warn(adev->dev, + "Invalid max frequency %d MHz specified for determinism\n", max); + return -EINVAL; + } + + /* Restore default min/max clocks and enable determinism */ + min_clk = dpm_context->dpm_tables.gfx_table.min; + max_clk = dpm_context->dpm_tables.gfx_table.max; + ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); + if (!ret) { + usleep_range(500, 1000); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_EnableDeterminism, + max, NULL); + if (ret) + dev_err(adev->dev, + "Failed to enable determinism at GFX clock %d MHz\n", max); + } + } + + return ret; +} + +static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, + long input[], uint32_t size) +{ + struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + uint32_t min_clk; + uint32_t max_clk; + int ret = 0; + + /* Only allowed in manual or determinism mode */ + if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) + return -EINVAL; + + switch (type) { + case PP_OD_EDIT_SCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } + + if (input[0] == 0) { + if (input[1] < dpm_context->dpm_tables.gfx_table.min) { + dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", + input[1], dpm_context->dpm_tables.gfx_table.min); + return -EINVAL; + } + smu->gfx_actual_hard_min_freq = input[1]; + } else if (input[0] == 1) { + if (input[1] > dpm_context->dpm_tables.gfx_table.max) { + dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], dpm_context->dpm_tables.gfx_table.max); + return -EINVAL; + } + smu->gfx_actual_soft_max_freq = input[1]; + } else { + return -EINVAL; + } + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } else { + /* Use the default frequencies for manual and determinism mode */ + min_clk = dpm_context->dpm_tables.gfx_table.min; + max_clk = dpm_context->dpm_tables.gfx_table.max; + + return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); + } + break; + case PP_OD_COMMIT_DPM_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } else { + min_clk = smu->gfx_actual_hard_min_freq; + max_clk = smu->gfx_actual_soft_max_freq; + return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); + } + break; + default: + return -ENOSYS; + } + + return ret; +} + +static bool aldebaran_is_dpm_running(struct smu_context *smu) +{ + int ret = 0; + uint32_t feature_mask[2]; + unsigned long feature_enabled; + ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); + feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | + ((uint64_t)feature_mask[1] << 32)); + return !!(feature_enabled & SMC_DPM_FEATURE); +} + +static void aldebaran_get_unique_id(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + SmuMetrics_t *metrics = smu->smu_table.metrics_table; + uint32_t upper32 = 0, lower32 = 0; + int ret; + + mutex_lock(&smu->metrics_lock); + ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); + if (ret) + goto out_unlock; + + upper32 = metrics->PublicSerialNumUpper32; + lower32 = metrics->PublicSerialNumLower32; + +out_unlock: + mutex_unlock(&smu->metrics_lock); + + adev->unique_id = ((uint64_t)upper32 << 32) | lower32; + sprintf(adev->serial, "%016llx", adev->unique_id); +} + +static bool aldebaran_is_baco_supported(struct smu_context *smu) +{ + /* aldebaran is not support baco */ + + return false; +} + +static int aldebaran_set_df_cstate(struct smu_context *smu, + enum pp_df_cstate state) +{ + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); +} + +static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) +{ + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GmiPwrDnControl, + en ? 1 : 0, + NULL); +} + +static const struct throttling_logging_label { + uint32_t feature_mask; + const char *label; +} logging_label[] = { + {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, + {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, + {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, + {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, +}; +static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) +{ + int ret; + int throttler_idx, throtting_events = 0, buf_idx = 0; + struct amdgpu_device *adev = smu->adev; + uint32_t throttler_status; + char log_buf[256]; + + ret = aldebaran_get_smu_metrics_data(smu, + METRICS_THROTTLER_STATUS, + &throttler_status); + if (ret) + return; + + memset(log_buf, 0, sizeof(log_buf)); + for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); + throttler_idx++) { + if (throttler_status & logging_label[throttler_idx].feature_mask) { + throtting_events++; + buf_idx += snprintf(log_buf + buf_idx, + sizeof(log_buf) - buf_idx, + "%s%s", + throtting_events > 1 ? " and " : "", + logging_label[throttler_idx].label); + if (buf_idx >= sizeof(log_buf)) { + dev_err(adev->dev, "buffer overflow!\n"); + log_buf[sizeof(log_buf) - 1] = '\0'; + break; + } + } + } + + dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", + log_buf); + kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status); +} + +static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t esm_ctrl; + + /* TODO: confirm this on real target */ + esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); + if ((esm_ctrl >> 15) & 0x1FFFF) + return (((esm_ctrl >> 8) & 0x3F) + 128); + + return smu_v13_0_get_current_pcie_link_speed(smu); +} + +static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct gpu_metrics_v1_1 *gpu_metrics = + (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + SmuMetrics_t metrics; + int i, ret = 0; + + ret = smu_cmn_get_metrics_table(smu, + &metrics, + true); + if (ret) + return ret; + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + + gpu_metrics->temperature_edge = metrics.TemperatureEdge; + gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; + gpu_metrics->temperature_mem = metrics.TemperatureHBM; + gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; + gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; + gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; + + gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; + gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; + gpu_metrics->average_mm_activity = 0; + + gpu_metrics->average_socket_power = metrics.AverageSocketPower; + gpu_metrics->energy_accumulator = 0; + + gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; + gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; + gpu_metrics->average_vclk0_frequency = 0; + gpu_metrics->average_dclk0_frequency = 0; + + gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; + gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; + gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; + + gpu_metrics->throttle_status = metrics.ThrottlerStatus; + + gpu_metrics->current_fan_speed = 0; + + gpu_metrics->pcie_link_width = + smu_v13_0_get_current_pcie_link_width(smu); + gpu_metrics->pcie_link_speed = + aldebaran_get_current_pcie_link_speed(smu); + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; + gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; + + for (i = 0; i < NUM_HBM_INSTANCES; i++) + gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; + + *table = (void *)gpu_metrics; + + return sizeof(struct gpu_metrics_v1_1); +} + +static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) +{ +#if 0 + struct amdgpu_device *adev = smu->adev; + u32 smu_version; + uint32_t val; + /** + * PM FW version support mode1 reset from 68.07 + */ + smu_cmn_get_smc_version(smu, NULL, &smu_version); + if ((smu_version < 0x00440700)) + return false; + /** + * mode1 reset relies on PSP, so we should check if + * PSP is alive. + */ + val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); + + return val != 0x0; +#endif + return true; +} + +static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) +{ + return true; +} + +static const struct pptable_funcs aldebaran_ppt_funcs = { + /* init dpm */ + .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, + /* dpm/clk tables */ + .set_default_dpm_table = aldebaran_set_default_dpm_table, + .populate_umd_state_clk = aldebaran_populate_umd_state_clk, + .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, + .print_clk_levels = aldebaran_print_clk_levels, + .force_clk_levels = aldebaran_force_clk_levels, + .read_sensor = aldebaran_read_sensor, + .set_performance_level = aldebaran_set_performance_level, + .get_power_limit = aldebaran_get_power_limit, + .is_dpm_running = aldebaran_is_dpm_running, + .get_unique_id = aldebaran_get_unique_id, + .init_microcode = smu_v13_0_init_microcode, + .load_microcode = smu_v13_0_load_microcode, + .fini_microcode = smu_v13_0_fini_microcode, + .init_smc_tables = aldebaran_init_smc_tables, + .fini_smc_tables = smu_v13_0_fini_smc_tables, + .init_power = smu_v13_0_init_power, + .fini_power = smu_v13_0_fini_power, + .check_fw_status = smu_v13_0_check_fw_status, + /* pptable related */ + .setup_pptable = aldebaran_setup_pptable, + .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, + .check_fw_version = smu_v13_0_check_fw_version, + .write_pptable = smu_cmn_write_pptable, + .set_driver_table_location = smu_v13_0_set_driver_table_location, + .set_tool_table_location = smu_v13_0_set_tool_table_location, + .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, + .system_features_control = aldebaran_system_features_control, + .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, + .send_smc_msg = smu_cmn_send_smc_msg, + .get_enabled_mask = smu_cmn_get_enabled_mask, + .feature_is_enabled = smu_cmn_feature_is_enabled, + .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, + .set_power_limit = smu_v13_0_set_power_limit, + .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, + .enable_thermal_alert = smu_v13_0_enable_thermal_alert, + .disable_thermal_alert = smu_v13_0_disable_thermal_alert, + .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, + .register_irq_handler = smu_v13_0_register_irq_handler, + .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, + .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, + .baco_is_support= aldebaran_is_baco_supported, + .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, + .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, + .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, + .set_df_cstate = aldebaran_set_df_cstate, + .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, + .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, + .get_gpu_metrics = aldebaran_get_gpu_metrics, + .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, + .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, + .mode1_reset = smu_v13_0_mode1_reset, + .mode2_reset = smu_v13_0_mode2_reset, +}; + +void aldebaran_set_ppt_funcs(struct smu_context *smu) +{ + smu->ppt_funcs = &aldebaran_ppt_funcs; + smu->message_map = aldebaran_message_map; + smu->clock_map = aldebaran_clk_map; + smu->feature_map = aldebaran_feature_mask_map; + smu->table_map = aldebaran_table_map; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h new file mode 100644 index 0000000000000000000000000000000000000000..33a85d57cf15a379ec7f76b7eb41ffff9848d603 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h @@ -0,0 +1,72 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __ALDEBARAN_PPT_H__ +#define __ALDEBARAN_PPT_H__ + +#define ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL 0x3 +#define ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL 0x3 +#define ALDEBARAN_UMD_PSTATE_MCLK_LEVEL 0x2 + +#define MAX_DPM_NUMBER 16 +#define MAX_PCIE_CONF 2 + +struct aldebaran_dpm_level { + bool enabled; + uint32_t value; + uint32_t param1; +}; + +struct aldebaran_dpm_state { + uint32_t soft_min_level; + uint32_t soft_max_level; + uint32_t hard_min_level; + uint32_t hard_max_level; +}; + +struct aldebaran_single_dpm_table { + uint32_t count; + struct aldebaran_dpm_state dpm_state; + struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER]; +}; + +struct aldebaran_pcie_table { + uint16_t count; + uint8_t pcie_gen[MAX_PCIE_CONF]; + uint8_t pcie_lane[MAX_PCIE_CONF]; + uint32_t lclk[MAX_PCIE_CONF]; +}; + +struct aldebaran_dpm_table { + struct aldebaran_single_dpm_table soc_table; + struct aldebaran_single_dpm_table gfx_table; + struct aldebaran_single_dpm_table mem_table; + struct aldebaran_single_dpm_table eclk_table; + struct aldebaran_single_dpm_table vclk_table; + struct aldebaran_single_dpm_table dclk_table; + struct aldebaran_single_dpm_table fclk_table; + struct aldebaran_pcie_table pcie_table; +}; + +extern void aldebaran_set_ppt_funcs(struct smu_context *smu); + +#endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c new file mode 100644 index 0000000000000000000000000000000000000000..bd3a9c89dc440c963730601d0b3494b14e79ed60 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -0,0 +1,1811 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#define SMU_13_0_PARTIAL_PPTABLE +#define SWSMU_CODE_LAYER_L3 + +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "atomfirmware.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_atombios.h" +#include "smu_v13_0.h" +#include "soc15_common.h" +#include "atom.h" +#include "amdgpu_ras.h" +#include "smu_cmn.h" + +#include "asic_reg/thm/thm_13_0_2_offset.h" +#include "asic_reg/thm/thm_13_0_2_sh_mask.h" +#include "asic_reg/mp/mp_13_0_2_offset.h" +#include "asic_reg/mp/mp_13_0_2_sh_mask.h" +#include "asic_reg/smuio/smuio_13_0_2_offset.h" +#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h" + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); + +#define SMU13_VOLTAGE_SCALE 4 + +#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms + +#define LINK_WIDTH_MAX 6 +#define LINK_SPEED_MAX 3 + +#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define smnPCIE_LC_SPEED_CNTL 0x11140290 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE + +static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; +static int link_speed[] = {25, 50, 80, 160}; + +int smu_v13_0_init_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + const char *chip_name; + char fw_name[30]; + int err = 0; + const struct smc_firmware_header_v1_0 *hdr; + const struct common_firmware_header *header; + struct amdgpu_firmware_info *ucode = NULL; + + switch (adev->asic_type) { + case CHIP_ALDEBARAN: + chip_name = "aldebaran"; + break; + default: + dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type); + return -EINVAL; + } + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); + + err = request_firmware(&adev->pm.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->pm.fw); + if (err) + goto out; + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + amdgpu_ucode_print_smc_hdr(&hdr->header); + adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; + ucode->ucode_id = AMDGPU_UCODE_ID_SMC; + ucode->fw = adev->pm.fw; + header = (const struct common_firmware_header *)ucode->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + +out: + if (err) { + DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + } + return err; +} + +void smu_v13_0_fini_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + adev->pm.fw_version = 0; +} + +int smu_v13_0_load_microcode(struct smu_context *smu) +{ +#if 0 + struct amdgpu_device *adev = smu->adev; + const uint32_t *src; + const struct smc_firmware_header_v1_0 *hdr; + uint32_t addr_start = MP1_SRAM; + uint32_t i; + uint32_t smc_fw_size; + uint32_t mp1_fw_flags; + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + src = (const uint32_t *)(adev->pm.fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + smc_fw_size = hdr->header.ucode_size_bytes; + + for (i = 1; i < smc_fw_size/4 - 1; i++) { + WREG32_PCIE(addr_start, src[i]); + addr_start += 4; + } + + WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), + 1 & MP1_SMN_PUB_CTRL__RESET_MASK); + WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), + 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); + + for (i = 0; i < adev->usec_timeout; i++) { + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -ETIME; +#endif + return 0; +} + +int smu_v13_0_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags; + + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + + if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + +int smu_v13_0_check_fw_version(struct smu_context *smu) +{ + uint32_t if_version = 0xff, smu_version = 0xff; + uint16_t smu_major; + uint8_t smu_minor, smu_debug; + int ret = 0; + + ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); + if (ret) + return ret; + + smu_major = (smu_version >> 16) & 0xffff; + smu_minor = (smu_version >> 8) & 0xff; + smu_debug = (smu_version >> 0) & 0xff; + + switch (smu->adev->asic_type) { + case CHIP_ALDEBARAN: + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; + break; + default: + dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; + break; + } + + dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n", + smu_version, smu_major, smu_minor, smu_debug); + + /* + * 1. if_version mismatch is not critical as our fw is designed + * to be backward compatible. + * 2. New fw usually brings some optimizations. But that's visible + * only on the paired driver. + * Considering above, we just leave user a warning message instead + * of halt driver loading. + */ + if (if_version != smu->smc_driver_if_version) { + dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " + "smu fw version = 0x%08x (%d.%d.%d)\n", + smu->smc_driver_if_version, if_version, + smu_version, smu_major, smu_minor, smu_debug); + dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); + } + + return ret; +} + +static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table, + uint32_t *size, uint32_t pptable_id) +{ + struct amdgpu_device *adev = smu->adev; + const struct smc_firmware_header_v2_1 *v2_1; + struct smc_soft_pptable_entry *entries; + uint32_t pptable_count = 0; + int i = 0; + + v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; + entries = (struct smc_soft_pptable_entry *) + ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); + pptable_count = le32_to_cpu(v2_1->pptable_count); + for (i = 0; i < pptable_count; i++) { + if (le32_to_cpu(entries[i].id) == pptable_id) { + *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); + *size = le32_to_cpu(entries[i].ppt_size_bytes); + break; + } + } + + if (i == pptable_count) + return -EINVAL; + + return 0; +} + +int smu_v13_0_setup_pptable(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + const struct smc_firmware_header_v1_0 *hdr; + int ret, index; + uint32_t size = 0; + uint16_t atom_table_size; + uint8_t frev, crev; + void *table; + uint16_t version_major, version_minor; + + /* temporarily hardcode to use vbios pptable */ + smu->smu_table.boot_values.pp_table_id = 0; + + if (amdgpu_smu_pptable_id >= 0) { + smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id; + dev_info(adev->dev, "override pptable id %d\n", amdgpu_smu_pptable_id); + } + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + version_major = le16_to_cpu(hdr->header.header_version_major); + version_minor = le16_to_cpu(hdr->header.header_version_minor); + if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { + dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); + switch (version_minor) { + case 1: + ret = smu_v13_0_set_pptable_v2_1(smu, &table, &size, + smu->smu_table.boot_values.pp_table_id); + break; + default: + ret = -EINVAL; + break; + } + if (ret) + return ret; + + } else { + dev_info(adev->dev, "use vbios provided pptable\n"); + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + powerplayinfo); + + ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, + (uint8_t **)&table); + if (ret) + return ret; + size = atom_table_size; + } + + if (!smu->smu_table.power_play_table) + smu->smu_table.power_play_table = table; + if (!smu->smu_table.power_play_table_size) + smu->smu_table.power_play_table_size = size; + + return 0; +} + +int smu_v13_0_init_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + int ret = 0; + + smu_table->driver_pptable = + kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); + if (!smu_table->driver_pptable) { + ret = -ENOMEM; + goto err0_out; + } + + smu_table->max_sustainable_clocks = + kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL); + if (!smu_table->max_sustainable_clocks) { + ret = -ENOMEM; + goto err1_out; + } + + /* Aldebaran does not support OVERDRIVE */ + if (tables[SMU_TABLE_OVERDRIVE].size) { + smu_table->overdrive_table = + kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); + if (!smu_table->overdrive_table) { + ret = -ENOMEM; + goto err2_out; + } + + smu_table->boot_overdrive_table = + kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); + if (!smu_table->boot_overdrive_table) { + ret = -ENOMEM; + goto err3_out; + } + } + + return 0; + +err3_out: + kfree(smu_table->overdrive_table); +err2_out: + kfree(smu_table->max_sustainable_clocks); +err1_out: + kfree(smu_table->driver_pptable); +err0_out: + return ret; +} + +int smu_v13_0_fini_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + kfree(smu_table->gpu_metrics_table); + kfree(smu_table->boot_overdrive_table); + kfree(smu_table->overdrive_table); + kfree(smu_table->max_sustainable_clocks); + kfree(smu_table->driver_pptable); + smu_table->gpu_metrics_table = NULL; + smu_table->boot_overdrive_table = NULL; + smu_table->overdrive_table = NULL; + smu_table->max_sustainable_clocks = NULL; + smu_table->driver_pptable = NULL; + kfree(smu_table->hardcode_pptable); + smu_table->hardcode_pptable = NULL; + + kfree(smu_table->metrics_table); + kfree(smu_table->watermarks_table); + smu_table->metrics_table = NULL; + smu_table->watermarks_table = NULL; + smu_table->metrics_time = 0; + + kfree(smu_dpm->dpm_context); + kfree(smu_dpm->golden_dpm_context); + kfree(smu_dpm->dpm_current_power_state); + kfree(smu_dpm->dpm_request_power_state); + smu_dpm->dpm_context = NULL; + smu_dpm->golden_dpm_context = NULL; + smu_dpm->dpm_context_size = 0; + smu_dpm->dpm_current_power_state = NULL; + smu_dpm->dpm_request_power_state = NULL; + + return 0; +} + +int smu_v13_0_init_power(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + + if (smu_power->power_context || smu_power->power_context_size != 0) + return -EINVAL; + + smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context), + GFP_KERNEL); + if (!smu_power->power_context) + return -ENOMEM; + smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context); + + return 0; +} + +int smu_v13_0_fini_power(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + + if (!smu_power->power_context || smu_power->power_context_size == 0) + return -EINVAL; + + kfree(smu_power->power_context); + smu_power->power_context = NULL; + smu_power->power_context_size = 0; + + return 0; +} + +static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, + uint8_t clk_id, + uint8_t syspll_id, + uint32_t *clk_freq) +{ + struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + int ret, index; + + input.clk_id = clk_id; + input.syspll_id = syspll_id; + input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, + getsmuclockinfo); + + ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, + (uint32_t *)&input); + if (ret) + return -EINVAL; + + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; + *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; + + return 0; +} + +int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) +{ + int ret, index; + uint16_t size; + uint8_t frev, crev; + struct atom_common_table_header *header; + struct atom_firmware_info_v3_4 *v_3_4; + struct atom_firmware_info_v3_3 *v_3_3; + struct atom_firmware_info_v3_1 *v_3_1; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); + + ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, + (uint8_t **)&header); + if (ret) + return ret; + + if (header->format_revision != 3) { + dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); + return -EINVAL; + } + + switch (header->content_revision) { + case 0: + case 1: + case 2: + v_3_1 = (struct atom_firmware_info_v3_1 *)header; + smu->smu_table.boot_values.revision = v_3_1->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = 0; + break; + case 3: + v_3_3 = (struct atom_firmware_info_v3_3 *)header; + smu->smu_table.boot_values.revision = v_3_3->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; + break; + case 4: + default: + v_3_4 = (struct atom_firmware_info_v3_4 *)header; + smu->smu_table.boot_values.revision = v_3_4->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; + break; + } + + smu->smu_table.boot_values.format_revision = header->format_revision; + smu->smu_table.boot_values.content_revision = header->content_revision; + + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.socclk); + + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.dcefclk); + + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_ECLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.eclk); + + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_VCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.vclk); + + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_DCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.dclk); + + if ((smu->smu_table.boot_values.format_revision == 3) && + (smu->smu_table.boot_values.content_revision >= 2)) + smu_v13_0_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, + (uint8_t)SMU11_SYSPLL1_2_ID, + &smu->smu_table.boot_values.fclk); + + return 0; +} + + +int smu_v13_0_notify_memory_pool_location(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *memory_pool = &smu_table->memory_pool; + int ret = 0; + uint64_t address; + uint32_t address_low, address_high; + + if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) + return ret; + + address = memory_pool->mc_address; + address_high = (uint32_t)upper_32_bits(address); + address_low = (uint32_t)lower_32_bits(address); + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, + address_high, NULL); + if (ret) + return ret; + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, + address_low, NULL); + if (ret) + return ret; + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, + (uint32_t)memory_pool->size, NULL); + if (ret) + return ret; + + return ret; +} + +int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) +{ + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); + if (ret) + dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); + + return ret; +} + +int smu_v13_0_set_driver_table_location(struct smu_context *smu) +{ + struct smu_table *driver_table = &smu->smu_table.driver_table; + int ret = 0; + + if (driver_table->mc_address) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetDriverDramAddrHigh, + upper_32_bits(driver_table->mc_address), + NULL); + if (!ret) + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetDriverDramAddrLow, + lower_32_bits(driver_table->mc_address), + NULL); + } + + return ret; +} + +int smu_v13_0_set_tool_table_location(struct smu_context *smu) +{ + int ret = 0; + struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; + + if (tool_table->mc_address) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetToolsDramAddrHigh, + upper_32_bits(tool_table->mc_address), + NULL); + if (!ret) + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetToolsDramAddrLow, + lower_32_bits(tool_table->mc_address), + NULL); + } + + return ret; +} + +int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count) +{ + int ret = 0; + + if (!smu->pm_enabled) + return ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); + + return ret; +} + + +int smu_v13_0_set_allowed_mask(struct smu_context *smu) +{ + struct smu_feature *feature = &smu->smu_feature; + int ret = 0; + uint32_t feature_mask[2]; + + mutex_lock(&feature->mutex); + if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) + goto failed; + + bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, + feature_mask[1], NULL); + if (ret) + goto failed; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, + feature_mask[0], NULL); + if (ret) + goto failed; + +failed: + mutex_unlock(&feature->mutex); + return ret; +} + +int smu_v13_0_system_features_control(struct smu_context *smu, + bool en) +{ + struct smu_feature *feature = &smu->smu_feature; + uint32_t feature_mask[2]; + int ret = 0; + + ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : + SMU_MSG_DisableAllSmuFeatures), NULL); + if (ret) + return ret; + + bitmap_zero(feature->enabled, feature->feature_num); + bitmap_zero(feature->supported, feature->feature_num); + + if (en) { + ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); + if (ret) + return ret; + + bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, + feature->feature_num); + bitmap_copy(feature->supported, (unsigned long *)&feature_mask, + feature->feature_num); + } + + return ret; +} + +int smu_v13_0_notify_display_change(struct smu_context *smu) +{ + int ret = 0; + + if (!smu->pm_enabled) + return ret; + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && + smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); + + return ret; +} + + static int +smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, + enum smu_clk_type clock_select) +{ + int ret = 0; + int clk_id; + + if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || + (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clock_select); + if (clk_id < 0) + return -EINVAL; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, + clk_id << 16, clock); + if (ret) { + dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); + return ret; + } + + if (*clock != 0) + return 0; + + /* if DC limit is zero, return AC limit */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, + clk_id << 16, clock); + if (ret) { + dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); + return ret; + } + + return 0; +} + +int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu) +{ + struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks = + smu->smu_table.max_sustainable_clocks; + int ret = 0; + + max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; + max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; + max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; + max_sustainable_clocks->display_clock = 0xFFFFFFFF; + max_sustainable_clocks->phy_clock = 0xFFFFFFFF; + max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->uclock), + SMU_UCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", + __func__); + return ret; + } + } + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->soc_clock), + SMU_SOCCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", + __func__); + return ret; + } + } + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->dcef_clock), + SMU_DCEFCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", + __func__); + return ret; + } + + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->display_clock), + SMU_DISPCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", + __func__); + return ret; + } + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->phy_clock), + SMU_PHYCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", + __func__); + return ret; + } + ret = smu_v13_0_get_max_sustainable_clock(smu, + &(max_sustainable_clocks->pixel_clock), + SMU_PIXCLK); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", + __func__); + return ret; + } + } + + if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) + max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; + + return 0; +} + +int smu_v13_0_get_current_power_limit(struct smu_context *smu, + uint32_t *power_limit) +{ + int power_src; + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) + return -EINVAL; + + power_src = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_PWR, + smu->adev->pm.ac_power ? + SMU_POWER_SOURCE_AC : + SMU_POWER_SOURCE_DC); + if (power_src < 0) + return -EINVAL; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetPptLimit, + power_src << 16, + power_limit); + if (ret) + dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); + + return ret; +} + +int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n) +{ + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { + dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); + return -EOPNOTSUPP; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL); + if (ret) { + dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); + return ret; + } + + smu->current_power_limit = n; + + return 0; +} + +int smu_v13_0_enable_thermal_alert(struct smu_context *smu) +{ + if (smu->smu_table.thermal_controller_type) + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); + + return 0; +} + +int smu_v13_0_disable_thermal_alert(struct smu_context *smu) +{ + return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); +} + +static uint16_t convert_to_vddc(uint8_t vid) +{ + return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE); +} + +int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t vdd = 0, val_vid = 0; + + if (!value) + return -EINVAL; + val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) & + SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> + SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; + + vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); + + *value = vdd; + + return 0; + +} + +int +smu_v13_0_display_clock_voltage_request(struct smu_context *smu, + struct pp_display_clock_request + *clock_req) +{ + enum amd_pp_clock_type clk_type = clock_req->clock_type; + int ret = 0; + enum smu_clk_type clk_select = 0; + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || + smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + switch (clk_type) { + case amd_pp_dcef_clock: + clk_select = SMU_DCEFCLK; + break; + case amd_pp_disp_clock: + clk_select = SMU_DISPCLK; + break; + case amd_pp_pixel_clock: + clk_select = SMU_PIXCLK; + break; + case amd_pp_phy_clock: + clk_select = SMU_PHYCLK; + break; + case amd_pp_mem_clock: + clk_select = SMU_UCLK; + break; + default: + dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); + ret = -EINVAL; + break; + } + + if (ret) + goto failed; + + if (clk_select == SMU_UCLK && smu->disable_uclk_switch) + return 0; + + ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); + + if(clk_select == SMU_UCLK) + smu->hard_min_uclk_req_from_dal = clk_freq; + } + +failed: + return ret; +} + +uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) +{ + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) + return AMD_FAN_CTRL_MANUAL; + else + return AMD_FAN_CTRL_AUTO; +} + + static int +smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) +{ + int ret = 0; + + if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) + return 0; + + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); + if (ret) + dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", + __func__, (auto_fan_control ? "Start" : "Stop")); + + return ret; +} + + static int +smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) +{ + struct amdgpu_device *adev = smu->adev; + + WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, + REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), + CG_FDO_CTRL2, TMIN, 0)); + WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, + REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), + CG_FDO_CTRL2, FDO_PWM_MODE, mode)); + + return 0; +} + + int +smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t duty100, duty; + uint64_t tmp64; + + if (speed > 100) + speed = 100; + + if (smu_v13_0_auto_fan_control(smu, 0)) + return -EINVAL; + + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1), + CG_FDO_CTRL1, FMAX_DUTY100); + if (!duty100) + return -EINVAL; + + tmp64 = (uint64_t)speed * duty100; + do_div(tmp64, 100); + duty = (uint32_t)tmp64; + + WREG32_SOC15(THM, 0, regCG_FDO_CTRL0, + REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0), + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); + + return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); +} + + int +smu_v13_0_set_fan_control_mode(struct smu_context *smu, + uint32_t mode) +{ + int ret = 0; + + switch (mode) { + case AMD_FAN_CTRL_NONE: + ret = smu_v13_0_set_fan_speed_percent(smu, 100); + break; + case AMD_FAN_CTRL_MANUAL: + ret = smu_v13_0_auto_fan_control(smu, 0); + break; + case AMD_FAN_CTRL_AUTO: + ret = smu_v13_0_auto_fan_control(smu, 1); + break; + default: + break; + } + + if (ret) { + dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); + return -EINVAL; + } + + return ret; +} + +int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, + uint32_t speed) +{ + struct amdgpu_device *adev = smu->adev; + int ret; + uint32_t tach_period, crystal_clock_freq; + + if (!speed) + return -EINVAL; + + ret = smu_v13_0_auto_fan_control(smu, 0); + if (ret) + return ret; + + crystal_clock_freq = amdgpu_asic_get_xclk(adev); + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); + WREG32_SOC15(THM, 0, regCG_TACH_CTRL, + REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL), + CG_TACH_CTRL, TARGET_PERIOD, + tach_period)); + + ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); + + return ret; +} + +int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, + uint32_t pstate) +{ + int ret = 0; + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetXgmiMode, + pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, + NULL); + return ret; +} + +static int smu_v13_0_set_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned tyep, + enum amdgpu_interrupt_state state) +{ + struct smu_context *smu = &adev->smu; + uint32_t low, high; + uint32_t val = 0; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* For THM irqs */ + val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); + WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); + + WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); + + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* For THM irqs */ + low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, + smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); + high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, + smu->thermal_range.software_shutdown_temp); + + val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); + val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); + WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); + + val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); + val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); + val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); + WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); + + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); + + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + default: + break; + } + + return 0; +} + +static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu) +{ + return smu_cmn_send_smc_msg(smu, + SMU_MSG_ReenableAcDcInterrupt, + NULL); +} + +#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ +#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ +#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 + +static int smu_v13_0_irq_process(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct smu_context *smu = &adev->smu; + uint32_t client_id = entry->client_id; + uint32_t src_id = entry->src_id; + /* + * ctxid is used to distinguish different + * events for SMCToHost interrupt. + */ + uint32_t ctxid = entry->src_data[0]; + uint32_t data; + + if (client_id == SOC15_IH_CLIENTID_THM) { + switch (src_id) { + case THM_11_0__SRCID__THM_DIG_THERM_L2H: + dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); + /* + * SW CTF just occurred. + * Try to do a graceful shutdown to prevent further damage. + */ + dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); + orderly_poweroff(true); + break; + case THM_11_0__SRCID__THM_DIG_THERM_H2L: + dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); + break; + default: + dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", + src_id); + break; + } + } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { + dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); + /* + * HW CTF just occurred. Shutdown to prevent further damage. + */ + dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); + orderly_poweroff(true); + } else if (client_id == SOC15_IH_CLIENTID_MP1) { + if (src_id == 0xfe) { + /* ACK SMUToHost interrupt */ + data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); + + switch (ctxid) { + case 0x3: + dev_dbg(adev->dev, "Switched to AC mode!\n"); + smu_v13_0_ack_ac_dc_interrupt(&adev->smu); + break; + case 0x4: + dev_dbg(adev->dev, "Switched to DC mode!\n"); + smu_v13_0_ack_ac_dc_interrupt(&adev->smu); + break; + case 0x7: + /* + * Increment the throttle interrupt counter + */ + atomic64_inc(&smu->throttle_int_counter); + + if (!atomic_read(&adev->throttling_logging_enabled)) + return 0; + + if (__ratelimit(&adev->throttling_logging_rs)) + schedule_work(&smu->throttling_logging_work); + + break; + } + } + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = +{ + .set = smu_v13_0_set_irq_state, + .process = smu_v13_0_irq_process, +}; + +int smu_v13_0_register_irq_handler(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct amdgpu_irq_src *irq_src = &smu->irq_source; + int ret = 0; + + irq_src->num_types = 1; + irq_src->funcs = &smu_v13_0_irq_funcs; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, + THM_11_0__SRCID__THM_DIG_THERM_L2H, + irq_src); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, + THM_11_0__SRCID__THM_DIG_THERM_H2L, + irq_src); + if (ret) + return ret; + + /* Register CTF(GPIO_19) interrupt */ + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, + SMUIO_11_0__SRCID__SMUIO_GPIO19, + irq_src); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, + 0xfe, + irq_src); + if (ret) + return ret; + + return ret; +} + +int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, + struct pp_smu_nv_clock_table *max_clocks) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL; + + if (!max_clocks || !table_context->max_sustainable_clocks) + return -EINVAL; + + sustainable_clocks = table_context->max_sustainable_clocks; + + max_clocks->dcfClockInKhz = + (unsigned int) sustainable_clocks->dcef_clock * 1000; + max_clocks->displayClockInKhz = + (unsigned int) sustainable_clocks->display_clock * 1000; + max_clocks->phyClockInKhz = + (unsigned int) sustainable_clocks->phy_clock * 1000; + max_clocks->pixelClockInKhz = + (unsigned int) sustainable_clocks->pixel_clock * 1000; + max_clocks->uClockInKhz = + (unsigned int) sustainable_clocks->uclock * 1000; + max_clocks->socClockInKhz = + (unsigned int) sustainable_clocks->soc_clock * 1000; + max_clocks->dscClockInKhz = 0; + max_clocks->dppClockInKhz = 0; + max_clocks->fabricClockInKhz = 0; + + return 0; +} + +int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); + + return ret; +} + +int smu_v13_0_mode1_reset(struct smu_context *smu) +{ + u32 smu_version; + int ret = 0; + /* + * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 + */ + smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (smu_version < 0x00440700) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); + else + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL); + + if (!ret) + msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + + return ret; +} + +int smu_v13_0_mode2_reset(struct smu_context *smu) +{ + u32 smu_version; + int ret = 0; + struct amdgpu_device *adev = smu->adev; + smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (smu_version >= 0x00440700) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL); + else + dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", smu_version); + /*TODO: mode2 reset wait time should be shorter, will modify it later*/ + if (!ret) + msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + return ret; +} + +int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t *min, uint32_t *max) +{ + int ret = 0, clk_id = 0; + uint32_t param = 0; + uint32_t clock_limit; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + clock_limit = smu->smu_table.boot_values.uclk; + break; + case SMU_GFXCLK: + case SMU_SCLK: + clock_limit = smu->smu_table.boot_values.gfxclk; + break; + case SMU_SOCCLK: + clock_limit = smu->smu_table.boot_values.socclk; + break; + default: + clock_limit = 0; + break; + } + + /* clock in Mhz unit */ + if (min) + *min = clock_limit / 100; + if (max) + *max = clock_limit / 100; + + return 0; + } + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) { + ret = -EINVAL; + goto failed; + } + param = (clk_id & 0xffff) << 16; + + if (max) { + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); + if (ret) + goto failed; + } + + if (min) { + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); + if (ret) + goto failed; + } + +failed: + return ret; +} + +int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0, clk_id = 0; + uint32_t param; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + if (clk_type == SMU_GFXCLK) + amdgpu_gfx_off_ctrl(adev, false); + + if (max > 0) { + param = (uint32_t)((clk_id << 16) | (max & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, + param, NULL); + if (ret) + goto out; + } + + if (min > 0) { + param = (uint32_t)((clk_id << 16) | (min & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, + param, NULL); + if (ret) + goto out; + } + +out: + if (clk_type == SMU_GFXCLK) + amdgpu_gfx_off_ctrl(adev, true); + + return ret; +} + +int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + int ret = 0, clk_id = 0; + uint32_t param; + + if (min <= 0 && max <= 0) + return -EINVAL; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + if (max > 0) { + param = (uint32_t)((clk_id << 16) | (max & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, + param, NULL); + if (ret) + return ret; + } + + if (min > 0) { + param = (uint32_t)((clk_id << 16) | (min & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, + param, NULL); + if (ret) + return ret; + } + + return ret; +} + +int smu_v13_0_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct smu_13_0_dpm_context *dpm_context = + smu->smu_dpm.dpm_context; + struct smu_13_0_dpm_table *gfx_table = + &dpm_context->dpm_tables.gfx_table; + struct smu_13_0_dpm_table *mem_table = + &dpm_context->dpm_tables.uclk_table; + struct smu_13_0_dpm_table *soc_table = + &dpm_context->dpm_tables.soc_table; + struct smu_umd_pstate_table *pstate_table = + &smu->pstate_table; + struct amdgpu_device *adev = smu->adev; + uint32_t sclk_min = 0, sclk_max = 0; + uint32_t mclk_min = 0, mclk_max = 0; + uint32_t socclk_min = 0, socclk_max = 0; + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + sclk_min = sclk_max = gfx_table->max; + mclk_min = mclk_max = mem_table->max; + socclk_min = socclk_max = soc_table->max; + break; + case AMD_DPM_FORCED_LEVEL_LOW: + sclk_min = sclk_max = gfx_table->min; + mclk_min = mclk_max = mem_table->min; + socclk_min = socclk_max = soc_table->min; + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + sclk_min = gfx_table->min; + sclk_max = gfx_table->max; + mclk_min = mem_table->min; + mclk_max = mem_table->max; + socclk_min = soc_table->min; + socclk_max = soc_table->max; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; + mclk_min = mclk_max = pstate_table->uclk_pstate.standard; + socclk_min = socclk_max = pstate_table->socclk_pstate.standard; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: + mclk_min = mclk_max = pstate_table->uclk_pstate.min; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; + mclk_min = mclk_max = pstate_table->uclk_pstate.peak; + socclk_min = socclk_max = pstate_table->socclk_pstate.peak; + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: + return 0; + default: + dev_err(adev->dev, "Invalid performance level %d\n", level); + return -EINVAL; + } + + mclk_min = mclk_max = 0; + socclk_min = socclk_max = 0; + + if (sclk_min && sclk_max) { + ret = smu_v13_0_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + sclk_min, + sclk_max); + if (ret) + return ret; + } + + if (mclk_min && mclk_max) { + ret = smu_v13_0_set_soft_freq_limited_range(smu, + SMU_MCLK, + mclk_min, + mclk_max); + if (ret) + return ret; + } + + if (socclk_min && socclk_max) { + ret = smu_v13_0_set_soft_freq_limited_range(smu, + SMU_SOCCLK, + socclk_min, + socclk_max); + if (ret) + return ret; + } + + return ret; +} + +int smu_v13_0_set_power_source(struct smu_context *smu, + enum smu_power_src_type power_src) +{ + int pwr_source; + + pwr_source = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_PWR, + (uint32_t)power_src); + if (pwr_source < 0) + return -EINVAL; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_NotifyPowerSource, + pwr_source, + NULL); +} + +int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint16_t level, + uint32_t *value) +{ + int ret = 0, clk_id = 0; + uint32_t param; + + if (!value) + return -EINVAL; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetDpmFreqByIndex, + param, + value); + if (ret) + return ret; + + /* + * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM + * now, we un-support it + */ + *value = *value & 0x7fffffff; + + return ret; +} + +int smu_v13_0_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + return smu_v13_0_get_dpm_freq_by_index(smu, + clk_type, + 0xff, + value); +} + +int smu_v13_0_set_single_dpm_table(struct smu_context *smu, + enum smu_clk_type clk_type, + struct smu_13_0_dpm_table *single_dpm_table) +{ + int ret = 0; + uint32_t clk; + int i; + + ret = smu_v13_0_get_dpm_level_count(smu, + clk_type, + &single_dpm_table->count); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) { + ret = smu_v13_0_get_dpm_freq_by_index(smu, + clk_type, + i, + &clk); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); + return ret; + } + + single_dpm_table->dpm_levels[i].value = clk; + single_dpm_table->dpm_levels[i].enabled = true; + + if (i == 0) + single_dpm_table->min = clk; + else if (i == single_dpm_table->count - 1) + single_dpm_table->max = clk; + } + + return 0; +} + +int smu_v13_0_get_dpm_level_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min_value, + uint32_t *max_value) +{ + uint32_t level_count = 0; + int ret = 0; + + if (!min_value && !max_value) + return -EINVAL; + + if (min_value) { + /* by default, level 0 clock value as min value */ + ret = smu_v13_0_get_dpm_freq_by_index(smu, + clk_type, + 0, + min_value); + if (ret) + return ret; + } + + if (max_value) { + ret = smu_v13_0_get_dpm_level_count(smu, + clk_type, + &level_count); + if (ret) + return ret; + + ret = smu_v13_0_get_dpm_freq_by_index(smu, + clk_type, + level_count - 1, + max_value); + if (ret) + return ret; + } + + return ret; +} + +int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & + PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) + >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; +} + +int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu) +{ + uint32_t width_level; + + width_level = smu_v13_0_get_current_pcie_link_width_level(smu); + if (width_level > LINK_WIDTH_MAX) + width_level = 0; + + return link_width[width_level]; +} + +int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & + PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) + >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; +} + +int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) +{ + uint32_t speed_level; + + speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu); + if (speed_level > LINK_SPEED_MAX) + speed_level = 0; + + return link_speed[speed_level]; +} + diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index bcedd4d92e356c172fa1d6c00d37b8fe4ce8b97f..4b45953b36d813ac7cae97b5ff6d0a687faeeda6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -73,7 +73,7 @@ static void smu_cmn_read_arg(struct smu_context *smu, { struct amdgpu_device *adev = smu->adev; - *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82); + *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); } static int smu_cmn_wait_for_response(struct smu_context *smu) @@ -82,7 +82,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu) uint32_t cur_value, i, timeout = adev->usec_timeout * 10; for (i = 0; i < timeout; i++) { - cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90); + cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) return cur_value; @@ -93,7 +93,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu) if (i == timeout) return -ETIME; - return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90); + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); } int smu_cmn_send_msg_without_waiting(struct smu_context *smu, @@ -111,9 +111,9 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu, return ret; } - WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); - WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param); - WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); return 0; } @@ -758,9 +758,15 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) case METRICS_VERSION(1, 0): structure_size = sizeof(struct gpu_metrics_v1_0); break; + case METRICS_VERSION(1, 1): + structure_size = sizeof(struct gpu_metrics_v1_1); + break; case METRICS_VERSION(2, 0): structure_size = sizeof(struct gpu_metrics_v2_0); break; + case METRICS_VERSION(2, 1): + structure_size = sizeof(struct gpu_metrics_v2_1); + break; default: return; } diff --git a/drivers/gpu/drm/arc/Kconfig b/drivers/gpu/drm/arc/Kconfig deleted file mode 100644 index e8f3d63e0b914a86653da842780f632480f5a5d8..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config DRM_ARCPGU - tristate "ARC PGU" - depends on DRM && OF - select DRM_KMS_CMA_HELPER - select DRM_KMS_HELPER - help - Choose this option if you have an ARC PGU controller. - - If M is selected the module will be called arcpgu. diff --git a/drivers/gpu/drm/arc/Makefile b/drivers/gpu/drm/arc/Makefile deleted file mode 100644 index c7028b7427b3de94b704d5ad76a41f0e5c9ca476..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -arcpgu-y := arcpgu_crtc.o arcpgu_hdmi.o arcpgu_sim.o arcpgu_drv.o -obj-$(CONFIG_DRM_ARCPGU) += arcpgu.o diff --git a/drivers/gpu/drm/arc/arcpgu.h b/drivers/gpu/drm/arc/arcpgu.h deleted file mode 100644 index 6aac44b953ad1cc271158e1a85eeba8ba3d07985..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#ifndef _ARCPGU_H_ -#define _ARCPGU_H_ - -struct arcpgu_drm_private { - void __iomem *regs; - struct clk *clk; - struct drm_framebuffer *fb; - struct drm_crtc crtc; - struct drm_plane *plane; -}; - -#define crtc_to_arcpgu_priv(x) container_of(x, struct arcpgu_drm_private, crtc) - -static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu, - unsigned int reg, u32 value) -{ - iowrite32(value, arcpgu->regs + reg); -} - -static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu, - unsigned int reg) -{ - return ioread32(arcpgu->regs + reg); -} - -int arc_pgu_setup_crtc(struct drm_device *dev); -int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np); -int arcpgu_drm_sim_init(struct drm_device *drm, struct device_node *np); - -#endif diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c deleted file mode 100644 index 895cdd991af688b6aa5482adadfc3f05387efd4f..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu_crtc.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arcpgu.h" -#include "arcpgu_regs.h" - -#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1)) - -static const u32 arc_pgu_supported_formats[] = { - DRM_FORMAT_RGB565, - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, -}; - -static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc) -{ - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - const struct drm_framebuffer *fb = crtc->primary->state->fb; - uint32_t pixel_format = fb->format->format; - u32 format = DRM_FORMAT_INVALID; - int i; - u32 reg_ctrl; - - for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) { - if (arc_pgu_supported_formats[i] == pixel_format) - format = arc_pgu_supported_formats[i]; - } - - if (WARN_ON(format == DRM_FORMAT_INVALID)) - return; - - reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); - if (format == DRM_FORMAT_RGB565) - reg_ctrl &= ~ARCPGU_MODE_XRGB8888; - else - reg_ctrl |= ARCPGU_MODE_XRGB8888; - arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl); -} - -static const struct drm_crtc_funcs arc_pgu_crtc_funcs = { - .destroy = drm_crtc_cleanup, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .reset = drm_atomic_helper_crtc_reset, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, -}; - -static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc, - const struct drm_display_mode *mode) -{ - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - long rate, clk_rate = mode->clock * 1000; - long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */ - - rate = clk_round_rate(arcpgu->clk, clk_rate); - if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0)) - return MODE_OK; - - return MODE_NOCLOCK; -} - -static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc) -{ - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - struct drm_display_mode *m = &crtc->state->adjusted_mode; - u32 val; - - arc_pgu_write(arcpgu, ARCPGU_REG_FMT, - ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal)); - - arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC, - ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay, - m->crtc_hsync_end - m->crtc_hdisplay)); - - arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC, - ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay, - m->crtc_vsync_end - m->crtc_vdisplay)); - - arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE, - ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start, - m->crtc_vblank_end - m->crtc_vblank_start)); - - val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); - - if (m->flags & DRM_MODE_FLAG_PVSYNC) - val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST; - else - val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST); - - if (m->flags & DRM_MODE_FLAG_PHSYNC) - val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST; - else - val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST); - - arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val); - arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); - arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); - - arc_pgu_set_pxl_fmt(crtc); - - clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); -} - -static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - - clk_prepare_enable(arcpgu->clk); - arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, - arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | - ARCPGU_CTRL_ENABLE_MASK); -} - -static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - - clk_disable_unprepare(arcpgu->clk); - arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, - arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) & - ~ARCPGU_CTRL_ENABLE_MASK); -} - -static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = { - .mode_valid = arc_pgu_crtc_mode_valid, - .mode_set_nofb = arc_pgu_crtc_mode_set_nofb, - .atomic_enable = arc_pgu_crtc_atomic_enable, - .atomic_disable = arc_pgu_crtc_atomic_disable, -}; - -static void arc_pgu_plane_atomic_update(struct drm_plane *plane, - struct drm_plane_state *state) -{ - struct arcpgu_drm_private *arcpgu; - struct drm_gem_cma_object *gem; - - if (!plane->state->crtc || !plane->state->fb) - return; - - arcpgu = crtc_to_arcpgu_priv(plane->state->crtc); - gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0); - arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); -} - -static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = { - .atomic_update = arc_pgu_plane_atomic_update, -}; - -static const struct drm_plane_funcs arc_pgu_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, - .reset = drm_atomic_helper_plane_reset, - .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -}; - -static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm) -{ - struct arcpgu_drm_private *arcpgu = drm->dev_private; - struct drm_plane *plane = NULL; - int ret; - - plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); - if (!plane) - return ERR_PTR(-ENOMEM); - - ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs, - arc_pgu_supported_formats, - ARRAY_SIZE(arc_pgu_supported_formats), - NULL, - DRM_PLANE_TYPE_PRIMARY, NULL); - if (ret) - return ERR_PTR(ret); - - drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs); - arcpgu->plane = plane; - - return plane; -} - -int arc_pgu_setup_crtc(struct drm_device *drm) -{ - struct arcpgu_drm_private *arcpgu = drm->dev_private; - struct drm_plane *primary; - int ret; - - primary = arc_pgu_plane_init(drm); - if (IS_ERR(primary)) - return PTR_ERR(primary); - - ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL, - &arc_pgu_crtc_funcs, NULL); - if (ret) { - drm_plane_cleanup(primary); - return ret; - } - - drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs); - return 0; -} diff --git a/drivers/gpu/drm/arc/arcpgu_drv.c b/drivers/gpu/drm/arc/arcpgu_drv.c deleted file mode 100644 index 077d006b1fbf50f9488203969d0fab5c8a9498b5..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu_drv.c +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arcpgu.h" -#include "arcpgu_regs.h" - -static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { - .fb_create = drm_gem_fb_create, - .atomic_check = drm_atomic_helper_check, - .atomic_commit = drm_atomic_helper_commit, -}; - -static void arcpgu_setup_mode_config(struct drm_device *drm) -{ - drm_mode_config_init(drm); - drm->mode_config.min_width = 0; - drm->mode_config.min_height = 0; - drm->mode_config.max_width = 1920; - drm->mode_config.max_height = 1080; - drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; -} - -DEFINE_DRM_GEM_CMA_FOPS(arcpgu_drm_ops); - -static int arcpgu_load(struct drm_device *drm) -{ - struct platform_device *pdev = to_platform_device(drm->dev); - struct arcpgu_drm_private *arcpgu; - struct device_node *encoder_node = NULL, *endpoint_node = NULL; - struct resource *res; - int ret; - - arcpgu = devm_kzalloc(&pdev->dev, sizeof(*arcpgu), GFP_KERNEL); - if (arcpgu == NULL) - return -ENOMEM; - - drm->dev_private = arcpgu; - - arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); - if (IS_ERR(arcpgu->clk)) - return PTR_ERR(arcpgu->clk); - - arcpgu_setup_mode_config(drm); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - arcpgu->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(arcpgu->regs)) - return PTR_ERR(arcpgu->regs); - - dev_info(drm->dev, "arc_pgu ID: 0x%x\n", - arc_pgu_read(arcpgu, ARCPGU_REG_ID)); - - /* Get the optional framebuffer memory resource */ - ret = of_reserved_mem_device_init(drm->dev); - if (ret && ret != -ENODEV) - return ret; - - if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) - return -ENODEV; - - if (arc_pgu_setup_crtc(drm) < 0) - return -ENODEV; - - /* - * There is only one output port inside each device. It is linked with - * encoder endpoint. - */ - endpoint_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL); - if (endpoint_node) { - encoder_node = of_graph_get_remote_port_parent(endpoint_node); - of_node_put(endpoint_node); - } - - if (encoder_node) { - ret = arcpgu_drm_hdmi_init(drm, encoder_node); - of_node_put(encoder_node); - if (ret < 0) - return ret; - } else { - dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation platform\n"); - ret = arcpgu_drm_sim_init(drm, NULL); - if (ret < 0) - return ret; - } - - drm_mode_config_reset(drm); - drm_kms_helper_poll_init(drm); - - platform_set_drvdata(pdev, drm); - return 0; -} - -static int arcpgu_unload(struct drm_device *drm) -{ - drm_kms_helper_poll_fini(drm); - drm_atomic_helper_shutdown(drm); - drm_mode_config_cleanup(drm); - - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static int arcpgu_show_pxlclock(struct seq_file *m, void *arg) -{ - struct drm_info_node *node = (struct drm_info_node *)m->private; - struct drm_device *drm = node->minor->dev; - struct arcpgu_drm_private *arcpgu = drm->dev_private; - unsigned long clkrate = clk_get_rate(arcpgu->clk); - unsigned long mode_clock = arcpgu->crtc.mode.crtc_clock * 1000; - - seq_printf(m, "hw : %lu\n", clkrate); - seq_printf(m, "mode: %lu\n", mode_clock); - return 0; -} - -static struct drm_info_list arcpgu_debugfs_list[] = { - { "clocks", arcpgu_show_pxlclock, 0 }, -}; - -static void arcpgu_debugfs_init(struct drm_minor *minor) -{ - drm_debugfs_create_files(arcpgu_debugfs_list, - ARRAY_SIZE(arcpgu_debugfs_list), - minor->debugfs_root, minor); -} -#endif - -static const struct drm_driver arcpgu_drm_driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, - .name = "arcpgu", - .desc = "ARC PGU Controller", - .date = "20160219", - .major = 1, - .minor = 0, - .patchlevel = 0, - .fops = &arcpgu_drm_ops, - DRM_GEM_CMA_DRIVER_OPS, -#ifdef CONFIG_DEBUG_FS - .debugfs_init = arcpgu_debugfs_init, -#endif -}; - -static int arcpgu_probe(struct platform_device *pdev) -{ - struct drm_device *drm; - int ret; - - drm = drm_dev_alloc(&arcpgu_drm_driver, &pdev->dev); - if (IS_ERR(drm)) - return PTR_ERR(drm); - - ret = arcpgu_load(drm); - if (ret) - goto err_unref; - - ret = drm_dev_register(drm, 0); - if (ret) - goto err_unload; - - drm_fbdev_generic_setup(drm, 16); - - return 0; - -err_unload: - arcpgu_unload(drm); - -err_unref: - drm_dev_put(drm); - - return ret; -} - -static int arcpgu_remove(struct platform_device *pdev) -{ - struct drm_device *drm = platform_get_drvdata(pdev); - - drm_dev_unregister(drm); - arcpgu_unload(drm); - drm_dev_put(drm); - - return 0; -} - -static const struct of_device_id arcpgu_of_table[] = { - {.compatible = "snps,arcpgu"}, - {} -}; - -MODULE_DEVICE_TABLE(of, arcpgu_of_table); - -static struct platform_driver arcpgu_platform_driver = { - .probe = arcpgu_probe, - .remove = arcpgu_remove, - .driver = { - .name = "arcpgu", - .of_match_table = arcpgu_of_table, - }, -}; - -module_platform_driver(arcpgu_platform_driver); - -MODULE_AUTHOR("Carlos Palminha "); -MODULE_DESCRIPTION("ARC PGU DRM driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/arc/arcpgu_hdmi.c b/drivers/gpu/drm/arc/arcpgu_hdmi.c deleted file mode 100644 index 52839934f2fb52304d92a63fe0670a8e2f2f1e1a..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu_hdmi.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#include -#include -#include -#include - -#include "arcpgu.h" - -static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = { - .destroy = drm_encoder_cleanup, -}; - -int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np) -{ - struct drm_encoder *encoder; - struct drm_bridge *bridge; - - int ret = 0; - - encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); - if (encoder == NULL) - return -ENOMEM; - - /* Locate drm bridge from the hdmi encoder DT node */ - bridge = of_drm_find_bridge(np); - if (!bridge) - return -EPROBE_DEFER; - - encoder->possible_crtcs = 1; - encoder->possible_clones = 0; - ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, - DRM_MODE_ENCODER_TMDS, NULL); - if (ret) - return ret; - - /* Link drm_bridge to encoder */ - ret = drm_bridge_attach(encoder, bridge, NULL, 0); - if (ret) - drm_encoder_cleanup(encoder); - - return ret; -} diff --git a/drivers/gpu/drm/arc/arcpgu_regs.h b/drivers/gpu/drm/arc/arcpgu_regs.h deleted file mode 100644 index b689a382d556ca42ac313c1c1e463c882b648083..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu_regs.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#ifndef _ARC_PGU_REGS_H_ -#define _ARC_PGU_REGS_H_ - -#define ARCPGU_REG_CTRL 0x00 -#define ARCPGU_REG_STAT 0x04 -#define ARCPGU_REG_FMT 0x10 -#define ARCPGU_REG_HSYNC 0x14 -#define ARCPGU_REG_VSYNC 0x18 -#define ARCPGU_REG_ACTIVE 0x1c -#define ARCPGU_REG_BUF0_ADDR 0x40 -#define ARCPGU_REG_STRIDE 0x50 -#define ARCPGU_REG_START_SET 0x84 - -#define ARCPGU_REG_ID 0x3FC - -#define ARCPGU_CTRL_ENABLE_MASK 0x02 -#define ARCPGU_CTRL_VS_POL_MASK 0x1 -#define ARCPGU_CTRL_VS_POL_OFST 0x3 -#define ARCPGU_CTRL_HS_POL_MASK 0x1 -#define ARCPGU_CTRL_HS_POL_OFST 0x4 -#define ARCPGU_MODE_XRGB8888 BIT(2) -#define ARCPGU_STAT_BUSY_MASK 0x02 - -#endif diff --git a/drivers/gpu/drm/arc/arcpgu_sim.c b/drivers/gpu/drm/arc/arcpgu_sim.c deleted file mode 100644 index 37d961668dfec9e5fb9a156208190d1f38202730..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/arc/arcpgu_sim.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ARC PGU DRM driver. - * - * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) - */ - -#include -#include -#include - -#include "arcpgu.h" - -#define XRES_DEF 640 -#define YRES_DEF 480 - -#define XRES_MAX 8192 -#define YRES_MAX 8192 - - -struct arcpgu_drm_connector { - struct drm_connector connector; -}; - -static int arcpgu_drm_connector_get_modes(struct drm_connector *connector) -{ - int count; - - count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX); - drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); - return count; -} - -static void arcpgu_drm_connector_destroy(struct drm_connector *connector) -{ - drm_connector_unregister(connector); - drm_connector_cleanup(connector); -} - -static const struct drm_connector_helper_funcs -arcpgu_drm_connector_helper_funcs = { - .get_modes = arcpgu_drm_connector_get_modes, -}; - -static const struct drm_connector_funcs arcpgu_drm_connector_funcs = { - .reset = drm_atomic_helper_connector_reset, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = arcpgu_drm_connector_destroy, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = { - .destroy = drm_encoder_cleanup, -}; - -int arcpgu_drm_sim_init(struct drm_device *drm, struct device_node *np) -{ - struct arcpgu_drm_connector *arcpgu_connector; - struct drm_encoder *encoder; - struct drm_connector *connector; - int ret; - - encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); - if (encoder == NULL) - return -ENOMEM; - - encoder->possible_crtcs = 1; - encoder->possible_clones = 0; - - ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, - DRM_MODE_ENCODER_VIRTUAL, NULL); - if (ret) - return ret; - - arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector), - GFP_KERNEL); - if (!arcpgu_connector) { - ret = -ENOMEM; - goto error_encoder_cleanup; - } - - connector = &arcpgu_connector->connector; - drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs); - - ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, - DRM_MODE_CONNECTOR_VIRTUAL); - if (ret < 0) { - dev_err(drm->dev, "failed to initialize drm connector\n"); - goto error_encoder_cleanup; - } - - ret = drm_connector_attach_encoder(connector, encoder); - if (ret < 0) { - dev_err(drm->dev, "could not attach connector to encoder\n"); - drm_connector_unregister(connector); - goto error_connector_cleanup; - } - - return 0; - -error_connector_cleanup: - drm_connector_cleanup(connector); - -error_encoder_cleanup: - drm_encoder_cleanup(encoder); - return ret; -} diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h b/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h index 32273cf18f7c55e53f9d7ee37c9e42eb2238ea63..cf7a183f773d012a107f3a0f61aaa5baf286077a 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h @@ -82,17 +82,6 @@ struct komeda_format_caps_table { extern u64 komeda_supported_modifiers[]; -static inline const char *komeda_get_format_name(u32 fourcc, u64 modifier) -{ - struct drm_format_name_buf buf; - static char name[64]; - - snprintf(name, sizeof(name), "%s with modifier: 0x%llx.", - drm_get_format_name(fourcc, &buf), modifier); - - return name; -} - const struct komeda_format_caps * komeda_get_format_caps(struct komeda_format_caps_table *table, u32 fourcc, u64 modifier); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c index 170f9dc8ec19c4a292c8cc64313fb661272f1f0f..3c372d2deb0a697bbb4a20287ba3a48c4e74f29d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c @@ -276,8 +276,8 @@ bool komeda_fb_is_layer_supported(struct komeda_fb *kfb, u32 layer_type, supported = komeda_format_mod_supported(&mdev->fmt_tbl, layer_type, fourcc, modifier, rot); if (!supported) - DRM_DEBUG_ATOMIC("Layer TYPE: %d doesn't support fb FMT: %s.\n", - layer_type, komeda_get_format_name(fourcc, modifier)); + DRM_DEBUG_ATOMIC("Layer TYPE: %d doesn't support fb FMT: %p4cc with modifier: 0x%llx.\n", + layer_type, &fourcc, modifier); return supported; } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c index 034ee08482e0f38d4a3b70b327347b69a2c2808e..aeda4e5ec4f48368e5d3aa24a6b1131553c4e09f 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c @@ -73,6 +73,7 @@ static const struct drm_driver komeda_kms_driver = { static void komeda_kms_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; + bool fence_cookie = dma_fence_begin_signalling(); drm_atomic_helper_commit_modeset_disables(dev, old_state); @@ -85,6 +86,8 @@ static void komeda_kms_commit_tail(struct drm_atomic_state *old_state) drm_atomic_helper_wait_for_flip_done(dev, old_state); + dma_fence_end_signalling(fence_cookie); + drm_atomic_helper_cleanup_planes(dev, old_state); } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 98e915e325ddffad2d9f47ea8b675f62c153c213..d63d83800a8a3876679d6d6641a349b60f68945e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -49,10 +49,8 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, dflow->rot = drm_rotation_simplify(st->rotation, caps->supported_rots); if (!has_bits(dflow->rot, caps->supported_rots)) { - DRM_DEBUG_ATOMIC("rotation(0x%x) isn't supported by %s.\n", - dflow->rot, - komeda_get_format_name(caps->fourcc, - fb->modifier)); + DRM_DEBUG_ATOMIC("rotation(0x%x) isn't supported by %p4cc with modifier: 0x%llx.\n", + dflow->rot, &caps->fourcc, fb->modifier); return -EINVAL; } @@ -71,20 +69,23 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, */ static int komeda_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); struct komeda_plane *kplane = to_kplane(plane); - struct komeda_plane_state *kplane_st = to_kplane_st(state); + struct komeda_plane_state *kplane_st = to_kplane_st(new_plane_state); struct komeda_layer *layer = kplane->layer; struct drm_crtc_state *crtc_st; struct komeda_crtc_state *kcrtc_st; struct komeda_data_flow_cfg dflow; int err; - if (!state->crtc || !state->fb) + if (!new_plane_state->crtc || !new_plane_state->fb) return 0; - crtc_st = drm_atomic_get_crtc_state(state->state, state->crtc); + crtc_st = drm_atomic_get_crtc_state(state, + new_plane_state->crtc); if (IS_ERR(crtc_st) || !crtc_st->enable) { DRM_DEBUG_ATOMIC("Cannot update plane on a disabled CRTC.\n"); return -EINVAL; @@ -96,7 +97,7 @@ komeda_plane_atomic_check(struct drm_plane *plane, kcrtc_st = to_kcrtc_st(crtc_st); - err = komeda_plane_init_data_flow(state, kcrtc_st, &dflow); + err = komeda_plane_init_data_flow(new_plane_state, kcrtc_st, &dflow); if (err) return err; @@ -115,7 +116,7 @@ komeda_plane_atomic_check(struct drm_plane *plane, */ static void komeda_plane_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { } diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index a3234bfb09173bece770982908a5f2ff35b9ff40..7adb065169e974966c756feaac4fe70c0d4a1eb4 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -229,12 +229,14 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { }; static int hdlcd_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); int i; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; - u32 src_h = state->src_h >> 16; + u32 src_h = new_plane_state->src_h >> 16; /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */ if (src_h >= HDLCD_MAX_YRES) { @@ -242,23 +244,27 @@ static int hdlcd_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } - for_each_new_crtc_in_state(state->state, crtc, crtc_state, i) { + for_each_new_crtc_in_state(state, crtc, crtc_state, + i) { /* we cannot disable the plane while the CRTC is active */ - if (!state->fb && crtc_state->active) + if (!new_plane_state->fb && crtc_state->active) return -EINVAL; - return drm_atomic_helper_check_plane_state(state, crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, - false, true); + return drm_atomic_helper_check_plane_state(new_plane_state, + crtc_state, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + false, true); } return 0; } static void hdlcd_plane_atomic_update(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { - struct drm_framebuffer *fb = plane->state->fb; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + struct drm_framebuffer *fb = new_plane_state->fb; struct hdlcd_drm_private *hdlcd; u32 dest_h; dma_addr_t scanout_start; @@ -266,8 +272,8 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, if (!fb) return; - dest_h = drm_rect_height(&plane->state->dst); - scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dest_h = drm_rect_height(&new_plane_state->dst); + scanout_start = drm_fb_cma_get_gem_addr(fb, new_plane_state, 0); hdlcd = plane->dev->dev_private; hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index fceda010d65a1fa1fc88db24f163179ef8ba6873..d83c7366b348ba7faa7949bcc5f185266644dfe6 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -234,6 +234,7 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; int i; + bool fence_cookie = dma_fence_begin_signalling(); pm_runtime_get_sync(drm->dev); @@ -260,6 +261,8 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) malidp_atomic_commit_hw_done(state); + dma_fence_end_signalling(fence_cookie); + pm_runtime_put(drm->dev); drm_atomic_helper_cleanup_planes(drm, state); diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c index 7d0e7b031e447f24a83e9197d92879754eab4169..f5847a79dd7e8712c28e4060709207faf4e358ca 100644 --- a/drivers/gpu/drm/arm/malidp_mw.c +++ b/drivers/gpu/drm/arm/malidp_mw.c @@ -151,11 +151,8 @@ malidp_mw_encoder_atomic_check(struct drm_encoder *encoder, malidp_hw_get_format_id(&malidp->dev->hw->map, SE_MEMWRITE, fb->format->format, !!fb->modifier); if (mw_state->format == MALIDP_INVALID_FORMAT_ID) { - struct drm_format_name_buf format_name; - - DRM_DEBUG_KMS("Invalid pixel format %s\n", - drm_get_format_name(fb->format->format, - &format_name)); + DRM_DEBUG_KMS("Invalid pixel format %p4cc\n", + &fb->format->format); return -EINVAL; } diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 351a85088d0ecc4b9f02183066bc97546edd5530..ddbba67f0283a815674523c80475ee430f98f08f 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -502,20 +502,22 @@ static void malidp_de_prefetch_settings(struct malidp_plane *mp, } static int malidp_de_plane_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); struct malidp_plane *mp = to_malidp_plane(plane); - struct malidp_plane_state *ms = to_malidp_plane_state(state); - bool rotated = state->rotation & MALIDP_ROTATED_MASK; + struct malidp_plane_state *ms = to_malidp_plane_state(new_plane_state); + bool rotated = new_plane_state->rotation & MALIDP_ROTATED_MASK; struct drm_framebuffer *fb; - u16 pixel_alpha = state->pixel_blend_mode; + u16 pixel_alpha = new_plane_state->pixel_blend_mode; int i, ret; unsigned int block_w, block_h; - if (!state->crtc || WARN_ON(!state->fb)) + if (!new_plane_state->crtc || WARN_ON(!new_plane_state->fb)) return 0; - fb = state->fb; + fb = new_plane_state->fb; ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, mp->layer->id, fb->format->format, @@ -541,15 +543,15 @@ static int malidp_de_plane_check(struct drm_plane *plane, DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); return -EINVAL; } - if ((state->src_x >> 16) % block_w || (state->src_y >> 16) % block_h) { + if ((new_plane_state->src_x >> 16) % block_w || (new_plane_state->src_y >> 16) % block_h) { DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); return -EINVAL; } - if ((state->crtc_w > mp->hwdev->max_line_size) || - (state->crtc_h > mp->hwdev->max_line_size) || - (state->crtc_w < mp->hwdev->min_line_size) || - (state->crtc_h < mp->hwdev->min_line_size)) + if ((new_plane_state->crtc_w > mp->hwdev->max_line_size) || + (new_plane_state->crtc_h > mp->hwdev->max_line_size) || + (new_plane_state->crtc_w < mp->hwdev->min_line_size) || + (new_plane_state->crtc_h < mp->hwdev->min_line_size)) return -EINVAL; /* @@ -559,15 +561,15 @@ static int malidp_de_plane_check(struct drm_plane *plane, */ if (ms->n_planes == 3 && !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && - (state->fb->pitches[1] != state->fb->pitches[2])) + (new_plane_state->fb->pitches[1] != new_plane_state->fb->pitches[2])) return -EINVAL; - ret = malidp_se_check_scaling(mp, state); + ret = malidp_se_check_scaling(mp, new_plane_state); if (ret) return ret; /* validate the rotation constraints for each layer */ - if (state->rotation != DRM_MODE_ROTATE_0) { + if (new_plane_state->rotation != DRM_MODE_ROTATE_0) { if (mp->layer->rot == ROTATE_NONE) return -EINVAL; if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) @@ -588,11 +590,11 @@ static int malidp_de_plane_check(struct drm_plane *plane, } ms->rotmem_size = 0; - if (state->rotation & MALIDP_ROTATED_MASK) { + if (new_plane_state->rotation & MALIDP_ROTATED_MASK) { int val; - val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, - state->crtc_h, + val = mp->hwdev->hw->rotmem_required(mp->hwdev, new_plane_state->crtc_w, + new_plane_state->crtc_h, fb->format->format, !!(fb->modifier)); if (val < 0) @@ -602,7 +604,7 @@ static int malidp_de_plane_check(struct drm_plane *plane, } /* HW can't support plane + pixel blending */ - if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) && + if ((new_plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE) && (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && fb->format->has_alpha) return -EINVAL; @@ -789,13 +791,16 @@ static void malidp_de_set_plane_afbc(struct drm_plane *plane) } static void malidp_de_plane_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct malidp_plane *mp; struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); - struct drm_plane_state *state = plane->state; - u16 pixel_alpha = state->pixel_blend_mode; - u8 plane_alpha = state->alpha >> 8; + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); + u16 pixel_alpha = new_state->pixel_blend_mode; + u8 plane_alpha = new_state->alpha >> 8; u32 src_w, src_h, dest_w, dest_h, val; int i; struct drm_framebuffer *fb = plane->state->fb; @@ -811,12 +816,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, src_h = fb->height; } else { /* convert src values from Q16 fixed point to integer */ - src_w = state->src_w >> 16; - src_h = state->src_h >> 16; + src_w = new_state->src_w >> 16; + src_h = new_state->src_h >> 16; } - dest_w = state->crtc_w; - dest_h = state->crtc_h; + dest_w = new_state->crtc_w; + dest_h = new_state->crtc_h; val = malidp_hw_read(mp->hwdev, mp->layer->base); val = (val & ~LAYER_FORMAT_MASK) | ms->format; @@ -828,7 +833,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, malidp_de_set_mmu_control(mp, ms); malidp_de_set_plane_pitches(mp, ms->n_planes, - state->fb->pitches); + new_state->fb->pitches); if ((plane->state->color_encoding != old_state->color_encoding) || (plane->state->color_range != old_state->color_range)) @@ -841,8 +846,8 @@ static void malidp_de_plane_update(struct drm_plane *plane, malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), mp->layer->base + MALIDP_LAYER_COMP_SIZE); - malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | - LAYER_V_VAL(state->crtc_y), + malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) | + LAYER_V_VAL(new_state->crtc_y), mp->layer->base + MALIDP_LAYER_OFFSET); if (mp->layer->id == DE_SMART) { @@ -864,19 +869,19 @@ static void malidp_de_plane_update(struct drm_plane *plane, val &= ~LAYER_ROT_MASK; /* setup the rotation and axis flip bits */ - if (state->rotation & DRM_MODE_ROTATE_MASK) + if (new_state->rotation & DRM_MODE_ROTATE_MASK) val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << LAYER_ROT_OFFSET; - if (state->rotation & DRM_MODE_REFLECT_X) + if (new_state->rotation & DRM_MODE_REFLECT_X) val |= LAYER_H_FLIP; - if (state->rotation & DRM_MODE_REFLECT_Y) + if (new_state->rotation & DRM_MODE_REFLECT_Y) val |= LAYER_V_FLIP; val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); - if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) { + if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) { val |= LAYER_COMP_PLANE; - } else if (state->fb->format->has_alpha) { + } else if (new_state->fb->format->has_alpha) { /* We only care about blend mode if the format has alpha */ switch (pixel_alpha) { case DRM_MODE_BLEND_PREMULTI: @@ -890,9 +895,9 @@ static void malidp_de_plane_update(struct drm_plane *plane, val |= LAYER_ALPHA(plane_alpha); val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); - if (state->crtc) { + if (new_state->crtc) { struct malidp_crtc_state *m = - to_malidp_crtc_state(state->crtc->state); + to_malidp_crtc_state(new_state->crtc->state); if (m->scaler_config.scale_enable && m->scaler_config.plane_src_id == mp->layer->id) @@ -907,7 +912,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, } static void malidp_de_plane_disable(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { struct malidp_plane *mp = to_malidp_plane(plane); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 6346b890279a055f695400489a702fb02658a51a..d3e3e5fdc39046442b0791bf8a045045887960b7 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -66,9 +66,12 @@ static inline u32 armada_csc(struct drm_plane_state *state) /* === Plane support === */ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { - struct drm_plane_state *state = plane->state; + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); struct armada_crtc *dcrtc; struct armada_regs *regs; unsigned int idx; @@ -76,62 +79,64 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); - if (!state->fb || WARN_ON(!state->crtc)) + if (!new_state->fb || WARN_ON(!new_state->crtc)) return; DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", plane->base.id, plane->name, - state->crtc->base.id, state->crtc->name, - state->fb->base.id, - old_state->visible, state->visible); + new_state->crtc->base.id, new_state->crtc->name, + new_state->fb->base.id, + old_state->visible, new_state->visible); - dcrtc = drm_to_armada_crtc(state->crtc); + dcrtc = drm_to_armada_crtc(new_state->crtc); regs = dcrtc->regs + dcrtc->regs_idx; idx = 0; - if (!old_state->visible && state->visible) + if (!old_state->visible && new_state->visible) armada_reg_queue_mod(regs, idx, 0, CFG_PDWN16x66 | CFG_PDWN32x66, LCD_SPU_SRAM_PARA1); - val = armada_src_hw(state); + val = armada_src_hw(new_state); if (armada_src_hw(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); - val = armada_dst_yx(state); + val = armada_dst_yx(new_state); if (armada_dst_yx(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); - val = armada_dst_hw(state); + val = armada_dst_hw(new_state); if (armada_dst_hw(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); /* FIXME: overlay on an interlaced display */ - if (old_state->src.x1 != state->src.x1 || - old_state->src.y1 != state->src.y1 || - old_state->fb != state->fb || - state->crtc->state->mode_changed) { + if (old_state->src.x1 != new_state->src.x1 || + old_state->src.y1 != new_state->src.y1 || + old_state->fb != new_state->fb || + new_state->crtc->state->mode_changed) { const struct drm_format_info *format; u16 src_x; - armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0), LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1), LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2), LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0), LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1), LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2), LCD_SPU_DMA_START_ADDR_V1); - val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0); + val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state, + 0); armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); - val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2); + val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state, + 2); armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); - cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | - CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) | + cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) | + CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) | CFG_CBSH_ENA; - if (state->visible) + if (new_state->visible) cfg |= CFG_DMA_ENA; /* @@ -139,28 +144,28 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, * U/V planes to swap. Compensate for it by also toggling * the UV swap. */ - format = state->fb->format; - src_x = state->src.x1 >> 16; + format = new_state->fb->format; + src_x = new_state->src.x1 >> 16; if (format->num_planes == 1 && src_x & (format->hsub - 1)) cfg ^= CFG_DMA_MOD(CFG_SWAPUV); - if (to_armada_plane_state(state)->interlace) + if (to_armada_plane_state(new_state)->interlace) cfg |= CFG_DMA_FTOGGLE; cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU | CFG_YUV2RGB) | CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE | CFG_DMA_ENA; - } else if (old_state->visible != state->visible) { - cfg = state->visible ? CFG_DMA_ENA : 0; + } else if (old_state->visible != new_state->visible) { + cfg = new_state->visible ? CFG_DMA_ENA : 0; cfg_mask = CFG_DMA_ENA; } else { cfg = cfg_mask = 0; } - if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || - drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { + if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) || + drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) { cfg_mask |= CFG_DMA_HSMOOTH; - if (drm_rect_width(&state->src) >> 16 != - drm_rect_width(&state->dst)) + if (drm_rect_width(&new_state->src) >> 16 != + drm_rect_width(&new_state->dst)) cfg |= CFG_DMA_HSMOOTH; } @@ -168,41 +173,41 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, armada_reg_queue_mod(regs, idx, cfg, cfg_mask, LCD_SPU_DMA_CTRL0); - val = armada_spu_contrast(state); - if ((!old_state->visible && state->visible) || + val = armada_spu_contrast(new_state); + if ((!old_state->visible && new_state->visible) || armada_spu_contrast(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); - val = armada_spu_saturation(state); - if ((!old_state->visible && state->visible) || + val = armada_spu_saturation(new_state); + if ((!old_state->visible && new_state->visible) || armada_spu_saturation(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); - if (!old_state->visible && state->visible) + if (!old_state->visible && new_state->visible) armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE); - val = armada_csc(state); - if ((!old_state->visible && state->visible) || + val = armada_csc(new_state); + if ((!old_state->visible && new_state->visible) || armada_csc(old_state) != val) armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, LCD_SPU_IOPAD_CONTROL); - val = drm_to_overlay_state(state)->colorkey_yr; - if ((!old_state->visible && state->visible) || + val = drm_to_overlay_state(new_state)->colorkey_yr; + if ((!old_state->visible && new_state->visible) || drm_to_overlay_state(old_state)->colorkey_yr != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); - val = drm_to_overlay_state(state)->colorkey_ug; - if ((!old_state->visible && state->visible) || + val = drm_to_overlay_state(new_state)->colorkey_ug; + if ((!old_state->visible && new_state->visible) || drm_to_overlay_state(old_state)->colorkey_ug != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); - val = drm_to_overlay_state(state)->colorkey_vb; - if ((!old_state->visible && state->visible) || + val = drm_to_overlay_state(new_state)->colorkey_vb; + if ((!old_state->visible && new_state->visible) || drm_to_overlay_state(old_state)->colorkey_vb != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); - val = drm_to_overlay_state(state)->colorkey_mode; - if ((!old_state->visible && state->visible) || + val = drm_to_overlay_state(new_state)->colorkey_mode; + if ((!old_state->visible && new_state->visible) || drm_to_overlay_state(old_state)->colorkey_mode != val) armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK, LCD_SPU_DMA_CTRL1); - val = drm_to_overlay_state(state)->colorkey_enable; - if (((!old_state->visible && state->visible) || + val = drm_to_overlay_state(new_state)->colorkey_enable; + if (((!old_state->visible && new_state->visible) || drm_to_overlay_state(old_state)->colorkey_enable != val) && dcrtc->variant->has_spu_adv_reg) armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | @@ -212,8 +217,10 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct armada_crtc *dcrtc; struct armada_regs *regs; unsigned int idx = 0; diff --git a/drivers/gpu/drm/armada/armada_plane.c b/drivers/gpu/drm/armada/armada_plane.c index e7cc2b343bcb16abfac49f11b986e7d4f4d9546a..40209e49f34a84cc391639a50d3f1df2d1a5dcdd 100644 --- a/drivers/gpu/drm/armada/armada_plane.c +++ b/drivers/gpu/drm/armada/armada_plane.c @@ -106,59 +106,67 @@ void armada_drm_plane_cleanup_fb(struct drm_plane *plane, } int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { - struct armada_plane_state *st = to_armada_plane_state(state); - struct drm_crtc *crtc = state->crtc; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + struct armada_plane_state *st = to_armada_plane_state(new_plane_state); + struct drm_crtc *crtc = new_plane_state->crtc; struct drm_crtc_state *crtc_state; bool interlace; int ret; - if (!state->fb || WARN_ON(!state->crtc)) { - state->visible = false; + if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc)) { + new_plane_state->visible = false; return 0; } - if (state->state) - crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); + if (state) + crtc_state = drm_atomic_get_existing_crtc_state(state, + crtc); else crtc_state = crtc->state; - ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0, + ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + 0, INT_MAX, true, false); if (ret) return ret; interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE; if (interlace) { - if ((state->dst.y1 | state->dst.y2) & 1) + if ((new_plane_state->dst.y1 | new_plane_state->dst.y2) & 1) return -EINVAL; - st->src_hw = drm_rect_height(&state->src) >> 17; - st->dst_yx = state->dst.y1 >> 1; - st->dst_hw = drm_rect_height(&state->dst) >> 1; + st->src_hw = drm_rect_height(&new_plane_state->src) >> 17; + st->dst_yx = new_plane_state->dst.y1 >> 1; + st->dst_hw = drm_rect_height(&new_plane_state->dst) >> 1; } else { - st->src_hw = drm_rect_height(&state->src) >> 16; - st->dst_yx = state->dst.y1; - st->dst_hw = drm_rect_height(&state->dst); + st->src_hw = drm_rect_height(&new_plane_state->src) >> 16; + st->dst_yx = new_plane_state->dst.y1; + st->dst_hw = drm_rect_height(&new_plane_state->dst); } st->src_hw <<= 16; - st->src_hw |= drm_rect_width(&state->src) >> 16; + st->src_hw |= drm_rect_width(&new_plane_state->src) >> 16; st->dst_yx <<= 16; - st->dst_yx |= state->dst.x1 & 0x0000ffff; + st->dst_yx |= new_plane_state->dst.x1 & 0x0000ffff; st->dst_hw <<= 16; - st->dst_hw |= drm_rect_width(&state->dst) & 0x0000ffff; + st->dst_hw |= drm_rect_width(&new_plane_state->dst) & 0x0000ffff; - armada_drm_plane_calc(state, st->addrs, st->pitches, interlace); + armada_drm_plane_calc(new_plane_state, st->addrs, st->pitches, + interlace); st->interlace = interlace; return 0; } static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { - struct drm_plane_state *state = plane->state; + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); struct armada_crtc *dcrtc; struct armada_regs *regs; u32 cfg, cfg_mask, val; @@ -166,71 +174,72 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); - if (!state->fb || WARN_ON(!state->crtc)) + if (!new_state->fb || WARN_ON(!new_state->crtc)) return; DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", plane->base.id, plane->name, - state->crtc->base.id, state->crtc->name, - state->fb->base.id, - old_state->visible, state->visible); + new_state->crtc->base.id, new_state->crtc->name, + new_state->fb->base.id, + old_state->visible, new_state->visible); - dcrtc = drm_to_armada_crtc(state->crtc); + dcrtc = drm_to_armada_crtc(new_state->crtc); regs = dcrtc->regs + dcrtc->regs_idx; idx = 0; - if (!old_state->visible && state->visible) { + if (!old_state->visible && new_state->visible) { val = CFG_PDWN64x66; - if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420) + if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420) val |= CFG_PDWN256x24; armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1); } - val = armada_src_hw(state); + val = armada_src_hw(new_state); if (armada_src_hw(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN); - val = armada_dst_yx(state); + val = armada_dst_yx(new_state); if (armada_dst_yx(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN); - val = armada_dst_hw(state); + val = armada_dst_hw(new_state); if (armada_dst_hw(old_state) != val) armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN); - if (old_state->src.x1 != state->src.x1 || - old_state->src.y1 != state->src.y1 || - old_state->fb != state->fb || - state->crtc->state->mode_changed) { - armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0), + if (old_state->src.x1 != new_state->src.x1 || + old_state->src.y1 != new_state->src.y1 || + old_state->fb != new_state->fb || + new_state->crtc->state->mode_changed) { + armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0), LCD_CFG_GRA_START_ADDR0); - armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0), + armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0), LCD_CFG_GRA_START_ADDR1); - armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff, + armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0), + 0xffff, LCD_CFG_GRA_PITCH); } - if (old_state->fb != state->fb || - state->crtc->state->mode_changed) { - cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | - CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod); - if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420) + if (old_state->fb != new_state->fb || + new_state->crtc->state->mode_changed) { + cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) | + CFG_GRA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod); + if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420) cfg |= CFG_PALETTE_ENA; - if (state->visible) + if (new_state->visible) cfg |= CFG_GRA_ENA; - if (to_armada_plane_state(state)->interlace) + if (to_armada_plane_state(new_state)->interlace) cfg |= CFG_GRA_FTOGGLE; cfg_mask = CFG_GRAFORMAT | CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU | CFG_YUV2RGB) | CFG_PALETTE_ENA | CFG_GRA_FTOGGLE | CFG_GRA_ENA; - } else if (old_state->visible != state->visible) { - cfg = state->visible ? CFG_GRA_ENA : 0; + } else if (old_state->visible != new_state->visible) { + cfg = new_state->visible ? CFG_GRA_ENA : 0; cfg_mask = CFG_GRA_ENA; } else { cfg = cfg_mask = 0; } - if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || - drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { + if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) || + drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) { cfg_mask |= CFG_GRA_HSMOOTH; - if (drm_rect_width(&state->src) >> 16 != - drm_rect_width(&state->dst)) + if (drm_rect_width(&new_state->src) >> 16 != + drm_rect_width(&new_state->dst)) cfg |= CFG_GRA_HSMOOTH; } @@ -242,8 +251,10 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct armada_crtc *dcrtc; struct armada_regs *regs; unsigned int idx = 0; diff --git a/drivers/gpu/drm/armada/armada_plane.h b/drivers/gpu/drm/armada/armada_plane.h index 2707ec781941b3bfd04164283e5406408970c795..51dab8d8da22d86b9f67ed0f41306a8373411cdf 100644 --- a/drivers/gpu/drm/armada/armada_plane.h +++ b/drivers/gpu/drm/armada/armada_plane.h @@ -26,7 +26,7 @@ int armada_drm_plane_prepare_fb(struct drm_plane *plane, void armada_drm_plane_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state); int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state); + struct drm_atomic_state *state); void armada_plane_reset(struct drm_plane *plane); struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane); void armada_plane_destroy_state(struct drm_plane *plane, diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/aspeed_gfx.h index f1e7e56abc02dda9bdbd7169eb76bde40df9e070..96501152bafac38ff5ab99ae6bd7117b4aca52da 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h @@ -11,6 +11,11 @@ struct aspeed_gfx { struct reset_control *rst; struct regmap *scu; + u32 dac_reg; + u32 vga_scratch_reg; + u32 throd_val; + u32 scan_line_max; + struct drm_simple_display_pipe pipe; struct drm_connector connector; }; @@ -100,6 +105,3 @@ int aspeed_gfx_create_output(struct drm_device *drm); /* CRT_THROD */ #define CRT_THROD_LOW(x) (x) #define CRT_THROD_HIGH(x) ((x) << 8) - -/* Default Threshold Seting */ -#define G5_CRT_THROD_VAL (CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3C)) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c index e54686c31a90decf023d70f812a112302495bfc4..098f96d4d50d82dd2a7be340461b9329edb31013 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -9,8 +9,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -59,8 +59,8 @@ static void aspeed_gfx_enable_controller(struct aspeed_gfx *priv) u32 ctrl1 = readl(priv->base + CRT_CTRL1); u32 ctrl2 = readl(priv->base + CRT_CTRL2); - /* SCU2C: set DAC source for display output to Graphics CRT (GFX) */ - regmap_update_bits(priv->scu, 0x2c, BIT(16), BIT(16)); + /* Set DAC source for display output to Graphics CRT (GFX) */ + regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), BIT(16)); writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1); writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); @@ -74,7 +74,7 @@ static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv) writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1); writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); - regmap_update_bits(priv->scu, 0x2c, BIT(16), 0); + regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) @@ -127,7 +127,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) * Terminal Count: memory size of one scan line */ d_offset = m->hdisplay * bpp / 8; - t_count = (m->hdisplay * bpp + 127) / 128; + t_count = DIV_ROUND_UP(m->hdisplay * bpp, priv->scan_line_max); + writel(CRT_DISP_OFFSET(d_offset) | CRT_TERM_COUNT(t_count), priv->base + CRT_OFFSET); @@ -135,7 +136,7 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) * Threshold: FIFO thresholds of refill and stop (16 byte chunks * per line, rounded up) */ - writel(G5_CRT_THROD_VAL, priv->base + CRT_THROD); + writel(priv->throd_val, priv->base + CRT_THROD); } static void aspeed_gfx_pipe_enable(struct drm_simple_display_pipe *pipe, @@ -219,7 +220,7 @@ static const struct drm_simple_display_pipe_funcs aspeed_gfx_funcs = { .enable = aspeed_gfx_pipe_enable, .disable = aspeed_gfx_pipe_disable, .update = aspeed_gfx_pipe_update, - .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb, .enable_vblank = aspeed_gfx_enable_vblank, .disable_vblank = aspeed_gfx_disable_vblank, }; diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index 457ec04950f7db2cc5619d7ec1f1655cba5cb99c..b53fee6f1c170a83a0a95c9bc9f9b500ca269363 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,34 @@ * which is available under NDA from ASPEED. */ +struct aspeed_gfx_config { + u32 dac_reg; /* DAC register in SCU */ + u32 vga_scratch_reg; /* VGA scratch register in SCU */ + u32 throd_val; /* Default Threshold Seting */ + u32 scan_line_max; /* Max memory size of one scan line */ +}; + +static const struct aspeed_gfx_config ast2400_config = { + .dac_reg = 0x2c, + .vga_scratch_reg = 0x50, + .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12), + .scan_line_max = 64, +}; + +static const struct aspeed_gfx_config ast2500_config = { + .dac_reg = 0x2c, + .vga_scratch_reg = 0x50, + .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c), + .scan_line_max = 128, +}; + +static const struct of_device_id aspeed_gfx_match[] = { + { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config }, + { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config }, + { }, +}; +MODULE_DEVICE_TABLE(of, aspeed_gfx_match); + static const struct drm_mode_config_funcs aspeed_gfx_mode_config_funcs = { .fb_create = drm_gem_fb_create, .atomic_check = drm_atomic_helper_check, @@ -97,12 +126,13 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data) return IRQ_NONE; } - - static int aspeed_gfx_load(struct drm_device *drm) { struct platform_device *pdev = to_platform_device(drm->dev); struct aspeed_gfx *priv = to_aspeed_gfx(drm); + struct device_node *np = pdev->dev.of_node; + const struct aspeed_gfx_config *config; + const struct of_device_id *match; struct resource *res; int ret; @@ -111,10 +141,23 @@ static int aspeed_gfx_load(struct drm_device *drm) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu"); + match = of_match_device(aspeed_gfx_match, &pdev->dev); + if (!match) + return -EINVAL; + config = match->data; + + priv->dac_reg = config->dac_reg; + priv->vga_scratch_reg = config->vga_scratch_reg; + priv->throd_val = config->throd_val; + priv->scan_line_max = config->scan_line_max; + + priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon"); if (IS_ERR(priv->scu)) { - dev_err(&pdev->dev, "failed to find SCU regmap\n"); - return PTR_ERR(priv->scu); + priv->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu"); + if (IS_ERR(priv->scu)) { + dev_err(&pdev->dev, "failed to find SCU regmap\n"); + return PTR_ERR(priv->scu); + } } ret = of_reserved_mem_device_init(drm->dev); @@ -202,14 +245,6 @@ static const struct drm_driver aspeed_gfx_driver = { .minor = 0, }; -static const struct of_device_id aspeed_gfx_match[] = { - { .compatible = "aspeed,ast2500-gfx" }, - { } -}; - -#define ASPEED_SCU_VGA0 0x50 -#define ASPEED_SCU_MISC_CTRL 0x2c - static ssize_t dac_mux_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -224,7 +259,7 @@ static ssize_t dac_mux_store(struct device *dev, struct device_attribute *attr, if (val > 3) return -EINVAL; - rc = regmap_update_bits(priv->scu, ASPEED_SCU_MISC_CTRL, 0x30000, val << 16); + rc = regmap_update_bits(priv->scu, priv->dac_reg, 0x30000, val << 16); if (rc < 0) return 0; @@ -237,7 +272,7 @@ static ssize_t dac_mux_show(struct device *dev, struct device_attribute *attr, c u32 reg; int rc; - rc = regmap_read(priv->scu, ASPEED_SCU_MISC_CTRL, ®); + rc = regmap_read(priv->scu, priv->dac_reg, ®); if (rc) return rc; @@ -252,7 +287,7 @@ vga_pw_show(struct device *dev, struct device_attribute *attr, char *buf) u32 reg; int rc; - rc = regmap_read(priv->scu, ASPEED_SCU_VGA0, ®); + rc = regmap_read(priv->scu, priv->vga_scratch_reg, ®); if (rc) return rc; @@ -284,7 +319,7 @@ static int aspeed_gfx_probe(struct platform_device *pdev) if (ret) return ret; - dev_set_drvdata(&pdev->dev, priv); + platform_set_drvdata(pdev, priv); ret = sysfs_create_group(&pdev->dev.kobj, &aspeed_sysfs_attr_group); if (ret) diff --git a/drivers/gpu/drm/ast/Makefile b/drivers/gpu/drm/ast/Makefile index 2265a8a624dd702805c16a58d1c74990388f1286..438a2d05b115dbca16dd9f574a27e3b42543caac 100644 --- a/drivers/gpu/drm/ast/Makefile +++ b/drivers/gpu/drm/ast/Makefile @@ -3,7 +3,6 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ast-y := ast_cursor.o ast_drv.o ast_main.o ast_mm.o ast_mode.o ast_post.o \ - ast_dp501.o +ast-y := ast_drv.o ast_main.o ast_mm.o ast_mode.o ast_post.o ast_dp501.o obj-$(CONFIG_DRM_AST) := ast.o diff --git a/drivers/gpu/drm/ast/ast_cursor.c b/drivers/gpu/drm/ast/ast_cursor.c deleted file mode 100644 index fac1ee79c372e65af6be7d2d1cc7479f111a27a5..0000000000000000000000000000000000000000 --- a/drivers/gpu/drm/ast/ast_cursor.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * Parts based on xf86-video-ast - * Copyright (c) 2005 ASPEED Technology Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - */ -/* - * Authors: Dave Airlie - */ - -#include -#include - -#include "ast_drv.h" - -static void ast_cursor_fini(struct ast_private *ast) -{ - size_t i; - struct drm_gem_vram_object *gbo; - - for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { - gbo = ast->cursor.gbo[i]; - drm_gem_vram_unpin(gbo); - drm_gem_vram_put(gbo); - } -} - -static void ast_cursor_release(struct drm_device *dev, void *ptr) -{ - struct ast_private *ast = to_ast_private(dev); - - ast_cursor_fini(ast); -} - -/* - * Allocate cursor BOs and pin them at the end of VRAM. - */ -int ast_cursor_init(struct ast_private *ast) -{ - struct drm_device *dev = &ast->base; - size_t size, i; - struct drm_gem_vram_object *gbo; - int ret; - - size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); - - for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { - gbo = drm_gem_vram_create(dev, size, 0); - if (IS_ERR(gbo)) { - ret = PTR_ERR(gbo); - goto err_drm_gem_vram_put; - } - ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | - DRM_GEM_VRAM_PL_FLAG_TOPDOWN); - if (ret) { - drm_gem_vram_put(gbo); - goto err_drm_gem_vram_put; - } - ast->cursor.gbo[i] = gbo; - } - - return drmm_add_action_or_reset(dev, ast_cursor_release, NULL); - -err_drm_gem_vram_put: - while (i) { - --i; - gbo = ast->cursor.gbo[i]; - drm_gem_vram_unpin(gbo); - drm_gem_vram_put(gbo); - } - return ret; -} - -static void update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height) -{ - union { - u32 ul; - u8 b[4]; - } srcdata32[2], data32; - union { - u16 us; - u8 b[2]; - } data16; - u32 csum = 0; - s32 alpha_dst_delta, last_alpha_dst_delta; - u8 __iomem *dstxor; - const u8 *srcxor; - int i, j; - u32 per_pixel_copy, two_pixel_copy; - - alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; - last_alpha_dst_delta = alpha_dst_delta - (width << 1); - - srcxor = src; - dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; - per_pixel_copy = width & 1; - two_pixel_copy = width >> 1; - - for (j = 0; j < height; j++) { - for (i = 0; i < two_pixel_copy; i++) { - srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; - srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; - data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); - data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); - data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); - data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); - - writel(data32.ul, dstxor); - csum += data32.ul; - - dstxor += 4; - srcxor += 8; - - } - - for (i = 0; i < per_pixel_copy; i++) { - srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; - data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); - data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); - writew(data16.us, dstxor); - csum += (u32)data16.us; - - dstxor += 2; - srcxor += 4; - } - dstxor += last_alpha_dst_delta; - } - - /* write checksum + signature */ - dst += AST_HWC_SIZE; - writel(csum, dst); - writel(width, dst + AST_HWC_SIGNATURE_SizeX); - writel(height, dst + AST_HWC_SIGNATURE_SizeY); - writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); - writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); -} - -int ast_cursor_blit(struct ast_private *ast, struct drm_framebuffer *fb) -{ - struct drm_device *dev = &ast->base; - struct drm_gem_vram_object *dst_gbo = ast->cursor.gbo[ast->cursor.next_index]; - struct drm_gem_vram_object *src_gbo = drm_gem_vram_of_gem(fb->obj[0]); - struct dma_buf_map src_map, dst_map; - void __iomem *dst; - void *src; - int ret; - - if (drm_WARN_ON_ONCE(dev, fb->width > AST_MAX_HWC_WIDTH) || - drm_WARN_ON_ONCE(dev, fb->height > AST_MAX_HWC_HEIGHT)) - return -EINVAL; - - ret = drm_gem_vram_vmap(src_gbo, &src_map); - if (ret) - return ret; - src = src_map.vaddr; /* TODO: Use mapping abstraction properly */ - - ret = drm_gem_vram_vmap(dst_gbo, &dst_map); - if (ret) - goto err_drm_gem_vram_vunmap; - dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */ - - /* do data transfer to cursor BO */ - update_cursor_image(dst, src, fb->width, fb->height); - - drm_gem_vram_vunmap(dst_gbo, &dst_map); - drm_gem_vram_vunmap(src_gbo, &src_map); - - return 0; - -err_drm_gem_vram_vunmap: - drm_gem_vram_vunmap(src_gbo, &src_map); - return ret; -} - -static void ast_cursor_set_base(struct ast_private *ast, u64 address) -{ - u8 addr0 = (address >> 3) & 0xff; - u8 addr1 = (address >> 11) & 0xff; - u8 addr2 = (address >> 19) & 0xff; - - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); -} - -void ast_cursor_page_flip(struct ast_private *ast) -{ - struct drm_device *dev = &ast->base; - struct drm_gem_vram_object *gbo; - s64 off; - - gbo = ast->cursor.gbo[ast->cursor.next_index]; - - off = drm_gem_vram_offset(gbo); - if (drm_WARN_ON_ONCE(dev, off < 0)) - return; /* Bug: we didn't pin the cursor HW BO to VRAM. */ - - ast_cursor_set_base(ast, off); - - ++ast->cursor.next_index; - ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo); -} - -static void ast_cursor_set_location(struct ast_private *ast, u16 x, u16 y, - u8 x_offset, u8 y_offset) -{ - u8 x0 = (x & 0x00ff); - u8 x1 = (x & 0x0f00) >> 8; - u8 y0 = (y & 0x00ff); - u8 y1 = (y & 0x0700) >> 8; - - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0); - ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1); -} - -void ast_cursor_show(struct ast_private *ast, int x, int y, - unsigned int offset_x, unsigned int offset_y) -{ - struct drm_device *dev = &ast->base; - struct drm_gem_vram_object *gbo = ast->cursor.gbo[ast->cursor.next_index]; - struct dma_buf_map map; - u8 x_offset, y_offset; - u8 __iomem *dst; - u8 __iomem *sig; - u8 jreg; - int ret; - - ret = drm_gem_vram_vmap(gbo, &map); - if (drm_WARN_ONCE(dev, ret, "drm_gem_vram_vmap() failed, ret=%d\n", ret)) - return; - dst = map.vaddr_iomem; /* TODO: Use mapping abstraction properly */ - - sig = dst + AST_HWC_SIZE; - writel(x, sig + AST_HWC_SIGNATURE_X); - writel(y, sig + AST_HWC_SIGNATURE_Y); - - drm_gem_vram_vunmap(gbo, &map); - - if (x < 0) { - x_offset = (-x) + offset_x; - x = 0; - } else { - x_offset = offset_x; - } - if (y < 0) { - y_offset = (-y) + offset_y; - y = 0; - } else { - y_offset = offset_y; - } - - ast_cursor_set_location(ast, x, y, x_offset, y_offset); - - /* dummy write to fire HWC */ - jreg = 0x02 | - 0x01; /* enable ARGB4444 cursor */ - ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); -} - -void ast_cursor_hide(struct ast_private *ast) -{ - ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); -} diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index ea8164e7a6dc6f81bb6db7a26baa16101e3299f2..01837bea18c251b9b7dcb64a553a0c08e579a1f4 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -138,6 +139,7 @@ static void ast_pci_remove(struct pci_dev *pdev) struct drm_device *dev = pci_get_drvdata(pdev); drm_dev_unregister(dev); + drm_atomic_helper_shutdown(dev); } static int ast_drm_freeze(struct drm_device *dev) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index f871fc36c2f7aaa320de71b2bc60b516ae2616f5..e82ab862877035d019950c71bfd2fdd3a8f78fa9 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -81,6 +81,9 @@ enum ast_tx_chip { #define AST_DRAM_4Gx16 7 #define AST_DRAM_8Gx16 8 +/* + * Cursor plane + */ #define AST_MAX_HWC_WIDTH 64 #define AST_MAX_HWC_HEIGHT 64 @@ -99,6 +102,28 @@ enum ast_tx_chip { #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 +struct ast_cursor_plane { + struct drm_plane base; + + struct { + struct drm_gem_vram_object *gbo; + struct dma_buf_map map; + u64 off; + } hwc[AST_DEFAULT_HWC_NUM]; + + unsigned int next_hwc_index; +}; + +static inline struct ast_cursor_plane * +to_ast_cursor_plane(struct drm_plane *plane) +{ + return container_of(plane, struct ast_cursor_plane, base); +} + +/* + * Connector with i2c channel + */ + struct ast_i2c_chan { struct i2c_adapter adapter; struct drm_device *dev; @@ -116,6 +141,10 @@ to_ast_connector(struct drm_connector *connector) return container_of(connector, struct ast_connector, base); } +/* + * Device + */ + struct ast_private { struct drm_device base; @@ -130,13 +159,8 @@ struct ast_private { int fb_mtrr; - struct { - struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM]; - unsigned int next_index; - } cursor; - struct drm_plane primary_plane; - struct drm_plane cursor_plane; + struct ast_cursor_plane cursor_plane; struct drm_crtc crtc; struct drm_encoder encoder; struct ast_connector connector; @@ -179,6 +203,9 @@ struct ast_private *ast_device_create(const struct drm_driver *drv, #define AST_IO_VGAIR1_VREFRESH BIT(3) +#define AST_IO_VGACRCB_HWC_ENABLED BIT(1) +#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ + #define __ast_read(x) \ static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ u##x val = 0;\ @@ -314,12 +341,4 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); -/* ast_cursor.c */ -int ast_cursor_init(struct ast_private *ast); -int ast_cursor_blit(struct ast_private *ast, struct drm_framebuffer *fb); -void ast_cursor_page_flip(struct ast_private *ast); -void ast_cursor_show(struct ast_private *ast, int x, int y, - unsigned int offset_x, unsigned int offset_y); -void ast_cursor_hide(struct ast_private *ast); - #endif diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 988b270fea5ebe9cfd682e5f6fb3003d8f2c4372..36d9575aa27ba8b0f68591a0718b00753bb37b28 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -535,48 +536,54 @@ static const uint32_t ast_primary_plane_formats[] = { }; static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); struct drm_crtc_state *crtc_state; struct ast_crtc_state *ast_crtc_state; int ret; - if (!state->crtc) + if (!new_plane_state->crtc) return 0; - crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); + crtc_state = drm_atomic_get_new_crtc_state(state, + new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, false, true); if (ret) return ret; - if (!state->visible) + if (!new_plane_state->visible) return 0; ast_crtc_state = to_ast_crtc_state(crtc_state); - ast_crtc_state->format = state->fb->format; + ast_crtc_state->format = new_plane_state->fb->format; return 0; } static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct drm_device *dev = plane->dev; struct ast_private *ast = to_ast_private(dev); - struct drm_plane_state *state = plane->state; + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); struct drm_gem_vram_object *gbo; s64 gpu_addr; - struct drm_framebuffer *fb = state->fb; + struct drm_framebuffer *fb = new_state->fb; struct drm_framebuffer *old_fb = old_state->fb; if (!old_fb || (fb->format != old_fb->format)) { - struct drm_crtc_state *crtc_state = state->crtc->state; + struct drm_crtc_state *crtc_state = new_state->crtc->state; struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info; @@ -597,7 +604,7 @@ ast_primary_plane_helper_atomic_update(struct drm_plane *plane, static void ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { struct ast_private *ast = to_ast_private(plane->dev); @@ -621,55 +628,161 @@ static const struct drm_plane_funcs ast_primary_plane_funcs = { .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, }; +static int ast_primary_plane_init(struct ast_private *ast) +{ + struct drm_device *dev = &ast->base; + struct drm_plane *primary_plane = &ast->primary_plane; + int ret; + + ret = drm_universal_plane_init(dev, primary_plane, 0x01, + &ast_primary_plane_funcs, + ast_primary_plane_formats, + ARRAY_SIZE(ast_primary_plane_formats), + NULL, DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) { + drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret); + return ret; + } + drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs); + + return 0; +} + /* * Cursor plane */ -static const uint32_t ast_cursor_plane_formats[] = { - DRM_FORMAT_ARGB8888, -}; +static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height) +{ + union { + u32 ul; + u8 b[4]; + } srcdata32[2], data32; + union { + u16 us; + u8 b[2]; + } data16; + u32 csum = 0; + s32 alpha_dst_delta, last_alpha_dst_delta; + u8 __iomem *dstxor; + const u8 *srcxor; + int i, j; + u32 per_pixel_copy, two_pixel_copy; + + alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; + last_alpha_dst_delta = alpha_dst_delta - (width << 1); + + srcxor = src; + dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; + per_pixel_copy = width & 1; + two_pixel_copy = width >> 1; + + for (j = 0; j < height; j++) { + for (i = 0; i < two_pixel_copy; i++) { + srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; + srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; + data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); + data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); + data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); + data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); + + writel(data32.ul, dstxor); + csum += data32.ul; + + dstxor += 4; + srcxor += 8; + + } -static int -ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane, - struct drm_plane_state *new_state) + for (i = 0; i < per_pixel_copy; i++) { + srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; + data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); + data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); + writew(data16.us, dstxor); + csum += (u32)data16.us; + + dstxor += 2; + srcxor += 4; + } + dstxor += last_alpha_dst_delta; + } + + /* write checksum + signature */ + dst += AST_HWC_SIZE; + writel(csum, dst); + writel(width, dst + AST_HWC_SIGNATURE_SizeX); + writel(height, dst + AST_HWC_SIGNATURE_SizeY); + writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); + writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); +} + +static void ast_set_cursor_base(struct ast_private *ast, u64 address) { - struct drm_framebuffer *fb = new_state->fb; - struct drm_crtc *crtc = new_state->crtc; - struct ast_private *ast; - int ret; + u8 addr0 = (address >> 3) & 0xff; + u8 addr1 = (address >> 11) & 0xff; + u8 addr2 = (address >> 19) & 0xff; - if (!crtc || !fb) - return 0; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); +} - ast = to_ast_private(plane->dev); +static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y, + u8 x_offset, u8 y_offset) +{ + u8 x0 = (x & 0x00ff); + u8 x1 = (x & 0x0f00) >> 8; + u8 y0 = (y & 0x00ff); + u8 y1 = (y & 0x0700) >> 8; + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1); +} - ret = ast_cursor_blit(ast, fb); - if (ret) - return ret; +static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled) +{ + static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP | + AST_IO_VGACRCB_HWC_ENABLED); - return 0; + u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP; + + if (enabled) + vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb); } +static const uint32_t ast_cursor_plane_formats[] = { + DRM_FORMAT_ARGB8888, +}; + static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_atomic_state *state) { - struct drm_framebuffer *fb = state->fb; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + struct drm_framebuffer *fb = new_plane_state->fb; struct drm_crtc_state *crtc_state; int ret; - if (!state->crtc) + if (!new_plane_state->crtc) return 0; - crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); + crtc_state = drm_atomic_get_new_crtc_state(state, + new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, true, true); if (ret) return ret; - if (!state->visible) + if (!new_plane_state->visible) return 0; if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) @@ -680,51 +793,192 @@ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { - struct drm_plane_state *state = plane->state; - struct drm_framebuffer *fb = state->fb; + struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); + struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, + plane); + struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state); + struct drm_framebuffer *fb = new_state->fb; struct ast_private *ast = to_ast_private(plane->dev); + struct dma_buf_map dst_map = + ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map; + u64 dst_off = + ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off; + struct dma_buf_map src_map = shadow_plane_state->map[0]; unsigned int offset_x, offset_y; + u16 x, y; + u8 x_offset, y_offset; + u8 __iomem *dst; + u8 __iomem *sig; + const u8 *src; + + src = src_map.vaddr; /* TODO: Use mapping abstraction properly */ + dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */ + sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */ + + /* + * Do data transfer to HW cursor BO. If a new cursor image was installed, + * point the scanout engine to dst_gbo's offset and page-flip the HWC buffers. + */ + + ast_update_cursor_image(dst, src, fb->width, fb->height); + + if (new_state->fb != old_state->fb) { + ast_set_cursor_base(ast, dst_off); + + ++ast_cursor_plane->next_hwc_index; + ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc); + } + + /* + * Update location in HWC signature and registers. + */ + + writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X); + writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y); offset_x = AST_MAX_HWC_WIDTH - fb->width; - offset_y = AST_MAX_HWC_WIDTH - fb->height; + offset_y = AST_MAX_HWC_HEIGHT - fb->height; - if (state->fb != old_state->fb) { - /* A new cursor image was installed. */ - ast_cursor_page_flip(ast); + if (new_state->crtc_x < 0) { + x_offset = (-new_state->crtc_x) + offset_x; + x = 0; + } else { + x_offset = offset_x; + x = new_state->crtc_x; + } + if (new_state->crtc_y < 0) { + y_offset = (-new_state->crtc_y) + offset_y; + y = 0; + } else { + y_offset = offset_y; + y = new_state->crtc_y; } - ast_cursor_show(ast, state->crtc_x, state->crtc_y, - offset_x, offset_y); + ast_set_cursor_location(ast, x, y, x_offset, y_offset); + + /* Dummy write to enable HWC and make the HW pick-up the changes. */ + ast_set_cursor_enabled(ast, true); } static void ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { struct ast_private *ast = to_ast_private(plane->dev); - ast_cursor_hide(ast); + ast_set_cursor_enabled(ast, false); } static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { - .prepare_fb = ast_cursor_plane_helper_prepare_fb, - .cleanup_fb = NULL, /* not required for cursor plane */ + DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, .atomic_check = ast_cursor_plane_helper_atomic_check, .atomic_update = ast_cursor_plane_helper_atomic_update, .atomic_disable = ast_cursor_plane_helper_atomic_disable, }; +static void ast_cursor_plane_destroy(struct drm_plane *plane) +{ + struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); + size_t i; + struct drm_gem_vram_object *gbo; + struct dma_buf_map map; + + for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) { + gbo = ast_cursor_plane->hwc[i].gbo; + map = ast_cursor_plane->hwc[i].map; + drm_gem_vram_vunmap(gbo, &map); + drm_gem_vram_unpin(gbo); + drm_gem_vram_put(gbo); + } + + drm_plane_cleanup(plane); +} + static const struct drm_plane_funcs ast_cursor_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, - .reset = drm_atomic_helper_plane_reset, - .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, + .destroy = ast_cursor_plane_destroy, + DRM_GEM_SHADOW_PLANE_FUNCS, }; +static int ast_cursor_plane_init(struct ast_private *ast) +{ + struct drm_device *dev = &ast->base; + struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane; + struct drm_plane *cursor_plane = &ast_cursor_plane->base; + size_t size, i; + struct drm_gem_vram_object *gbo; + struct dma_buf_map map; + int ret; + s64 off; + + /* + * Allocate backing storage for cursors. The BOs are permanently + * pinned to the top end of the VRAM. + */ + + size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); + + for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) { + gbo = drm_gem_vram_create(dev, size, 0); + if (IS_ERR(gbo)) { + ret = PTR_ERR(gbo); + goto err_hwc; + } + ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | + DRM_GEM_VRAM_PL_FLAG_TOPDOWN); + if (ret) + goto err_drm_gem_vram_put; + ret = drm_gem_vram_vmap(gbo, &map); + if (ret) + goto err_drm_gem_vram_unpin; + off = drm_gem_vram_offset(gbo); + if (off < 0) { + ret = off; + goto err_drm_gem_vram_vunmap; + } + ast_cursor_plane->hwc[i].gbo = gbo; + ast_cursor_plane->hwc[i].map = map; + ast_cursor_plane->hwc[i].off = off; + } + + /* + * Create the cursor plane. The plane's destroy callback will release + * the backing storages' BO memory. + */ + + ret = drm_universal_plane_init(dev, cursor_plane, 0x01, + &ast_cursor_plane_funcs, + ast_cursor_plane_formats, + ARRAY_SIZE(ast_cursor_plane_formats), + NULL, DRM_PLANE_TYPE_CURSOR, NULL); + if (ret) { + drm_err(dev, "drm_universal_plane failed(): %d\n", ret); + goto err_hwc; + } + drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs); + + return 0; + +err_hwc: + while (i) { + --i; + gbo = ast_cursor_plane->hwc[i].gbo; + map = ast_cursor_plane->hwc[i].map; +err_drm_gem_vram_vunmap: + drm_gem_vram_vunmap(gbo, &map); +err_drm_gem_vram_unpin: + drm_gem_vram_unpin(gbo); +err_drm_gem_vram_put: + drm_gem_vram_put(gbo); + } + return ret; +} + /* * CRTC */ @@ -917,7 +1171,7 @@ static int ast_crtc_init(struct drm_device *dev) int ret; ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane, - &ast->cursor_plane, &ast_crtc_funcs, + &ast->cursor_plane.base, &ast_crtc_funcs, NULL); if (ret) return ret; @@ -1109,10 +1363,6 @@ int ast_mode_config_init(struct ast_private *ast) struct pci_dev *pdev = to_pci_dev(dev->dev); int ret; - ret = ast_cursor_init(ast); - if (ret) - return ret; - ret = drmm_mode_config_init(dev); if (ret) return ret; @@ -1138,30 +1388,14 @@ int ast_mode_config_init(struct ast_private *ast) dev->mode_config.helper_private = &ast_mode_config_helper_funcs; - memset(&ast->primary_plane, 0, sizeof(ast->primary_plane)); - ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01, - &ast_primary_plane_funcs, - ast_primary_plane_formats, - ARRAY_SIZE(ast_primary_plane_formats), - NULL, DRM_PLANE_TYPE_PRIMARY, NULL); - if (ret) { - drm_err(dev, "ast: drm_universal_plane_init() failed: %d\n", ret); + + ret = ast_primary_plane_init(ast); + if (ret) return ret; - } - drm_plane_helper_add(&ast->primary_plane, - &ast_primary_plane_helper_funcs); - ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01, - &ast_cursor_plane_funcs, - ast_cursor_plane_formats, - ARRAY_SIZE(ast_cursor_plane_formats), - NULL, DRM_PLANE_TYPE_CURSOR, NULL); - if (ret) { - drm_err(dev, "drm_universal_plane_failed(): %d\n", ret); + ret = ast_cursor_plane_init(ast); + if (ret) return ret; - } - drm_plane_helper_add(&ast->cursor_plane, - &ast_cursor_plane_helper_funcs); ast_crtc_init(dev); ast_encoder_init(dev); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index 98fb53b75f7738605d2c343384e4af3a2791df05..65af56e4712943a5eff0f2bfcc597dc66a72da38 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -557,103 +557,10 @@ static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data) return IRQ_HANDLED; } -struct atmel_hlcdc_dc_commit { - struct work_struct work; - struct drm_device *dev; - struct drm_atomic_state *state; -}; - -static void -atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit) -{ - struct drm_device *dev = commit->dev; - struct atmel_hlcdc_dc *dc = dev->dev_private; - struct drm_atomic_state *old_state = commit->state; - - /* Apply the atomic update. */ - drm_atomic_helper_commit_modeset_disables(dev, old_state); - drm_atomic_helper_commit_planes(dev, old_state, 0); - drm_atomic_helper_commit_modeset_enables(dev, old_state); - - drm_atomic_helper_wait_for_vblanks(dev, old_state); - - drm_atomic_helper_cleanup_planes(dev, old_state); - - drm_atomic_state_put(old_state); - - /* Complete the commit, wake up any waiter. */ - spin_lock(&dc->commit.wait.lock); - dc->commit.pending = false; - wake_up_all_locked(&dc->commit.wait); - spin_unlock(&dc->commit.wait.lock); - - kfree(commit); -} - -static void atmel_hlcdc_dc_atomic_work(struct work_struct *work) -{ - struct atmel_hlcdc_dc_commit *commit = - container_of(work, struct atmel_hlcdc_dc_commit, work); - - atmel_hlcdc_dc_atomic_complete(commit); -} - -static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool async) -{ - struct atmel_hlcdc_dc *dc = dev->dev_private; - struct atmel_hlcdc_dc_commit *commit; - int ret; - - ret = drm_atomic_helper_prepare_planes(dev, state); - if (ret) - return ret; - - /* Allocate the commit object. */ - commit = kzalloc(sizeof(*commit), GFP_KERNEL); - if (!commit) { - ret = -ENOMEM; - goto error; - } - - INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work); - commit->dev = dev; - commit->state = state; - - spin_lock(&dc->commit.wait.lock); - ret = wait_event_interruptible_locked(dc->commit.wait, - !dc->commit.pending); - if (ret == 0) - dc->commit.pending = true; - spin_unlock(&dc->commit.wait.lock); - - if (ret) - goto err_free; - - /* We have our own synchronization through the commit lock. */ - BUG_ON(drm_atomic_helper_swap_state(state, false) < 0); - - /* Swap state succeeded, this is the point of no return. */ - drm_atomic_state_get(state); - if (async) - queue_work(dc->wq, &commit->work); - else - atmel_hlcdc_dc_atomic_complete(commit); - - return 0; - -err_free: - kfree(commit); -error: - drm_atomic_helper_cleanup_planes(dev, state); - return ret; -} - static const struct drm_mode_config_funcs mode_config_funcs = { .fb_create = drm_gem_fb_create, .atomic_check = drm_atomic_helper_check, - .atomic_commit = atmel_hlcdc_dc_atomic_commit, + .atomic_commit = drm_atomic_helper_commit, }; static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) @@ -712,11 +619,6 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) if (!dc) return -ENOMEM; - dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0); - if (!dc->wq) - return -ENOMEM; - - init_waitqueue_head(&dc->commit.wait); dc->desc = match->data; dc->hlcdc = dev_get_drvdata(dev->dev->parent); dev->dev_private = dc; @@ -724,7 +626,7 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) ret = clk_prepare_enable(dc->hlcdc->periph_clk); if (ret) { dev_err(dev->dev, "failed to enable periph_clk\n"); - goto err_destroy_wq; + return ret; } pm_runtime_enable(dev->dev); @@ -761,9 +663,6 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) pm_runtime_disable(dev->dev); clk_disable_unprepare(dc->hlcdc->periph_clk); -err_destroy_wq: - destroy_workqueue(dc->wq); - return ret; } @@ -771,7 +670,6 @@ static void atmel_hlcdc_dc_unload(struct drm_device *dev) { struct atmel_hlcdc_dc *dc = dev->dev_private; - flush_workqueue(dc->wq); drm_kms_helper_poll_fini(dev); drm_atomic_helper_shutdown(dev); drm_mode_config_cleanup(dev); @@ -784,7 +682,6 @@ static void atmel_hlcdc_dc_unload(struct drm_device *dev) pm_runtime_disable(dev->dev); clk_disable_unprepare(dc->hlcdc->periph_clk); - destroy_workqueue(dc->wq); } static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 469d4507e57646eb72ec05eba3b7af5808bedcbe..5b5c774e0edf49717fe66e6a390c85f48c5a0d7a 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -331,9 +331,7 @@ struct atmel_hlcdc_dc_desc { * @crtc: CRTC provided by the display controller * @planes: instantiated planes * @layers: active HLCDC layers - * @wq: display controller workqueue * @suspend: used to store the HLCDC state when entering suspend - * @commit: used for async commit handling */ struct atmel_hlcdc_dc { const struct atmel_hlcdc_dc_desc *desc; @@ -341,15 +339,10 @@ struct atmel_hlcdc_dc { struct atmel_hlcdc *hlcdc; struct drm_crtc *crtc; struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; - struct workqueue_struct *wq; struct { u32 imr; struct drm_atomic_state *state; } suspend; - struct { - wait_queue_head_t wait; - bool pending; - } commit; }; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index 15bc93163833b1a41838b55f65bc455884d6e6ee..a077d93c78d7b5e39a1b73b40a93452be5c8a94e 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -593,22 +593,23 @@ atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane, } static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, - struct drm_plane_state *s) + struct drm_atomic_state *state) { + struct drm_plane_state *s = drm_atomic_get_new_plane_state(state, p); struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); - struct atmel_hlcdc_plane_state *state = + struct atmel_hlcdc_plane_state *hstate = drm_plane_state_to_atmel_hlcdc_plane_state(s); const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; - struct drm_framebuffer *fb = state->base.fb; + struct drm_framebuffer *fb = hstate->base.fb; const struct drm_display_mode *mode; struct drm_crtc_state *crtc_state; int ret; int i; - if (!state->base.crtc || WARN_ON(!fb)) + if (!hstate->base.crtc || WARN_ON(!fb)) return 0; - crtc_state = drm_atomic_get_existing_crtc_state(s->state, s->crtc); + crtc_state = drm_atomic_get_existing_crtc_state(state, s->crtc); mode = &crtc_state->adjusted_mode; ret = drm_atomic_helper_check_plane_state(s, crtc_state, @@ -617,101 +618,101 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, if (ret || !s->visible) return ret; - state->src_x = s->src.x1; - state->src_y = s->src.y1; - state->src_w = drm_rect_width(&s->src); - state->src_h = drm_rect_height(&s->src); - state->crtc_x = s->dst.x1; - state->crtc_y = s->dst.y1; - state->crtc_w = drm_rect_width(&s->dst); - state->crtc_h = drm_rect_height(&s->dst); + hstate->src_x = s->src.x1; + hstate->src_y = s->src.y1; + hstate->src_w = drm_rect_width(&s->src); + hstate->src_h = drm_rect_height(&s->src); + hstate->crtc_x = s->dst.x1; + hstate->crtc_y = s->dst.y1; + hstate->crtc_w = drm_rect_width(&s->dst); + hstate->crtc_h = drm_rect_height(&s->dst); - if ((state->src_x | state->src_y | state->src_w | state->src_h) & + if ((hstate->src_x | hstate->src_y | hstate->src_w | hstate->src_h) & SUBPIXEL_MASK) return -EINVAL; - state->src_x >>= 16; - state->src_y >>= 16; - state->src_w >>= 16; - state->src_h >>= 16; + hstate->src_x >>= 16; + hstate->src_y >>= 16; + hstate->src_w >>= 16; + hstate->src_h >>= 16; - state->nplanes = fb->format->num_planes; - if (state->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES) + hstate->nplanes = fb->format->num_planes; + if (hstate->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES) return -EINVAL; - for (i = 0; i < state->nplanes; i++) { + for (i = 0; i < hstate->nplanes; i++) { unsigned int offset = 0; int xdiv = i ? fb->format->hsub : 1; int ydiv = i ? fb->format->vsub : 1; - state->bpp[i] = fb->format->cpp[i]; - if (!state->bpp[i]) + hstate->bpp[i] = fb->format->cpp[i]; + if (!hstate->bpp[i]) return -EINVAL; - switch (state->base.rotation & DRM_MODE_ROTATE_MASK) { + switch (hstate->base.rotation & DRM_MODE_ROTATE_MASK) { case DRM_MODE_ROTATE_90: - offset = (state->src_y / ydiv) * + offset = (hstate->src_y / ydiv) * fb->pitches[i]; - offset += ((state->src_x + state->src_w - 1) / - xdiv) * state->bpp[i]; - state->xstride[i] = -(((state->src_h - 1) / ydiv) * + offset += ((hstate->src_x + hstate->src_w - 1) / + xdiv) * hstate->bpp[i]; + hstate->xstride[i] = -(((hstate->src_h - 1) / ydiv) * fb->pitches[i]) - - (2 * state->bpp[i]); - state->pstride[i] = fb->pitches[i] - state->bpp[i]; + (2 * hstate->bpp[i]); + hstate->pstride[i] = fb->pitches[i] - hstate->bpp[i]; break; case DRM_MODE_ROTATE_180: - offset = ((state->src_y + state->src_h - 1) / + offset = ((hstate->src_y + hstate->src_h - 1) / ydiv) * fb->pitches[i]; - offset += ((state->src_x + state->src_w - 1) / - xdiv) * state->bpp[i]; - state->xstride[i] = ((((state->src_w - 1) / xdiv) - 1) * - state->bpp[i]) - fb->pitches[i]; - state->pstride[i] = -2 * state->bpp[i]; + offset += ((hstate->src_x + hstate->src_w - 1) / + xdiv) * hstate->bpp[i]; + hstate->xstride[i] = ((((hstate->src_w - 1) / xdiv) - 1) * + hstate->bpp[i]) - fb->pitches[i]; + hstate->pstride[i] = -2 * hstate->bpp[i]; break; case DRM_MODE_ROTATE_270: - offset = ((state->src_y + state->src_h - 1) / + offset = ((hstate->src_y + hstate->src_h - 1) / ydiv) * fb->pitches[i]; - offset += (state->src_x / xdiv) * state->bpp[i]; - state->xstride[i] = ((state->src_h - 1) / ydiv) * + offset += (hstate->src_x / xdiv) * hstate->bpp[i]; + hstate->xstride[i] = ((hstate->src_h - 1) / ydiv) * fb->pitches[i]; - state->pstride[i] = -fb->pitches[i] - state->bpp[i]; + hstate->pstride[i] = -fb->pitches[i] - hstate->bpp[i]; break; case DRM_MODE_ROTATE_0: default: - offset = (state->src_y / ydiv) * fb->pitches[i]; - offset += (state->src_x / xdiv) * state->bpp[i]; - state->xstride[i] = fb->pitches[i] - - ((state->src_w / xdiv) * - state->bpp[i]); - state->pstride[i] = 0; + offset = (hstate->src_y / ydiv) * fb->pitches[i]; + offset += (hstate->src_x / xdiv) * hstate->bpp[i]; + hstate->xstride[i] = fb->pitches[i] - + ((hstate->src_w / xdiv) * + hstate->bpp[i]); + hstate->pstride[i] = 0; break; } - state->offsets[i] = offset + fb->offsets[i]; + hstate->offsets[i] = offset + fb->offsets[i]; } /* * Swap width and size in case of 90 or 270 degrees rotation */ - if (drm_rotation_90_or_270(state->base.rotation)) { - swap(state->src_w, state->src_h); + if (drm_rotation_90_or_270(hstate->base.rotation)) { + swap(hstate->src_w, hstate->src_h); } if (!desc->layout.size && - (mode->hdisplay != state->crtc_w || - mode->vdisplay != state->crtc_h)) + (mode->hdisplay != hstate->crtc_w || + mode->vdisplay != hstate->crtc_h)) return -EINVAL; - if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) && + if ((hstate->crtc_h != hstate->src_h || hstate->crtc_w != hstate->src_w) && (!desc->layout.memsize || - state->base.fb->format->has_alpha)) + hstate->base.fb->format->has_alpha)) return -EINVAL; return 0; } static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, - struct drm_plane_state *old_state) + struct drm_atomic_state *state) { struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); @@ -730,27 +731,29 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, - struct drm_plane_state *old_s) + struct drm_atomic_state *state) { + struct drm_plane_state *new_s = drm_atomic_get_new_plane_state(state, + p); struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); - struct atmel_hlcdc_plane_state *state = - drm_plane_state_to_atmel_hlcdc_plane_state(p->state); + struct atmel_hlcdc_plane_state *hstate = + drm_plane_state_to_atmel_hlcdc_plane_state(new_s); u32 sr; - if (!p->state->crtc || !p->state->fb) + if (!new_s->crtc || !new_s->fb) return; - if (!state->base.visible) { - atmel_hlcdc_plane_atomic_disable(p, old_s); + if (!hstate->base.visible) { + atmel_hlcdc_plane_atomic_disable(p, state); return; } - atmel_hlcdc_plane_update_pos_and_size(plane, state); - atmel_hlcdc_plane_update_general_settings(plane, state); - atmel_hlcdc_plane_update_format(plane, state); - atmel_hlcdc_plane_update_clut(plane, state); - atmel_hlcdc_plane_update_buffers(plane, state); - atmel_hlcdc_plane_update_disc_area(plane, state); + atmel_hlcdc_plane_update_pos_and_size(plane, hstate); + atmel_hlcdc_plane_update_general_settings(plane, hstate); + atmel_hlcdc_plane_update_format(plane, hstate); + atmel_hlcdc_plane_update_clut(plane, hstate); + atmel_hlcdc_plane_update_buffers(plane, hstate); + atmel_hlcdc_plane_update_disc_area(plane, hstate); /* Enable the overrun interrupts. */ atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index e4110d6ca7b3c86ab26dbabb8f0b6485521007b1..dba62f92d05101c992a32070519f2610837f1310 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -27,6 +27,19 @@ config DRM_CDNS_DSI Support Cadence DPI to DSI bridge. This is an internal bridge and is meant to be directly embedded in a SoC. +config DRM_CHIPONE_ICN6211 + tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge" + depends on OF + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + help + ICN6211 is MIPI-DSI/RGB Converter bridge from chipone. + + It has a flexible configuration of MIPI DSI signal input + and produce RGB565, RGB666, RGB888 output format. + + If in doubt, say "N". + config DRM_CHRONTEL_CH7033 tristate "Chrontel CH7033 Video Encoder" depends on OF @@ -48,6 +61,20 @@ config DRM_DISPLAY_CONNECTOR on ARM-based platforms. Saying Y here when this driver is not needed will not cause any issue. +config DRM_LONTIUM_LT8912B + tristate "Lontium LT8912B DSI/HDMI bridge" + depends on OF + select DRM_PANEL_BRIDGE + select DRM_KMS_HELPER + select REGMAP_I2C + help + Driver for Lontium LT8912B DSI to HDMI bridge + chip driver. + Please say Y if you have such hardware. + + Say M here if you want to support this hardware as a module. + The module will be named "lontium-lt8912b". + config DRM_LONTIUM_LT9611 tristate "Lontium LT9611 DSI/HDMI bridge" select SND_SOC_HDMI_CODEC if SND_SOC diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 86e7acc76f8d6170e2ae98571a8c1b3cf67aa349..5c61b50c1663ecf823d974cc1d0682a3a22dae5c 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o +obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o +obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c index d9164fab044d03d05c4a6dca1bb39e092e0fbb1e..aa6cda458eb9be79fa82bae08f85f85b4522f870 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c @@ -550,28 +550,38 @@ static int anx6345_bridge_attach(struct drm_bridge *bridge, DRM_MODE_CONNECTOR_eDP); if (err) { DRM_ERROR("Failed to initialize connector: %d\n", err); - return err; + goto aux_unregister; } drm_connector_helper_add(&anx6345->connector, &anx6345_connector_helper_funcs); - err = drm_connector_register(&anx6345->connector); - if (err) { - DRM_ERROR("Failed to register connector: %d\n", err); - return err; - } - anx6345->connector.polled = DRM_CONNECTOR_POLL_HPD; err = drm_connector_attach_encoder(&anx6345->connector, bridge->encoder); if (err) { DRM_ERROR("Failed to link up connector to encoder: %d\n", err); - return err; + goto connector_cleanup; + } + + err = drm_connector_register(&anx6345->connector); + if (err) { + DRM_ERROR("Failed to register connector: %d\n", err); + goto connector_cleanup; } return 0; +connector_cleanup: + drm_connector_cleanup(&anx6345->connector); +aux_unregister: + drm_dp_aux_unregister(&anx6345->aux); + return err; +} + +static void anx6345_bridge_detach(struct drm_bridge *bridge) +{ + drm_dp_aux_unregister(&bridge_to_anx6345(bridge)->aux); } static enum drm_mode_status @@ -624,6 +634,7 @@ static void anx6345_bridge_enable(struct drm_bridge *bridge) static const struct drm_bridge_funcs anx6345_bridge_funcs = { .attach = anx6345_bridge_attach, + .detach = anx6345_bridge_detach, .mode_valid = anx6345_bridge_mode_valid, .disable = anx6345_bridge_disable, .enable = anx6345_bridge_enable, diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index 81debd02c1693a97fc3f6456efe232b60e999fe9..f20558618220836bf1e9bea331375a7a568b9e6e 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@ -918,28 +918,38 @@ static int anx78xx_bridge_attach(struct drm_bridge *bridge, DRM_MODE_CONNECTOR_DisplayPort); if (err) { DRM_ERROR("Failed to initialize connector: %d\n", err); - return err; + goto aux_unregister; } drm_connector_helper_add(&anx78xx->connector, &anx78xx_connector_helper_funcs); - err = drm_connector_register(&anx78xx->connector); - if (err) { - DRM_ERROR("Failed to register connector: %d\n", err); - return err; - } - anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD; err = drm_connector_attach_encoder(&anx78xx->connector, bridge->encoder); if (err) { DRM_ERROR("Failed to link up connector to encoder: %d\n", err); - return err; + goto connector_cleanup; + } + + err = drm_connector_register(&anx78xx->connector); + if (err) { + DRM_ERROR("Failed to register connector: %d\n", err); + goto connector_cleanup; } return 0; +connector_cleanup: + drm_connector_cleanup(&anx78xx->connector); +aux_unregister: + drm_dp_aux_unregister(&anx78xx->aux); + return err; +} + +static void anx78xx_bridge_detach(struct drm_bridge *bridge) +{ + drm_dp_aux_unregister(&bridge_to_anx78xx(bridge)->aux); } static enum drm_mode_status @@ -1013,6 +1023,7 @@ static void anx78xx_bridge_enable(struct drm_bridge *bridge) static const struct drm_bridge_funcs anx78xx_bridge_funcs = { .attach = anx78xx_bridge_attach, + .detach = anx78xx_bridge_detach, .mode_valid = anx78xx_bridge_mode_valid, .disable = anx78xx_bridge_disable, .mode_set = anx78xx_bridge_mode_set, diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index aa1bb86293fdf49a19c8ae5271f39d50f136956a..f115233b1cb93d2b88943a35680ec32c6930ae8a 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1782,6 +1782,7 @@ int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev) err_disable_pm_runtime: pm_runtime_disable(dp->dev); + drm_dp_aux_unregister(&dp->aux); return ret; } diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 65cc05982f826300ceac4d6bbb228ed82061666e..23283ba0c4f933256aa78de5464d023056db7b00 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -875,12 +876,25 @@ static int sp_tx_edid_read(struct anx7625_data *ctx, static void anx7625_power_on(struct anx7625_data *ctx) { struct device *dev = &ctx->client->dev; + int ret, i; if (!ctx->pdata.low_power_mode) { DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); return; } + for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { + ret = regulator_enable(ctx->pdata.supplies[i].consumer); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", + i, ret); + goto reg_err; + } + usleep_range(2000, 2100); + } + + usleep_range(4000, 4100); + /* Power on pin enable */ gpiod_set_value(ctx->pdata.gpio_p_on, 1); usleep_range(10000, 11000); @@ -889,11 +903,16 @@ static void anx7625_power_on(struct anx7625_data *ctx) usleep_range(10000, 11000); DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); + return; +reg_err: + for (--i; i >= 0; i--) + regulator_disable(ctx->pdata.supplies[i].consumer); } static void anx7625_power_standby(struct anx7625_data *ctx) { struct device *dev = &ctx->client->dev; + int ret; if (!ctx->pdata.low_power_mode) { DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); @@ -904,6 +923,12 @@ static void anx7625_power_standby(struct anx7625_data *ctx) usleep_range(1000, 1100); gpiod_set_value(ctx->pdata.gpio_p_on, 0); usleep_range(1000, 1100); + + ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), + ctx->pdata.supplies); + if (ret < 0) + DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); + DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); } @@ -1742,6 +1767,15 @@ static int anx7625_i2c_probe(struct i2c_client *client, platform->client = client; i2c_set_clientdata(client, platform); + pdata->supplies[0].supply = "vdd10"; + pdata->supplies[1].supply = "vdd18"; + pdata->supplies[2].supply = "vdd33"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), + pdata->supplies); + if (ret) { + DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); + return ret; + } anx7625_init_gpio(platform); atomic_set(&platform->power_status, 0); diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h index 193ad86c54503d91d614e49d5213bbde62a359a1..e4a086b3a3d7b49157c353c9b397b6d146b2a3c1 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.h +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h @@ -350,6 +350,7 @@ struct s_edid_data { struct anx7625_platform_data { struct gpio_desc *gpio_p_on; struct gpio_desc *gpio_reset; + struct regulator_bulk_data supplies[3]; struct drm_bridge *panel_bridge; int intp_irq; u32 low_power_mode; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index d0c65610ebb5c3633a61f34890e855ba9180d4e4..989a05bc81979428ebd98814cf28ded0a07c7610 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -2457,7 +2457,7 @@ static int cdns_mhdp_probe(struct platform_device *pdev) static int cdns_mhdp_remove(struct platform_device *pdev) { - struct cdns_mhdp_device *mhdp = dev_get_drvdata(&pdev->dev); + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); unsigned long timeout = msecs_to_jiffies(100); bool stop_fw = false; int ret; diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c new file mode 100644 index 0000000000000000000000000000000000000000..a6151db95586836c7cd20e91c36df29849adaec7 --- /dev/null +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Amarula Solutions(India) + * Author: Jagan Teki + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include