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Commit ed8c953e authored by Andrew Jeffery's avatar Andrew Jeffery Committed by Greg Kroah-Hartman
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ARM: dts: everest: Add phase corrections for eMMC



commit faffd1b2 upstream.

The values were determined experimentally via boot tests, not by
measuring the bus behaviour with a scope. We plan to do scope
measurements to confirm or refine the values and will update the
devicetree if necessary once these have been obtained.

However, with the patch we can write and read data without issue, where
as booting the system without the patch failed at the point of mounting
the rootfs.

Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210628013605.1257346-1-andrew@aj.id.au


Fixes: 2fc88f92 ("mmc: sdhci-of-aspeed: Expose clock phase controls")
Fixes: a5c51684 ("ARM: dts: aspeed: Add Everest BMC machine")
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent cc02a1bd
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