From 550ee52d823845f882ddadcd032b33169866a739 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 27 Nov 2009 13:47:09 +0100 Subject: [PATCH 001/370] [ARM] pxa/raumfeld: add platform support This adds support for Raumfeld's 'Controller', 'Connector', 'Speaker S' and 'Speaker M' devices. They're all based on PXA303 SoCs. Signed-off-by: Daniel Mack Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 18 + arch/arm/mach-pxa/Makefile | 3 + arch/arm/mach-pxa/raumfeld.c | 1100 ++++++++++++++++++++++++++++++++++ 3 files changed, 1121 insertions(+) create mode 100644 arch/arm/mach-pxa/raumfeld.c diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 8a0837ea02942..fdb966e590a2d 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -415,6 +415,24 @@ config MACH_TREO680 Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. +config MACH_RAUMFELD_RC + bool "Raumfeld Controller" + select PXA3xx + select CPU_PXA300 + select HAVE_PWM + +config MACH_RAUMFELD_CONNECTOR + bool "Raumfeld Connector" + select PXA3xx + select CPU_PXA300 + select PXA_SSP + +config MACH_RAUMFELD_SPEAKER + bool "Raumfeld Speaker" + select PXA3xx + select CPU_PXA300 + select PXA_SSP + config PXA_SHARPSL bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" select SHARP_SCOOP diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f64afda7e6f63..9d831939b3c59 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -89,6 +89,9 @@ obj-$(CONFIG_MACH_E740) += e740.o obj-$(CONFIG_MACH_E750) += e750.o obj-$(CONFIG_MACH_E400) += e400.o obj-$(CONFIG_MACH_E800) += e800.o +obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o +obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o +obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o # Support for blinky lights led-y := leds.o diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c new file mode 100644 index 0000000000000..06717d7995cbe --- /dev/null +++ b/arch/arm/mach-pxa/raumfeld.c @@ -0,0 +1,1100 @@ +/* + * arch/arm/mach-pxa/raumfeld.c + * + * Support for the following Raumfeld devices: + * + * * Controller + * * Connector + * * Speaker S/M + * + * See http://www.raumfeld.com for details. + * + * Copyright (c) 2009 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "generic.h" +#include "devices.h" +#include "clock.h" + +/* common GPIO definitions */ + +/* inputs */ +#define GPIO_ON_OFF (14) +#define GPIO_VOLENC_A (19) +#define GPIO_VOLENC_B (20) +#define GPIO_CHARGE_DONE (23) +#define GPIO_CHARGE_IND (27) +#define GPIO_TOUCH_IRQ (32) +#define GPIO_ETH_IRQ (40) +#define GPIO_SPI_MISO (98) +#define GPIO_ACCEL_IRQ (104) +#define GPIO_RESCUE_BOOT (115) +#define GPIO_DOCK_DETECT (116) +#define GPIO_KEY1 (117) +#define GPIO_KEY2 (118) +#define GPIO_KEY3 (119) +#define GPIO_CHARGE_USB_OK (112) +#define GPIO_CHARGE_DC_OK (101) +#define GPIO_CHARGE_USB_SUSP (102) + +/* outputs */ +#define GPIO_SHUTDOWN_SUPPLY (16) +#define GPIO_SHUTDOWN_BATT (18) +#define GPIO_CHRG_PEN2 (31) +#define GPIO_TFT_VA_EN (33) +#define GPIO_SPDIF_CS (34) +#define GPIO_LED2 (35) +#define GPIO_LED1 (36) +#define GPIO_SPDIF_RESET (38) +#define GPIO_SPI_CLK (95) +#define GPIO_MCLK_DAC_CS (96) +#define GPIO_SPI_MOSI (97) +#define GPIO_W1_PULLUP_ENABLE (105) +#define GPIO_DISPLAY_ENABLE (106) +#define GPIO_MCLK_RESET (111) +#define GPIO_W2W_RESET (113) +#define GPIO_W2W_PDN (114) +#define GPIO_CODEC_RESET (120) +#define GPIO_AUDIO_VA_ENABLE (124) +#define GPIO_ACCEL_CS (125) +#define GPIO_ONE_WIRE (126) + +/* + * GPIO configurations + */ +static mfp_cfg_t raumfeld_controller_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* One-wire */ + GPIO126_GPIO | MFP_LPM_FLOAT, + GPIO105_GPIO | MFP_PULL_LOW | MFP_LPM_PULL_LOW, + + /* CHRG_USB_OK */ + GPIO101_GPIO | MFP_PULL_HIGH, + /* CHRG_USB_OK */ + GPIO112_GPIO | MFP_PULL_HIGH, + /* CHRG_USB_SUSP */ + GPIO102_GPIO, + /* DISPLAY_ENABLE */ + GPIO106_GPIO, + /* DOCK_DETECT */ + GPIO116_GPIO | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* LCD */ + GPIO54_LCD_LDD_0, + GPIO55_LCD_LDD_1, + GPIO56_LCD_LDD_2, + GPIO57_LCD_LDD_3, + GPIO58_LCD_LDD_4, + GPIO59_LCD_LDD_5, + GPIO60_LCD_LDD_6, + GPIO61_LCD_LDD_7, + GPIO62_LCD_LDD_8, + GPIO63_LCD_LDD_9, + GPIO64_LCD_LDD_10, + GPIO65_LCD_LDD_11, + GPIO66_LCD_LDD_12, + GPIO67_LCD_LDD_13, + GPIO68_LCD_LDD_14, + GPIO69_LCD_LDD_15, + GPIO70_LCD_LDD_16, + GPIO71_LCD_LDD_17, + GPIO72_LCD_FCLK, + GPIO73_LCD_LCLK, + GPIO74_LCD_PCLK, + GPIO75_LCD_BIAS, +}; + +static mfp_cfg_t raumfeld_connector_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* Ethernet */ + GPIO1_nCS2, /* CS */ + GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ + + /* SSP for I2S */ + GPIO85_SSP1_SCLK, + GPIO89_SSP1_EXTCLK, + GPIO86_SSP1_FRM, + GPIO87_SSP1_TXD, + GPIO88_SSP1_RXD, + GPIO90_SSP1_SYSCLK, + + /* SSP2 for S/PDIF */ + GPIO25_SSP2_SCLK, + GPIO26_SSP2_FRM, + GPIO27_SSP2_TXD, + GPIO29_SSP2_EXTCLK, +}; + +static mfp_cfg_t raumfeld_speaker_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* Ethernet */ + GPIO1_nCS2, /* CS */ + GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ + + /* SSP for I2S */ + GPIO85_SSP1_SCLK, + GPIO89_SSP1_EXTCLK, + GPIO86_SSP1_FRM, + GPIO87_SSP1_TXD, + GPIO88_SSP1_RXD, + GPIO90_SSP1_SYSCLK, +}; + +/* + * SMSC LAN9220 Ethernet + */ + +static struct resource smc91x_resources[] = { + { + .start = PXA3xx_CS2_PHYS, + .end = PXA3xx_CS2_PHYS + 0xfffff, + .flags = IORESOURCE_MEM, + }, + { + .start = gpio_to_irq(GPIO_ETH_IRQ), + .end = gpio_to_irq(GPIO_ETH_IRQ), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, + } +}; + +static struct smsc911x_platform_config raumfeld_smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +}; + +static struct platform_device smc91x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, + .dev = { + .platform_data = &raumfeld_smsc911x_config, + } +}; + +/** + * NAND + */ + +static struct mtd_partition raumfeld_nand_partitions[] = { + { + .name = "Bootloader", + .offset = 0, + .size = 0xa0000, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "BootloaderEnvironment", + .offset = 0xa0000, + .size = 0x20000, + }, + { + .name = "BootloaderSplashScreen", + .offset = 0xc0000, + .size = 0x60000, + }, + { + .name = "UBI", + .offset = 0x120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct pxa3xx_nand_platform_data raumfeld_nand_info = { + .enable_arbiter = 1, + .keep_config = 1, + .parts = raumfeld_nand_partitions, + .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions), +}; + +/** + * USB (OHCI) support + */ + +static struct pxaohci_platform_data raumfeld_ohci_info = { + .port_mode = PMM_GLOBAL_MODE, + .flags = ENABLE_PORT1, +}; + +/** + * Rotary encoder input device + */ + +static struct rotary_encoder_platform_data raumfeld_rotary_encoder_info = { + .steps = 24, + .axis = REL_X, + .relative_axis = 1, + .gpio_a = GPIO_VOLENC_A, + .gpio_b = GPIO_VOLENC_B, + .inverted_a = 1, + .inverted_b = 0, +}; + +static struct platform_device rotary_encoder_device = { + .name = "rotary-encoder", + .id = 0, + .dev = { + .platform_data = &raumfeld_rotary_encoder_info, + } +}; + +/** + * GPIO buttons + */ + +static struct gpio_keys_button gpio_keys_button[] = { + { + .code = KEY_F1, + .type = EV_KEY, + .gpio = GPIO_KEY1, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 1", + }, + { + .code = KEY_F2, + .type = EV_KEY, + .gpio = GPIO_KEY2, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 2", + }, + { + .code = KEY_F3, + .type = EV_KEY, + .gpio = GPIO_KEY3, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 3", + }, + { + .code = KEY_F4, + .type = EV_KEY, + .gpio = GPIO_RESCUE_BOOT, + .active_low = 0, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "rescue boot button", + }, + { + .code = KEY_F5, + .type = EV_KEY, + .gpio = GPIO_DOCK_DETECT, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "dock detect", + }, + { + .code = KEY_F6, + .type = EV_KEY, + .gpio = GPIO_ON_OFF, + .active_low = 0, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "on/off button", + }, +}; + +static struct gpio_keys_platform_data gpio_keys_platform_data = { + .buttons = gpio_keys_button, + .nbuttons = ARRAY_SIZE(gpio_keys_button), + .rep = 0, +}; + +static struct platform_device raumfeld_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_keys_platform_data, + } +}; + +/** + * GPIO LEDs + */ + +static struct gpio_led raumfeld_leds[] = { + { + .name = "raumfeld:1", + .gpio = GPIO_LED1, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "raumfeld:2", + .gpio = GPIO_LED2, + .active_low = 0, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + } +}; + +static struct gpio_led_platform_data raumfeld_led_platform_data = { + .leds = raumfeld_leds, + .num_leds = ARRAY_SIZE(raumfeld_leds), +}; + +static struct platform_device raumfeld_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &raumfeld_led_platform_data, + }, +}; + +/** + * One-wire (W1 bus) support + */ + +static void w1_enable_external_pullup(int enable) +{ + gpio_set_value(GPIO_W1_PULLUP_ENABLE, enable); + msleep(100); +} + +static struct w1_gpio_platform_data w1_gpio_platform_data = { + .pin = GPIO_ONE_WIRE, + .is_open_drain = 0, + .enable_external_pullup = w1_enable_external_pullup, +}; + +struct platform_device raumfeld_w1_gpio_device = { + .name = "w1-gpio", + .dev = { + .platform_data = &w1_gpio_platform_data + } +}; + +static void __init raumfeld_w1_init(void) +{ + int ret = gpio_request(GPIO_W1_PULLUP_ENABLE, + "W1 external pullup enable"); + + if (ret < 0) + pr_warning("Unable to request GPIO_W1_PULLUP_ENABLE\n"); + else + gpio_direction_output(GPIO_W1_PULLUP_ENABLE, 0); + + platform_device_register(&raumfeld_w1_gpio_device); +} + +/** + * Framebuffer device + */ + +/* PWM controlled backlight */ +static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 100, + .dft_brightness = 100, + /* 10000 ns = 10 ms ^= 100 kHz */ + .pwm_period_ns = 10000, +}; + +static struct platform_device raumfeld_pwm_backlight_device = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &raumfeld_pwm_backlight_data, + } +}; + +/* LT3593 controlled backlight */ +static struct gpio_led raumfeld_lt3593_led = { + .name = "backlight", + .gpio = mfp_to_gpio(MFP_PIN_GPIO17), + .default_state = LEDS_GPIO_DEFSTATE_ON, +}; + +static struct gpio_led_platform_data raumfeld_lt3593_platform_data = { + .leds = &raumfeld_lt3593_led, + .num_leds = 1, +}; + +static struct platform_device raumfeld_lt3593_device = { + .name = "leds-lt3593", + .id = -1, + .dev = { + .platform_data = &raumfeld_lt3593_platform_data, + }, +}; + +static struct pxafb_mode_info sharp_lq043t3dx02_mode = { + .pixclock = 111000, + .xres = 480, + .yres = 272, + .bpp = 16, + .hsync_len = 4, + .left_margin = 2, + .right_margin = 1, + .vsync_len = 1, + .upper_margin = 3, + .lower_margin = 1, + .sync = 0, +}; + +static struct pxafb_mach_info raumfeld_sharp_lcd_info = { + .modes = &sharp_lq043t3dx02_mode, + .num_modes = 1, + .video_mem_size = 0x400000, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +static void __init raumfeld_lcd_init(void) +{ + int ret; + + set_pxa_fb_info(&raumfeld_sharp_lcd_info); + + /* Earlier devices had the backlight regulator controlled + * via PWM, later versions use another controller for that */ + if ((system_rev & 0xff) < 2) { + mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT; + pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1); + platform_device_register(&raumfeld_pwm_backlight_device); + } else + platform_device_register(&raumfeld_lt3593_device); + + ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable"); + if (ret < 0) + pr_warning("Unable to request GPIO_TFT_VA_EN\n"); + else + gpio_direction_output(GPIO_TFT_VA_EN, 1); + + ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable"); + if (ret < 0) + pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); + else + gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); +} + +/** + * SPI devices + */ + +struct spi_gpio_platform_data raumfeld_spi_platform_data = { + .sck = GPIO_SPI_CLK, + .mosi = GPIO_SPI_MOSI, + .miso = GPIO_SPI_MISO, + .num_chipselect = 3, +}; + +static struct platform_device raumfeld_spi_device = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &raumfeld_spi_platform_data, + } +}; + +static struct lis3lv02d_platform_data lis3_pdata = { + .click_flags = LIS3_CLICK_SINGLE_X | + LIS3_CLICK_SINGLE_Y | + LIS3_CLICK_SINGLE_Z, + .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, + .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | + LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | + LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, + .wakeup_thresh = 10, + .click_thresh_x = 10, + .click_thresh_y = 10, + .click_thresh_z = 10, +}; + +#define SPI_AK4104 \ +{ \ + .modalias = "ak4104", \ + .max_speed_hz = 10000, \ + .bus_num = 0, \ + .chip_select = 0, \ + .controller_data = (void *) GPIO_SPDIF_CS, \ +} + +#define SPI_LIS3 \ +{ \ + .modalias = "lis3lv02d_spi", \ + .max_speed_hz = 1000000, \ + .bus_num = 0, \ + .chip_select = 1, \ + .controller_data = (void *) GPIO_ACCEL_CS, \ + .platform_data = &lis3_pdata, \ + .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ +} + +#define SPI_DAC7512 \ +{ \ + .modalias = "dac7512", \ + .max_speed_hz = 1000000, \ + .bus_num = 0, \ + .chip_select = 2, \ + .controller_data = (void *) GPIO_MCLK_DAC_CS, \ +} + +static struct spi_board_info connector_spi_devices[] __initdata = { + SPI_AK4104, + SPI_DAC7512, +}; + +static struct spi_board_info speaker_spi_devices[] __initdata = { + SPI_DAC7512, +}; + +static struct spi_board_info controller_spi_devices[] __initdata = { + SPI_LIS3, +}; + +/** + * MMC for Marvell Libertas 8688 via SDIO + */ + +static int raumfeld_mci_init(struct device *dev, irq_handler_t isr, void *data) +{ + gpio_set_value(GPIO_W2W_RESET, 1); + gpio_set_value(GPIO_W2W_PDN, 1); + + return 0; +} + +static void raumfeld_mci_exit(struct device *dev, void *data) +{ + gpio_set_value(GPIO_W2W_RESET, 0); + gpio_set_value(GPIO_W2W_PDN, 0); +} + +static struct pxamci_platform_data raumfeld_mci_platform_data = { + .init = raumfeld_mci_init, + .exit = raumfeld_mci_exit, + .detect_delay = 20, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, +}; + +/* + * External power / charge logic + */ + +static int power_supply_init(struct device *dev) +{ + return 0; +} + +static void power_supply_exit(struct device *dev) +{ +} + +static int raumfeld_is_ac_online(void) +{ + return !gpio_get_value(GPIO_CHARGE_DC_OK); +} + +static int raumfeld_is_usb_online(void) +{ + return 0; +} + +static char *raumfeld_power_supplicants[] = { "ds2760-battery.0" }; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = raumfeld_is_ac_online, + .is_usb_online = raumfeld_is_usb_online, + .exit = power_supply_exit, + .supplied_to = raumfeld_power_supplicants, + .num_supplicants = ARRAY_SIZE(raumfeld_power_supplicants) +}; + +static struct resource power_supply_resources[] = { + { + .name = "ac", + .flags = IORESOURCE_IRQ | + IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, + .start = GPIO_CHARGE_DC_OK, + .end = GPIO_CHARGE_DC_OK, + }, +}; + +static irqreturn_t charge_done_irq(int irq, void *dev_id) +{ + struct power_supply *psy; + + psy = power_supply_get_by_name("ds2760-battery.0"); + + if (psy) + power_supply_set_battery_charged(psy); + + return IRQ_HANDLED; +} + +static struct platform_device raumfeld_power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &power_supply_info, + }, + .resource = power_supply_resources, + .num_resources = ARRAY_SIZE(power_supply_resources), +}; + +static void __init raumfeld_power_init(void) +{ + int ret; + + /* Set PEN2 high to enable maximum charge current */ + ret = gpio_request(GPIO_CHRG_PEN2, "CHRG_PEN2"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHRG_PEN2\n"); + else + gpio_direction_output(GPIO_CHRG_PEN2, 1); + + ret = gpio_request(GPIO_CHARGE_DC_OK, "CABLE_DC_OK"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHARGE_DC_OK\n"); + + ret = gpio_request(GPIO_CHARGE_USB_SUSP, "CHARGE_USB_SUSP"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHARGE_USB_SUSP\n"); + else + gpio_direction_output(GPIO_CHARGE_USB_SUSP, 0); + + power_supply_resources[0].start = gpio_to_irq(GPIO_CHARGE_DC_OK); + power_supply_resources[0].end = gpio_to_irq(GPIO_CHARGE_DC_OK); + + ret = request_irq(gpio_to_irq(GPIO_CHARGE_DONE), + &charge_done_irq, IORESOURCE_IRQ_LOWEDGE, + "charge_done", NULL); + + if (ret < 0) + printk(KERN_ERR "%s: unable to register irq %d\n", __func__, + GPIO_CHARGE_DONE); + else + platform_device_register(&raumfeld_power_supply); +} + +/* Fixed regulator for AUDIO_VA, 0-0048 maps to the cs4270 codec device */ + +static struct regulator_consumer_supply audio_va_consumer_supply = + REGULATOR_SUPPLY("va", "0-0048"); + +struct regulator_init_data audio_va_initdata = { + .consumer_supplies = &audio_va_consumer_supply, + .num_consumer_supplies = 1, + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config audio_va_config = { + .supply_name = "audio_va", + .microvolts = 5000000, + .gpio = GPIO_AUDIO_VA_ENABLE, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &audio_va_initdata, +}; + +static struct platform_device audio_va_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &audio_va_config, + }, +}; + +/* Dummy supplies for Codec's VD/VLC */ + +static struct regulator_consumer_supply audio_dummy_supplies[] = { + REGULATOR_SUPPLY("vd", "0-0048"), + REGULATOR_SUPPLY("vlc", "0-0048"), +}; + +struct regulator_init_data audio_dummy_initdata = { + .consumer_supplies = audio_dummy_supplies, + .num_consumer_supplies = ARRAY_SIZE(audio_dummy_supplies), + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config audio_dummy_config = { + .supply_name = "audio_vd", + .microvolts = 3300000, + .gpio = -1, + .init_data = &audio_dummy_initdata, +}; + +static struct platform_device audio_supply_dummy_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &audio_dummy_config, + }, +}; + +static struct platform_device *audio_regulator_devices[] = { + &audio_va_device, + &audio_supply_dummy_device, +}; + +/** + * Regulator support via MAX8660 + */ + +static struct regulator_consumer_supply vcc_mmc_supply = + REGULATOR_SUPPLY("vmmc", "pxa2xx-mci.0"); + +static struct regulator_init_data vcc_mmc_init_data = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + }, + .consumer_supplies = &vcc_mmc_supply, + .num_consumer_supplies = 1, +}; + +struct max8660_subdev_data max8660_v6_subdev_data = { + .id = MAX8660_V6, + .name = "vmmc", + .platform_data = &vcc_mmc_init_data, +}; + +static struct max8660_platform_data max8660_pdata = { + .subdevs = &max8660_v6_subdev_data, + .num_subdevs = 1, +}; + +/** + * I2C devices + */ + +static struct i2c_board_info raumfeld_pwri2c_board_info = { + .type = "max8660", + .addr = 0x34, + .platform_data = &max8660_pdata, +}; + +static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = { + .type = "cs4270", + .addr = 0x48, +}; + +static struct eeti_ts_platform_data eeti_ts_pdata = { + .irq_active_high = 1, +}; + +static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = { + .type = "eeti_ts", + .addr = 0x0a, + .irq = gpio_to_irq(GPIO_TOUCH_IRQ), + .platform_data = &eeti_ts_pdata, +}; + +static struct platform_device *raumfeld_common_devices[] = { + &raumfeld_gpio_keys_device, + &raumfeld_led_device, + &raumfeld_spi_device, +}; + +static void __init raumfeld_audio_init(void) +{ + int ret; + + ret = gpio_request(GPIO_CODEC_RESET, "cs4270 reset"); + if (ret < 0) + pr_warning("unable to request GPIO_CODEC_RESET\n"); + else + gpio_direction_output(GPIO_CODEC_RESET, 1); + + ret = gpio_request(GPIO_SPDIF_RESET, "ak4104 s/pdif reset"); + if (ret < 0) + pr_warning("unable to request GPIO_SPDIF_RESET\n"); + else + gpio_direction_output(GPIO_SPDIF_RESET, 1); + + ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset"); + if (ret < 0) + pr_warning("unable to request GPIO_MCLK_RESET\n"); + else + gpio_direction_output(GPIO_MCLK_RESET, 1); + + platform_add_devices(ARRAY_AND_SIZE(audio_regulator_devices)); +} + +static void __init raumfeld_common_init(void) +{ + int ret; + + /* The on/off button polarity has changed after revision 1 */ + if ((system_rev & 0xff) > 1) { + int i; + + for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++) + if (!strcmp(gpio_keys_button[i].desc, "on/off button")) + gpio_keys_button[i].active_low = 1; + } + + enable_irq_wake(IRQ_WAKEUP0); + + pxa3xx_set_nand_info(&raumfeld_nand_info); + pxa3xx_set_i2c_power_info(NULL); + pxa_set_ohci_info(&raumfeld_ohci_info); + pxa_set_mci_info(&raumfeld_mci_platform_data); + pxa_set_i2c_info(NULL); + pxa_set_ffuart_info(NULL); + + ret = gpio_request(GPIO_W2W_RESET, "Wi2Wi reset"); + if (ret < 0) + pr_warning("Unable to request GPIO_W2W_RESET\n"); + else + gpio_direction_output(GPIO_W2W_RESET, 0); + + ret = gpio_request(GPIO_W2W_PDN, "Wi2Wi powerup"); + if (ret < 0) + pr_warning("Unable to request GPIO_W2W_PDN\n"); + else + gpio_direction_output(GPIO_W2W_PDN, 0); + + /* this can be used to switch off the device */ + ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, + "supply shutdown"); + if (ret < 0) + pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n"); + else + gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0); + + platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices)); + i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1); +} + +static void __init raumfeld_controller_init(void) +{ + int ret; + + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_controller_pin_config)); + platform_device_register(&rotary_encoder_device); + spi_register_board_info(ARRAY_AND_SIZE(controller_spi_devices)); + i2c_register_board_info(0, &raumfeld_controller_i2c_board_info, 1); + + ret = gpio_request(GPIO_SHUTDOWN_BATT, "battery shutdown"); + if (ret < 0) + pr_warning("Unable to request GPIO_SHUTDOWN_BATT\n"); + else + gpio_direction_output(GPIO_SHUTDOWN_BATT, 0); + + raumfeld_common_init(); + raumfeld_power_init(); + raumfeld_lcd_init(); + raumfeld_w1_init(); +} + +static void __init raumfeld_connector_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_connector_pin_config)); + spi_register_board_info(ARRAY_AND_SIZE(connector_spi_devices)); + i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); + + platform_device_register(&smc91x_device); + + raumfeld_audio_init(); + raumfeld_common_init(); +} + +static void __init raumfeld_speaker_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_speaker_pin_config)); + spi_register_board_info(ARRAY_AND_SIZE(speaker_spi_devices)); + i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); + + platform_device_register(&smc91x_device); + platform_device_register(&rotary_encoder_device); + + raumfeld_audio_init(); + raumfeld_common_init(); +} + +/* physical memory regions */ +#define RAUMFELD_SDRAM_BASE 0xa0000000 /* SDRAM region */ + +#ifdef CONFIG_MACH_RAUMFELD_RC +MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_controller_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_connector_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_speaker_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif -- GitLab From e863c884cd18dca9533c352655af73d921f4a311 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 27 Nov 2009 13:47:11 +0100 Subject: [PATCH 002/370] [ARM] pxa/raumfeld: add defconfig Signed-off-by: Daniel Mack Signed-off-by: Eric Miao --- arch/arm/configs/raumfeld_defconfig | 1898 +++++++++++++++++++++++++++ 1 file changed, 1898 insertions(+) create mode 100644 arch/arm/configs/raumfeld_defconfig diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig new file mode 100644 index 0000000000000..acb1a8f30e31a --- /dev/null +++ b/arch/arm/configs/raumfeld_defconfig @@ -0,0 +1,1898 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc5 +# Sun Nov 1 21:57:32 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +CONFIG_SLOW_WORK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# + +# +# Supported PXA3xx Processor Variants +# +CONFIG_CPU_PXA300=y +# CONFIG_CPU_PXA310 is not set +CONFIG_CPU_PXA320=y +# CONFIG_CPU_PXA930 is not set +# CONFIG_CPU_PXA935 is not set +# CONFIG_CPU_PXA950 is not set + +# +# Intel/Marvell Dev Platforms (sorted by hardware release time) +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_ZYLONITE is not set +# CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_TAVOREVB is not set +# CONFIG_MACH_SAAR is not set + +# +# Third Party Dev Platforms (sorted by vendor name) +# +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_VIPER is not set +# CONFIG_MACH_BALLOON3 is not set +# CONFIG_MACH_CSB726 is not set +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_EXEDA is not set +# CONFIG_MACH_CM_X300 is not set +# CONFIG_ARCH_GUMSTIX is not set +# CONFIG_MACH_INTELMOTE2 is not set +# CONFIG_MACH_STARGATE2 is not set +# CONFIG_MACH_XCEP is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_PCM027 is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_COLIBRI300 is not set +# CONFIG_MACH_COLIBRI320 is not set + +# +# End-user Products (sorted by vendor name) +# +# CONFIG_MACH_H4700 is not set +# CONFIG_MACH_H5000 is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_MIOA701 is not set +# CONFIG_PXA_EZX is not set +# CONFIG_MACH_MP900C is not set +# CONFIG_ARCH_PXA_PALM is not set +CONFIG_MACH_RAUMFELD_RC=y +CONFIG_MACH_RAUMFELD_CONNECTOR=y +CONFIG_MACH_RAUMFELD_PROTO=y +CONFIG_MACH_RAUMFELD_SPEAKER=y +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_PXA_ESERIES is not set +CONFIG_PXA3xx=y +CONFIG_PXA_SSP=y +CONFIG_PLAT_PXA=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSC3=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_IO_36=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_XSC3L2=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_IWMMXT=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyS0,115200 rw" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_DEFAULT_PS_VALUE=1 +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +CONFIG_MTD_NAND_PXA3xx=y +# CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_ISL29003=y +CONFIG_TI_DAC7512=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=y +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_IWM is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_AX8817X is not set +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +CONFIG_USB_NET_MCS7830=y +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +# CONFIG_SPI_PXA2XX is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +CONFIG_W1=m + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_W1_MASTER_GPIO=m + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2760=m +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_PDA_POWER=y +# CONFIG_APM_POWER is not set +CONFIG_BATTERY_DS2760=m +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_LIS3_SPI=y +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX8660=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_OVERLAY is not set +# CONFIG_FB_PXA_SMARTPANEL is not set +# CONFIG_FB_PXA_PARAMETERS is not set +CONFIG_PXA3XX_GCU=y +# CONFIG_FB_MBX is not set +# CONFIG_FB_W100 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RAUMFELD_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_ARM=y +CONFIG_SND_PXA2XX_LIB=y +# CONFIG_SND_PXA2XX_AC97 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_PXA2XX_SOC=y +CONFIG_SND_PXA_SOC_SSP=y +CONFIG_SND_SOC_RAUMFELD=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AK4104=y +CONFIG_SND_SOC_CS4270=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_PXA=m +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_LT3593=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SA1100 is not set +CONFIG_RTC_DRV_PXA=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT2_FS_XIP=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_XIP=y +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- GitLab From e7cc894120bb809738cebcd87b5ed3057bbe51fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 17 Dec 2009 14:56:57 +0100 Subject: [PATCH 003/370] [ARM] pxa/ttc_dkb: remove duplicate macro definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ARRAY_AND_SIZE is already defined arch/arm/mach-mmp/common.h which is already included. Signed-off-by: Uwe Kleine-König Cc: Russell King Cc: Bin Yang Acked-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/ttc_dkb.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 8f49b2b126089..b22dec4abf78e 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -24,8 +24,6 @@ #include "common.h" -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - static unsigned long ttc_dkb_pin_config[] __initdata = { /* UART2 */ GPIO47_UART2_RXD, -- GitLab From 5113f81520278ba17c64031fa01aeafc9a83f9d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Dec 2009 10:07:15 +0100 Subject: [PATCH 004/370] imx/mx2: fold crm_regs.h into its only consumer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Rabin Vincent --- arch/arm/mach-mx2/clock_imx21.c | 231 +++++++++++++++++++++++++++- arch/arm/mach-mx2/crm_regs.h | 258 -------------------------------- 2 files changed, 230 insertions(+), 259 deletions(-) delete mode 100644 arch/arm/mach-mx2/crm_regs.h diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 91901b5d56c2e..df3ad3836576f 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -23,11 +23,240 @@ #include #include +#include #include #include #include -#include "crm_regs.h" +/* Register offsets */ +#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) +#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) +#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) +#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) +#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) +#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) +#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) +#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) +#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) +#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) +#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) +#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) +#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) +#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) + +#define CCM_CSCR_PRESC_OFFSET 29 +#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) + +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) +#define CCM_CSCR_SD_OFFSET 24 +#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) +#define CCM_CSCR_SPLLRES (1 << 22) +#define CCM_CSCR_MPLLRES (1 << 21) +#define CCM_CSCR_SSI2_OFFSET 20 +#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) +#define CCM_CSCR_SSI1_OFFSET 19 +#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) +#define CCM_CSCR_FIR_OFFSET 18 +#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) +#define CCM_CSCR_IPDIV_OFFSET 9 +#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) + +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN 1 + +#define CCM_MPCTL0_CPLM (1 << 31) +#define CCM_MPCTL0_PD_OFFSET 26 +#define CCM_MPCTL0_PD_MASK (0xf << 26) +#define CCM_MPCTL0_MFD_OFFSET 16 +#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_MPCTL0_MFI_OFFSET 10 +#define CCM_MPCTL0_MFI_MASK (0xf << 10) +#define CCM_MPCTL0_MFN_OFFSET 0 +#define CCM_MPCTL0_MFN_MASK 0x3ff + +#define CCM_MPCTL1_LF (1 << 15) +#define CCM_MPCTL1_BRMO (1 << 6) + +#define CCM_SPCTL0_CPLM (1 << 31) +#define CCM_SPCTL0_PD_OFFSET 26 +#define CCM_SPCTL0_PD_MASK (0xf << 26) +#define CCM_SPCTL0_MFD_OFFSET 16 +#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_SPCTL0_MFI_OFFSET 10 +#define CCM_SPCTL0_MFI_MASK (0xf << 10) +#define CCM_SPCTL0_MFN_OFFSET 0 +#define CCM_SPCTL0_MFN_MASK 0x3ff + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +#define CCM_OSC26MCTL_PEAK_OFFSET 16 +#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) +#define CCM_OSC26MCTL_AGC_OFFSET 8 +#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) +#define CCM_OSC26MCTL_ANATEST_OFFSET 0 +#define CCM_OSC26MCTL_ANATEST_MASK 0x3f + +#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 +#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) +#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 +#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) +#define CCM_PCDR0_NFCDIV_OFFSET 12 +#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) +#define CCM_PCDR0_48MDIV_OFFSET 5 +#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) +#define CCM_PCDR0_FIRIDIV_OFFSET 0 +#define CCM_PCDR0_FIRIDIV_MASK 0x1f +#define CCM_PCDR1_PERDIV4_OFFSET 24 +#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) +#define CCM_PCDR1_PERDIV3_OFFSET 16 +#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) +#define CCM_PCDR1_PERDIV2_OFFSET 8 +#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) +#define CCM_PCDR1_PERDIV1_OFFSET 0 +#define CCM_PCDR1_PERDIV1_MASK 0x3f + +#define CCM_PCCR_HCLK_CSI_OFFSET 31 +#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_DMA_OFFSET 30 +#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BROM_OFFSET 28 +#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_EMMA_OFFSET 27 +#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_LCDC_OFFSET 26 +#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 +#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 +#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BMI_OFFSET 23 +#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) +#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 +#define CCM_PCCR_PERCLK4_OFFSET 22 +#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 +#define CCM_PCCR_SLCDC_OFFSET 21 +#define CCM_PCCR_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_BAUD_OFFSET 20 +#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) +#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_NFC_OFFSET 19 +#define CCM_PCCR_NFC_REG CCM_PCCR0 +#define CCM_PCCR_LCDC_OFFSET 18 +#define CCM_PCCR_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_BAUD_OFFSET 17 +#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_BAUD_OFFSET 16 +#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_EMMA_OFFSET 15 +#define CCM_PCCR_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_USBOTG_OFFSET 14 +#define CCM_PCCR_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_DMA_OFFSET 13 +#define CCM_PCCR_DMA_REG CCM_PCCR0 +#define CCM_PCCR_I2C1_OFFSET 12 +#define CCM_PCCR_I2C1_REG CCM_PCCR0 +#define CCM_PCCR_GPIO_OFFSET 11 +#define CCM_PCCR_GPIO_REG CCM_PCCR0 +#define CCM_PCCR_SDHC2_OFFSET 10 +#define CCM_PCCR_SDHC2_REG CCM_PCCR0 +#define CCM_PCCR_SDHC1_OFFSET 9 +#define CCM_PCCR_SDHC1_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_OFFSET 8 +#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) +#define CCM_PCCR_FIRI_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_IPG_OFFSET 7 +#define CCM_PCCR_SSI2_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_IPG_OFFSET 6 +#define CCM_PCCR_SSI1_REG CCM_PCCR0 +#define CCM_PCCR_CSPI2_OFFSET 5 +#define CCM_PCCR_CSPI2_REG CCM_PCCR0 +#define CCM_PCCR_CSPI1_OFFSET 4 +#define CCM_PCCR_CSPI1_REG CCM_PCCR0 +#define CCM_PCCR_UART4_OFFSET 3 +#define CCM_PCCR_UART4_REG CCM_PCCR0 +#define CCM_PCCR_UART3_OFFSET 2 +#define CCM_PCCR_UART3_REG CCM_PCCR0 +#define CCM_PCCR_UART2_OFFSET 1 +#define CCM_PCCR_UART2_REG CCM_PCCR0 +#define CCM_PCCR_UART1_OFFSET 0 +#define CCM_PCCR_UART1_REG CCM_PCCR0 + +#define CCM_PCCR_OWIRE_OFFSET 31 +#define CCM_PCCR_OWIRE_REG CCM_PCCR1 +#define CCM_PCCR_KPP_OFFSET 30 +#define CCM_PCCR_KPP_REG CCM_PCCR1 +#define CCM_PCCR_RTC_OFFSET 29 +#define CCM_PCCR_RTC_REG CCM_PCCR1 +#define CCM_PCCR_PWM_OFFSET 28 +#define CCM_PCCR_PWM_REG CCM_PCCR1 +#define CCM_PCCR_GPT3_OFFSET 27 +#define CCM_PCCR_GPT3_REG CCM_PCCR1 +#define CCM_PCCR_GPT2_OFFSET 26 +#define CCM_PCCR_GPT2_REG CCM_PCCR1 +#define CCM_PCCR_GPT1_OFFSET 25 +#define CCM_PCCR_GPT1_REG CCM_PCCR1 +#define CCM_PCCR_WDT_OFFSET 24 +#define CCM_PCCR_WDT_REG CCM_PCCR1 +#define CCM_PCCR_CSPI3_OFFSET 23 +#define CCM_PCCR_CSPI3_REG CCM_PCCR1 + +#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) +#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) +#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) +#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) +#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) +#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) +#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) +#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) +#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) +#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) +#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) +#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) +#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) +#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) +#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) +#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) +#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) +#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) +#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) +#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) +#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) +#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) +#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) +#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) +#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) +#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) +#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) +#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) +#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) +#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) +#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) +#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) +#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) +#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) +#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) +#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) +#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) + +#define CCM_CCSR_32KSR (1 << 15) + +#define CCM_CCSR_CLKMODE1 (1 << 9) +#define CCM_CCSR_CLKMODE0 (1 << 8) + +#define CCM_CCSR_CLKOSEL_OFFSET 0 +#define CCM_CCSR_CLKOSEL_MASK 0x1f + +#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ +#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ static int _clk_enable(struct clk *clk) { diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h deleted file mode 100644 index 749de76b3f953..0000000000000 --- a/arch/arm/mach-mx2/crm_regs.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__ - -#include - -/* Register offsets */ -#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) -#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) -#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) -#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) -#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) -#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) -#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) -#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) -#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) -#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) -#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) -#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) -#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) -#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) - -#define CCM_CSCR_PRESC_OFFSET 29 -#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) - -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) -#define CCM_CSCR_SD_OFFSET 24 -#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) -#define CCM_CSCR_SPLLRES (1 << 22) -#define CCM_CSCR_MPLLRES (1 << 21) -#define CCM_CSCR_SSI2_OFFSET 20 -#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) -#define CCM_CSCR_SSI1_OFFSET 19 -#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) -#define CCM_CSCR_FIR_OFFSET 18 -#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) -#define CCM_CSCR_SP (1 << 17) -#define CCM_CSCR_MCU (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) -#define CCM_CSCR_IPDIV_OFFSET 9 -#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) - -#define CCM_CSCR_OSC26MDIV (1 << 4) -#define CCM_CSCR_OSC26M (1 << 3) -#define CCM_CSCR_FPM (1 << 2) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN 1 - - - -#define CCM_MPCTL0_CPLM (1 << 31) -#define CCM_MPCTL0_PD_OFFSET 26 -#define CCM_MPCTL0_PD_MASK (0xf << 26) -#define CCM_MPCTL0_MFD_OFFSET 16 -#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_MPCTL0_MFI_OFFSET 10 -#define CCM_MPCTL0_MFI_MASK (0xf << 10) -#define CCM_MPCTL0_MFN_OFFSET 0 -#define CCM_MPCTL0_MFN_MASK 0x3ff - -#define CCM_MPCTL1_LF (1 << 15) -#define CCM_MPCTL1_BRMO (1 << 6) - -#define CCM_SPCTL0_CPLM (1 << 31) -#define CCM_SPCTL0_PD_OFFSET 26 -#define CCM_SPCTL0_PD_MASK (0xf << 26) -#define CCM_SPCTL0_MFD_OFFSET 16 -#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_SPCTL0_MFI_OFFSET 10 -#define CCM_SPCTL0_MFI_MASK (0xf << 10) -#define CCM_SPCTL0_MFN_OFFSET 0 -#define CCM_SPCTL0_MFN_MASK 0x3ff - -#define CCM_SPCTL1_LF (1 << 15) -#define CCM_SPCTL1_BRMO (1 << 6) - -#define CCM_OSC26MCTL_PEAK_OFFSET 16 -#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) -#define CCM_OSC26MCTL_AGC_OFFSET 8 -#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) -#define CCM_OSC26MCTL_ANATEST_OFFSET 0 -#define CCM_OSC26MCTL_ANATEST_MASK 0x3f - -#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 -#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) -#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 -#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) -#define CCM_PCDR0_NFCDIV_OFFSET 12 -#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) -#define CCM_PCDR0_48MDIV_OFFSET 5 -#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) -#define CCM_PCDR0_FIRIDIV_OFFSET 0 -#define CCM_PCDR0_FIRIDIV_MASK 0x1f -#define CCM_PCDR1_PERDIV4_OFFSET 24 -#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) -#define CCM_PCDR1_PERDIV3_OFFSET 16 -#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) -#define CCM_PCDR1_PERDIV2_OFFSET 8 -#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) -#define CCM_PCDR1_PERDIV1_OFFSET 0 -#define CCM_PCDR1_PERDIV1_MASK 0x3f - -#define CCM_PCCR_HCLK_CSI_OFFSET 31 -#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_DMA_OFFSET 30 -#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BROM_OFFSET 28 -#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_EMMA_OFFSET 27 -#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_LCDC_OFFSET 26 -#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 -#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 -#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BMI_OFFSET 23 -#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) -#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 -#define CCM_PCCR_PERCLK4_OFFSET 22 -#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 -#define CCM_PCCR_SLCDC_OFFSET 21 -#define CCM_PCCR_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_BAUD_OFFSET 20 -#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) -#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_NFC_OFFSET 19 -#define CCM_PCCR_NFC_REG CCM_PCCR0 -#define CCM_PCCR_LCDC_OFFSET 18 -#define CCM_PCCR_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_BAUD_OFFSET 17 -#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_BAUD_OFFSET 16 -#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_EMMA_OFFSET 15 -#define CCM_PCCR_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_USBOTG_OFFSET 14 -#define CCM_PCCR_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_DMA_OFFSET 13 -#define CCM_PCCR_DMA_REG CCM_PCCR0 -#define CCM_PCCR_I2C1_OFFSET 12 -#define CCM_PCCR_I2C1_REG CCM_PCCR0 -#define CCM_PCCR_GPIO_OFFSET 11 -#define CCM_PCCR_GPIO_REG CCM_PCCR0 -#define CCM_PCCR_SDHC2_OFFSET 10 -#define CCM_PCCR_SDHC2_REG CCM_PCCR0 -#define CCM_PCCR_SDHC1_OFFSET 9 -#define CCM_PCCR_SDHC1_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_OFFSET 8 -#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) -#define CCM_PCCR_FIRI_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_IPG_OFFSET 7 -#define CCM_PCCR_SSI2_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_IPG_OFFSET 6 -#define CCM_PCCR_SSI1_REG CCM_PCCR0 -#define CCM_PCCR_CSPI2_OFFSET 5 -#define CCM_PCCR_CSPI2_REG CCM_PCCR0 -#define CCM_PCCR_CSPI1_OFFSET 4 -#define CCM_PCCR_CSPI1_REG CCM_PCCR0 -#define CCM_PCCR_UART4_OFFSET 3 -#define CCM_PCCR_UART4_REG CCM_PCCR0 -#define CCM_PCCR_UART3_OFFSET 2 -#define CCM_PCCR_UART3_REG CCM_PCCR0 -#define CCM_PCCR_UART2_OFFSET 1 -#define CCM_PCCR_UART2_REG CCM_PCCR0 -#define CCM_PCCR_UART1_OFFSET 0 -#define CCM_PCCR_UART1_REG CCM_PCCR0 - -#define CCM_PCCR_OWIRE_OFFSET 31 -#define CCM_PCCR_OWIRE_REG CCM_PCCR1 -#define CCM_PCCR_KPP_OFFSET 30 -#define CCM_PCCR_KPP_REG CCM_PCCR1 -#define CCM_PCCR_RTC_OFFSET 29 -#define CCM_PCCR_RTC_REG CCM_PCCR1 -#define CCM_PCCR_PWM_OFFSET 28 -#define CCM_PCCR_PWM_REG CCM_PCCR1 -#define CCM_PCCR_GPT3_OFFSET 27 -#define CCM_PCCR_GPT3_REG CCM_PCCR1 -#define CCM_PCCR_GPT2_OFFSET 26 -#define CCM_PCCR_GPT2_REG CCM_PCCR1 -#define CCM_PCCR_GPT1_OFFSET 25 -#define CCM_PCCR_GPT1_REG CCM_PCCR1 -#define CCM_PCCR_WDT_OFFSET 24 -#define CCM_PCCR_WDT_REG CCM_PCCR1 -#define CCM_PCCR_CSPI3_OFFSET 23 -#define CCM_PCCR_CSPI3_REG CCM_PCCR1 - -#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) -#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) -#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) -#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) -#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) -#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) -#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) -#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) -#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) -#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) -#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) -#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) -#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) -#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) -#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) -#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) -#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) -#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) -#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) -#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) -#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) -#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) -#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) -#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) -#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) -#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) -#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) -#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) -#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) -#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) -#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) -#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) -#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) -#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) -#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) -#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) -#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) - - -#define CCM_CCSR_32KSR (1 << 15) - -#define CCM_CCSR_CLKMODE1 (1 << 9) -#define CCM_CCSR_CLKMODE0 (1 << 8) - -#define CCM_CCSR_CLKOSEL_OFFSET 0 -#define CCM_CCSR_CLKOSEL_MASK 0x1f - -#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ -#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ - -#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ -- GitLab From 318859fdff2caf4455749ff0097efb8f3e9b6879 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Dec 2009 11:04:06 +0100 Subject: [PATCH 005/370] imx/clock-imx21: use a macro to define registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way the base address isn't hard coded in each register definition Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Rabin Vincent --- arch/arm/mach-mx2/clock_imx21.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index df3ad3836576f..1922e531ba46f 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -28,21 +28,23 @@ #include #include +#define IO_ADDR_CCM(off) (IO_ADDRESS(CCM_BASE_ADDR) + (off)) + /* Register offsets */ -#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) -#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) -#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) -#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) -#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) -#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) -#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) -#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) -#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) -#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) -#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) -#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) -#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) -#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) #define CCM_CSCR_PRESC_OFFSET 29 #define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) -- GitLab From b70564686a3a3eac7c2da09722091dcf5b07d5a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Dec 2009 09:57:27 +0100 Subject: [PATCH 006/370] imx/clock-imx27: use a macro to define registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way the base address isn't hard coded in each register definition Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Rabin Vincent Cc: Javier Martin Cc: Valentin Longchamp --- arch/arm/mach-mx2/clock_imx27.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index b010bf9ceaaba..a53320860986b 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -29,21 +29,23 @@ #include #include +#define IO_ADDR_CCM(off) (IO_ADDRESS(CCM_BASE_ADDR) + (off)) + /* Register offsets */ -#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) -#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) -#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) -#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) -#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) -#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) -#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) -#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) -#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) -#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) -#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) -#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) -#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) -#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) #define CCM_CSCR_UPDATE_DIS (1 << 31) #define CCM_CSCR_SSI2 (1 << 23) -- GitLab From 3f35d1f5e4507ea4eb7ff5feaf624737c1b47631 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 9 Dec 2009 11:32:11 +0100 Subject: [PATCH 007/370] imx/mach-mx2: use constants namespaced by the corresponding SOC (easy part) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This just leaves devices.c, generic.c and serial.c to clean up. As these files are used on more than one SOC they need some more work. Signed-off-by: Uwe Kleine-König Cc: Holger Schurig Cc: Rabin Vincent Cc: Javier Martin Cc: Valentin Longchamp Cc: Jean Delvare Cc: Eric Benard Cc: Ivo Clarysse Cc: Vladimir Barinov Cc: Daniel Schaeffer Cc: Simon POLETTE Cc: Fabio Estevam Cc: Alan Carvalho de Assis Cc: Luotao Fu --- arch/arm/mach-mx2/clock_imx21.c | 5 +++-- arch/arm/mach-mx2/clock_imx27.c | 5 +++-- arch/arm/mach-mx2/cpu_imx27.c | 2 +- arch/arm/mach-mx2/eukrea_cpuimx27.c | 12 ++++++------ arch/arm/mach-mx2/mx21ads.c | 10 +++++----- arch/arm/mach-mx2/mx27ads.c | 6 +++--- arch/arm/mach-mx2/mx27lite.c | 4 ++-- arch/arm/mach-mx2/mx27pdk.c | 4 ++-- arch/arm/mach-mx2/mxt_td60.c | 4 ++-- arch/arm/mach-mx2/pca100.c | 4 ++-- arch/arm/mach-mx2/pcm038.c | 8 ++++---- arch/arm/mach-mx2/pcm970-baseboard.c | 4 ++-- 12 files changed, 35 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 1922e531ba46f..6ab3c729a4562 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -28,7 +28,7 @@ #include #include -#define IO_ADDR_CCM(off) (IO_ADDRESS(CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (IO_ADDRESS(MX21_CCM_BASE_ADDR) + (off)) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) @@ -1235,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&uart_clk[0]); #endif - mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); + mxc_timer_init(&gpt_clk[0], IO_ADDRESS(MX21_GPT1_BASE_ADDR), + MX21_INT_GPT1); return 0; } diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index a53320860986b..6db98566a7208 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -29,7 +29,7 @@ #include #include -#define IO_ADDR_CCM(off) (IO_ADDRESS(CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (IO_ADDRESS(MX27_CCM_BASE_ADDR) + (off)) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) @@ -757,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif - mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); + mxc_timer_init(&gpt1_clk, IO_ADDRESS(MX27_GPT1_BASE_ADDR), + MX27_INT_GPT1); return 0; } diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c index d9e3bf9644c9e..8c50c5e7c0339 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-mx2/cpu_imx27.c @@ -39,7 +39,7 @@ static void query_silicon_parameter(void) * the silicon revision very early we read it here to * avoid any further hooks */ - val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); + val = __raw_readl(IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); cpu_silicon_rev = (int)(val >> 28); cpu_partnumber = (int)((val >> 12) & 0xFFFF); diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c index 7b187606682c8..8e4f3d08e32ca 100644 --- a/arch/arm/mach-mx2/eukrea_cpuimx27.c +++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c @@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) static struct plat_serial8250_port serial_platform_data[] = { { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000), .irq = IRQ_GPIOB(23), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000), .irq = IRQ_GPIOB(22), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000), .irq = IRQ_GPIOB(27), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000), .irq = IRQ_GPIOB(30), .uartclk = 14745600, .regshift = 1, @@ -224,8 +224,8 @@ static struct sys_timer eukrea_cpuimx27_timer = { }; MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c index cf5f77cbc2f1c..eb4a6e855595b 100644 --- a/arch/arm/mach-mx2/mx21ads.c +++ b/arch/arm/mach-mx2/mx21ads.c @@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = { }; static struct resource mx21ads_flash_resource = { - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + 0x02000000 - 1, + .start = MX21_CS0_BASE_ADDR, + .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, .flags = IORESOURCE_MEM, }; @@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = { */ { .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(CS1_BASE_ADDR), + .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), .length = MX21ADS_MMIO_SIZE, .type = MT_DEVICE, }, @@ -284,8 +284,8 @@ static struct sys_timer mx21ads_timer = { MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX21_AIPI_BASE_ADDR, + .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx21ads_map_io, .init_irq = mx21_init_irq, diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c index 83e412b713e67..385fc1c9ad389 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mx27ads.c @@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = { static struct map_desc mx27ads_io_desc[] __initdata = { { .virtual = PBC_BASE_ADDRESS, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), .length = SZ_1M, .type = MT_DEVICE, }, @@ -334,8 +334,8 @@ static void __init mx27ads_map_io(void) MACHINE_START(MX27ADS, "Freescale i.MX27ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27ads_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c index 82ea227ea0cfc..ca6ab1265f3ee 100644 --- a/arch/arm/mach-mx2/mx27lite.c +++ b/arch/arm/mach-mx2/mx27lite.c @@ -85,8 +85,8 @@ static struct sys_timer mx27lite_timer = { }; MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c index 6761d1b79e438..595fea46b6f7a 100644 --- a/arch/arm/mach-mx2/mx27pdk.c +++ b/arch/arm/mach-mx2/mx27pdk.c @@ -85,8 +85,8 @@ static struct sys_timer mx27pdk_timer = { MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mxt_td60.c index 8bcc1a5b88296..9ed4e492fc73e 100644 --- a/arch/arm/mach-mx2/mxt_td60.c +++ b/arch/arm/mach-mx2/mxt_td60.c @@ -284,8 +284,8 @@ static struct sys_timer mxt_td60_timer = { MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c index aea3d340d2e16..55dbf5a64e006 100644 --- a/arch/arm/mach-mx2/pca100.c +++ b/arch/arm/mach-mx2/pca100.c @@ -233,8 +233,8 @@ static struct sys_timer pca100_timer = { }; MACHINE_START(PCA100, "phyCARD-i.MX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index 906d59b0a7aa4..a2e2ea16c1360 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c @@ -108,8 +108,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { }; static struct resource pcm038_sram_resource = { - .start = CS1_BASE_ADDR, - .end = CS1_BASE_ADDR + 512 * 1024 - 1, + .start = MX27_CS1_BASE_ADDR, + .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1, .flags = IORESOURCE_MEM, }; @@ -328,8 +328,8 @@ static struct sys_timer pcm038_timer = { }; MACHINE_START(PCM038, "phyCORE-i.MX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index 3cb7f457e5d08..60d54465ada1f 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c @@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = { static struct resource pcm970_sja1000_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0x100 - 1, + .start = MX27_CS4_BASE_ADDR, + .end = MX27_CS4_BASE_ADDR + 0x100 - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_GPIOE(19), -- GitLab From f568dd7f5805bfa9e99f6df866300498b55eb8f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 9 Dec 2009 11:57:21 +0100 Subject: [PATCH 008/370] imx/mach-mx3: use constants namespaced by the corresponding SOC (easy part) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This just leaves cpu.c, devices.c and mm.c to clean up. As these files are used on more than one SOC they need some more work. Signed-off-by: Uwe Kleine-König Cc: Russell King Cc: Alberto Panizzo Cc: Valentin Longchamp Cc: Daniel Mack Cc: Guennadi Liakhovetski Cc: Yoichi Yuasa Cc: Mark Brown Cc: Magnus Lilja Cc: Fabio Estevam Cc: Sascha Hauer Cc: Harro Haan Cc: Jean Delvare Cc: Luotao Fu Cc: Ilya Yanok --- arch/arm/mach-mx3/armadillo5x0.c | 12 +++++------ arch/arm/mach-mx3/clock-imx35.c | 4 ++-- arch/arm/mach-mx3/clock.c | 4 ++-- arch/arm/mach-mx3/crm_regs.h | 2 +- arch/arm/mach-mx3/iomux.c | 2 +- arch/arm/mach-mx3/kzmarm11.c | 20 +++++++++---------- arch/arm/mach-mx3/mx31ads.c | 14 ++++++------- arch/arm/mach-mx3/mx31lilly.c | 8 ++++---- arch/arm/mach-mx3/mx31lite.c | 14 ++++++------- arch/arm/mach-mx3/mx31moboard.c | 4 ++-- arch/arm/mach-mx3/mx31pdk.c | 10 +++++----- arch/arm/mach-mx3/mx35pdk.c | 4 ++-- arch/arm/mach-mx3/pcm037.c | 16 +++++++-------- arch/arm/mach-mx3/pcm043.c | 4 ++-- arch/arm/mach-mx3/qong.c | 14 ++++++------- .../plat-mxc/include/mach/board-kzmarm11.h | 18 ++++++++--------- 16 files changed, 75 insertions(+), 75 deletions(-) diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index 54aab401dbdf7..aac5f81c2420c 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c @@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { static struct resource armadillo5x0_nor_flash_resource = { .flags = IORESOURCE_MEM, - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + SZ_64M - 1, + .start = MX31_CS0_BASE_ADDR, + .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, }; static struct platform_device armadillo5x0_nor_flash = { @@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = { */ static struct resource armadillo5x0_smc911x_resources[] = { { - .start = CS3_BASE_ADDR, - .end = CS3_BASE_ADDR + SZ_32M - 1, + .start = MX31_CS3_BASE_ADDR, + .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), @@ -406,8 +406,8 @@ static struct sys_timer armadillo5x0_timer = { MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 7584b4c6c556d..e65e862774ef4 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -28,7 +28,7 @@ #include #include -#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define CCM_BASE IO_ADDRESS(MX35_CCM_BASE_ADDR) #define CCM_CCMR 0x00 #define CCM_PDR0 0x04 @@ -504,7 +504,7 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); - mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); + mxc_timer_init(&gpt_clk, IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index 27a318af0d200..cc03a61116e2e 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -618,14 +618,14 @@ int __init mx31_clocks_init(unsigned long fref) mx31_read_cpu_rev(); - if (mx31_revision() >= CHIP_REV_2_0) { + if (mx31_revision() >= MX31_CHIP_REV_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; __raw_writel(reg, MXC_CCM_PMCR1); } - mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); + mxc_timer_init(&ipg_clk, IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index adfa3627ad842..e25cd92dd427f 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h @@ -24,7 +24,7 @@ #define CKIH_CLK_FREQ_27MHZ 27000000 #define CKIL_CLK_FREQ 32768 -#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define MXC_CCM_BASE IO_ADDRESS(MX31_CCM_BASE_ADDR) /* Register addresses */ #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index c66ccbcdc11b8..6381e561961cc 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c @@ -29,7 +29,7 @@ /* * IOMUX register (base) addresses */ -#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) +#define IOMUX_BASE IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) #define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) #define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) #define IOMUXGPR (IOMUX_BASE + 0x008) diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/kzmarm11.c index 6fa99ce3008a9..849631ecfe4ba 100644 --- a/arch/arm/mach-mx3/kzmarm11.c +++ b/arch/arm/mach-mx3/kzmarm11.c @@ -128,8 +128,8 @@ static struct smsc911x_platform_config kzm_smsc9118_config = { static struct resource kzm_smsc9118_resources[] = { { - .start = CS5_BASE_ADDR, - .end = CS5_BASE_ADDR + SZ_128K - 1, + .start = MX31_CS5_BASE_ADDR, + .end = MX31_CS5_BASE_ADDR + SZ_128K - 1, .flags = IORESOURCE_MEM, }, { @@ -222,15 +222,15 @@ static void __init kzm_board_init(void) */ static struct map_desc kzm_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE, .type = MT_DEVICE }, { - .virtual = CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS5_BASE_ADDR), - .length = CS5_SIZE, + .virtual = MX31_CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), + .length = MX31_CS5_SIZE, .type = MT_DEVICE }, }; @@ -258,8 +258,8 @@ static struct sys_timer kzm_timer = { * initialize __mach_desc_KZM_ARM11_01 data structure. */ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = kzm_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index 3e7bafa2ddbbf..66991165127c2 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -60,7 +60,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), + .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), .irq = EXPIO_INT_XUART_INTA, .uartclk = 14745600, .regshift = 0, @@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, }, { .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), + .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), .irq = EXPIO_INT_XUART_INTB, .uartclk = 14745600, .regshift = 0, @@ -494,9 +494,9 @@ static void mxc_init_i2c(void) */ static struct map_desc mx31ads_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE / 2, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE / 2, .type = MT_DEVICE }, }; @@ -541,8 +541,8 @@ static struct sys_timer mx31ads_timer = { */ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31ads_map_io, .init_irq = mx31ads_init_irq, diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c index 9ce029f554b9a..ffccea98531b4 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mx31lilly.c @@ -57,8 +57,8 @@ static struct resource smsc91x_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0xffff, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 0xffff, .flags = IORESOURCE_MEM, }, { @@ -195,8 +195,8 @@ static struct sys_timer mx31lilly_timer = { }; MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index 789b20d1730fd..1e263978b1d85 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -82,8 +82,8 @@ static struct smsc911x_platform_config smsc911x_config = { static struct resource smsc911x_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0x100, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 0x100, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), @@ -214,9 +214,9 @@ static struct platform_device physmap_flash_device = { */ static struct map_desc mx31lite_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE, .type = MT_DEVICE } }; @@ -287,8 +287,8 @@ struct sys_timer mx31lite_timer = { MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31lite_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index cfd605d078ecf..9428827f89444 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -569,8 +569,8 @@ struct sys_timer mx31moboard_timer = { MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c index 18715f1aa7eb6..e71e3b4016284 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mx31pdk.c @@ -211,9 +211,9 @@ static int __init mx31pdk_init_expio(void) */ static struct map_desc mx31pdk_io_desc[] __initdata = { { - .virtual = CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS5_BASE_ADDR), - .length = CS5_SIZE, + .virtual = MX31_CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), + .length = MX31_CS5_SIZE, .type = MT_DEVICE, }, }; @@ -256,8 +256,8 @@ static struct sys_timer mx31pdk_timer = { */ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31pdk_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c index 0bbc65ea23c8b..2d11bf053c785 100644 --- a/arch/arm/mach-mx3/mx35pdk.c +++ b/arch/arm/mach-mx3/mx35pdk.c @@ -106,8 +106,8 @@ struct sys_timer mx35pdk_timer = { MACHINE_START(MX35_3DS, "Freescale MX35PDK") /* Maintainer: Freescale Semiconductor, Inc */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 5be396917c999..701fac9894328 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c @@ -248,8 +248,8 @@ static struct imxuart_platform_data uart_pdata = { static struct resource smsc911x_resources[] = { { - .start = CS1_BASE_ADDR + 0x300, - .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, + .start = MX31_CS1_BASE_ADDR + 0x300, + .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), @@ -281,8 +281,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { }; static struct resource pcm038_sram_resource = { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 512 * 1024 - 1, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, .flags = IORESOURCE_MEM, }; @@ -536,8 +536,8 @@ static struct mx3fb_platform_data mx3fb_pdata = { static struct resource pcm970_sja1000_resources[] = { { - .start = CS5_BASE_ADDR, - .end = CS5_BASE_ADDR + 0x100 - 1, + .start = MX31_CS5_BASE_ADDR, + .end = MX31_CS5_BASE_ADDR + 0x100 - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), @@ -636,8 +636,8 @@ struct sys_timer pcm037_timer = { MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c index e3aa829be586c..1212194fb9c2e 100644 --- a/arch/arm/mach-mx3/pcm043.c +++ b/arch/arm/mach-mx3/pcm043.c @@ -248,8 +248,8 @@ struct sys_timer pcm043_timer = { MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c index 044511f1b9a99..3c1e7364f74a2 100644 --- a/arch/arm/mach-mx3/qong.c +++ b/arch/arm/mach-mx3/qong.c @@ -43,7 +43,7 @@ #define QONG_FPGA_VERSION(major, minor, rev) \ (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) -#define QONG_FPGA_BASEADDR CS1_BASE_ADDR +#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR #define QONG_FPGA_PERIPH_SIZE (1 << 24) #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR @@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = { }; static struct resource qong_flash_resource = { - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, + .start = MX31_CS0_BASE_ADDR, + .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1, .flags = IORESOURCE_MEM, }; @@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = { }; static struct resource qong_nand_resource = { - .start = CS3_BASE_ADDR, - .end = CS3_BASE_ADDR + SZ_32M - 1, + .start = MX31_CS3_BASE_ADDR, + .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -275,8 +275,8 @@ static struct sys_timer qong_timer = { MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h index 05ff2f31ef1f5..93cc66f104c78 100644 --- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h +++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h @@ -21,19 +21,19 @@ /* * KZM-ARM11-01 Board Control Registers on FPGA */ -#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) +#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) +#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) +#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) +#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) +#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) +#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) +#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) +#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) /* * External UART for touch panel on FPGA */ -#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) +#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) #endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ -- GitLab From 60d644cae9d96e13547c69fbac22e800790e6054 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 9 Dec 2009 19:52:57 +0100 Subject: [PATCH 009/370] imx/mx3: rename clock.c and iomux.c to {clock,iomux}-imx31.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files are only used on imx31. This makes the name consistent with the imx35 files. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Daniel Mack Cc: Fabio Estevam Cc: Valentin Longchamp --- arch/arm/mach-mx3/Makefile | 2 +- arch/arm/mach-mx3/{clock.c => clock-imx31.c} | 0 arch/arm/mach-mx3/{iomux.c => iomux-imx31.c} | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/mach-mx3/{clock.c => clock-imx31.c} (100%) rename arch/arm/mach-mx3/{iomux.c => iomux-imx31.c} (100%) diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 93c7b296be6a4..03e25d604455a 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,7 +5,7 @@ # Object file lists. obj-y := mm.o devices.o cpu.o -obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o +obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock-imx31.c similarity index 100% rename from arch/arm/mach-mx3/clock.c rename to arch/arm/mach-mx3/clock-imx31.c diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux-imx31.c similarity index 100% rename from arch/arm/mach-mx3/iomux.c rename to arch/arm/mach-mx3/iomux-imx31.c -- GitLab From 5c4c62bcb27cf9200553edeaecac1ab8cc2add91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 9 Dec 2009 20:09:35 +0100 Subject: [PATCH 010/370] imx/mx1: add newline at end of Makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Paulius Zaleckas Cc: Darius Augulis Cc: Mauro Carvalho Chehab --- arch/arm/mach-mx1/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index 7f86fe073ec67..b72f53638543b 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o # Specific board support obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += scb9328.o \ No newline at end of file +obj-$(CONFIG_MACH_SCB9328) += scb9328.o -- GitLab From 95c00464dda726c49ac8c45228bee8bf395ffa97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 9 Dec 2009 20:12:07 +0100 Subject: [PATCH 011/370] imx/mx1: rename files defining a machine to mach-$mach.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Paulius Zaleckas Cc: Darius Augulis Cc: Mauro Carvalho Chehab --- arch/arm/mach-mx1/Makefile | 4 ++-- arch/arm/mach-mx1/{mx1ads.c => mach-mx1ads.c} | 2 +- arch/arm/mach-mx1/{scb9328.c => mach-scb9328.c} | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm/mach-mx1/{mx1ads.c => mach-mx1ads.c} (98%) rename arch/arm/mach-mx1/{scb9328.c => mach-scb9328.c} (98%) diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index b72f53638543b..297d17210e116 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile @@ -10,5 +10,5 @@ obj-y += generic.o clock.o devices.o obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o # Specific board support -obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += scb9328.o +obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o +obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c similarity index 98% rename from arch/arm/mach-mx1/mx1ads.c rename to arch/arm/mach-mx1/mach-mx1ads.c index 30f04e56fafeb..a39433afb5123 100644 --- a/arch/arm/mach-mx1/mx1ads.c +++ b/arch/arm/mach-mx1/mach-mx1ads.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-imx/mx1ads.c + * arch/arm/mach-imx/mach-mx1ads.c * * Initially based on: * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c similarity index 98% rename from arch/arm/mach-mx1/scb9328.c rename to arch/arm/mach-mx1/mach-scb9328.c index 325d98df6053d..b9530d76e99d2 100644 --- a/arch/arm/mach-mx1/scb9328.c +++ b/arch/arm/mach-mx1/mach-scb9328.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-mx1/scb9328.c + * linux/arch/arm/mach-mx1/mach-scb9328.c * * Copyright (c) 2004 Sascha Hauer * Copyright (c) 2006-2008 Juergen Beisert -- GitLab From bc727390f0a7d7069a39cd97451fa890caa0010e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Dec 2009 10:19:43 +0100 Subject: [PATCH 012/370] imx: rename Kconfig symbol for "Eukrea CPUIMX27 module" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not using MACH_CPUIMX27 makes machine_is_cpuimx27 always return 0 independent of building support for this machine. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Jean Delvare Cc: Eric Benard --- arch/arm/mach-mx2/Kconfig | 6 +++--- arch/arm/mach-mx2/Makefile | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index b96c6a3893637..a8bc33749b28a 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -55,7 +55,7 @@ config MACH_PCM970_BASEBOARD endchoice -config MACH_EUKREA_CPUIMX27 +config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" depends on MACH_MX27 help @@ -64,14 +64,14 @@ config MACH_EUKREA_CPUIMX27 config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" - depends on MACH_EUKREA_CPUIMX27 + depends on MACH_CPUIMX27 help This adds support for the internal SDHC2 used on CPUIMX27 used for wifi or eMMC. choice prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX27 + depends on MACH_CPUIMX27 default MACH_EUKREA_MBIMX27_BASEBOARD config MACH_EUKREA_MBIMX27_BASEBOARD diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 52aca0aaf9b5d..2ba9997c70871 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o +obj-$(CONFIG_MACH_CPUIMX27) += eukrea_cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += pca100.o obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o -- GitLab From f747f935431c796749752037b8cf7d3f76e96b47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Dec 2009 10:25:07 +0100 Subject: [PATCH 013/370] imx: rename Kconfig symbol for "LogicPD MX27 LITEKIT platform" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not using MACH_IMX27LITE makes machine_is_imx27lite always return 0 independent of building support for this machine. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Daniel Schaeffer --- arch/arm/configs/mx27_defconfig | 2 +- arch/arm/mach-mx2/Kconfig | 2 +- arch/arm/mach-mx2/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig index edfdd6faf800f..b4c1366e9e0d2 100644 --- a/arch/arm/configs/mx27_defconfig +++ b/arch/arm/configs/mx27_defconfig @@ -200,7 +200,7 @@ CONFIG_MACH_MX27ADS=y CONFIG_MACH_PCM038=y CONFIG_MACH_PCM970_BASEBOARD=y CONFIG_MACH_MX27_3DS=y -CONFIG_MACH_MX27LITE=y +CONFIG_MACH_IMX27LITE=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index a8bc33749b28a..7bc797c1c3a2e 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -90,7 +90,7 @@ config MACH_MX27_3DS Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. -config MACH_MX27LITE +config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" depends on MACH_MX27 help diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 2ba9997c70871..a3406984e6bd0 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o obj-$(CONFIG_MACH_PCM038) += pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o -obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o +obj-$(CONFIG_MACH_IMX27LITE) += mx27lite.o obj-$(CONFIG_MACH_CPUIMX27) += eukrea_cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += pca100.o -- GitLab From 386c5cf7a9a1d6856f17bde43174f751fac1bc0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Dec 2009 10:34:04 +0100 Subject: [PATCH 014/370] imx/mx2: rename files defining a machine to mach-$mach.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Eric Benard --- arch/arm/mach-mx2/Makefile | 17 ++++++++--------- .../{eukrea_cpuimx27.c => mach-cpuimx27.c} | 0 .../mach-mx2/{mx27lite.c => mach-imx27lite.c} | 0 arch/arm/mach-mx2/{mx21ads.c => mach-mx21ads.c} | 0 .../arm/mach-mx2/{mx27pdk.c => mach-mx27_3ds.c} | 0 arch/arm/mach-mx2/{mx27ads.c => mach-mx27ads.c} | 0 .../mach-mx2/{mxt_td60.c => mach-mxt_td60.c} | 0 arch/arm/mach-mx2/{pca100.c => mach-pca100.c} | 0 arch/arm/mach-mx2/{pcm038.c => mach-pcm038.c} | 0 9 files changed, 8 insertions(+), 9 deletions(-) rename arch/arm/mach-mx2/{eukrea_cpuimx27.c => mach-cpuimx27.c} (100%) rename arch/arm/mach-mx2/{mx27lite.c => mach-imx27lite.c} (100%) rename arch/arm/mach-mx2/{mx21ads.c => mach-mx21ads.c} (100%) rename arch/arm/mach-mx2/{mx27pdk.c => mach-mx27_3ds.c} (100%) rename arch/arm/mach-mx2/{mx27ads.c => mach-mx27ads.c} (100%) rename arch/arm/mach-mx2/{mxt_td60.c => mach-mxt_td60.c} (100%) rename arch/arm/mach-mx2/{pca100.c => mach-pca100.c} (100%) rename arch/arm/mach-mx2/{pcm038.c => mach-pcm038.c} (100%) diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index a3406984e6bd0..3710893a94ab4 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -11,14 +11,13 @@ obj-$(CONFIG_MACH_MX21) += clock_imx21.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o obj-$(CONFIG_MACH_MX27) += clock_imx27.o -obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o -obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o -obj-$(CONFIG_MACH_PCM038) += pcm038.o +obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o +obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o -obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o -obj-$(CONFIG_MACH_IMX27LITE) += mx27lite.o -obj-$(CONFIG_MACH_CPUIMX27) += eukrea_cpuimx27.o +obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o +obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o +obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o -obj-$(CONFIG_MACH_PCA100) += pca100.o -obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o - +obj-$(CONFIG_MACH_PCA100) += mach-pca100.o +obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c similarity index 100% rename from arch/arm/mach-mx2/eukrea_cpuimx27.c rename to arch/arm/mach-mx2/mach-cpuimx27.c diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c similarity index 100% rename from arch/arm/mach-mx2/mx27lite.c rename to arch/arm/mach-mx2/mach-imx27lite.c diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c similarity index 100% rename from arch/arm/mach-mx2/mx21ads.c rename to arch/arm/mach-mx2/mach-mx21ads.c diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mach-mx27_3ds.c similarity index 100% rename from arch/arm/mach-mx2/mx27pdk.c rename to arch/arm/mach-mx2/mach-mx27_3ds.c diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c similarity index 100% rename from arch/arm/mach-mx2/mx27ads.c rename to arch/arm/mach-mx2/mach-mx27ads.c diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c similarity index 100% rename from arch/arm/mach-mx2/mxt_td60.c rename to arch/arm/mach-mx2/mach-mxt_td60.c diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/mach-pca100.c similarity index 100% rename from arch/arm/mach-mx2/pca100.c rename to arch/arm/mach-mx2/mach-pca100.c diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c similarity index 100% rename from arch/arm/mach-mx2/pcm038.c rename to arch/arm/mach-mx2/mach-pcm038.c -- GitLab From edc34a90613bbb393c019882f85b74f24066ca19 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jan 2010 18:24:49 +0000 Subject: [PATCH 015/370] mx31ads: Convert 1133-EV1 to use dev_name to specify consumer devices This means we don't need to go running round working out struct devices at runtime. Signed-off-by: Mark Brown Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31ads.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index 0497c152be18c..cda570be124e4 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -307,12 +307,8 @@ static struct regulator_init_data ldo1_data = { }; static struct regulator_consumer_supply ldo2_consumers[] = { - { - .supply = "AVDD", - }, - { - .supply = "HPVDD", - }, + { .supply = "AVDD", .dev_name = "1-001a" }, + { .supply = "HPVDD", .dev_name = "1-001a" }, }; /* CODEC and SIM */ @@ -382,8 +378,6 @@ static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { static int mx31_wm8350_init(struct wm8350 *wm8350) { - int i; - wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, @@ -419,10 +413,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350) WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, WM8350_GPIO_DEBOUNCE_OFF); - /* Fix up for our own supplies. */ - for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++) - ldo2_consumers[i].dev = wm8350->dev; - wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); -- GitLab From becc670a1bda8f240a93e45d9794f9f79713ffdb Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jan 2010 18:24:50 +0000 Subject: [PATCH 016/370] mx31ads: Allow enable/disable of switchable supplies They will be automatically powered off at startup so users will need to enable them for use. Signed-off-by: Mark Brown Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31ads.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index cda570be124e4..718fbe6615ef6 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -302,6 +302,7 @@ static struct regulator_init_data ldo1_data = { .min_uV = 2800000, .max_uV = 2800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, .apply_uV = 1, }, }; @@ -318,6 +319,7 @@ static struct regulator_init_data ldo2_data = { .min_uV = 3300000, .max_uV = 3300000, .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, .apply_uV = 1, }, .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), -- GitLab From 321ed164369bb5e4888eb24d70ebc64c232ffc31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 10 Dec 2009 10:41:26 +0100 Subject: [PATCH 017/370] imx/mx3: rename files defining a machine to mach-$mach.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While at it remove some superfluous parenthesis. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Daniel Mack Cc: Fabio Estevam Cc: Valentin Longchamp --- arch/arm/mach-mx3/Makefile | 24 +++++++++---------- .../{armadillo5x0.c => mach-armadillo5x0.c} | 2 +- .../{kzmarm11.c => mach-kzm_arm11_01.c} | 2 +- .../mach-mx3/{mx31pdk.c => mach-mx31_3ds.c} | 2 +- .../mach-mx3/{mx31ads.c => mach-mx31ads.c} | 2 +- .../{mx31lilly.c => mach-mx31lilly.c} | 2 +- .../mach-mx3/{mx31lite.c => mach-mx31lite.c} | 2 +- .../{mx31moboard.c => mach-mx31moboard.c} | 2 +- .../mach-mx3/{mx35pdk.c => mach-mx35pdk.c} | 0 arch/arm/mach-mx3/{pcm037.c => mach-pcm037.c} | 2 +- .../{pcm037_eet.c => mach-pcm037_eet.c} | 0 arch/arm/mach-mx3/{pcm043.c => mach-pcm043.c} | 0 arch/arm/mach-mx3/{qong.c => mach-qong.c} | 2 +- 13 files changed, 21 insertions(+), 21 deletions(-) rename arch/arm/mach-mx3/{armadillo5x0.c => mach-armadillo5x0.c} (99%) rename arch/arm/mach-mx3/{kzmarm11.c => mach-kzm_arm11_01.c} (99%) rename arch/arm/mach-mx3/{mx31pdk.c => mach-mx31_3ds.c} (99%) rename arch/arm/mach-mx3/{mx31ads.c => mach-mx31ads.c} (99%) rename arch/arm/mach-mx3/{mx31lilly.c => mach-mx31lilly.c} (98%) rename arch/arm/mach-mx3/{mx31lite.c => mach-mx31lite.c} (99%) rename arch/arm/mach-mx3/{mx31moboard.c => mach-mx31moboard.c} (99%) rename arch/arm/mach-mx3/{mx35pdk.c => mach-mx35pdk.c} (100%) rename arch/arm/mach-mx3/{pcm037.c => mach-pcm037.c} (99%) rename arch/arm/mach-mx3/{pcm037_eet.c => mach-pcm037_eet.c} (100%) rename arch/arm/mach-mx3/{pcm043.c => mach-pcm043.c} (100%) rename arch/arm/mach-mx3/{qong.c => mach-qong.c} (99%) diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 03e25d604455a..670fbb57b7d19 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -7,16 +7,16 @@ obj-y := mm.o devices.o cpu.o obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o -obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ +obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o +obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o +obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o +obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o +obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o +obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o +obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o -obj-$(CONFIG_MACH_QONG) += qong.o -obj-$(CONFIG_MACH_PCM043) += pcm043.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o +obj-$(CONFIG_MACH_QONG) += mach-qong.o +obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o +obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o +obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c similarity index 99% rename from arch/arm/mach-mx3/armadillo5x0.c rename to arch/arm/mach-mx3/mach-armadillo5x0.c index aac5f81c2420c..1fed146324f50 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -407,7 +407,7 @@ static struct sys_timer armadillo5x0_timer = { MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c similarity index 99% rename from arch/arm/mach-mx3/kzmarm11.c rename to arch/arm/mach-mx3/mach-kzm_arm11_01.c index 849631ecfe4ba..2850b0b463541 100644 --- a/arch/arm/mach-mx3/kzmarm11.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -259,7 +259,7 @@ static struct sys_timer kzm_timer = { */ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = kzm_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mach-mx31_3ds.c similarity index 99% rename from arch/arm/mach-mx3/mx31pdk.c rename to arch/arm/mach-mx3/mach-mx31_3ds.c index e71e3b4016284..88af58514a761 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -257,7 +257,7 @@ static struct sys_timer mx31pdk_timer = { MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31pdk_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c similarity index 99% rename from arch/arm/mach-mx3/mx31ads.c rename to arch/arm/mach-mx3/mach-mx31ads.c index 66991165127c2..1bcf22647f76d 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -542,7 +542,7 @@ static struct sys_timer mx31ads_timer = { MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31ads_map_io, .init_irq = mx31ads_init_irq, diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c similarity index 98% rename from arch/arm/mach-mx3/mx31lilly.c rename to arch/arm/mach-mx3/mach-mx31lilly.c index ffccea98531b4..9225cb72dd01b 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -196,7 +196,7 @@ static struct sys_timer mx31lilly_timer = { MACHINE_START(LILLY1131, "INCO startec LILLY-1131") .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c similarity index 99% rename from arch/arm/mach-mx3/mx31lite.c rename to arch/arm/mach-mx3/mach-mx31lite.c index 1e263978b1d85..8589e3d1dada2 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -288,7 +288,7 @@ struct sys_timer mx31lite_timer = { MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31lite_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c similarity index 99% rename from arch/arm/mach-mx3/mx31moboard.c rename to arch/arm/mach-mx3/mach-mx31moboard.c index 9428827f89444..63f991f8817ff 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -570,7 +570,7 @@ struct sys_timer mx31moboard_timer = { MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c similarity index 100% rename from arch/arm/mach-mx3/mx35pdk.c rename to arch/arm/mach-mx3/mach-mx35pdk.c diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c similarity index 99% rename from arch/arm/mach-mx3/pcm037.c rename to arch/arm/mach-mx3/mach-pcm037.c index 701fac9894328..d9bd7d2b0ade5 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -637,7 +637,7 @@ struct sys_timer pcm037_timer = { MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c similarity index 100% rename from arch/arm/mach-mx3/pcm037_eet.c rename to arch/arm/mach-mx3/mach-pcm037_eet.c diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c similarity index 100% rename from arch/arm/mach-mx3/pcm043.c rename to arch/arm/mach-mx3/mach-pcm043.c diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/mach-qong.c similarity index 99% rename from arch/arm/mach-mx3/qong.c rename to arch/arm/mach-mx3/mach-qong.c index 3c1e7364f74a2..93991f1592114 100644 --- a/arch/arm/mach-mx3/qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -276,7 +276,7 @@ static struct sys_timer qong_timer = { MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ .phys_io = MX31_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, -- GitLab From 1f2ddd64da6e53365102d831aa9e0446b78f0300 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 19:05:04 +0100 Subject: [PATCH 018/370] imx: provide helper macro to define IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Dmitriy Taychenachev --- arch/arm/plat-mxc/include/mach/hardware.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 78db75475f693..db14c56930a3a 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,6 +22,11 @@ #include +#define IMX_IO_ADDRESS(addr, module) \ + ((void __force __iomem *) \ + (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) + #ifdef CONFIG_ARCH_MX3 #include #include -- GitLab From a3f5ac7838a93977f71288310336a725eb6e62db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 17:29:39 +0100 Subject: [PATCH 019/370] imx21: define and use MX21_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Rabin Vincent Cc: Agustín Ferrín Pozuelo --- arch/arm/mach-mx2/clock_imx21.c | 4 ++-- arch/arm/plat-mxc/include/mach/mx21.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 6ab3c729a4562..2367b6c5f071e 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -28,7 +28,7 @@ #include #include -#define IO_ADDR_CCM(off) (IO_ADDRESS(MX21_CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR) + (off)) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) @@ -1235,7 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&uart_clk[0]); #endif - mxc_timer_init(&gpt_clk[0], IO_ADDRESS(MX21_GPT1_BASE_ADDR), + mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1); return 0; } diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index bb297d8765a79..5b9f062cfd255 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -92,6 +92,11 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ +#define MX21_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ + IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ + IMX_IO_ADDRESS(x, MX21_X_MEMC)) + /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 #define MX21_INT_GPIO 8 -- GitLab From bc9ea6c7f5352f8857525b054bc3df784be1b8d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 17:30:27 +0100 Subject: [PATCH 020/370] imx27: define and use MX27_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Rabin Vincent Cc: Javier Martin Cc: Valentin Longchamp Cc: Holger Schurig --- arch/arm/mach-mx2/clock_imx27.c | 4 ++-- arch/arm/mach-mx2/cpu_imx27.c | 3 ++- arch/arm/plat-mxc/include/mach/mx27.h | 5 +++++ 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index 6db98566a7208..bb9f60318fde5 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -29,7 +29,7 @@ #include #include -#define IO_ADDR_CCM(off) (IO_ADDRESS(MX27_CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR) + (off)) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) @@ -757,7 +757,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif - mxc_timer_init(&gpt1_clk, IO_ADDRESS(MX27_GPT1_BASE_ADDR), + mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); return 0; diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c index 8c50c5e7c0339..d8d3b2d84dc57 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-mx2/cpu_imx27.c @@ -39,7 +39,8 @@ static void query_silicon_parameter(void) * the silicon revision very early we read it here to * avoid any further hooks */ - val = __raw_readl(IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); + val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + + SYS_CHIP_ID)); cpu_silicon_rev = (int)(val >> 28); cpu_partnumber = (int)((val >> 12) & 0xFFFF); diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index e2ae19f517107..cd292ffc1f7ee 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -114,6 +114,11 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ +#define MX27_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ + IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ + IMX_IO_ADDRESS(x, MX27_X_MEMC)) + /* fixed interrupt numbers */ #define MX27_INT_I2C2 1 #define MX27_INT_GPT6 2 -- GitLab From 1273e7686f0c122bf58592c57387471c7f4eaa1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 19:06:12 +0100 Subject: [PATCH 021/370] imx31: define and use MX31_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Daniel Mack Cc: Greg Kroah-Hartman Cc: Mark Brown Cc: Magnus Lilja --- arch/arm/mach-mx3/clock-imx31.c | 3 ++- arch/arm/mach-mx3/crm_regs.h | 2 +- arch/arm/mach-mx3/iomux-imx31.c | 2 +- arch/arm/plat-mxc/ehci.c | 4 ++-- arch/arm/plat-mxc/include/mach/board-mx31ads.h | 2 +- arch/arm/plat-mxc/include/mach/mx31.h | 7 +++++++ 6 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index cc03a61116e2e..d22a66f502a86 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -625,7 +625,8 @@ int __init mx31_clocks_init(unsigned long fref) __raw_writel(reg, MXC_CCM_PMCR1); } - mxc_timer_init(&ipg_clk, IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); + mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), + MX31_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index e25cd92dd427f..37a8a07beda3e 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h @@ -24,7 +24,7 @@ #define CKIH_CLK_FREQ_27MHZ 27000000 #define CKIL_CLK_FREQ 32768 -#define MXC_CCM_BASE IO_ADDRESS(MX31_CCM_BASE_ADDR) +#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) /* Register addresses */ #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c index 6381e561961cc..a1d7fa5123dcd 100644 --- a/arch/arm/mach-mx3/iomux-imx31.c +++ b/arch/arm/mach-mx3/iomux-imx31.c @@ -29,7 +29,7 @@ /* * IOMUX register (base) addresses */ -#define IOMUX_BASE IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) +#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) #define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) #define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) #define IOMUXGPR (IOMUX_BASE + 0x008) diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 41599be882e8d..8df03f36295cd 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -43,7 +43,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) unsigned int v; if (cpu_is_mx31()) { - v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -79,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; } - writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 2cbfa35e82ff6..095a199591c6e 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -14,7 +14,7 @@ #include /* Base address of PBC controller */ -#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT /* Offsets for the PBC Controller register */ /* PBC Board status register offset */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index b8b47d139eb56..0c005af2c8cf4 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -109,6 +109,13 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 +#define MX31_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ + IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MX31_SPBA0)) + #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 -- GitLab From df9375fad4f99b28f5a500d9aa2cbb04e065ac97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 19:07:04 +0100 Subject: [PATCH 022/370] imx25: redefine MX25_IO_ADDRESS using IMX_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King --- arch/arm/plat-mxc/include/mach/mx25.h | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 854e2dc584816..7a8982dfd926a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -22,21 +22,10 @@ #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) -#define MX25_AIPS2_IO_ADDRESS(x) \ - (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) -#define MX25_AVIC_IO_ADDRESS(x) \ - (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT) - -#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) - -#define MX25_IO_ADDRESS(x) \ - (void __force __iomem *) \ - (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \ - __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \ - __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \ - 0xDEADBEEF) +#define MX25_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX25_AVIC)) #define UART1_BASE_ADDR 0x43f90000 #define UART2_BASE_ADDR 0x43f94000 -- GitLab From 6ef9af6871e3f220c6c7facf90babe6931d972bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 19:07:20 +0100 Subject: [PATCH 023/370] imx35: define and use MX35_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Jürgen Beisert Cc: Rabin Vincent Cc: Valentin Longchamp --- arch/arm/mach-mx3/clock-imx35.c | 5 +++-- arch/arm/plat-mxc/include/mach/mx35.h | 7 +++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index e65e862774ef4..07d630ebc2865 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -28,7 +28,7 @@ #include #include -#define CCM_BASE IO_ADDRESS(MX35_CCM_BASE_ADDR) +#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR) #define CCM_CCMR 0x00 #define CCM_PDR0 0x04 @@ -504,7 +504,8 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); - mxc_timer_init(&gpt_clk, IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); + mxc_timer_init(&gpt_clk, + MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); return 0; } diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index af871bce35b69..0e453b34ab922 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -104,6 +104,13 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 +#define MX35_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ + IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MX35_SPBA0)) + /* * Interrupt numbers */ -- GitLab From 59e2608169bf4199f9f9e08a8abe80132e9416f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 16 Dec 2009 19:08:09 +0100 Subject: [PATCH 024/370] mx3/kzm_arm11_01: define and use board specific IO_ADDRESS macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King --- arch/arm/mach-mx3/mach-kzm_arm11_01.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 2850b0b463541..2484dddca549b 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -46,13 +46,18 @@ #include "devices.h" +#define KZM_ARM11_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX31_CS4) ?: \ + IMX_IO_ADDRESS(x, MX31_CS5) ?: \ + MX31_IO_ADDRESS(x)) + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* * KZM-ARM11-01 has an external UART on FPGA */ static struct plat_serial8250_port serial_platform_data[] = { { - .membase = IO_ADDRESS(KZM_ARM11_16550), + .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550), .mapbase = KZM_ARM11_16550, .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), .irqflags = IRQ_TYPE_EDGE_RISING, @@ -102,9 +107,9 @@ static int __init kzm_init_ext_uart(void) /* * Unmask UART interrupt */ - tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); + tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); tmp |= 0x2; - __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); + __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); return platform_device_register(&serial_device); } -- GitLab From a9b7a2dd217bd43e122b604ec99b63e0211c38aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 17 Dec 2009 11:56:43 +0100 Subject: [PATCH 025/370] imx: mangle addresses after adding the offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit don't use IO_ADDRESS($base) + $offset but IO_ADDRESS($base + $offset) Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Rabin Vincent Cc: "Agustín Ferrín Pozuelo" Cc: Javier Martin Cc: Valentin Longchamp Cc: Daniel Mack Cc: Dmitriy Taychenachev --- arch/arm/mach-mx2/clock_imx21.c | 2 +- arch/arm/mach-mx2/clock_imx27.c | 2 +- arch/arm/mach-mx3/cpu.c | 2 +- arch/arm/plat-mxc/include/mach/mxc.h | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 2367b6c5f071e..8974faf9cef0f 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -28,7 +28,7 @@ #include #include -#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index bb9f60318fde5..68bf93e6e9075 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -29,7 +29,7 @@ #include #include -#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR) + (off)) +#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index db828809c6758..861afe0fe3ad6 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c @@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void) u32 i, srev; /* read SREV register from IIM module */ - srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); + srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV)); for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) if (srev == mx31_cpu_type[i].srev) { diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 51990536b8459..2b14126f8b511 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -121,9 +121,9 @@ extern unsigned int __mxc_cpu_type; #endif #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) -#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) -#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) -#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) +#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) +#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) +#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) #endif #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) -- GitLab From aae7019382896cf1075a93acc564e42601bc44a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 17 Dec 2009 17:17:54 +0100 Subject: [PATCH 026/370] imx: only define deprecated symbols conditionally MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define deprecated symbols in an #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS ... All files that still depend on the old definitions get -DIMX_NEEDS_DEPRECATED_SYMBOLS passed to the compiler. When all remaining users are fixed this allows including the soc specific headers unconditionally. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Eric Benard Cc: Fabio Estevam Cc: Alan Carvalho de Assis Cc: Daniel Mack Cc: Alberto Panizzo Cc: Ilya Yanok Cc: Holger Schurig Cc: Jiri Kosina Cc: Magnus Lilja --- arch/arm/mach-mx2/Makefile | 3 +++ arch/arm/mach-mx3/Makefile | 4 ++++ arch/arm/plat-mxc/Makefile | 4 ++++ arch/arm/plat-mxc/include/mach/mx21.h | 2 ++ arch/arm/plat-mxc/include/mach/mx27.h | 2 ++ arch/arm/plat-mxc/include/mach/mx2x.h | 2 ++ arch/arm/plat-mxc/include/mach/mx31.h | 2 ++ arch/arm/plat-mxc/include/mach/mx35.h | 2 ++ arch/arm/plat-mxc/include/mach/mx3x.h | 2 ++ 9 files changed, 23 insertions(+) diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 3710893a94ab4..a9c94e39e3212 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -5,6 +5,9 @@ # Object file lists. obj-y := generic.o devices.o serial.o +CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_serial.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX21) += clock_imx21.o diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 670fbb57b7d19..62b60931d87cd 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,6 +5,9 @@ # Object file lists. obj-y := mm.o devices.o cpu.o +CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o @@ -13,6 +16,7 @@ obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o +CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o obj-$(CONFIG_MACH_QONG) += mach-qong.o diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 996cbac6932c7..7322bca8f5fba 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -7,9 +7,13 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o +CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_dma-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o +CFLAGS_audmux-v1.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o +CFLAGS_audmux-v2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 5b9f062cfd255..5e2f16e599956 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -184,6 +184,7 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR @@ -216,5 +217,6 @@ #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX +#endif #endif /* __ASM_ARCH_MXC_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index cd292ffc1f7ee..62746c0cd5cec 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -230,6 +230,7 @@ extern int mx27_revision(void); #endif +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR @@ -297,5 +298,6 @@ extern int mx27_revision(void); #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 #define DMA_REQ_NFC MX27_DMA_REQ_NFC +#endif #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index f2eaf140ed026..396470e8d93ec 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -176,6 +176,7 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT @@ -287,5 +288,6 @@ #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX +#endif #endif /* __ASM_ARCH_MXC_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 0c005af2c8cf4..53da4c5976a96 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -193,6 +193,7 @@ #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 #define MX31_SYSTEM_REV_NUM 3 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR @@ -223,3 +224,4 @@ #define MXC_INT_UART5 MX31_INT_UART5 #define MXC_INT_CCM MX31_INT_CCM #define MXC_INT_PCMCIA MX31_INT_PCMCIA +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 0e453b34ab922..ff2d2f0bfc931 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -187,6 +187,7 @@ #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR #define MXC_INT_OWIRE MX35_INT_OWIRE @@ -202,3 +203,4 @@ #define MXC_INT_MLB MX35_INT_MLB #define MXC_INT_SPDIF MX35_INT_SPDIF #define MXC_INT_FEC MX35_INT_FEC +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index be69272407ad9..5ae0b002d796c 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -269,6 +269,7 @@ static inline int mx31_revision(void) } #endif +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR #define L2CC_SIZE MX3x_L2CC_SIZE @@ -401,5 +402,6 @@ static inline int mx31_revision(void) #define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM +#endif #endif /* __ASM_ARCH_MXC_MX31_H__ */ -- GitLab From d13ab097ae9671be6765c7a8f1946641db5a7dac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 5 Jan 2010 11:27:42 +0100 Subject: [PATCH 027/370] imx: remove mx1ads defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For some time now the defconfig for mx1ads produces a kernel for a versatile board. As CONFIG_ARCH_MX1ADS is included in the mx1 defconfig just get rid of mx1ads_defconfig. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer --- arch/arm/configs/mx1ads_defconfig | 742 ------------------------------ 1 file changed, 742 deletions(-) delete mode 100644 arch/arm/configs/mx1ads_defconfig diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig deleted file mode 100644 index 3cabbb6d9276e..0000000000000 --- a/arch/arm/configs/mx1ads_defconfig +++ /dev/null @@ -1,742 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-rc1-bk2 -# Sun Mar 27 02:15:46 2005 -# -CONFIG_ARM=y -CONFIG_MMU=y -CONFIG_UID16=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_IOMAP=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# System Type -# -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARCH_IMX=y -# CONFIG_ARCH_H720X is not set - -# -# IMX Implementations -# -CONFIG_ARCH_MX1ADS=y - -# -# Processor Type -# -CONFIG_CPU_ARM920T=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set - -# -# Bus support -# -CONFIG_ISA=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_PREEMPT=y -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySMX0,57600n8 ip=bootp root=/dev/nfs" -# CONFIG_XIP_KERNEL is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_FPE_FASTFPE=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set - -# -# Power management options -# -# CONFIG_PM is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_ROM=y -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=m -CONFIG_PACKET_MMAP=y -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_SMC91X is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -# CONFIG_PPPOE is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_RTC=m -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -# CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -CONFIG_FRAME_POINTER=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_CRC_CCITT=y -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -- GitLab From 4631166124d928d3e9372a57b1477ce6335332c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 8 Jan 2010 12:29:11 +0100 Subject: [PATCH 028/370] imx: remove unneeded include of mach/hardware.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This include isn't needed and hurts when defining static inline functions in mach/hardware.h (or files included by mach/hardware.h). The reason is that the consumers of mach/uncompress.h are compiled using -Dstatic= so the code for all inline function is included in e.g. arch/arm/boot/compressed/misc.o. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Jörg Knobloch Cc: Alan Carvalho de Assis Cc: Daniel Mack Cc: Dmitriy Taychenachev --- arch/arm/plat-mxc/include/mach/uncompress.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 4d5d395ad63b6..d189f00f23668 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -1,8 +1,6 @@ /* * arch/arm/plat-mxc/include/mach/uncompress.h * - * - * * Copyright (C) 1999 ARM Limited * Copyright (C) Shane Nay (shane@minirl.com) * @@ -25,7 +23,6 @@ #define __MXC_BOOT_UNCOMPRESS -#include #include static unsigned long uart_base; -- GitLab From 3cdd54417d0f821825a353f7273d356399112f56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 8 Jan 2010 16:02:30 +0100 Subject: [PATCH 029/370] imx: properly protect mach/mx{1,[25][157x]}.h from multiple inclusion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some headers have used (now) wrong names or havn't had protection at all. This is needed before adding static inline functions to the headers. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Magnus Lilja Cc: Holger Schurig Cc: Jiri Kosina Cc: Daniel Mack --- arch/arm/plat-mxc/include/mach/mx1.h | 6 +++--- arch/arm/plat-mxc/include/mach/mx21.h | 6 +++--- arch/arm/plat-mxc/include/mach/mx25.h | 2 +- arch/arm/plat-mxc/include/mach/mx27.h | 6 +++--- arch/arm/plat-mxc/include/mach/mx2x.h | 6 +++--- arch/arm/plat-mxc/include/mach/mx31.h | 5 +++++ arch/arm/plat-mxc/include/mach/mx35.h | 4 ++++ arch/arm/plat-mxc/include/mach/mx3x.h | 6 +++--- 8 files changed, 25 insertions(+), 16 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 1b2890a5c452e..b652a9c25865b 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -9,8 +9,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_MXC_MX1_H__ -#define __ASM_ARCH_MXC_MX1_H__ +#ifndef __MACH_MX1_H__ +#define __MACH_MX1_H__ #include @@ -161,4 +161,4 @@ #define DMA_REQ_UART1_T 30 #define DMA_REQ_UART1_R 31 -#endif /* __ASM_ARCH_MXC_MX1_H__ */ +#endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 5e2f16e599956..ed98b9c9f389c 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -22,8 +22,8 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX21_H__ -#define __ASM_ARCH_MXC_MX21_H__ +#ifndef __MACH_MX21_H__ +#define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 @@ -219,4 +219,4 @@ #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX #endif -#endif /* __ASM_ARCH_MXC_MX21_H__ */ +#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 7a8982dfd926a..18eb44c15eaaf 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -34,4 +34,4 @@ #define MX25_INT_FEC 57 -#endif /* __MACH_MX25_H__ */ +#endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 62746c0cd5cec..832b5804dcb5e 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -21,8 +21,8 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX27_H__ -#define __ASM_ARCH_MXC_MX27_H__ +#ifndef __MACH_MX27_H__ +#define __MACH_MX27_H__ #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 @@ -300,4 +300,4 @@ extern int mx27_revision(void); #define DMA_REQ_NFC MX27_DMA_REQ_NFC #endif -#endif /* __ASM_ARCH_MXC_MX27_H__ */ +#endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 396470e8d93ec..afb895a0b5b8f 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -20,8 +20,8 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX2x_H__ -#define __ASM_ARCH_MXC_MX2x_H__ +#ifndef __MACH_MX2x_H__ +#define __MACH_MX2x_H__ /* The following addresses are common between i.MX21 and i.MX27 */ @@ -290,4 +290,4 @@ #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX #endif -#endif /* __ASM_ARCH_MXC_MX2x_H__ */ +#endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 53da4c5976a96..62d26da10c665 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -1,3 +1,6 @@ +#ifndef __MACH_MX31_H__ +#define __MACH_MX31_H__ + /* * IRAM */ @@ -225,3 +228,5 @@ #define MXC_INT_CCM MX31_INT_CCM #define MXC_INT_PCMCIA MX31_INT_PCMCIA #endif + +#endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index ff2d2f0bfc931..526a55842ae53 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -1,3 +1,5 @@ +#ifndef __MACH_MX35_H__ +#define __MACH_MX35_H__ /* * IRAM */ @@ -204,3 +206,5 @@ #define MXC_INT_SPDIF MX35_INT_SPDIF #define MXC_INT_FEC MX35_INT_FEC #endif + +#endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 5ae0b002d796c..7a356de385f59 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -8,8 +8,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_MXC_MX31_H__ -#define __ASM_ARCH_MXC_MX31_H__ +#ifndef __MACH_MX3x_H__ +#define __MACH_MX3x_H__ /* * MX31 memory map: @@ -404,4 +404,4 @@ static inline int mx31_revision(void) #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM #endif -#endif /* __ASM_ARCH_MXC_MX31_H__ */ +#endif /* ifndef __MACH_MX3x_H__ */ -- GitLab From a8dfb6462a033984b99fee4122fe0799a31f5bb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 7 Jan 2010 11:27:17 +0100 Subject: [PATCH 030/370] imx: define functions to configure chip selects in the WEIM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This has the addional effect that the macros CSCR_U, CSCR_L and CSCR_A are not used anymore in mach-pcm038.c and mach-qong.c. These still use the deprecated IO_ADDRESS macro and shouldn't be used in new code. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Holger Schurig Cc: Dmitriy Taychenachev --- arch/arm/mach-mx2/mach-pcm038.c | 4 +--- arch/arm/mach-mx3/mach-qong.c | 4 +--- arch/arm/plat-mxc/include/mach/mx27.h | 19 +++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx31.h | 19 +++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 1 + 5 files changed, 41 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index a2e2ea16c1360..9636bb82f1e9c 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -173,9 +173,7 @@ static struct platform_device *platform_devices[] __initdata = { * setup other stuffs to access the sram. */ static void __init pcm038_init_sram(void) { - __raw_writel(0x0000d843, CSCR_U(1)); - __raw_writel(0x22252521, CSCR_L(1)); - __raw_writel(0x22220a00, CSCR_A(1)); + mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); } static struct imxi2c_platform_data pcm038_i2c_1_data = { diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index 93991f1592114..fdb819ae0e60d 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = { static void __init qong_init_nand_mtd(void) { /* init CS */ - __raw_writel(0x00004f00, CSCR_U(3)); - __raw_writel(0x20013b31, CSCR_L(3)); - __raw_writel(0x00020800, CSCR_A(3)); + mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); /* enable pin */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 832b5804dcb5e..bae9cd75beee3 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,6 +24,10 @@ #ifndef __MACH_MX27_H__ #define __MACH_MX27_H__ +#ifndef __ASSEMBLER__ +#include +#endif + #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M @@ -109,6 +113,11 @@ #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) +#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 /* IRAM */ @@ -119,6 +128,16 @@ IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#ifndef __ASSEMBLER__ +static inline void mx27_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs))); +} +#endif + /* fixed interrupt numbers */ #define MX27_INT_I2C2 1 #define MX27_INT_GPT6 2 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 62d26da10c665..fb90e119c2b5d 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -1,6 +1,10 @@ #ifndef __MACH_MX31_H__ #define __MACH_MX31_H__ +#ifndef __ASSEMBLER__ +#include +#endif + /* * IRAM */ @@ -110,6 +114,11 @@ #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR +#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX31_IO_ADDRESS(x) ( \ @@ -119,6 +128,16 @@ IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ IMX_IO_ADDRESS(x, MX31_SPBA0)) +#ifndef __ASSEMBLER__ +static inline void mx31_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs))); +} +#endif + #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 2b14126f8b511..800ae2a33b159 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -121,6 +121,7 @@ extern unsigned int __mxc_cpu_type; #endif #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) +/* These are deprecated, use mx[23][157]_setup_weimcs instead. */ #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) -- GitLab From b6d0c1bda9038354ff2f0c77da23fd32e0f11a1f Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 14 Jan 2010 11:24:13 +0200 Subject: [PATCH 031/370] mtd: mxc_nand: add MX25 to Kconfig Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 677cd53f18c34..4f99274b24c25 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -444,7 +444,7 @@ config MTD_NAND_FSL_UPM config MTD_NAND_MXC tristate "MXC NAND support" - depends on ARCH_MX2 || ARCH_MX3 + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 help This enables the driver for the NAND flash controller on the MXC processors. -- GitLab From 27f590258954ea0d22b43e33dd356bc76a8dfe7a Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 14 Jan 2010 11:24:14 +0200 Subject: [PATCH 032/370] mx25: add NAND support Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/devices.c | 20 ++++++++++++++++++++ arch/arm/mach-mx25/devices.h | 1 + arch/arm/plat-mxc/include/mach/mx25.h | 2 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 9fdeea1c083b8..dd4069725ef5a 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -438,3 +438,23 @@ struct platform_device mx25_fec_device = { .num_resources = ARRAY_SIZE(mx25_fec_resources), .resource = mx25_fec_resources, }; + +static struct resource mxc_nand_resources[] = { + { + .start = MX25_NFC_BASE_ADDR, + .end = MX25_NFC_BASE_ADDR + 0x1fff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_NANDFC, + .end = MX25_INT_NANDFC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_nand_device = { + .name = "mxc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + .resource = mxc_nand_resources, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index fe5420fcd11fb..8f5530062b435 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -18,3 +18,4 @@ extern struct platform_device mxc_i2c_device0; extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; +extern struct platform_device mxc_nand_device; diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 18eb44c15eaaf..021d208e86bc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -31,7 +31,9 @@ #define UART2_BASE_ADDR 0x43f94000 #define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_INT_FEC 57 +#define MX25_INT_NANDFC 33 #endif /* ifndef __MACH_MX25_H__ */ -- GitLab From b97235dfa1aba54786b19fc53ba026e47be86ac6 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 14 Jan 2010 11:24:15 +0200 Subject: [PATCH 033/370] mx25pdk: add NAND device support Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/mx25pdk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c index 921bc99ea231f..c8b1d3b9d010c 100644 --- a/arch/arm/mach-mx25/mx25pdk.c +++ b/arch/arm/mach-mx25/mx25pdk.c @@ -77,6 +77,12 @@ static void __init mx25pdk_fec_reset(void) gpio_set_value(FEC_RESET_B_GPIO, 1); } +static struct mxc_nand_platform_data mx25pdk_nand_board_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -84,6 +90,7 @@ static void __init mx25pdk_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_usbh2, NULL); + mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); -- GitLab From 70792bcfad5f4817fc067b7fdb0541d8b13b5502 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Nov 2009 00:40:47 +0000 Subject: [PATCH 034/370] ARM: SAMSUNG: Move to plat-samsung Move the header to plat-samsung where it can be used by all the platforms, and readies it for the next round of clock updates where the clock code will be amalgamated. Signed-off-by: Ben Dooks --- arch/arm/{plat-s3c => plat-samsung}/include/plat/clock.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/clock.h (100%) diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/clock.h rename to arch/arm/plat-samsung/include/plat/clock.h -- GitLab From f9c4f1e4ddf40103dcf85e23d00230ab8ece2a89 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Nov 2009 01:10:57 +0000 Subject: [PATCH 035/370] ARM: S3C64XX: Cleanup common init code in s3c6400-clock.c Remove the four fields from clksrc_clk.clk which are always the same and init them when the clock is registered. This helps remove the amount of repeated code. This is a re-work of Harald Welte's clock changes for the latest kernel. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/s3c6400-clock.c | 49 +++------------------------ 1 file changed, 5 insertions(+), 44 deletions(-) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index ffd56deb9e81a..aba08c7d312f5 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -360,10 +360,6 @@ static struct clksrc_clk clk_mmc0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_MMC0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC0_SHIFT, .mask = S3C6400_CLKSRC_MMC0_MASK, @@ -378,10 +374,6 @@ static struct clksrc_clk clk_mmc1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_MMC1, .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC1_SHIFT, .mask = S3C6400_CLKSRC_MMC1_MASK, @@ -396,10 +388,6 @@ static struct clksrc_clk clk_mmc2 = { .id = 2, .ctrlbit = S3C_CLKCON_SCLK_MMC2, .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_MMC2_SHIFT, .mask = S3C6400_CLKSRC_MMC2_MASK, @@ -414,10 +402,6 @@ static struct clksrc_clk clk_usbhost = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_UHOST_SHIFT, .mask = S3C6400_CLKSRC_UHOST_MASK, @@ -432,10 +416,6 @@ static struct clksrc_clk clk_uart_uclk1 = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UART, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_UART_SHIFT, .mask = S3C6400_CLKSRC_UART_MASK, @@ -452,10 +432,6 @@ static struct clksrc_clk clk_spi0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_SPI0_SHIFT, .mask = S3C6400_CLKSRC_SPI0_MASK, @@ -470,10 +446,6 @@ static struct clksrc_clk clk_spi1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_SPI1_SHIFT, .mask = S3C6400_CLKSRC_SPI1_MASK, @@ -516,10 +488,6 @@ static struct clksrc_clk clk_audio0 = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, .mask = S3C6400_CLKSRC_AUDIO0_MASK, @@ -547,10 +515,6 @@ static struct clksrc_clk clk_audio1 = { .id = 1, .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, .mask = S3C6400_CLKSRC_AUDIO1_MASK, @@ -565,10 +529,6 @@ static struct clksrc_clk clk_irda = { .id = 0, .ctrlbit = S3C_CLKCON_SCLK_IRDA, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = S3C6400_CLKSRC_IRDA_SHIFT, .mask = S3C6400_CLKSRC_IRDA_MASK, @@ -592,10 +552,6 @@ static struct clksrc_clk clk_camif = { .id = -1, .ctrlbit = S3C_CLKCON_SCLK_CAM, .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, }, .shift = 0, .mask = 0, @@ -637,6 +593,11 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) return; } + clk->clk.get_rate = s3c64xx_getrate_clksrc; + clk->clk.set_rate = s3c64xx_setrate_clksrc; + clk->clk.set_parent = s3c64xx_setparent_clksrc; + clk->clk.round_rate = s3c64xx_roundrate_clksrc; + clk->clk.parent = srcs->sources[clksrc]; printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", -- GitLab From 8360493c4ae4c116339cd1cf4da100c3547f23af Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Nov 2009 01:31:32 +0000 Subject: [PATCH 036/370] ARM: S3C64XX: Compress s3c6400-clock.c code The individually named clocks are all static to the code and thus can be compressed into a single array and then the array can be referenced. This removes the need for a seperate array of pointers to clocks. Fix a minor problem of re-initialising the pointers in s3c6400_set_clksrc() as this is also called by the cpufreq code. Move these initialisations to the code that does the registration. Based on Harald Welte's original clock changes patch. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/s3c6400-clock.c | 334 ++++++++++++-------------- 1 file changed, 154 insertions(+), 180 deletions(-) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index aba08c7d312f5..6fde910e414cf 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -255,7 +255,6 @@ static struct clk_sources clkset_uhost = { .nr_sources = ARRAY_SIZE(clkset_uhost_list), }; - /* The peripheral clocks are all controlled via clocksource followed * by an optional divider and gate stage. We currently roll this into * one clock which hides the intermediate clock from the mux. @@ -354,105 +353,7 @@ static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, return rate; } -static struct clksrc_clk clk_mmc0 = { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_MMC0_SHIFT, - .mask = S3C6400_CLKSRC_MMC0_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_mmc1 = { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_MMC1_SHIFT, - .mask = S3C6400_CLKSRC_MMC1_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_mmc2 = { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_MMC2_SHIFT, - .mask = S3C6400_CLKSRC_MMC2_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_usbhost = { - .clk = { - .name = "usb-bus-host", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_UHOST_SHIFT, - .mask = S3C6400_CLKSRC_UHOST_MASK, - .sources = &clkset_uhost, - .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_uart_uclk1 = { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_UART_SHIFT, - .mask = S3C6400_CLKSRC_UART_MASK, - .sources = &clkset_uart, - .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -/* Where does UCLK0 come from? */ - -static struct clksrc_clk clk_spi0 = { - .clk = { - .name = "spi-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_SPI0, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_SPI0_SHIFT, - .mask = S3C6400_CLKSRC_SPI0_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -static struct clksrc_clk clk_spi1 = { - .clk = { - .name = "spi-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_SPI1, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_SPI1_SHIFT, - .mask = S3C6400_CLKSRC_SPI1_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; +/* clocks that feed other parts of the clock source tree */ static struct clk clk_iis_cd0 = { .name = "iis_cdclk0", @@ -482,20 +383,6 @@ static struct clk_sources clkset_audio0 = { .nr_sources = ARRAY_SIZE(clkset_audio0_list), }; -static struct clksrc_clk clk_audio0 = { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO0_MASK, - .sources = &clkset_audio0, - .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - static struct clk *clkset_audio1_list[] = { [0] = &clk_mout_epll.clk, [1] = &clk_dout_mpll, @@ -509,34 +396,6 @@ static struct clk_sources clkset_audio1 = { .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; -static struct clksrc_clk clk_audio1 = { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO1_MASK, - .sources = &clkset_audio1, - .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -static struct clksrc_clk clk_irda = { - .clk = { - .name = "irda-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_IRDA, - .enable = s3c64xx_sclk_ctrl, - }, - .shift = S3C6400_CLKSRC_IRDA_SHIFT, - .mask = S3C6400_CLKSRC_IRDA_MASK, - .sources = &clkset_irda, - .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - static struct clk *clkset_camif_list[] = { &clk_h2, }; @@ -546,18 +405,141 @@ static struct clk_sources clkset_camif = { .nr_sources = ARRAY_SIZE(clkset_camif_list), }; -static struct clksrc_clk clk_camif = { - .clk = { - .name = "camera", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_CAM, - .enable = s3c64xx_sclk_ctrl, +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_MMC0_SHIFT, + .mask = S3C6400_CLKSRC_MMC0_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, + .reg_divider = S3C_CLK_DIV1, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_MMC1_SHIFT, + .mask = S3C6400_CLKSRC_MMC1_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, + .reg_divider = S3C_CLK_DIV1, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_MMC2_SHIFT, + .mask = S3C6400_CLKSRC_MMC2_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, + .reg_divider = S3C_CLK_DIV1, + }, { + .clk = { + .name = "usb-bus-host", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_UHOST_SHIFT, + .mask = S3C6400_CLKSRC_UHOST_MASK, + .sources = &clkset_uhost, + .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, + .reg_divider = S3C_CLK_DIV1, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_UART_SHIFT, + .mask = S3C6400_CLKSRC_UART_MASK, + .sources = &clkset_uart, + .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { +/* Where does UCLK0 come from? */ + .clk = { + .name = "spi-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_SPI0_SHIFT, + .mask = S3C6400_CLKSRC_SPI0_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { + .clk = { + .name = "spi-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_SPI1_SHIFT, + .mask = S3C6400_CLKSRC_SPI1_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, + .mask = S3C6400_CLKSRC_AUDIO0_MASK, + .sources = &clkset_audio0, + .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, + .mask = S3C6400_CLKSRC_AUDIO1_MASK, + .sources = &clkset_audio1, + .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { + .clk = { + .name = "irda-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_IRDA, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = S3C6400_CLKSRC_IRDA_SHIFT, + .mask = S3C6400_CLKSRC_IRDA_MASK, + .sources = &clkset_irda, + .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, + .reg_divider = S3C_CLK_DIV2, + }, { + .clk = { + .name = "camera", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_CAM, + .enable = s3c64xx_sclk_ctrl, + }, + .shift = 0, + .mask = 0, + .sources = &clkset_camif, + .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, + .reg_divider = S3C_CLK_DIV0, }, - .shift = 0, - .mask = 0, - .sources = &clkset_camif, - .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, - .reg_divider = S3C_CLK_DIV0, }; /* Clock initialisation code */ @@ -566,17 +548,6 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, - &clk_mmc0, - &clk_mmc1, - &clk_mmc2, - &clk_usbhost, - &clk_uart_uclk1, - &clk_spi0, - &clk_spi1, - &clk_audio0, - &clk_audio1, - &clk_irda, - &clk_camif, }; static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) @@ -593,11 +564,6 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) return; } - clk->clk.get_rate = s3c64xx_getrate_clksrc; - clk->clk.set_rate = s3c64xx_setrate_clksrc; - clk->clk.set_parent = s3c64xx_setparent_clksrc; - clk->clk.round_rate = s3c64xx_roundrate_clksrc; - clk->clk.parent = srcs->sources[clksrc]; printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", @@ -664,6 +630,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) s3c6400_set_clksrc(init_parents[ptr]); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c6400_set_clksrc(&clksrcs[ptr]); } static struct clk *clks[] __initdata = { @@ -674,17 +643,6 @@ static struct clk *clks[] __initdata = { &clk_mout_epll.clk, &clk_mout_mpll.clk, &clk_dout_mpll, - &clk_mmc0.clk, - &clk_mmc1.clk, - &clk_mmc2.clk, - &clk_usbhost.clk, - &clk_uart_uclk1.clk, - &clk_spi0.clk, - &clk_spi1.clk, - &clk_audio0.clk, - &clk_audio1.clk, - &clk_irda.clk, - &clk_camif.clk, &clk_arm, }; @@ -716,4 +674,20 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) clkp->name, ret); } } + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { + clkp = &clksrcs[ptr].clk; + + /* all clksrc clocks have these */ + clkp->get_rate = s3c64xx_getrate_clksrc; + clkp->set_rate = s3c64xx_setrate_clksrc; + clkp->set_parent = s3c64xx_setparent_clksrc; + clkp->round_rate = s3c64xx_roundrate_clksrc; + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } } -- GitLab From aa9ad6ad9c16e1daff41792c485f46e601a5af33 Mon Sep 17 00:00:00 2001 From: Harald Welte Date: Tue, 1 Dec 2009 01:24:34 +0000 Subject: [PATCH 037/370] ARM: SAMSUNG: Add core clock implementation for clksrc based clocks Add a core for the clksrc clock implementation, which is found in many of the newer Samsung SoCs into plat-samsung. Signed-off-by: Harald Welte [ben-linux@fluff.org: split from original patch to make change smaller] [ben-linux@fluff.org: split clk and clksrc changes] [ben-linux@fluff.org: moved to plat-samsung from plat-s3c] [ben-linux@fluff.org: re-wrote headers after splits] [ben-linux@fluff.org: added better documentation to headers] Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/Kconfig | 5 + arch/arm/plat-samsung/Makefile | 1 + arch/arm/plat-samsung/clock-clksrc.c | 177 ++++++++++++++++++ .../plat-samsung/include/plat/clock-clksrc.h | 75 ++++++++ 4 files changed, 258 insertions(+) create mode 100644 arch/arm/plat-samsung/clock-clksrc.c create mode 100644 arch/arm/plat-samsung/include/plat/clock-clksrc.h diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 486a0d6301e7d..e3ae68472ea74 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -13,5 +13,10 @@ config PLAT_SAMSUNG if PLAT_SAMSUNG +config SAMSUNG_CLKSRC + bool + help + Select the clock code for the clksrc implementation + used by newer systems such as the S3C64XX. endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 4478b9f7dc34d..ce736ce468fdc 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -9,3 +9,4 @@ obj-m := obj-n := dummy.o obj- := +obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c new file mode 100644 index 0000000000000..5872f0b62b7c2 --- /dev/null +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -0,0 +1,177 @@ +/* linux/arch/arm/plat-samsung/clock-clksrc.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static inline struct clksrc_clk *to_clksrc(struct clk *clk) +{ + return container_of(clk, struct clksrc_clk, clk); +} + +static inline u32 bit_mask(u32 shift, u32 nr_bits) +{ + u32 mask = 0xffffffff >> (32 - nr_bits); + + return mask << shift; +} + +static unsigned long s3c_getrate_clksrc(struct clk *clk) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv = __raw_readl(sclk->reg_div.reg); + u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); + + clkdiv &= mask; + clkdiv >>= sclk->reg_div.shift; + clkdiv++; + + rate /= clkdiv; + return rate; +} + +static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + void __iomem *reg = sclk->reg_div.reg; + unsigned int div; + u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); + u32 val; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + if (div > 16) + return -EINVAL; + + val = __raw_readl(reg); + val &= ~mask; + val |= (div - 1) << sclk->reg_div.shift; + __raw_writel(val, reg); + + return 0; +} + +static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + struct clksrc_sources *srcs = sclk->sources; + u32 clksrc = __raw_readl(sclk->reg_src.reg); + u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size); + int src_nr = -1; + int ptr; + + for (ptr = 0; ptr < srcs->nr_sources; ptr++) + if (srcs->sources[ptr] == parent) { + src_nr = ptr; + break; + } + + if (src_nr >= 0 && sclk->reg_src.reg) { + clk->parent = parent; + + clksrc &= ~mask; + clksrc |= src_nr << sclk->reg_src.shift; + + __raw_writel(clksrc, sclk->reg_src.reg); + return 0; + } + + return -EINVAL; +} + +static unsigned long s3c_roundrate_clksrc(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate >= parent_rate) + rate = parent_rate; + else { + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div == 0) + div = 1; + if (div > 16) + div = 16; + + rate = parent_rate / div; + } + + return rate; +} + +/* Clock initialisation code */ + +void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk) +{ + struct clksrc_sources *srcs = clk->sources; + u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); + u32 clksrc = 0; + + if (clk->reg_src.reg) + clksrc = __raw_readl(clk->reg_src.reg); + + clksrc &= mask; + clksrc >>= clk->reg_src.shift; + + if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { + printk(KERN_ERR "%s: bad source %d\n", + clk->clk.name, clksrc); + return; + } + + clk->clk.parent = srcs->sources[clksrc]; + + printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", + clk->clk.name, clk->clk.parent->name, clksrc, + clk_get_rate(&clk->clk)); +} + +void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) +{ + int ret; + + for (; size > 0; size--, clksrc++) { + /* fill in the default functions */ + if (!clksrc->clk.set_parent) + clksrc->clk.set_parent = s3c_setparent_clksrc; + if (!clksrc->clk.get_rate) + clksrc->clk.get_rate = s3c_getrate_clksrc; + if (!clksrc->clk.set_rate) + clksrc->clk.set_rate = s3c_setrate_clksrc; + if (!clksrc->clk.round_rate) + clksrc->clk.round_rate = s3c_roundrate_clksrc; + + s3c_set_clksrc(clksrc); + + ret = s3c24xx_register_clock(&clksrc->clk); + + if (ret < 0) { + printk(KERN_ERR "%s: failed to register %s (%d)\n", + __func__, clksrc->clk.name, ret); + } + } +} diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h new file mode 100644 index 0000000000000..283dfa0287573 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h @@ -0,0 +1,75 @@ +/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h + * + * Parts taken from arch/arm/plat-s3c64xx/clock.c + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * Copyright 2009 Ben Dooks + * Copyright 2009 Harald Welte + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/** + * struct clksrc_sources - list of sources for a given clock + * @sources: array of pointers to clocks + * @nr_sources: The size of @sources + */ +struct clksrc_sources { + unsigned int nr_sources; + struct clk **sources; +}; + +/** + * struct clksrc_reg - register definition for clock control bits + * @reg: pointer to the register in virtual memory. + * @shift: the shift in bits to where the bitfield is. + * @size: the size in bits of the bitfield. + * + * This specifies the size and position of the bits we are interested + * in within the register specified by @reg. + */ +struct clksrc_reg { + void __iomem *reg; + unsigned short shift; + unsigned short size; +}; + +/** + * struct clksrc_clk - class of clock for newer style samsung devices. + * @clk: the standard clock representation + * @sources: the sources for this clock + * @reg_src: the register definition for selecting the clock's source + * @reg_div: the register definition for the clock's output divisor + * + * This clock implements the features required by the newer SoCs where + * the standard clock block provides an input mux and a post-mux divisor + * to provide the periperhal's clock. + * + * The array of @sources provides the mapping of mux position to the + * clock, and @reg_src shows the code where to modify to change the mux + * position. The @reg_div defines how to change the divider settings on + * the output. + */ +struct clksrc_clk { + struct clk clk; + struct clksrc_sources *sources; + + struct clksrc_reg reg_src; + struct clksrc_reg reg_div; +}; + +extern void s3c_set_clksrc(struct clksrc_clk *clk); + +/** + * s3c_register_clksrc() register clocks from an array of clksrc clocks + * @srcs: The array of clocks to register + * @size: The size of the @srcs array. + * + * Initialise and register the array of clocks described by @srcs. + */ +extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size); -- GitLab From 399cae747426a6acdba8e347edef241a05a08b09 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 1 Dec 2009 01:24:35 +0000 Subject: [PATCH 038/370] ARM: S3C64XX: Use new clock-clksrc.c code for clocks. Move the s3c6400-clock.c implementation over to use the new common plat-samsung based clock-clksrc.c. Note, this does not delete the clocks definitions that are now unused in the regs-clock.h to reduce the quantity of change in this commit. Based on original patches by Harald Welte. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/Kconfig | 1 + arch/arm/plat-s3c64xx/s3c6400-clock.c | 241 +++++--------------------- 2 files changed, 40 insertions(+), 202 deletions(-) diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index e6da87a5885ca..bec12242706b4 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -13,6 +13,7 @@ config PLAT_S3C64XX select ARM_VIC select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select SAMSUNG_CLKSRC select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 6fde910e414cf..20af0c29979a9 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -29,6 +29,7 @@ #include #include +#include #include #include @@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = { #define clk_fout_mpll clk_mpll #define clk_fout_epll clk_epll -struct clk_sources { - unsigned int nr_sources; - struct clk **sources; -}; - -struct clksrc_clk { - struct clk clk; - unsigned int mask; - unsigned int shift; - - struct clk_sources *sources; - - unsigned int divider_shift; - void __iomem *reg_divider; -}; - static struct clk clk_fout_apll = { .name = "fout_apll", .id = -1, @@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = { [1] = &clk_fout_apll, }; -static struct clk_sources clk_src_apll = { +static struct clksrc_sources clk_src_apll = { .sources = clk_src_apll_list, .nr_sources = ARRAY_SIZE(clk_src_apll_list), }; @@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_APLL_MOUT, + .reg_src = { S3C_CLK_SRC, 0, 1 }, .sources = &clk_src_apll, }; @@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = { [1] = &clk_fout_epll, }; -static struct clk_sources clk_src_epll = { +static struct clksrc_sources clk_src_epll = { .sources = clk_src_epll_list, .nr_sources = ARRAY_SIZE(clk_src_epll_list), }; @@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_EPLL_MOUT, + .reg_src = { S3C_CLK_SRC, 2, 1 }, .sources = &clk_src_epll, }; @@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = { [1] = &clk_fout_mpll, }; -static struct clk_sources clk_src_mpll = { +static struct clksrc_sources clk_src_mpll = { .sources = clk_src_mpll_list, .nr_sources = ARRAY_SIZE(clk_src_mpll_list), }; @@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_MPLL_MOUT, + .reg_src = { S3C_CLK_SRC, 1, 1 }, .sources = &clk_src_mpll, }; @@ -214,7 +196,7 @@ static struct clk *clkset_spi_mmc_list[] = { &clk_27m, }; -static struct clk_sources clkset_spi_mmc = { +static struct clksrc_sources clkset_spi_mmc = { .sources = clkset_spi_mmc_list, .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), }; @@ -226,7 +208,7 @@ static struct clk *clkset_irda_list[] = { &clk_27m, }; -static struct clk_sources clkset_irda = { +static struct clksrc_sources clkset_irda = { .sources = clkset_irda_list, .nr_sources = ARRAY_SIZE(clkset_irda_list), }; @@ -238,7 +220,7 @@ static struct clk *clkset_uart_list[] = { NULL }; -static struct clk_sources clkset_uart = { +static struct clksrc_sources clkset_uart = { .sources = clkset_uart_list, .nr_sources = ARRAY_SIZE(clkset_uart_list), }; @@ -250,7 +232,7 @@ static struct clk *clkset_uhost_list[] = { &clk_fin_epll, }; -static struct clk_sources clkset_uhost = { +static struct clksrc_sources clkset_uhost = { .sources = clkset_uhost_list, .nr_sources = ARRAY_SIZE(clkset_uhost_list), }; @@ -265,94 +247,6 @@ static struct clk_sources clkset_uhost = { * have a common parent divisor so are not included here. */ -static inline struct clksrc_clk *to_clksrc(struct clk *clk) -{ - return container_of(clk, struct clksrc_clk, clk); -} - -static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv = __raw_readl(sclk->reg_divider); - - clkdiv >>= sclk->divider_shift; - clkdiv &= 0xf; - clkdiv++; - - rate /= clkdiv; - return rate; -} - -static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - void __iomem *reg = sclk->reg_divider; - unsigned int div; - u32 val; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - if (div > 16) - return -EINVAL; - - val = __raw_readl(reg); - val &= ~(0xf << sclk->divider_shift); - val |= (div - 1) << sclk->divider_shift; - __raw_writel(val, reg); - - return 0; -} - -static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - struct clk_sources *srcs = sclk->sources; - u32 clksrc = __raw_readl(S3C_CLK_SRC); - int src_nr = -1; - int ptr; - - for (ptr = 0; ptr < srcs->nr_sources; ptr++) - if (srcs->sources[ptr] == parent) { - src_nr = ptr; - break; - } - - if (src_nr >= 0) { - clksrc &= ~sclk->mask; - clksrc |= src_nr << sclk->shift; - - __raw_writel(clksrc, S3C_CLK_SRC); - - clk->parent = parent; - return 0; - } - - return -EINVAL; -} - -static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - rate = parent_rate; - else { - div = parent_rate / rate; - - if (div == 0) - div = 1; - if (div > 16) - div = 16; - - rate = parent_rate / div; - } - - return rate; -} - /* clocks that feed other parts of the clock source tree */ static struct clk clk_iis_cd0 = { @@ -378,7 +272,7 @@ static struct clk *clkset_audio0_list[] = { [4] = &clk_pcm_cd, }; -static struct clk_sources clkset_audio0 = { +static struct clksrc_sources clkset_audio0 = { .sources = clkset_audio0_list, .nr_sources = ARRAY_SIZE(clkset_audio0_list), }; @@ -391,7 +285,7 @@ static struct clk *clkset_audio1_list[] = { [4] = &clk_pcm_cd, }; -static struct clk_sources clkset_audio1 = { +static struct clksrc_sources clkset_audio1 = { .sources = clkset_audio1_list, .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; @@ -400,7 +294,7 @@ static struct clk *clkset_camif_list[] = { &clk_h2, }; -static struct clk_sources clkset_camif = { +static struct clksrc_sources clkset_camif = { .sources = clkset_camif_list, .nr_sources = ARRAY_SIZE(clkset_camif_list), }; @@ -413,11 +307,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC0, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_MMC0_SHIFT, - .mask = S3C6400_CLKSRC_MMC0_MASK, + .reg_src = { S3C_CLK_SRC, 18, 2 }, + .reg_div = { S3C_CLK_DIV1, 0, 4 }, .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, - .reg_divider = S3C_CLK_DIV1, }, { .clk = { .name = "mmc_bus", @@ -425,11 +317,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC1, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_MMC1_SHIFT, - .mask = S3C6400_CLKSRC_MMC1_MASK, + .reg_src = { S3C_CLK_SRC, 20, 2 }, + .reg_div = { S3C_CLK_DIV1, 4, 4 }, .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, - .reg_divider = S3C_CLK_DIV1, }, { .clk = { .name = "mmc_bus", @@ -437,11 +327,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC2, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_MMC2_SHIFT, - .mask = S3C6400_CLKSRC_MMC2_MASK, + .reg_src = { S3C_CLK_SRC, 22, 2 }, + .reg_div = { S3C_CLK_DIV1, 8, 4 }, .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, - .reg_divider = S3C_CLK_DIV1, }, { .clk = { .name = "usb-bus-host", @@ -449,11 +337,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_UHOST_SHIFT, - .mask = S3C6400_CLKSRC_UHOST_MASK, + .reg_src = { S3C_CLK_SRC, 5, 2 }, + .reg_div = { S3C_CLK_DIV1, 20, 4 }, .sources = &clkset_uhost, - .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, - .reg_divider = S3C_CLK_DIV1, }, { .clk = { .name = "uclk1", @@ -461,11 +347,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_UART, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_UART_SHIFT, - .mask = S3C6400_CLKSRC_UART_MASK, + .reg_src = { S3C_CLK_SRC, 13, 1 }, + .reg_div = { S3C_CLK_DIV2, 16, 4 }, .sources = &clkset_uart, - .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { /* Where does UCLK0 come from? */ .clk = { @@ -474,11 +358,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_SPI0_SHIFT, - .mask = S3C6400_CLKSRC_SPI0_MASK, + .reg_src = { S3C_CLK_SRC, 14, 2 }, + .reg_div = { S3C_CLK_DIV2, 0, 4 }, .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { .clk = { .name = "spi-bus", @@ -486,11 +368,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_SPI1_SHIFT, - .mask = S3C6400_CLKSRC_SPI1_MASK, + .reg_src = { S3C_CLK_SRC, 16, 2 }, + .reg_div = { S3C_CLK_DIV2, 4, 4 }, .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { .clk = { .name = "audio-bus", @@ -498,11 +378,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO0_MASK, + .reg_src = { S3C_CLK_SRC, 7, 3 }, + .reg_div = { S3C_CLK_DIV2, 8, 4 }, .sources = &clkset_audio0, - .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { .clk = { .name = "audio-bus", @@ -510,11 +388,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO1_MASK, + .reg_src = { S3C_CLK_SRC, 10, 3 }, + .reg_div = { S3C_CLK_DIV2, 12, 4 }, .sources = &clkset_audio1, - .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { .clk = { .name = "irda-bus", @@ -522,11 +398,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_IRDA, .enable = s3c64xx_sclk_ctrl, }, - .shift = S3C6400_CLKSRC_IRDA_SHIFT, - .mask = S3C6400_CLKSRC_IRDA_MASK, + .reg_src = { S3C_CLK_SRC, 24, 2 }, + .reg_div = { S3C_CLK_DIV2, 20, 4 }, .sources = &clkset_irda, - .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, - .reg_divider = S3C_CLK_DIV2, }, { .clk = { .name = "camera", @@ -534,11 +408,9 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_CAM, .enable = s3c64xx_sclk_ctrl, }, - .shift = 0, - .mask = 0, + .reg_div = { S3C_CLK_DIV0, 20, 4 }, + .reg_src = { NULL, 0, 0 }, .sources = &clkset_camif, - .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, - .reg_divider = S3C_CLK_DIV0, }, }; @@ -550,27 +422,6 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_mpll, }; -static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) -{ - struct clk_sources *srcs = clk->sources; - u32 clksrc = __raw_readl(S3C_CLK_SRC); - - clksrc &= clk->mask; - clksrc >>= clk->shift; - - if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { - printk(KERN_ERR "%s: bad source %d\n", - clk->clk.name, clksrc); - return; - } - - clk->clk.parent = srcs->sources[clksrc]; - - printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", - clk->clk.name, clk->clk.parent->name, clksrc, - clk_get_rate(&clk->clk)); -} - #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) void __init_or_cpufreq s3c6400_setup_clocks(void) @@ -629,10 +480,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) clk_f.rate = fclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c6400_set_clksrc(init_parents[ptr]); + s3c_set_clksrc(init_parents[ptr]); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c6400_set_clksrc(&clksrcs[ptr]); + s3c_set_clksrc(&clksrcs[ptr]); } static struct clk *clks[] __initdata = { @@ -675,19 +526,5 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) } } - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { - clkp = &clksrcs[ptr].clk; - - /* all clksrc clocks have these */ - clkp->get_rate = s3c64xx_getrate_clksrc; - clkp->set_rate = s3c64xx_setrate_clksrc; - clkp->set_parent = s3c64xx_setparent_clksrc; - clkp->round_rate = s3c64xx_roundrate_clksrc; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); } -- GitLab From 13bbd88504bfa0d205fa4121322869d8d7e083d0 Mon Sep 17 00:00:00 2001 From: Harald Welte Date: Tue, 1 Dec 2009 01:24:36 +0000 Subject: [PATCH 039/370] ARM: S3C64XX: Remove unused clock definitions from clock header Clean out the definitions we are no longer using after the new clock code updates. Signed-off-by: Harald Welte [ben-linux@fluff.org: split from initial patch provided] Signed-off-by: Ben Dooks --- .../plat-s3c64xx/include/plat/regs-clock.h | 71 +------------------ 1 file changed, 1 insertion(+), 70 deletions(-) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index ff46e7fa957ac..3ef62741e5d10 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -35,14 +35,6 @@ #define S3C_MEM0_GATE S3C_CLKREG(0x3C) /* CLKDIV0 */ -#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) -#define S3C6400_CLKDIV0_MFC_SHIFT (28) -#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) -#define S3C6400_CLKDIV0_JPEG_SHIFT (24) -#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) -#define S3C6400_CLKDIV0_CAM_SHIFT (20) -#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) -#define S3C6400_CLKDIV0_SECURITY_SHIFT (18) #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) #define S3C6400_CLKDIV0_PCLK_SHIFT (12) #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) @@ -51,42 +43,11 @@ #define S3C6400_CLKDIV0_HCLK_SHIFT (8) #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) #define S3C6400_CLKDIV0_MPLL_SHIFT (4) + #define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) #define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) #define S3C6400_CLKDIV0_ARM_SHIFT (0) -/* CLKDIV1 */ -#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) -#define S3C6410_CLKDIV1_FIMC_SHIFT (24) -#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) -#define S3C6400_CLKDIV1_UHOST_SHIFT (20) -#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) -#define S3C6400_CLKDIV1_SCALER_SHIFT (16) -#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) -#define S3C6400_CLKDIV1_LCD_SHIFT (12) -#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) -#define S3C6400_CLKDIV1_MMC2_SHIFT (8) -#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) -#define S3C6400_CLKDIV1_MMC1_SHIFT (4) -#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) -#define S3C6400_CLKDIV1_MMC0_SHIFT (0) - -/* CLKDIV2 */ -#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) -#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) -#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) -#define S3C6400_CLKDIV2_IRDA_SHIFT (20) -#define S3C6400_CLKDIV2_UART_MASK (0xf << 16) -#define S3C6400_CLKDIV2_UART_SHIFT (16) -#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) -#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) -#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) -#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) -#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) -#define S3C6400_CLKDIV2_SPI1_SHIFT (4) -#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) -#define S3C6400_CLKDIV2_SPI0_SHIFT (0) - /* HCLK GATE Registers */ #define S3C_CLKCON_HCLK_3DSE (1<<31) #define S3C_CLKCON_HCLK_UHOST (1<<29) @@ -192,34 +153,4 @@ #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) #define S3C6400_CLKSRC_MFC (1 << 4) -#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) -#define S3C6410_CLKSRC_TV27_SHIFT (31) -#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) -#define S3C6410_CLKSRC_DAC27_SHIFT (30) -#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) -#define S3C6400_CLKSRC_SCALER_SHIFT (28) -#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) -#define S3C6400_CLKSRC_LCD_SHIFT (26) -#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) -#define S3C6400_CLKSRC_IRDA_SHIFT (24) -#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) -#define S3C6400_CLKSRC_MMC2_SHIFT (22) -#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) -#define S3C6400_CLKSRC_MMC1_SHIFT (20) -#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) -#define S3C6400_CLKSRC_MMC0_SHIFT (18) -#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) -#define S3C6400_CLKSRC_SPI1_SHIFT (16) -#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) -#define S3C6400_CLKSRC_SPI0_SHIFT (14) -#define S3C6400_CLKSRC_UART_MASK (0x1 << 13) -#define S3C6400_CLKSRC_UART_SHIFT (13) -#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) -#define S3C6400_CLKSRC_AUDIO1_SHIFT (10) -#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) -#define S3C6400_CLKSRC_AUDIO0_SHIFT (7) -#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) -#define S3C6400_CLKSRC_UHOST_SHIFT (5) - - #endif /* _PLAT_REGS_CLOCK_H */ -- GitLab From b3bf41be06634d69959a68a2b53e1ffc92f0d103 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 1 Dec 2009 01:24:37 +0000 Subject: [PATCH 040/370] ARM: SAMSUNG: Reduce size of struct clk. Reduce the size of struct clk by 12 bytes and make defining clocks with common implementation functions easier by moving the set_rate, get_rate, round_rate and set_parent calls into a new structure called 'struct clk_ops' and using that instead. This change does make a few clocks larger as they need their own clk_ops, but this is outweighed by the number of clocks with either no ops or having a common set of ops. Update all the users of this. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2412/clock.c | 52 +++++---- arch/arm/mach-s3c2440/clock.c | 6 +- arch/arm/mach-s3c2442/clock.c | 6 +- arch/arm/mach-s3c2443/clock.c | 88 +++++++++----- arch/arm/plat-s3c/clock.c | 31 ++--- arch/arm/plat-s3c/pwm-clock.c | 94 +++++++-------- arch/arm/plat-s3c24xx/clock-dclk.c | 22 ++-- arch/arm/plat-s3c24xx/s3c244x-clock.c | 4 +- arch/arm/plat-s3c64xx/s3c6400-clock.c | 14 ++- arch/arm/plat-s5pc1xx/clock.c | 8 +- arch/arm/plat-s5pc1xx/s5pc100-clock.c | 126 +++++++++------------ arch/arm/plat-samsung/clock-clksrc.c | 17 +-- arch/arm/plat-samsung/include/plat/clock.h | 29 ++++- 13 files changed, 286 insertions(+), 211 deletions(-) diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index a037df5e1c2da..0c0505b025cb6 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -124,7 +124,9 @@ static struct clk clk_usysclk = { .name = "usysclk", .id = -1, .parent = &clk_xtal, - .set_parent = s3c2412_setparent_usysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_usysclk, + }, }; static struct clk clk_mrefclk = { @@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) static struct clk clk_usbsrc = { .name = "usbsrc", .id = -1, - .get_rate = s3c2412_getrate_usbsrc, - .set_rate = s3c2412_setrate_usbsrc, - .round_rate = s3c2412_roundrate_usbsrc, - .set_parent = s3c2412_setparent_usbsrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_usbsrc, + .set_rate = s3c2412_setrate_usbsrc, + .round_rate = s3c2412_roundrate_usbsrc, + .set_parent = s3c2412_setparent_usbsrc, + }, }; static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) @@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) static struct clk clk_msysclk = { .name = "msysclk", .id = -1, - .set_parent = s3c2412_setparent_msysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_msysclk, + }, }; static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) @@ -264,7 +270,9 @@ static struct clk clk_armclk = { .name = "armclk", .id = -1, .parent = &clk_msysclk, - .set_parent = s3c2412_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_armclk, + }, }; /* these next clocks have an divider immediately after them, @@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) static struct clk clk_uart = { .name = "uartclk", .id = -1, - .get_rate = s3c2412_getrate_uart, - .set_rate = s3c2412_setrate_uart, - .set_parent = s3c2412_setparent_uart, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_uart, + .set_rate = s3c2412_setrate_uart, + .set_parent = s3c2412_setparent_uart, + .round_rate = s3c2412_roundrate_clksrc, + }, }; static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) @@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) static struct clk clk_i2s = { .name = "i2sclk", .id = -1, - .get_rate = s3c2412_getrate_i2s, - .set_rate = s3c2412_setrate_i2s, - .set_parent = s3c2412_setparent_i2s, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_i2s, + .set_rate = s3c2412_setrate_i2s, + .set_parent = s3c2412_setparent_i2s, + .round_rate = s3c2412_roundrate_clksrc, + }, }; static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) @@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) static struct clk clk_cam = { .name = "camif-upll", /* same as 2440 name */ .id = -1, - .get_rate = s3c2412_getrate_cam, - .set_rate = s3c2412_setrate_cam, - .set_parent = s3c2412_setparent_cam, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_cam, + .set_rate = s3c2412_setrate_cam, + .set_parent = s3c2412_setparent_cam, + .round_rate = s3c2412_roundrate_clksrc, + }, }; /* standard clock definitions */ diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index d1c29b2537cda..3dc2426e23457 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c @@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = { static struct clk s3c2440_clk_cam_upll = { .name = "camif-upll", .id = -1, - .set_rate = s3c2440_camif_upll_setrate, - .round_rate = s3c2440_camif_upll_round, + .ops = &(struct clk_ops) { + .set_rate = s3c2440_camif_upll_setrate, + .round_rate = s3c2440_camif_upll_round, + }, }; static struct clk s3c2440_clk_ac97 = { diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c index ea1aa1f5157a7..d9b692a124802 100644 --- a/arch/arm/mach-s3c2442/clock.c +++ b/arch/arm/mach-s3c2442/clock.c @@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = { static struct clk s3c2442_clk_cam_upll = { .name = "camif-upll", .id = -1, - .set_rate = s3c2442_camif_upll_setrate, - .round_rate = s3c2442_camif_upll_round, + .ops = &(struct clk_ops) { + .set_rate = s3c2442_camif_upll_setrate, + .round_rate = s3c2442_camif_upll_round, + }, }; static int s3c2442_clk_add(struct sys_device *sysdev) diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 2785d69c95b0d..91db4f54bb332 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) static struct clk clk_epllref = { .name = "epllref", .id = -1, - .set_parent = s3c2443_setparent_epllref, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_epllref, + }, }; static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) @@ -205,7 +207,9 @@ static struct clk clk_mdivclk = { .name = "mdivclk", .parent = &clk_mpllref, .id = -1, - .get_rate = s3c2443_getrate_mdivclk, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_mdivclk, + }, }; static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) @@ -232,7 +236,9 @@ static struct clk clk_msysclk = { .name = "msysclk", .parent = &clk_xtal, .id = -1, - .set_parent = s3c2443_setparent_msysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_msysclk, + }, }; /* armdiv @@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) static struct clk clk_arm = { .name = "armclk", .id = -1, - .set_parent = s3c2443_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_armclk, + }, }; /* esysclk @@ -302,7 +310,9 @@ static struct clk clk_esysclk = { .name = "esysclk", .parent = &clk_epll, .id = -1, - .set_parent = s3c2443_setparent_esysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_esysclk, + }, }; /* uartclk @@ -341,9 +351,11 @@ static struct clk clk_uart = { .name = "uartclk", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_uart, - .set_rate = s3c2443_setrate_uart, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_uart, + .set_rate = s3c2443_setrate_uart, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* hsspi @@ -384,9 +396,11 @@ static struct clk clk_hsspi = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_HSSPICLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_hsspi, - .set_rate = s3c2443_setrate_hsspi, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_hsspi, + .set_rate = s3c2443_setrate_hsspi, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; /* usbhost @@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_USBHOST, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_usbhost, - .set_rate = s3c2443_setrate_usbhost, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_usbhost, + .set_rate = s3c2443_setrate_usbhost, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; /* clk_hsmcc_div @@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = { .name = "hsmmc-div", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_hsmmc_div, - .set_rate = s3c2443_setrate_hsmmc_div, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_hsmmc_div, + .set_rate = s3c2443_setrate_hsmmc_div, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) @@ -505,7 +523,9 @@ static struct clk clk_hsmmc = { .id = -1, .parent = &clk_hsmmc_div, .enable = s3c2443_enable_hsmmc, - .set_parent = s3c2443_setparent_hsmmc, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_hsmmc, + }, }; /* i2s_eplldiv @@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = { .name = "i2s-eplldiv", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_i2s_eplldiv, - .set_rate = s3c2443_setrate_i2s_eplldiv, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_i2s_eplldiv, + .set_rate = s3c2443_setrate_i2s_eplldiv, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* i2s-ref @@ -578,7 +600,9 @@ static struct clk clk_i2s = { .parent = &clk_i2s_eplldiv, .ctrlbit = S3C2443_SCLKCON_I2SCLK, .enable = s3c2443_clkcon_enable_s, - .set_parent = s3c2443_setparent_i2s, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_i2s, + }, }; /* cam-if @@ -618,9 +642,11 @@ static struct clk clk_cam = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_CAMCLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_cam, - .set_rate = s3c2443_setrate_cam, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_cam, + .set_rate = s3c2443_setrate_cam, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* display-if @@ -660,9 +686,11 @@ static struct clk clk_display = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_DISPCLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_display, - .set_rate = s3c2443_setrate_display, - .round_rate = s3c2443_roundrate_clksrc256, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_display, + .set_rate = s3c2443_setrate_display, + .round_rate = s3c2443_roundrate_clksrc256, + }, }; /* prediv @@ -685,7 +713,9 @@ static struct clk clk_prediv = { .name = "prediv", .id = -1, .parent = &clk_msysclk, - .get_rate = s3c2443_prediv_getrate, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_prediv_getrate, + }, }; /* standard clock definitions */ diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c index 619cfa82dcab2..fa91125c7e0e8 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-s3c/clock.c @@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk) if (clk->rate != 0) return clk->rate; - if (clk->get_rate != NULL) - return (clk->get_rate)(clk); + if (clk->ops != NULL && clk->ops->get_rate != NULL) + return (clk->ops->get_rate)(clk); if (clk->parent != NULL) return clk_get_rate(clk->parent); @@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk) long clk_round_rate(struct clk *clk, unsigned long rate) { - if (!IS_ERR(clk) && clk->round_rate) - return (clk->round_rate)(clk, rate); + if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) + return (clk->ops->round_rate)(clk, rate); return rate; } @@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) * the clock may have been made this way by choice. */ - WARN_ON(clk->set_rate == NULL); + WARN_ON(clk->ops == NULL); + WARN_ON(clk->ops && clk->ops->set_rate == NULL); - if (clk->set_rate == NULL) + if (clk->ops == NULL || clk->ops->set_rate == NULL) return -EINVAL; spin_lock(&clocks_lock); - ret = (clk->set_rate)(clk, rate); + ret = (clk->ops->set_rate)(clk, rate); spin_unlock(&clocks_lock); return ret; @@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) spin_lock(&clocks_lock); - if (clk->set_parent) - ret = (clk->set_parent)(clk, parent); + if (clk->ops && clk->ops->set_parent) + ret = (clk->ops->set_parent)(clk, parent); spin_unlock(&clocks_lock); @@ -230,6 +231,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_ops_def_setrate = { + .set_rate = clk_default_setrate, +}; + struct clk clk_xtal = { .name = "xtal", .id = -1, @@ -251,7 +256,7 @@ struct clk clk_epll = { struct clk clk_mpll = { .name = "mpll", .id = -1, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_upll = { @@ -267,7 +272,6 @@ struct clk clk_f = { .rate = 0, .parent = &clk_mpll, .ctrlbit = 0, - .set_rate = clk_default_setrate, }; struct clk clk_h = { @@ -276,7 +280,7 @@ struct clk clk_h = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_p = { @@ -285,7 +289,7 @@ struct clk clk_p = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_usb_bus = { @@ -296,7 +300,6 @@ struct clk clk_usb_bus = { }; - struct clk s3c24xx_uclk = { .name = "uclk", .id = -1, diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index a318215ab5352..1808fa88609a2 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c @@ -130,20 +130,22 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_pwm_scaler_ops = { + .get_rate = clk_pwm_scaler_get_rate, + .set_rate = clk_pwm_scaler_set_rate, + .round_rate = clk_pwm_scaler_round_rate, +}; + static struct clk clk_timer_scaler[] = { [0] = { .name = "pwm-scaler0", .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, + .ops = &clk_pwm_scaler_ops, }, [1] = { .name = "pwm-scaler1", .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, + .ops = &clk_pwm_scaler_ops, }, }; @@ -256,50 +258,46 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_tdiv_ops = { + .get_rate = clk_pwm_tdiv_get_rate, + .set_rate = clk_pwm_tdiv_set_rate, + .round_rate = clk_pwm_tdiv_round_rate, +}; + static struct pwm_tdiv_clk clk_timer_tdiv[] = { [0] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[0], }, }, [1] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[0], } }, [2] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, [3] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, [4] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, }; @@ -356,31 +354,35 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) return 0; } +static struct clk_ops clk_tin_ops = { + .set_parent = clk_pwm_tin_set_parent, +}; + static struct clk clk_tin[] = { [0] = { - .name = "pwm-tin", - .id = 0, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 0, + .ops = &clk_tin_ops, }, [1] = { - .name = "pwm-tin", - .id = 1, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 1, + .ops = &clk_tin_ops, }, [2] = { - .name = "pwm-tin", - .id = 2, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 2, + .ops = &clk_tin_ops, }, [3] = { - .name = "pwm-tin", - .id = 3, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 3, + .ops = &clk_tin_ops, }, [4] = { - .name = "pwm-tin", - .id = 4, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 4, + .ops = &clk_tin_ops, }, }; diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index ac061a1bcb37c..cf97caafe56b6 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c @@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) /* external clock definitions */ +static struct clk_ops dclk_ops = { + .set_parent = s3c24xx_dclk_setparent, + .set_rate = s3c24xx_set_dclk_rate, + .round_rate = s3c24xx_round_dclk_rate, +}; + struct clk s3c24xx_dclk0 = { .name = "dclk0", .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK0EN, .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, + .ops = &dclk_ops, }; struct clk s3c24xx_dclk1 = { @@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = { .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK1EN, .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, + .ops = &dclk_ops, +}; + +static struct clk_ops clkout_ops = { + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_clkout0 = { .name = "clkout0", .id = -1, - .set_parent = s3c24xx_clkout_setparent, + .ops = &clkout_ops, }; struct clk s3c24xx_clkout1 = { .name = "clkout1", .id = -1, - .set_parent = s3c24xx_clkout_setparent, + .ops = &clkout_ops, }; diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index 79371091aa383..f8d96130d1d1d 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c @@ -68,7 +68,9 @@ static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent) static struct clk clk_arm = { .name = "armclk", .id = -1, - .set_parent = s3c2440_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2440_setparent_armclk, + }, }; static int s3c244x_clk_add(struct sys_device *sysdev) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 20af0c29979a9..f85406a11385d 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -165,9 +165,11 @@ static struct clk clk_arm = { .name = "armclk", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s3c64xx_clk_arm_get_rate, - .set_rate = s3c64xx_clk_arm_set_rate, - .round_rate = s3c64xx_clk_arm_round_rate, + .ops = &(struct clk_ops) { + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, + .round_rate = s3c64xx_clk_arm_round_rate, + }, }; static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) @@ -182,11 +184,15 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) return rate; } +static struct clk_ops clk_dout_ops = { + .get_rate = s3c64xx_clk_doutmpll_get_rate, +}; + static struct clk clk_dout_mpll = { .name = "dout_mpll", .id = -1, .parent = &clk_mout_mpll.clk, - .get_rate = s3c64xx_clk_doutmpll_get_rate, + .ops = &clk_dout_ops, }; static struct clk *clkset_spi_mmc_list[] = { diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 26c21d8497909..2f4d8d4c4e1c8 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -70,6 +70,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_ops_default_setrate = { + .set_rate = clk_default_setrate, +}; + static int clk_dummy_enable(struct clk *clk, int enable) { return 0; @@ -81,8 +85,8 @@ struct clk clk_hd0 = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, .enable = clk_dummy_enable, + .ops = &clk_ops_default_setrate, }; struct clk clk_pd0 = { @@ -91,7 +95,7 @@ struct clk clk_pd0 = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, + .ops = &clk_ops_default_setrate, .enable = clk_dummy_enable, }; diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index b436d44510c8f..16f0b90773907 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -111,7 +111,9 @@ static struct clk clk_dout_apll = { .name = "dout_apll", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s5pc100_clk_dout_apll_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_apll_get_rate, + }, }; static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) @@ -165,9 +167,11 @@ static struct clk clk_arm = { .name = "armclk", .id = -1, .parent = &clk_dout_apll, - .get_rate = s5pc100_clk_arm_get_rate, - .set_rate = s5pc100_clk_arm_set_rate, - .round_rate = s5pc100_clk_arm_round_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_arm_get_rate, + .set_rate = s5pc100_clk_arm_set_rate, + .round_rate = s5pc100_clk_arm_round_rate, + }, }; static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) @@ -185,7 +189,9 @@ static struct clk clk_dout_d0_bus = { .name = "dout_d0_bus", .id = -1, .parent = &clk_arm, - .get_rate = s5pc100_clk_dout_d0_bus_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_d0_bus_get_rate, + }, }; static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) @@ -203,7 +209,9 @@ static struct clk clk_dout_pclkd0 = { .name = "dout_pclkd0", .id = -1, .parent = &clk_dout_d0_bus, - .get_rate = s5pc100_clk_dout_pclkd0_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_pclkd0_get_rate, + }, }; static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) @@ -221,7 +229,9 @@ static struct clk clk_dout_apll2 = { .name = "dout_apll2", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s5pc100_clk_dout_apll2_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_apll2_get_rate, + }, }; /* MPLL */ @@ -284,7 +294,9 @@ static struct clk clk_dout_d1_bus = { .name = "dout_d1_bus", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_d1_bus_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_d1_bus_get_rate, + }, }; static struct clk *clkset_onenand_list[] = { @@ -325,7 +337,9 @@ static struct clk clk_dout_pclkd1 = { .name = "dout_pclkd1", .id = -1, .parent = &clk_dout_d1_bus, - .get_rate = s5pc100_clk_dout_pclkd1_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_pclkd1_get_rate, + }, }; static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) @@ -345,7 +359,9 @@ static struct clk clk_dout_mpll2 = { .name = "dout_mpll2", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_mpll2_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_mpll2_get_rate, + }, }; static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) @@ -365,7 +381,9 @@ static struct clk clk_dout_cam = { .name = "dout_cam", .id = -1, .parent = &clk_dout_mpll2, - .get_rate = s5pc100_clk_dout_cam_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_cam_get_rate, + }, }; static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) @@ -385,7 +403,9 @@ static struct clk clk_dout_mpll = { .name = "dout_mpll", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_mpll_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_mpll_get_rate, + }, }; /* EPLL */ @@ -540,6 +560,13 @@ static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, return rate; } +static struct clk_ops s5pc100_clksrc_ops = { + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, +}; + static struct clk *clkset_spi_list[] = { &clk_mout_epll.clk, &clk_dout_mpll2, @@ -558,10 +585,7 @@ static struct clksrc_clk clk_spi0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + }, .shift = S5PC100_CLKSRC1_SPI0_SHIFT, .mask = S5PC100_CLKSRC1_SPI0_MASK, @@ -577,10 +601,7 @@ static struct clksrc_clk clk_spi1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC1_SPI1_SHIFT, .mask = S5PC100_CLKSRC1_SPI1_MASK, @@ -596,10 +617,7 @@ static struct clksrc_clk clk_spi2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC1_SPI2_SHIFT, .mask = S5PC100_CLKSRC1_SPI2_MASK, @@ -625,10 +643,7 @@ static struct clksrc_clk clk_uart_uclk1 = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC1_UART_SHIFT, .mask = S5PC100_CLKSRC1_UART_MASK, @@ -683,10 +698,7 @@ static struct clksrc_clk clk_audio0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, .mask = S5PC100_CLKSRC3_AUDIO0_MASK, @@ -716,10 +728,7 @@ static struct clksrc_clk clk_audio1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, .mask = S5PC100_CLKSRC3_AUDIO1_MASK, @@ -748,10 +757,7 @@ static struct clksrc_clk clk_audio2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, .mask = S5PC100_CLKSRC3_AUDIO2_MASK, @@ -801,10 +807,7 @@ static struct clksrc_clk clk_lcd = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_LCD_SHIFT, .mask = S5PC100_CLKSRC2_LCD_MASK, @@ -820,10 +823,7 @@ static struct clksrc_clk clk_fimc0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, .mask = S5PC100_CLKSRC2_FIMC0_MASK, @@ -839,10 +839,7 @@ static struct clksrc_clk clk_fimc1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, .mask = S5PC100_CLKSRC2_FIMC1_MASK, @@ -858,10 +855,7 @@ static struct clksrc_clk clk_fimc2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, .mask = S5PC100_CLKSRC2_FIMC2_MASK, @@ -889,10 +883,7 @@ static struct clksrc_clk clk_mmc0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_MMC0_SHIFT, .mask = S5PC100_CLKSRC2_MMC0_MASK, @@ -908,10 +899,7 @@ static struct clksrc_clk clk_mmc1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_MMC1_SHIFT, .mask = S5PC100_CLKSRC2_MMC1_MASK, @@ -927,10 +915,7 @@ static struct clksrc_clk clk_mmc2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC2_MMC2_SHIFT, .mask = S5PC100_CLKSRC2_MMC2_MASK, @@ -959,10 +944,7 @@ static struct clksrc_clk clk_usbhost = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, + .ops = &s5pc100_clksrc_ops, }, .shift = S5PC100_CLKSRC1_UHOST_SHIFT, .mask = S5PC100_CLKSRC1_UHOST_MASK, diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 5872f0b62b7c2..ad4e8723a811c 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -150,20 +150,21 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk) clk_get_rate(&clk->clk)); } +static struct clk_ops clksrc_ops = { + .set_parent = s3c_setparent_clksrc, + .get_rate = s3c_getrate_clksrc, + .set_rate = s3c_setrate_clksrc, + .round_rate = s3c_roundrate_clksrc, +}; + void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) { int ret; for (; size > 0; size--, clksrc++) { /* fill in the default functions */ - if (!clksrc->clk.set_parent) - clksrc->clk.set_parent = s3c_setparent_clksrc; - if (!clksrc->clk.get_rate) - clksrc->clk.get_rate = s3c_getrate_clksrc; - if (!clksrc->clk.set_rate) - clksrc->clk.set_rate = s3c_setrate_clksrc; - if (!clksrc->clk.round_rate) - clksrc->clk.round_rate = s3c_roundrate_clksrc; + if (!clksrc->clk.ops) + clksrc->clk.ops = &clksrc_ops; s3c_set_clksrc(clksrc); diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index d86af84b5b8cd..43324af24c6e8 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -11,6 +11,30 @@ #include +struct clk; + +/** + * struct clk_ops - standard clock operations + * @set_rate: set the clock rate, see clk_set_rate(). + * @get_rate: get the clock rate, see clk_get_rate(). + * @round_rate: round a given clock rate, see clk_round_rate(). + * @set_parent: set the clock's parent, see clk_set_parent(). + * + * Group the common clock implementations together so that we + * don't have to keep setting the same fiels again. We leave + * enable in struct clk. + * + * Adding an extra layer of indirection into the process should + * not be a problem as it is unlikely these operations are going + * to need to be called quickly. + */ +struct clk_ops { + int (*set_rate)(struct clk *c, unsigned long rate); + unsigned long (*get_rate)(struct clk *c); + unsigned long (*round_rate)(struct clk *c, unsigned long rate); + int (*set_parent)(struct clk *c, struct clk *parent); +}; + struct clk { struct list_head list; struct module *owner; @@ -21,11 +45,8 @@ struct clk { unsigned long rate; unsigned long ctrlbit; + struct clk_ops *ops; int (*enable)(struct clk *, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); }; /* other clocks which may be registered by board support */ -- GitLab From f3e0b724cc70ef5ee2a6e0d9dfafa2328c294ab3 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 8 Dec 2009 01:26:07 +0000 Subject: [PATCH 041/370] ARM: S3C64XX: Fixup .reg_src and .reg_div with named initialisers Change these two fields to have named initialisers as per the review comments from Kyungmin Park. sed used: s@\.reg_src\(.*\)=\(.*\){\(.*\),\(.*\),\(.*\)}@.reg_src\1=\2{ .reg =\3, .shift =\4, .size =\5 }@g s@\.reg_div\(.*\)=\(.*\){\(.*\),\(.*\),\(.*\)}@.reg_div\1=\2{ .reg =\3, .shift =\4, .size =\5 }@g Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/s3c6400-clock.c | 50 +++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index f85406a11385d..555d1aa6b5ace 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -69,7 +69,7 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .reg_src = { S3C_CLK_SRC, 0, 1 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, .sources = &clk_src_apll, }; @@ -88,7 +88,7 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .reg_src = { S3C_CLK_SRC, 2, 1 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, .sources = &clk_src_epll, }; @@ -107,7 +107,7 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .reg_src = { S3C_CLK_SRC, 1, 1 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, .sources = &clk_src_mpll, }; @@ -313,8 +313,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC0, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 18, 2 }, - .reg_div = { S3C_CLK_DIV1, 0, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, .sources = &clkset_spi_mmc, }, { .clk = { @@ -323,8 +323,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC1, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 20, 2 }, - .reg_div = { S3C_CLK_DIV1, 4, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, .sources = &clkset_spi_mmc, }, { .clk = { @@ -333,8 +333,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_MMC2, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 22, 2 }, - .reg_div = { S3C_CLK_DIV1, 8, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, .sources = &clkset_spi_mmc, }, { .clk = { @@ -343,8 +343,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 5, 2 }, - .reg_div = { S3C_CLK_DIV1, 20, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, .sources = &clkset_uhost, }, { .clk = { @@ -353,8 +353,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_UART, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 13, 1 }, - .reg_div = { S3C_CLK_DIV2, 16, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, .sources = &clkset_uart, }, { /* Where does UCLK0 come from? */ @@ -364,8 +364,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 14, 2 }, - .reg_div = { S3C_CLK_DIV2, 0, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, .sources = &clkset_spi_mmc, }, { .clk = { @@ -374,8 +374,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 16, 2 }, - .reg_div = { S3C_CLK_DIV2, 4, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, .sources = &clkset_spi_mmc, }, { .clk = { @@ -384,8 +384,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 7, 3 }, - .reg_div = { S3C_CLK_DIV2, 8, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, .sources = &clkset_audio0, }, { .clk = { @@ -394,8 +394,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 10, 3 }, - .reg_div = { S3C_CLK_DIV2, 12, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, .sources = &clkset_audio1, }, { .clk = { @@ -404,8 +404,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_IRDA, .enable = s3c64xx_sclk_ctrl, }, - .reg_src = { S3C_CLK_SRC, 24, 2 }, - .reg_div = { S3C_CLK_DIV2, 20, 4 }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, .sources = &clkset_irda, }, { .clk = { @@ -414,8 +414,8 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S3C_CLKCON_SCLK_CAM, .enable = s3c64xx_sclk_ctrl, }, - .reg_div = { S3C_CLK_DIV0, 20, 4 }, - .reg_src = { NULL, 0, 0 }, + .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, + .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, .sources = &clkset_camif, }, }; -- GitLab From 682e2b7d45878586ce84f6993da0b8a2981a399d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 9 Dec 2009 00:08:35 +0000 Subject: [PATCH 042/370] ARM: S3C64XX: Avoid announcing clksrc clocks twice The new code calls the clock setup code on registration which can be before the clock system has been fully initialised. The following code re-does this setup at the end of the clock registration and thus we get two printings. Update the calls to only print on the last pass or when doing the necessary resume work. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/s3c6400-clock.c | 4 ++-- arch/arm/plat-samsung/clock-clksrc.c | 16 +++++++++++----- .../arm/plat-samsung/include/plat/clock-clksrc.h | 10 +++++++++- 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 555d1aa6b5ace..cb2bf4bff0514 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -486,10 +486,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) clk_f.rate = fclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr]); + s3c_set_clksrc(init_parents[ptr], true); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr]); + s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index ad4e8723a811c..12129f8e509c8 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -125,7 +125,7 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk, /* Clock initialisation code */ -void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk) +void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce) { struct clksrc_sources *srcs = clk->sources; u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); @@ -145,9 +145,10 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk) clk->clk.parent = srcs->sources[clksrc]; - printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", - clk->clk.name, clk->clk.parent->name, clksrc, - clk_get_rate(&clk->clk)); + if (announce) + printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", + clk->clk.name, clk->clk.parent->name, clksrc, + clk_get_rate(&clk->clk)); } static struct clk_ops clksrc_ops = { @@ -166,7 +167,12 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) if (!clksrc->clk.ops) clksrc->clk.ops = &clksrc_ops; - s3c_set_clksrc(clksrc); + /* setup the clocksource, but do not announce it + * as it may be re-set by the setup routines + * called after the rest of the clocks have been + * registered + */ + s3c_set_clksrc(clksrc, false); ret = s3c24xx_register_clock(&clksrc->clk); diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h index 283dfa0287573..50a8ca7c37608 100644 --- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h +++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h @@ -63,7 +63,15 @@ struct clksrc_clk { struct clksrc_reg reg_div; }; -extern void s3c_set_clksrc(struct clksrc_clk *clk); +/** + * s3c_set_clksrc() - setup the clock from the register settings + * @clk: The clock to setup. + * @announce: true to announce the setting to printk(). + * + * Setup the clock from the current register settings, for when the + * kernel boots or if it is resuming from a possibly unknown state. + */ +extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce); /** * s3c_register_clksrc() register clocks from an array of clksrc clocks -- GitLab From 2c2f69b15d5420291a941ace10149e76f0af7ab0 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 23 Dec 2009 18:43:48 +0000 Subject: [PATCH 043/370] ARM: SAMSUNG: Move clock.c to arch/arm/plat-samsung This is the core implementation of the clock code for all Samsung based SoCs, so move it to arch/arm/plat-samsung (the clock.h file has already been moved). Since the file is built for every Samsung SoC, no changes are needed to the Kconfig system. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 3 +-- arch/arm/plat-samsung/Makefile | 4 ++++ arch/arm/{plat-s3c => plat-samsung}/clock.c | 0 3 files changed, 5 insertions(+), 2 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/clock.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 50444da984256..99f91ad1d5557 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -11,9 +11,8 @@ obj- := # Core support for all Samsung SoCs -obj-y += init.o +obj-y += init.o obj-y += time.o -obj-y += clock.o obj-y += pwm-clock.o obj-y += gpio.o obj-y += gpio-config.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index ce736ce468fdc..7612198bfa59f 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -9,4 +9,8 @@ obj-m := obj-n := dummy.o obj- := +# Objects we always build independent of SoC choice + +obj-y += clock.o + obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-samsung/clock.c similarity index 100% rename from arch/arm/plat-s3c/clock.c rename to arch/arm/plat-samsung/clock.c -- GitLab From fb6e76cd2309c76d2120e013ff34ff6ab27aad88 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 01:07:57 +0900 Subject: [PATCH 044/370] ARM: SAMSUNG: Do not allow get/set/round rate calls with no divider If the reg_div field is not set, then do not register clk_ops with the get/set/round rate calls as these will fail to work. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock-clksrc.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 12129f8e509c8..aaf7d5ebea96f 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -158,14 +158,25 @@ static struct clk_ops clksrc_ops = { .round_rate = s3c_roundrate_clksrc, }; +static struct clk_ops clksrc_ops_nodiv = { + .set_parent = s3c_setparent_clksrc, +}; + void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) { int ret; + WARN_ON(!clksrc->reg_div.reg && !clksrc->reg_src.reg); + for (; size > 0; size--, clksrc++) { /* fill in the default functions */ - if (!clksrc->clk.ops) - clksrc->clk.ops = &clksrc_ops; + + if (!clksrc->clk.ops) { + if (!clksrc->reg_div.reg) + clksrc->clk.ops = &clksrc_ops_nodiv; + else + clksrc->clk.ops = &clksrc_ops; + } /* setup the clocksource, but do not announce it * as it may be re-set by the setup routines -- GitLab From 1d9f13c49ed750260f40317629bdd66160a3ac16 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 01:21:38 +0900 Subject: [PATCH 045/370] ARM: SAMSUNG: Add call to register array of clocks Add s3c_register_clocks() to register an array of clocks, printing an error message if there is a problem. Replace all points in the code where this could be used. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 9 +-------- arch/arm/plat-s3c/pwm-clock.c | 18 ++++-------------- arch/arm/plat-s3c64xx/clock.c | 10 +--------- arch/arm/plat-s5pc1xx/clock.c | 12 ++---------- arch/arm/plat-samsung/clock.c | 22 ++++++++++++++++++++++ arch/arm/plat-samsung/include/plat/clock.h | 2 ++ 6 files changed, 32 insertions(+), 41 deletions(-) diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 91db4f54bb332..3eb8b935d64c2 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -1104,14 +1104,7 @@ void __init s3c2443_init_clocks(int xtal) /* register clocks from clock array */ - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); /* We must be careful disabling the clocks we are not intending to * be using at boot time, as subsystems such as the LCD which do diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index 1808fa88609a2..46c9381e083b2 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c @@ -430,25 +430,15 @@ __init void s3c_pwmclk_init(void) return; } - for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { + for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) clk_timer_scaler[clk].parent = clk_timers; - ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); - return; - } - } - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) { - ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pww tclk%d\n", clk); - return; - } - } + s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler)); + s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk)); for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { ret = clk_pwm_tdiv_register(clk); + if (ret < 0) { printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); return; diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 7a36e899360d5..ae5883c00e7ad 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -274,15 +274,7 @@ void __init s3c64xx_register_clocks(void) int ptr; s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 2f4d8d4c4e1c8..0aff16d1cc2c6 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -704,16 +704,8 @@ void __init s5pc1xx_register_clocks(void) s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - clkp = s5pc100_init_clocks; - size = ARRAY_SIZE(s5pc100_init_clocks); - - for (ptr = 0; ptr < size; ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(s5pc100_init_clocks, + ARRAY_SIZE(s5pc100_init_clocks)); clkp = s5pc100_init_clocks_disable; size = ARRAY_SIZE(s5pc100_init_clocks_disable); diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index fa91125c7e0e8..9194af91e4b7a 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -336,6 +336,28 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) return fails; } +/** + * s3c_register_clocks() - register an array of clocks + * @clkp: Pointer to the first clock in the array. + * @nr_clks: Number of clocks to register. + * + * Call s3c24xx_register_clock() on the @clkp array given, printing an + * error if it fails to register the clock (unlikely). + */ +void __initdata s3c_register_clocks(struct clk *clkp, int nr_clks) +{ + int ret; + + for (; nr_clks > 0; nr_clks--, clkp++) { + ret = s3c24xx_register_clock(clkp); + + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } +} + /* initalise all the clocks */ int __init s3c24xx_register_baseclocks(unsigned long xtal) diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 43324af24c6e8..bd41f828d15d0 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -87,6 +87,8 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable); extern int s3c24xx_register_clock(struct clk *clk); extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); +extern void s3c_register_clocks(struct clk *clk, int nr_clks); + extern int s3c24xx_register_baseclocks(unsigned long xtal); extern void s3c64xx_register_clocks(void); -- GitLab From 14235696d401e62f8f5740ca2fb917ab42b9fd18 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 01:53:25 +0900 Subject: [PATCH 046/370] ARM: SAMSUNG: Do not register set_parent call if no source If there is no source register defined, do not register a clksrc clock with a valid .set_parent in the ops. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock-clksrc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index aaf7d5ebea96f..33c633a8be8de 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -86,7 +86,7 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) break; } - if (src_nr >= 0 && sclk->reg_src.reg) { + if (src_nr >= 0) { clk->parent = parent; clksrc &= ~mask; @@ -162,6 +162,12 @@ static struct clk_ops clksrc_ops_nodiv = { .set_parent = s3c_setparent_clksrc, }; +static struct clk_ops clksrc_ops_nosrc = { + .get_rate = s3c_getrate_clksrc, + .set_rate = s3c_setrate_clksrc, + .round_rate = s3c_roundrate_clksrc, +}; + void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) { int ret; @@ -174,6 +180,8 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) if (!clksrc->clk.ops) { if (!clksrc->reg_div.reg) clksrc->clk.ops = &clksrc_ops_nodiv; + else if (!clksrc->reg_src.reg) + clksrc->clk.ops = &clksrc_ops_nosrc; else clksrc->clk.ops = &clksrc_ops; } -- GitLab From ed276849bc6a8ad5bb0f9fa94fe8305ee67bb6c6 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 12:50:23 +0900 Subject: [PATCH 047/370] ARM: SAMSUNG: Make clk_default_setrate and clk_ops_def_setrate visible This patch makes clk_default_setrate and clk_ops_def_setrate available to code outside plat-samsung clock code. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/clock.c | 14 ++------------ arch/arm/plat-samsung/clock.c | 4 ++-- arch/arm/plat-samsung/include/plat/clock.h | 3 +++ 3 files changed, 7 insertions(+), 14 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 0aff16d1cc2c6..aec0305174aa1 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -64,16 +64,6 @@ struct clk clk_54m = { .rate = 54000000, }; -static int clk_default_setrate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} - -static struct clk_ops clk_ops_default_setrate = { - .set_rate = clk_default_setrate, -}; - static int clk_dummy_enable(struct clk *clk, int enable) { return 0; @@ -86,7 +76,7 @@ struct clk clk_hd0 = { .parent = NULL, .ctrlbit = 0, .enable = clk_dummy_enable, - .ops = &clk_ops_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_pd0 = { @@ -95,7 +85,7 @@ struct clk clk_pd0 = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .ops = &clk_ops_default_setrate, + .ops = &clk_ops_def_setrate, .enable = clk_dummy_enable, }; diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 9194af91e4b7a..0c746ae7b2a63 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -225,13 +225,13 @@ EXPORT_SYMBOL(clk_set_parent); /* base clocks */ -static int clk_default_setrate(struct clk *clk, unsigned long rate) +int clk_default_setrate(struct clk *clk, unsigned long rate) { clk->rate = rate; return 0; } -static struct clk_ops clk_ops_def_setrate = { +struct clk_ops clk_ops_def_setrate = { .set_rate = clk_default_setrate, }; diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index bd41f828d15d0..22e011497502c 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -75,6 +75,9 @@ extern struct clk clk_h2; extern struct clk clk_27m; extern struct clk clk_48m; +extern int clk_default_setrate(struct clk *clk, unsigned long rate); +extern struct clk_ops clk_ops_def_setrate; + /* exports for arch/arm/mach-s3c2410 * * Please DO NOT use these outside of arch/arm/mach-s3c2410 -- GitLab From 9745626b65b856bf58e70feb4eee1e5471db699e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 02:39:28 +0900 Subject: [PATCH 048/370] ARM: SAMSUNG: Move pwm-clock code into plat-samsung Move the code for the pwm-clock into plat-samsung, as it is common to all Samsung SoCs. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 1 - arch/arm/plat-samsung/Makefile | 1 + arch/arm/{plat-s3c => plat-samsung}/pwm-clock.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/{plat-s3c => plat-samsung}/pwm-clock.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 99f91ad1d5557..ef10a9131bba5 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -13,7 +13,6 @@ obj- := obj-y += init.o obj-y += time.o -obj-y += pwm-clock.o obj-y += gpio.o obj-y += gpio-config.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 7612198bfa59f..d4d5f942d34c4 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -12,5 +12,6 @@ obj- := # Objects we always build independent of SoC choice obj-y += clock.o +obj-y += pwm-clock.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c similarity index 100% rename from arch/arm/plat-s3c/pwm-clock.c rename to arch/arm/plat-samsung/pwm-clock.c -- GitLab From b6a604137bb978d9f65b1228cf0bb691ece45cba Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 02:45:09 +0900 Subject: [PATCH 049/370] ARM: SAMSUNG: Move device definitions in plat-samsung Move all the platform device definitions from plat-s3c into plat-samsung Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Kconfig | 42 ------------------- arch/arm/plat-s3c/Makefile | 12 ------ arch/arm/plat-samsung/Kconfig | 42 +++++++++++++++++++ arch/arm/plat-samsung/Makefile | 12 ++++++ arch/arm/{plat-s3c => plat-samsung}/dev-fb.c | 0 .../{plat-s3c => plat-samsung}/dev-hsmmc.c | 0 .../{plat-s3c => plat-samsung}/dev-hsmmc1.c | 0 .../{plat-s3c => plat-samsung}/dev-hsmmc2.c | 0 .../arm/{plat-s3c => plat-samsung}/dev-i2c0.c | 0 .../arm/{plat-s3c => plat-samsung}/dev-i2c1.c | 0 .../arm/{plat-s3c => plat-samsung}/dev-nand.c | 0 .../dev-usb-hsotg.c | 0 arch/arm/{plat-s3c => plat-samsung}/dev-usb.c | 0 13 files changed, 54 insertions(+), 54 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/dev-fb.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-hsmmc.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-hsmmc1.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-hsmmc2.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-i2c0.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-i2c1.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-nand.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-usb-hsotg.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/dev-usb.c (100%) diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 9e9d0286e48f8..cd979b1f61206 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -170,46 +170,4 @@ config S3C_DMA help Internal configuration for S3C DMA core -# device definitions to compile in - -config S3C_DEV_HSMMC - bool - help - Compile in platform device definitions for HSMMC code - -config S3C_DEV_HSMMC1 - bool - help - Compile in platform device definitions for HSMMC channel 1 - -config S3C_DEV_HSMMC2 - bool - help - Compile in platform device definitions for HSMMC channel 2 - -config S3C_DEV_I2C1 - bool - help - Compile in platform device definitions for I2C channel 1 - -config S3C_DEV_FB - bool - help - Compile in platform device definition for framebuffer - -config S3C_DEV_USB_HOST - bool - help - Compile in platform device definition for USB host. - -config S3C_DEV_USB_HSOTG - bool - help - Compile in platform device definition for USB high-speed OtG - -config S3C_DEV_NAND - bool - help - Compile in platform device definition for NAND controller - endif diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index ef10a9131bba5..d86299556552f 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -29,15 +29,3 @@ obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o # PWM support obj-$(CONFIG_HAVE_PWM) += pwm.o - -# devices - -obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o -obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o -obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o -obj-y += dev-i2c0.o -obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o -obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o -obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o -obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o -obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index e3ae68472ea74..5a72a5235573d 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -19,4 +19,46 @@ config SAMSUNG_CLKSRC Select the clock code for the clksrc implementation used by newer systems such as the S3C64XX. +# device definitions to compile in + +config S3C_DEV_HSMMC + bool + help + Compile in platform device definitions for HSMMC code + +config S3C_DEV_HSMMC1 + bool + help + Compile in platform device definitions for HSMMC channel 1 + +config S3C_DEV_HSMMC2 + bool + help + Compile in platform device definitions for HSMMC channel 2 + +config S3C_DEV_I2C1 + bool + help + Compile in platform device definitions for I2C channel 1 + +config S3C_DEV_FB + bool + help + Compile in platform device definition for framebuffer + +config S3C_DEV_USB_HOST + bool + help + Compile in platform device definition for USB host. + +config S3C_DEV_USB_HSOTG + bool + help + Compile in platform device definition for USB high-speed OtG + +config S3C_DEV_NAND + bool + help + Compile in platform device definition for NAND controller + endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index d4d5f942d34c4..32f03e549d0a6 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -15,3 +15,15 @@ obj-y += clock.o obj-y += pwm-clock.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o + +# devices + +obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o +obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o +obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o +obj-y += dev-i2c0.o +obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o +obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o +obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o +obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c similarity index 100% rename from arch/arm/plat-s3c/dev-fb.c rename to arch/arm/plat-samsung/dev-fb.c diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c similarity index 100% rename from arch/arm/plat-s3c/dev-hsmmc.c rename to arch/arm/plat-samsung/dev-hsmmc.c diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c similarity index 100% rename from arch/arm/plat-s3c/dev-hsmmc1.c rename to arch/arm/plat-samsung/dev-hsmmc1.c diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c similarity index 100% rename from arch/arm/plat-s3c/dev-hsmmc2.c rename to arch/arm/plat-samsung/dev-hsmmc2.c diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c similarity index 100% rename from arch/arm/plat-s3c/dev-i2c0.c rename to arch/arm/plat-samsung/dev-i2c0.c diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c similarity index 100% rename from arch/arm/plat-s3c/dev-i2c1.c rename to arch/arm/plat-samsung/dev-i2c1.c diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c similarity index 100% rename from arch/arm/plat-s3c/dev-nand.c rename to arch/arm/plat-samsung/dev-nand.c diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c similarity index 100% rename from arch/arm/plat-s3c/dev-usb-hsotg.c rename to arch/arm/plat-samsung/dev-usb-hsotg.c diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c similarity index 100% rename from arch/arm/plat-s3c/dev-usb.c rename to arch/arm/plat-samsung/dev-usb.c -- GitLab From 4f830db9629e413e7c5523085ab009b0de5ae6d0 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 02:28:20 +0900 Subject: [PATCH 050/370] ARM: SAMSUNG: Move gpio-config.c into plat-samsung The arch/arm/plat-s3c/gpio-config.c file is common to pretty much all the Samsung SoCs, so move it to arch/arm/plat-samsung Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Kconfig | 33 ----------------- arch/arm/plat-s3c/Makefile | 1 - arch/arm/plat-samsung/Kconfig | 35 +++++++++++++++++++ arch/arm/plat-samsung/Makefile | 1 + .../{plat-s3c => plat-samsung}/gpio-config.c | 0 5 files changed, 36 insertions(+), 34 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/gpio-config.c (100%) diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index cd979b1f61206..454cc39b7adc1 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -130,39 +130,6 @@ config S3C_GPIO_TRACK Internal configuration option to enable the s3c specific gpio chip tracking if the platform requires it. -config S3C_GPIO_PULL_UPDOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_DOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_UP - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_CFG_S3C24XX - bool - help - Internal configuration to enable S3C24XX style GPIO configuration - functions. - -config S3C_GPIO_CFG_S3C64XX - bool - help - Internal configuration to enable S3C64XX style GPIO configuration - functions. - -config S5P_GPIO_CFG_S5PC1XX - bool - help - Internal configuration to enable S5PC1XX style GPIO configuration - functions. - # DMA config S3C_DMA diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index d86299556552f..ea4a001f67935 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -14,7 +14,6 @@ obj- := obj-y += init.o obj-y += time.o obj-y += gpio.o -obj-y += gpio-config.o # DMA support diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 5a72a5235573d..9e7daf29b86a4 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -19,6 +19,41 @@ config SAMSUNG_CLKSRC Select the clock code for the clksrc implementation used by newer systems such as the S3C64XX. +# options for gpio configuration support + +config S3C_GPIO_CFG_S3C24XX + bool + help + Internal configuration to enable S3C24XX style GPIO configuration + functions. + +config S3C_GPIO_CFG_S3C64XX + bool + help + Internal configuration to enable S3C64XX style GPIO configuration + functions. + +config S5P_GPIO_CFG_S5PC1XX + bool + help + Internal configuration to enable S5PC1XX style GPIO configuration + functions. + +config S3C_GPIO_PULL_UPDOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_DOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_UP + bool + help + Internal configuration to enable the correct GPIO pull helper + # device definitions to compile in config S3C_DEV_HSMMC diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 32f03e549d0a6..2c0143713ea99 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -13,6 +13,7 @@ obj- := obj-y += clock.o obj-y += pwm-clock.o +obj-y += gpio-config.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c similarity index 100% rename from arch/arm/plat-s3c/gpio-config.c rename to arch/arm/plat-samsung/gpio-config.c -- GitLab From 7162ba03729e0a47aaab44448ce2453f07a9664d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 10:14:51 +0900 Subject: [PATCH 051/370] ARM: SAMSUNG: Move IRQ VIC timer handling out to common header files Move the VIC based timer interrupt handling out of plat-s3c64xx and into plat-samsung to be re-used for other systems. This also reduces the code size as we now have a common init routine and use the irq_desc to store the interrupt number of the timer. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/Kconfig | 1 + arch/arm/plat-s3c64xx/irq.c | 90 ++----------------- arch/arm/plat-samsung/Kconfig | 7 ++ arch/arm/plat-samsung/Makefile | 2 + .../plat-samsung/include/plat/irq-vic-timer.h | 13 +++ arch/arm/plat-samsung/irq-vic-timer.c | 86 ++++++++++++++++++ 6 files changed, 116 insertions(+), 83 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/irq-vic-timer.h create mode 100644 arch/arm/plat-samsung/irq-vic-timer.c diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index bec12242706b4..02d716fb157a0 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -14,6 +14,7 @@ config PLAT_S3C64XX select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index 8dc5b6da97895..8b69bca05876f 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -21,78 +21,10 @@ #include #include +#include #include -#include #include -/* Timer interrupt handling */ - -static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) -{ - generic_handle_irq(sub_irq); -} - -static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER0); -} - -static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER1); -} - -static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER2); -} - -static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER3); -} - -static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER4); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~(1 << (irq - IRQ_TIMER0)); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= 1 << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_ack(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; - reg |= (1 << 5) << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .mask = s3c_irq_timer_mask, - .unmask = s3c_irq_timer_unmask, - .ack = s3c_irq_timer_ack, -}; - struct uart_irq { void __iomem *regs; unsigned int base_irq; @@ -227,7 +159,7 @@ static void __init s3c64xx_uart_irq(struct uart_irq *uirq) void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { - int uart, irq; + int uart; printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -237,20 +169,12 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) /* add the timer sub-irqs */ - set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); - set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); - set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); - set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); - set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); - - for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { - set_irq_chip(irq, &s3c_irq_timer); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) s3c64xx_uart_irq(&uart_irqs[uart]); } - - diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 9e7daf29b86a4..cedecd87d8999 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -19,6 +19,13 @@ config SAMSUNG_CLKSRC Select the clock code for the clksrc implementation used by newer systems such as the S3C64XX. +# options for IRQ support + +config SAMSUNG_IRQ_VIC_TIMER + bool + help + Internal configuration to build the VIC timer interrupt code. + # options for gpio configuration support config S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 2c0143713ea99..aa048c7337dd9 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -17,6 +17,8 @@ obj-y += gpio-config.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o +obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o + # devices obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h new file mode 100644 index 0000000000000..a90b53431b5b4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -0,0 +1,13 @@ +/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h + * + * Copyright (c) 2010 Simtec Electronics + * Ben Dooks + * + * Header file for Samsung SoC IRQ VIC timer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c new file mode 100644 index 0000000000000..0270519fcabca --- /dev/null +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -0,0 +1,86 @@ +/* arch/arm/plat-samsung/irq-vic-timer.c + * originally part of arch/arm/plat-s3c64xx/irq.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include + +static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) +{ + generic_handle_irq((int)desc->handler_data); +} + +/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ + +static void s3c_irq_timer_mask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg &= ~(1 << (irq - IRQ_TIMER0)); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_unmask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg |= 1 << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_ack(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; + reg |= (1 << 5) << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static struct irq_chip s3c_irq_timer = { + .name = "s3c-timer", + .mask = s3c_irq_timer_mask, + .unmask = s3c_irq_timer_unmask, + .ack = s3c_irq_timer_ack, +}; + +/** + * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ + * @parent_irq: The parent IRQ on the VIC for the timer. + * @timer_irq: The IRQ to be used for the timer. + * + * Register the necessary IRQ chaining and support for the timer IRQs + * chained of the VIC. + */ +void __init s3c_init_vic_timer_irq(unsigned int parent_irq, + unsigned int timer_irq) +{ + struct irq_desc *desc = irq_to_desc(parent_irq); + + set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + + set_irq_chip(timer_irq, &s3c_irq_timer); + set_irq_handler(timer_irq, handle_level_irq); + set_irq_flags(timer_irq, IRQF_VALID); + + desc->handler_data = (void *)timer_irq; +} -- GitLab From 51022cf6591ae2945960d034788bdeffa28cde13 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 6 Jan 2010 11:18:44 +0900 Subject: [PATCH 052/370] ARM: SAMSUNG: Move IRQ UART handling for newer devices to plat-samsung Move the handling for the UART interrupts out of the s3c64xx specific code and into plat-samsung so that it can be used by all implementations that need it. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/Kconfig | 1 + arch/arm/plat-s3c64xx/irq.c | 117 +------------- arch/arm/plat-samsung/Kconfig | 5 + arch/arm/plat-samsung/Makefile | 1 + arch/arm/plat-samsung/include/plat/irq-uart.h | 20 +++ arch/arm/plat-samsung/irq-uart.c | 143 ++++++++++++++++++ 6 files changed, 173 insertions(+), 114 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/irq-uart.h create mode 100644 arch/arm/plat-samsung/irq-uart.c diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 02d716fb157a0..0fba1f956b8a2 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -15,6 +15,7 @@ config PLAT_S3C64XX select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_IRQ_UART select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index 8b69bca05876f..b98451e8ee242 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -22,19 +22,10 @@ #include #include -#include +#include #include -struct uart_irq { - void __iomem *regs; - unsigned int base_irq; - unsigned int parent_irq; -}; - -/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] - * are consecutive when looking up the interrupt in the demux routines. - */ -static struct uart_irq uart_irqs[] = { +static struct s3c_uart_irq uart_irqs[] = { [0] = { .regs = S3C_VA_UART0, .base_irq = IRQ_S3CUART_BASE0, @@ -57,110 +48,9 @@ static struct uart_irq uart_irqs[] = { }, }; -static inline void __iomem *s3c_irq_uart_base(unsigned int irq) -{ - struct uart_irq *uirq = get_irq_chip_data(irq); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -/* UART interrupt registers, not worth adding to seperate include header */ - -static void s3c_irq_uart_mask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) -{ - struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; - u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); - int base = uirq->base_irq; - - if (pend & (1 << 0)) - generic_handle_irq(base); - if (pend & (1 << 1)) - generic_handle_irq(base + 1); - if (pend & (1 << 2)) - generic_handle_irq(base + 2); - if (pend & (1 << 3)) - generic_handle_irq(base + 3); -} - -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .mask = s3c_irq_uart_mask, - .unmask = s3c_irq_uart_unmask, - .mask_ack = s3c_irq_uart_maskack, - .ack = s3c_irq_uart_ack, -}; - -static void __init s3c64xx_uart_irq(struct uart_irq *uirq) -{ - void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; - - /* mask all interrupts at the start. */ - __raw_writel(0xf, reg_base + S3C64XX_UINTM); - - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -} void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { - int uart; - printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ @@ -175,6 +65,5 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); - for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) - s3c64xx_uart_irq(&uart_irqs[uart]); + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index cedecd87d8999..900b463fc197d 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -26,6 +26,11 @@ config SAMSUNG_IRQ_VIC_TIMER help Internal configuration to build the VIC timer interrupt code. +config SAMSUNG_IRQ_UART + bool + help + Internal configuration to build the IRQ UART demux code. + # options for gpio configuration support config S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index aa048c7337dd9..aeb7e12d1f637 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -17,6 +17,7 @@ obj-y += gpio-config.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o +obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o # devices diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h new file mode 100644 index 0000000000000..a9331e49bea36 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-uart.h @@ -0,0 +1,20 @@ +/* arch/arm/plat-samsung/include/plat/irq-uart.h + * + * Copyright (c) 2010 Simtec Electronics + * Ben Dooks + * + * Header file for Samsung SoC UART IRQ demux for S3C64XX and later + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct s3c_uart_irq { + void __iomem *regs; + unsigned int base_irq; + unsigned int parent_irq; +}; + +extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs); + diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c new file mode 100644 index 0000000000000..4f8c102674ae2 --- /dev/null +++ b/arch/arm/plat-samsung/irq-uart.c @@ -0,0 +1,143 @@ +/* arch/arm/plat-samsung/irq-uart.c + * originally part of arch/arm/plat-s3c64xx/irq.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * Samsung- UART Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] + * are consecutive when looking up the interrupt in the demux routines. + */ + +static inline void __iomem *s3c_irq_uart_base(unsigned int irq) +{ + struct s3c_uart_irq *uirq = get_irq_chip_data(irq); + return uirq->regs; +} + +static inline unsigned int s3c_irq_uart_bit(unsigned int irq) +{ + return irq & 3; +} + +static void s3c_irq_uart_mask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_maskack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_uart_unmask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg &= ~(1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_ack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) +{ + struct s3c_uart_irq *uirq = desc->handler_data; + u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); + int base = uirq->base_irq; + + if (pend & (1 << 0)) + generic_handle_irq(base); + if (pend & (1 << 1)) + generic_handle_irq(base + 1); + if (pend & (1 << 2)) + generic_handle_irq(base + 2); + if (pend & (1 << 3)) + generic_handle_irq(base + 3); +} + +static struct irq_chip s3c_irq_uart = { + .name = "s3c-uart", + .mask = s3c_irq_uart_mask, + .unmask = s3c_irq_uart_unmask, + .mask_ack = s3c_irq_uart_maskack, + .ack = s3c_irq_uart_ack, +}; + +static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) +{ + struct irq_desc *desc = irq_to_desc(uirq->parent_irq); + void __iomem *reg_base = uirq->regs; + unsigned int irq; + int offs; + + /* mask all interrupts at the start. */ + __raw_writel(0xf, reg_base + S3C64XX_UINTM); + + for (offs = 0; offs < 3; offs++) { + irq = uirq->base_irq + offs; + + set_irq_chip(irq, &s3c_irq_uart); + set_irq_chip_data(irq, uirq); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + desc->handler_data = uirq; + set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); +} + +/** + * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing + * @irq: The interrupt data for registering + * @nr_irqs: The number of interrupt descriptions in @irq. + * + * Register the UART interrupts specified by @irq including the demuxing + * routines. This supports the S3C6400 and newer style of devices. + */ +void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs) +{ + for (; nr_irqs > 0; nr_irqs--, irq++) + s3c_init_uart_irq(irq); +} -- GitLab From 5b39be4637bb795b2133dbee0eadbcc08bdd4134 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 7 Jan 2010 08:59:26 +0900 Subject: [PATCH 053/370] ARM: Add common entry code for system with two VICs Add a common entry-macro-vic2.S for systems where there are two VICs so that the machine or platform directories just need to setup the correct information before including into their own entry-macro.S file. Since this code is from the S3C64XX project, we update the S3C64XX machine entry code to use this new header. Signed-off-by: Ben Dooks --- arch/arm/include/asm/entry-macro-vic2.S | 57 +++++++++++++++++++ .../mach-s3c6400/include/mach/entry-macro.S | 28 +-------- arch/arm/mach-s3c6400/include/mach/map.h | 4 +- arch/arm/mach-s3c6400/include/mach/tick.h | 2 +- arch/arm/plat-s3c64xx/cpu.c | 4 +- arch/arm/plat-s3c64xx/include/plat/irqs.h | 8 +-- arch/arm/plat-s3c64xx/irq.c | 4 +- 7 files changed, 69 insertions(+), 38 deletions(-) create mode 100644 arch/arm/include/asm/entry-macro-vic2.S diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S new file mode 100644 index 0000000000000..3ceb85e438502 --- /dev/null +++ b/arch/arm/include/asm/entry-macro-vic2.S @@ -0,0 +1,57 @@ +/* arch/arm/include/asm/entry-macro-vic2.S + * + * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * Low-level IRQ helper macros for a device with two VICs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/* This should be included from with the necessary + * defines for virtual addresses and IRQ bases for the two vics. + * + * The code needs the following defined: + * IRQ_VIC0_BASE IRQ number of VIC0's first IRQ + * IRQ_VIC1_BASE IRQ number of VIC1's first IRQ + * VA_VIC0 Virtual address of VIC0 + * VA_VIC1 Virtual address of VIC1 + * + * Note, code assumes VIC0's virtual address is an ARM immediate constant + * away from VIC1. +*/ + +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, #IRQ_VIC0_BASE + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) + addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE) + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c6400/include/mach/entry-macro.S index fbd90d2cf355f..33a8fe2408825 100644 --- a/arch/arm/mach-s3c6400/include/mach/entry-macro.S +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S @@ -12,33 +12,7 @@ * warranty of any kind, whether express or implied. */ -#include #include #include - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - ldr \base, =S3C_VA_VIC0 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - @ check the vic0 - mov \irqnr, # S3C_IRQ_OFFSET + 31 - ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] - teq \irqstat, #0 - - @ otherwise try vic1 - addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) - addeq \irqnr, \irqnr, #32 - ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] - teqeq \irqstat, #0 - - clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm +#include diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 106ee13581e28..d4cd3abe3cba7 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -70,8 +70,8 @@ #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) /* place VICs close together */ -#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) -#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define VA_VIC0 (S3C_VA_IRQ + 0x00) +#define VA_VIC1 (S3C_VA_IRQ + 0x10000) /* compatibiltiy defines. */ #define S3C_PA_TIMER S3C64XX_PA_TIMER diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c6400/include/mach/tick.h index d9c0dc7014ecd..ebe18a9469b88 100644 --- a/arch/arm/mach-s3c6400/include/mach/tick.h +++ b/arch/arm/mach-s3c6400/include/mach/tick.h @@ -20,7 +20,7 @@ */ static inline u32 s3c24xx_ostimer_pending(void) { - u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); } diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 49796d2db86d5..c0e6f2a45154a 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -78,12 +78,12 @@ static struct map_desc s3c_iodesc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S3C_VA_VIC0, + .virtual = (unsigned long)VA_VIC0, .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), .length = SZ_16K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S3C_VA_VIC1, + .virtual = (unsigned long)VA_VIC1, .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), .length = SZ_16K, .type = MT_DEVICE, diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index 7956fd3bb194d..176fe15a61d60 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -24,8 +24,8 @@ #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) -#define S3C_VIC0_BASE S3C_IRQ(0) -#define S3C_VIC1_BASE S3C_IRQ(32) +#define IRQ_VIC0_BASE S3C_IRQ(0) +#define IRQ_VIC1_BASE S3C_IRQ(32) /* UART interrupts, each UART has 4 intterupts per channel so * use the space between the ISA and S3C main interrupts. Note, these @@ -59,8 +59,8 @@ /* VIC based IRQs */ -#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) +#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) /* VIC0 */ diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index b98451e8ee242..67a145d440f39 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -54,8 +54,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0); - vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0); + vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); + vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); /* add the timer sub-irqs */ -- GitLab From 85841bcedd6048dd37cab58a504e5317192324c6 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 11 Jan 2010 12:21:51 +0900 Subject: [PATCH 054/370] ARM: SAMSUNG: Add config option for number of additional GPIO pins. This patch adds a configuration option for specifing the number of additional GPIO pins to be used in addition to the GPIO pins supported onchip. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 900b463fc197d..faec4b8c626c8 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -66,6 +66,14 @@ config S3C_GPIO_PULL_UP help Internal configuration to enable the correct GPIO pull helper +config SAMSUNG_GPIO_EXTRA + int "Number of additional GPIO pins" + default 0 + help + Use additional GPIO space in addition to the GPIO's the SOC + provides. This allows expanding the GPIO space for use with + GPIO expanders. + # device definitions to compile in config S3C_DEV_HSMMC -- GitLab From 45426468148d77e8c5eaece21d2a16e063066567 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 12:19:28 +0900 Subject: [PATCH 055/370] ARM: S5PC1XX: Move to using generic clksrc_clk for clock code Remove the copy of the old s3c64xx struct clksrc_clk and use the new one in plat-samsung. This eliminates a bug in the set_parent() call where it failed to set the clk->parent after sucesfully updating the clock. The script that was used to automate much of the process will be supplied seperately. Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/Kconfig | 1 + arch/arm/plat-s5pc1xx/s5pc100-clock.c | 388 +++++++------------------- 2 files changed, 97 insertions(+), 292 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index b7b9e91c02434..5d97b1c3cef73 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -11,6 +11,7 @@ config PLAT_S5PC1XX select ARM_VIC select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select SAMSUNG_CLKSRC select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index 16f0b90773907..52c032c9d7bcd 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -51,23 +52,6 @@ static struct clk clk_ext_xtal_mux = { #define clk_fout_mpll clk_mpll #define clk_vclk_54m clk_54m -struct clk_sources { - unsigned int nr_sources; - struct clk **sources; -}; - -struct clksrc_clk { - struct clk clk; - unsigned int mask; - unsigned int shift; - - struct clk_sources *sources; - - unsigned int divider_shift; - void __iomem *reg_divider; - void __iomem *reg_source; -}; - /* APLL */ static struct clk clk_fout_apll = { .name = "fout_apll", @@ -80,7 +64,7 @@ static struct clk *clk_src_apll_list[] = { [1] = &clk_fout_apll, }; -static struct clk_sources clk_src_apll = { +static struct clksrc_sources clk_src_apll = { .sources = clk_src_apll_list, .nr_sources = ARRAY_SIZE(clk_src_apll_list), }; @@ -90,10 +74,8 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .shift = S5PC100_CLKSRC0_APLL_SHIFT, - .mask = S5PC100_CLKSRC0_APLL_MASK, .sources = &clk_src_apll, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, }, }; static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) @@ -240,7 +222,7 @@ static struct clk *clk_src_mpll_list[] = { [1] = &clk_fout_mpll, }; -static struct clk_sources clk_src_mpll = { +static struct clksrc_sources clk_src_mpll = { .sources = clk_src_mpll_list, .nr_sources = ARRAY_SIZE(clk_src_mpll_list), }; @@ -250,10 +232,8 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .shift = S5PC100_CLKSRC0_MPLL_SHIFT, - .mask = S5PC100_CLKSRC0_MPLL_MASK, .sources = &clk_src_mpll, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, }, }; static struct clk *clkset_am_list[] = { @@ -261,7 +241,7 @@ static struct clk *clkset_am_list[] = { [1] = &clk_dout_apll2, }; -static struct clk_sources clk_src_am = { +static struct clksrc_sources clk_src_am = { .sources = clkset_am_list, .nr_sources = ARRAY_SIZE(clkset_am_list), }; @@ -271,10 +251,8 @@ static struct clksrc_clk clk_mout_am = { .name = "mout_am", .id = -1, }, - .shift = S5PC100_CLKSRC0_AMMUX_SHIFT, - .mask = S5PC100_CLKSRC0_AMMUX_MASK, .sources = &clk_src_am, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, }, }; static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) @@ -304,7 +282,7 @@ static struct clk *clkset_onenand_list[] = { [1] = &clk_dout_d1_bus, }; -static struct clk_sources clk_src_onenand = { +static struct clksrc_sources clk_src_onenand = { .sources = clkset_onenand_list, .nr_sources = ARRAY_SIZE(clkset_onenand_list), }; @@ -314,10 +292,8 @@ static struct clksrc_clk clk_mout_onenand = { .name = "mout_onenand", .id = -1, }, - .shift = S5PC100_CLKSRC0_ONENAND_SHIFT, - .mask = S5PC100_CLKSRC0_ONENAND_MASK, .sources = &clk_src_onenand, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, }, }; static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) @@ -419,7 +395,7 @@ static struct clk *clk_src_epll_list[] = { [1] = &clk_fout_epll, }; -static struct clk_sources clk_src_epll = { +static struct clksrc_sources clk_src_epll = { .sources = clk_src_epll_list, .nr_sources = ARRAY_SIZE(clk_src_epll_list), }; @@ -429,10 +405,8 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .shift = S5PC100_CLKSRC0_EPLL_SHIFT, - .mask = S5PC100_CLKSRC0_EPLL_MASK, - .sources = &clk_src_epll, - .reg_source = S5PC100_CLKSRC0, + .sources = &clk_src_epll, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, }, }; /* HPLL */ @@ -446,7 +420,7 @@ static struct clk *clk_src_hpll_list[] = { [1] = &clk_fout_hpll, }; -static struct clk_sources clk_src_hpll = { +static struct clksrc_sources clk_src_hpll = { .sources = clk_src_hpll_list, .nr_sources = ARRAY_SIZE(clk_src_hpll_list), }; @@ -456,10 +430,8 @@ static struct clksrc_clk clk_mout_hpll = { .name = "mout_hpll", .id = -1, }, - .shift = S5PC100_CLKSRC0_HPLL_SHIFT, - .mask = S5PC100_CLKSRC0_HPLL_MASK, - .sources = &clk_src_hpll, - .reg_source = S5PC100_CLKSRC0, + .sources = &clk_src_hpll, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, }, }; /* Peripherals */ @@ -474,99 +446,6 @@ static struct clksrc_clk clk_mout_hpll = { * have a common parent divisor so are not included here. */ -static inline struct clksrc_clk *to_clksrc(struct clk *clk) -{ - return container_of(clk, struct clksrc_clk, clk); -} - -static unsigned long s5pc100_getrate_clksrc(struct clk *clk) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv = __raw_readl(sclk->reg_divider); - - clkdiv >>= sclk->divider_shift; - clkdiv &= 0xf; - clkdiv++; - - rate /= clkdiv; - return rate; -} - -static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - void __iomem *reg = sclk->reg_divider; - unsigned int div; - u32 val; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - if (div > 16) - return -EINVAL; - - val = __raw_readl(reg); - val &= ~(0xf << sclk->divider_shift); - val |= (div - 1) << sclk->divider_shift; - __raw_writel(val, reg); - - return 0; -} - -static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - struct clk_sources *srcs = sclk->sources; - u32 clksrc = __raw_readl(sclk->reg_source); - int src_nr = -1; - int ptr; - - for (ptr = 0; ptr < srcs->nr_sources; ptr++) - if (srcs->sources[ptr] == parent) { - src_nr = ptr; - break; - } - - if (src_nr >= 0) { - clksrc &= ~sclk->mask; - clksrc |= src_nr << sclk->shift; - - __raw_writel(clksrc, sclk->reg_source); - return 0; - } - - return -EINVAL; -} - -static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - rate = parent_rate; - else { - div = rate / parent_rate; - - if (div == 0) - div = 1; - if (div > 16) - div = 16; - - rate = parent_rate / div; - } - - return rate; -} - -static struct clk_ops s5pc100_clksrc_ops = { - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, -}; - static struct clk *clkset_spi_list[] = { &clk_mout_epll.clk, &clk_dout_mpll2, @@ -574,7 +453,7 @@ static struct clk *clkset_spi_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_spi = { +static struct clksrc_sources clkset_spi = { .sources = clkset_spi_list, .nr_sources = ARRAY_SIZE(clkset_spi_list), }; @@ -587,12 +466,9 @@ static struct clksrc_clk clk_spi0 = { .enable = s5pc100_sclk0_ctrl, }, - .shift = S5PC100_CLKSRC1_SPI0_SHIFT, - .mask = S5PC100_CLKSRC1_SPI0_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, }; static struct clksrc_clk clk_spi1 = { @@ -601,14 +477,10 @@ static struct clksrc_clk clk_spi1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC1_SPI1_SHIFT, - .mask = S5PC100_CLKSRC1_SPI1_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, }; static struct clksrc_clk clk_spi2 = { @@ -617,14 +489,10 @@ static struct clksrc_clk clk_spi2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC1_SPI2_SHIFT, - .mask = S5PC100_CLKSRC1_SPI2_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, }; static struct clk *clkset_uart_list[] = { @@ -632,7 +500,7 @@ static struct clk *clkset_uart_list[] = { &clk_dout_mpll, }; -static struct clk_sources clkset_uart = { +static struct clksrc_sources clkset_uart = { .sources = clkset_uart_list, .nr_sources = ARRAY_SIZE(clkset_uart_list), }; @@ -643,14 +511,10 @@ static struct clksrc_clk clk_uart_uclk1 = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC1_UART_SHIFT, - .mask = S5PC100_CLKSRC1_UART_MASK, - .sources = &clkset_uart, - .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, + .sources = &clkset_uart, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, }; static struct clk clk_iis_cd0 = { @@ -687,7 +551,7 @@ static struct clk *clkset_audio0_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio0 = { +static struct clksrc_sources clkset_audio0 = { .sources = clkset_audio0_list, .nr_sources = ARRAY_SIZE(clkset_audio0_list), }; @@ -698,14 +562,10 @@ static struct clksrc_clk clk_audio0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO0_MASK, - .sources = &clkset_audio0, - .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, + .sources = &clkset_audio0, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, }; static struct clk *clkset_audio1_list[] = { @@ -717,7 +577,7 @@ static struct clk *clkset_audio1_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio1 = { +static struct clksrc_sources clkset_audio1 = { .sources = clkset_audio1_list, .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; @@ -728,14 +588,10 @@ static struct clksrc_clk clk_audio1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO1_MASK, - .sources = &clkset_audio1, - .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, + .sources = &clkset_audio1, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, }; static struct clk *clkset_audio2_list[] = { @@ -746,7 +602,7 @@ static struct clk *clkset_audio2_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio2 = { +static struct clksrc_sources clkset_audio2 = { .sources = clkset_audio2_list, .nr_sources = ARRAY_SIZE(clkset_audio2_list), }; @@ -757,14 +613,10 @@ static struct clksrc_clk clk_audio2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO2_MASK, - .sources = &clkset_audio2, - .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, + .sources = &clkset_audio2, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, }; static struct clk *clkset_spdif_list[] = { @@ -773,7 +625,7 @@ static struct clk *clkset_spdif_list[] = { &clk_audio2.clk, }; -static struct clk_sources clkset_spdif = { +static struct clksrc_sources clkset_spdif = { .sources = clkset_spdif_list, .nr_sources = ARRAY_SIZE(clkset_spdif_list), }; @@ -783,10 +635,8 @@ static struct clksrc_clk clk_spdif = { .name = "spdif", .id = -1, }, - .shift = S5PC100_CLKSRC3_SPDIF_SHIFT, - .mask = S5PC100_CLKSRC3_SPDIF_MASK, .sources = &clkset_spdif, - .reg_source = S5PC100_CLKSRC3, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, }; static struct clk *clkset_lcd_fimc_list[] = { @@ -796,7 +646,7 @@ static struct clk *clkset_lcd_fimc_list[] = { &clk_vclk_54m, }; -static struct clk_sources clkset_lcd_fimc = { +static struct clksrc_sources clkset_lcd_fimc = { .sources = clkset_lcd_fimc_list, .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), }; @@ -807,14 +657,10 @@ static struct clksrc_clk clk_lcd = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_LCD_SHIFT, - .mask = S5PC100_CLKSRC2_LCD_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, }; static struct clksrc_clk clk_fimc0 = { @@ -823,14 +669,10 @@ static struct clksrc_clk clk_fimc0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC0_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, }; static struct clksrc_clk clk_fimc1 = { @@ -839,14 +681,10 @@ static struct clksrc_clk clk_fimc1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC1_MASK, .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, }; static struct clksrc_clk clk_fimc2 = { @@ -855,14 +693,10 @@ static struct clksrc_clk clk_fimc2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, .enable = s5pc100_sclk1_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC2_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, }; static struct clk *clkset_mmc_list[] = { @@ -872,7 +706,7 @@ static struct clk *clkset_mmc_list[] = { &clk_mout_hpll.clk , }; -static struct clk_sources clkset_mmc = { +static struct clksrc_sources clkset_mmc = { .sources = clkset_mmc_list, .nr_sources = ARRAY_SIZE(clkset_mmc_list), }; @@ -883,14 +717,10 @@ static struct clksrc_clk clk_mmc0 = { .id = 0, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_MMC0_SHIFT, - .mask = S5PC100_CLKSRC2_MMC0_MASK, - .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, }; static struct clksrc_clk clk_mmc1 = { @@ -899,14 +729,10 @@ static struct clksrc_clk clk_mmc1 = { .id = 1, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_MMC1_SHIFT, - .mask = S5PC100_CLKSRC2_MMC1_MASK, - .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, }; static struct clksrc_clk clk_mmc2 = { @@ -915,14 +741,10 @@ static struct clksrc_clk clk_mmc2 = { .id = 2, .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC2_MMC2_SHIFT, - .mask = S5PC100_CLKSRC2_MMC2_MASK, .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, }; @@ -933,7 +755,7 @@ static struct clk *clkset_usbhost_list[] = { &clk_48m, }; -static struct clk_sources clkset_usbhost = { +static struct clksrc_sources clkset_usbhost = { .sources = clkset_usbhost_list, .nr_sources = ARRAY_SIZE(clkset_usbhost_list), }; @@ -944,14 +766,10 @@ static struct clksrc_clk clk_usbhost = { .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, .enable = s5pc100_sclk0_ctrl, - .ops = &s5pc100_clksrc_ops, }, - .shift = S5PC100_CLKSRC1_UHOST_SHIFT, - .mask = S5PC100_CLKSRC1_UHOST_MASK, - .sources = &clkset_usbhost, - .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, + .sources = &clkset_usbhost, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, }; /* Clock initialisation code */ @@ -981,27 +799,6 @@ static struct clksrc_clk *init_parents[] = { &clk_usbhost, }; -static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk) -{ - struct clk_sources *srcs = clk->sources; - u32 clksrc = __raw_readl(clk->reg_source); - - clksrc &= clk->mask; - clksrc >>= clk->shift; - - if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { - printk(KERN_ERR "%s: bad source %d\n", - clk->clk.name, clksrc); - return; - } - - clk->clk.parent = srcs->sources[clksrc]; - - printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n", - clk->clk.name, clk->clk.parent->name, clksrc, - print_mhz(clk_get_rate(&clk->clk))); -} - #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) void __init_or_cpufreq s5pc100_setup_clocks(void) @@ -1065,50 +862,54 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) clk_f.rate = armclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s5pc100_set_clksrc(init_parents[ptr]); + s3c_set_clksrc(init_parents[ptr], true); } static struct clk *clks[] __initdata = { &clk_ext_xtal_mux, - &clk_mout_apll.clk, &clk_dout_apll, &clk_dout_d0_bus, &clk_dout_pclkd0, &clk_dout_apll2, - &clk_mout_mpll.clk, &clk_mout_am.clk, &clk_dout_d1_bus, - &clk_mout_onenand.clk, &clk_dout_pclkd1, &clk_dout_mpll2, &clk_dout_cam, &clk_dout_mpll, - &clk_mout_epll.clk, &clk_fout_epll, &clk_iis_cd0, &clk_iis_cd1, &clk_iis_cd2, &clk_pcm_cd0, &clk_pcm_cd1, - &clk_spi0.clk, - &clk_spi1.clk, - &clk_spi2.clk, - &clk_uart_uclk1.clk, - &clk_audio0.clk, - &clk_audio1.clk, - &clk_audio2.clk, - &clk_spdif.clk, - &clk_lcd.clk, - &clk_fimc0.clk, - &clk_fimc1.clk, - &clk_fimc2.clk, - &clk_mmc0.clk, - &clk_mmc1.clk, - &clk_mmc2.clk, - &clk_usbhost.clk, &clk_arm, }; +/* simplest change - will aggregate clocks later */ +static struct clksrc_clk *clks_src[] = { + &clk_mout_apll, + &clk_mout_mpll, + &clk_mout_onenand, + &clk_mout_epll, + &clk_spi0, + &clk_spi1, + &clk_spi2, + &clk_uart_uclk1, + &clk_audio0, + &clk_audio1, + &clk_audio2, + &clk_spdif, + &clk_lcd, + &clk_fimc0, + &clk_fimc1, + &clk_fimc2, + &clk_mmc0, + &clk_mmc1, + &clk_mmc2, + &clk_usbhost, +}; + void __init s5pc100_register_clocks(void) { struct clk *clkp; @@ -1123,4 +924,7 @@ void __init s5pc100_register_clocks(void) clkp->name, ret); } } + + for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++) + s3c_register_clksrc(clks_src[ptr], 1); } -- GitLab From 1d026d9b1671bcb05e7b00f545f1d62476e9063c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 12:39:58 +0900 Subject: [PATCH 056/370] ARM: S5PC1XX: Move clock definitions around ready to turn into clksrc arrays Move the clock definitions around ready to turn the clocks into an array of clocks and register them in one go. Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/s5pc100-clock.c | 250 +++++++++++++------------- 1 file changed, 127 insertions(+), 123 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index 52c032c9d7bcd..a9e37302f82fe 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -446,6 +446,45 @@ static struct clksrc_clk clk_mout_hpll = { * have a common parent divisor so are not included here. */ +static struct clk clk_iis_cd0 = { + .name = "iis_cdclk0", + .id = -1, +}; + +static struct clk clk_iis_cd1 = { + .name = "iis_cdclk1", + .id = -1, +}; + +static struct clk clk_iis_cd2 = { + .name = "iis_cdclk2", + .id = -1, +}; + +static struct clk clk_pcm_cd0 = { + .name = "pcm_cdclk0", + .id = -1, +}; + +static struct clk clk_pcm_cd1 = { + .name = "pcm_cdclk1", + .id = -1, +}; + +static struct clk *clkset_audio0_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd0, + &clk_pcm_cd0, + &clk_mout_hpll.clk, +}; + +static struct clksrc_sources clkset_audio0 = { + .sources = clkset_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_audio0_list), +}; + static struct clk *clkset_spi_list[] = { &clk_mout_epll.clk, &clk_dout_mpll2, @@ -458,6 +497,94 @@ static struct clksrc_sources clkset_spi = { .nr_sources = ARRAY_SIZE(clkset_spi_list), }; +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_audio1_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd1, + &clk_pcm_cd1, + &clk_mout_hpll.clk, +}; + +static struct clksrc_sources clkset_audio1 = { + .sources = clkset_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_audio1_list), +}; + +static struct clk *clkset_audio2_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd2, + &clk_mout_hpll.clk, +}; + +static struct clksrc_sources clkset_audio2 = { + .sources = clkset_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_audio2_list), +}; + +static struct clksrc_clk clk_audio0; +static struct clksrc_clk clk_audio1; +static struct clksrc_clk clk_audio2; + +static struct clk *clkset_spdif_list[] = { + &clk_audio0.clk, + &clk_audio1.clk, + &clk_audio2.clk, +}; + +static struct clksrc_sources clkset_spdif = { + .sources = clkset_spdif_list, + .nr_sources = ARRAY_SIZE(clkset_spdif_list), +}; + +static struct clk *clkset_lcd_fimc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_mout_hpll.clk, + &clk_vclk_54m, +}; + +static struct clksrc_sources clkset_lcd_fimc = { + .sources = clkset_lcd_fimc_list, + .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), +}; + +static struct clk *clkset_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_mout_hpll.clk , +}; + +static struct clksrc_sources clkset_mmc = { + .sources = clkset_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_mmc_list), +}; + +static struct clk *clkset_usbhost_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_mout_hpll.clk, + &clk_48m, +}; + +static struct clksrc_sources clkset_usbhost = { + .sources = clkset_usbhost_list, + .nr_sources = ARRAY_SIZE(clkset_usbhost_list), +}; + static struct clksrc_clk clk_spi0 = { .clk = { .name = "spi_bus", @@ -495,16 +622,6 @@ static struct clksrc_clk clk_spi2 = { .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, }; -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, -}; - -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; - static struct clksrc_clk clk_uart_uclk1 = { .clk = { .name = "uclk1", @@ -517,45 +634,6 @@ static struct clksrc_clk clk_uart_uclk1 = { .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, }; -static struct clk clk_iis_cd0 = { - .name = "iis_cdclk0", - .id = -1, -}; - -static struct clk clk_iis_cd1 = { - .name = "iis_cdclk1", - .id = -1, -}; - -static struct clk clk_iis_cd2 = { - .name = "iis_cdclk2", - .id = -1, -}; - -static struct clk clk_pcm_cd0 = { - .name = "pcm_cdclk0", - .id = -1, -}; - -static struct clk clk_pcm_cd1 = { - .name = "pcm_cdclk1", - .id = -1, -}; - -static struct clk *clkset_audio0_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd0, - &clk_pcm_cd0, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio0 = { - .sources = clkset_audio0_list, - .nr_sources = ARRAY_SIZE(clkset_audio0_list), -}; - static struct clksrc_clk clk_audio0 = { .clk = { .name = "audio-bus", @@ -568,20 +646,6 @@ static struct clksrc_clk clk_audio0 = { .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, }; -static struct clk *clkset_audio1_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd1, - &clk_pcm_cd1, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio1 = { - .sources = clkset_audio1_list, - .nr_sources = ARRAY_SIZE(clkset_audio1_list), -}; - static struct clksrc_clk clk_audio1 = { .clk = { .name = "audio-bus", @@ -594,18 +658,6 @@ static struct clksrc_clk clk_audio1 = { .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, }; -static struct clk *clkset_audio2_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd2, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio2 = { - .sources = clkset_audio2_list, - .nr_sources = ARRAY_SIZE(clkset_audio2_list), -}; static struct clksrc_clk clk_audio2 = { .clk = { @@ -619,17 +671,6 @@ static struct clksrc_clk clk_audio2 = { .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, }; -static struct clk *clkset_spdif_list[] = { - &clk_audio0.clk, - &clk_audio1.clk, - &clk_audio2.clk, -}; - -static struct clksrc_sources clkset_spdif = { - .sources = clkset_spdif_list, - .nr_sources = ARRAY_SIZE(clkset_spdif_list), -}; - static struct clksrc_clk clk_spdif = { .clk = { .name = "spdif", @@ -639,18 +680,6 @@ static struct clksrc_clk clk_spdif = { .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, }; -static struct clk *clkset_lcd_fimc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_mout_hpll.clk, - &clk_vclk_54m, -}; - -static struct clksrc_sources clkset_lcd_fimc = { - .sources = clkset_lcd_fimc_list, - .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), -}; - static struct clksrc_clk clk_lcd = { .clk = { .name = "lcd", @@ -699,18 +728,6 @@ static struct clksrc_clk clk_fimc2 = { .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, }; -static struct clk *clkset_mmc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_mout_hpll.clk , -}; - -static struct clksrc_sources clkset_mmc = { - .sources = clkset_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_mmc_list), -}; - static struct clksrc_clk clk_mmc0 = { .clk = { .name = "mmc_bus", @@ -747,19 +764,6 @@ static struct clksrc_clk clk_mmc2 = { .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, }; - -static struct clk *clkset_usbhost_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_mout_hpll.clk, - &clk_48m, -}; - -static struct clksrc_sources clkset_usbhost = { - .sources = clkset_usbhost_list, - .nr_sources = ARRAY_SIZE(clkset_usbhost_list), -}; - static struct clksrc_clk clk_usbhost = { .clk = { .name = "usbhost", -- GitLab From c837e88cf9e18c311332cc1c8c488993a201d568 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 12:49:17 +0900 Subject: [PATCH 057/370] ARM: S5PC1XX: Change clksrc_clks to use array of clocks Remove the individual 'struct clksrc_clks' and place them into an array so that we can simply use s3c_register_clksrcs to register tham all in one go. Since the spdif clock relies on the audio clock, move the audio clocks into their own arrary. Thanks to Marek Szyprowski for testing and pointing out the four clocks what where missed from the clock list. Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/s5pc100-clock.c | 416 +++++++++++--------------- 1 file changed, 179 insertions(+), 237 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index a9e37302f82fe..2bf6c57a96a2b 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -534,14 +534,44 @@ static struct clksrc_sources clkset_audio2 = { .nr_sources = ARRAY_SIZE(clkset_audio2_list), }; -static struct clksrc_clk clk_audio0; -static struct clksrc_clk clk_audio1; -static struct clksrc_clk clk_audio2; +static struct clksrc_clk clksrc_audio[] = { + { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio0, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, + }, { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio1, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, + }, { + .clk = { + .name = "audio-bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio2, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, + }, +}; static struct clk *clkset_spdif_list[] = { - &clk_audio0.clk, - &clk_audio1.clk, - &clk_audio2.clk, + &clksrc_audio[0].clk, + &clksrc_audio[1].clk, + &clksrc_audio[2].clk, }; static struct clksrc_sources clkset_spdif = { @@ -585,195 +615,136 @@ static struct clksrc_sources clkset_usbhost = { .nr_sources = ARRAY_SIZE(clkset_usbhost_list), }; -static struct clksrc_clk clk_spi0 = { - .clk = { - .name = "spi_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, -}; - -static struct clksrc_clk clk_spi1 = { - .clk = { - .name = "spi_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, -}; - -static struct clksrc_clk clk_spi2 = { - .clk = { - .name = "spi_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, -}; - -static struct clksrc_clk clk_uart_uclk1 = { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_uart, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, -}; - -static struct clksrc_clk clk_audio0 = { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio0, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, -}; - -static struct clksrc_clk clk_audio1 = { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio1, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, -}; - - -static struct clksrc_clk clk_audio2 = { - .clk = { - .name = "audio-bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio2, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, -}; - -static struct clksrc_clk clk_spdif = { - .clk = { - .name = "spdif", - .id = -1, - }, - .sources = &clkset_spdif, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, -}; - -static struct clksrc_clk clk_lcd = { - .clk = { - .name = "lcd", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, -}; - -static struct clksrc_clk clk_fimc0 = { - .clk = { - .name = "fimc", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, -}; - -static struct clksrc_clk clk_fimc1 = { - .clk = { - .name = "fimc", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, -}; - -static struct clksrc_clk clk_fimc2 = { - .clk = { - .name = "fimc", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, -}; - -static struct clksrc_clk clk_mmc0 = { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, -}; - -static struct clksrc_clk clk_mmc1 = { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, -}; - -static struct clksrc_clk clk_mmc2 = { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, -}; - -static struct clksrc_clk clk_usbhost = { - .clk = { - .name = "usbhost", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_usbhost, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, +static struct clksrc_clk clksrc_clks[] = { + { + .clk = { + .name = "spi_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, + }, { + .clk = { + .name = "spi_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, + }, { + .clk = { + .name = "spi_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_uart, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, + }, { + .clk = { + .name = "spdif", + .id = -1, + }, + .sources = &clkset_spdif, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, + }, { + .clk = { + .name = "lcd", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, + }, { + .clk = { + .name = "usbhost", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_usbhost, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, + } }; /* Clock initialisation code */ @@ -785,22 +756,6 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_onenand, &clk_mout_epll, &clk_mout_hpll, - &clk_spi0, - &clk_spi1, - &clk_spi2, - &clk_uart_uclk1, - &clk_audio0, - &clk_audio1, - &clk_audio2, - &clk_spdif, - &clk_lcd, - &clk_fimc0, - &clk_fimc1, - &clk_fimc2, - &clk_mmc0, - &clk_mmc1, - &clk_mmc2, - &clk_usbhost, }; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) @@ -867,6 +822,12 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++) + s3c_set_clksrc(clksrc_audio + ptr, true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) + s3c_set_clksrc(clksrc_clks + ptr, true); } static struct clk *clks[] __initdata = { @@ -875,8 +836,13 @@ static struct clk *clks[] __initdata = { &clk_dout_d0_bus, &clk_dout_pclkd0, &clk_dout_apll2, + &clk_mout_apll.clk, + &clk_mout_mpll.clk, + &clk_mout_epll.clk, + &clk_mout_hpll.clk, &clk_mout_am.clk, &clk_dout_d1_bus, + &clk_mout_onenand.clk, &clk_dout_pclkd1, &clk_dout_mpll2, &clk_dout_cam, @@ -890,30 +856,6 @@ static struct clk *clks[] __initdata = { &clk_arm, }; -/* simplest change - will aggregate clocks later */ -static struct clksrc_clk *clks_src[] = { - &clk_mout_apll, - &clk_mout_mpll, - &clk_mout_onenand, - &clk_mout_epll, - &clk_spi0, - &clk_spi1, - &clk_spi2, - &clk_uart_uclk1, - &clk_audio0, - &clk_audio1, - &clk_audio2, - &clk_spdif, - &clk_lcd, - &clk_fimc0, - &clk_fimc1, - &clk_fimc2, - &clk_mmc0, - &clk_mmc1, - &clk_mmc2, - &clk_usbhost, -}; - void __init s5pc100_register_clocks(void) { struct clk *clkp; @@ -929,6 +871,6 @@ void __init s5pc100_register_clocks(void) } } - for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++) - s3c_register_clksrc(clks_src[ptr], 1); + s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio)); + s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); } -- GitLab From 37872bb9efddf9518cc77c43f9fa8fc6bfd3d727 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 12:52:43 +0900 Subject: [PATCH 058/370] ARM: SAMSUNG: Add script to change old clksrc_clk to new register defs This script is used to change the old style clksrc_clk as originally found in plat-s3c64xx to the new style. It is here for reference if needed for future code merges. Signed-off-by: Ben Dooks --- .../arm/Samsung/clksrc-change-registers.awk | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100755 Documentation/arm/Samsung/clksrc-change-registers.awk diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk new file mode 100755 index 0000000000000..0c50220851fbd --- /dev/null +++ b/Documentation/arm/Samsung/clksrc-change-registers.awk @@ -0,0 +1,167 @@ +#!/usr/bin/awk -f +# +# Copyright 2010 Ben Dooks +# +# Released under GPLv2 + +# example usage +# ./clksrc-change-registers.awk arch/arm/plat-s5pc1xx/include/plat/regs-clock.h < src > dst + +function extract_value(s) +{ + eqat = index(s, "=") + comat = index(s, ",") + return substr(s, eqat+2, (comat-eqat)-2) +} + +function remove_brackets(b) +{ + return substr(b, 2, length(b)-2) +} + +function splitdefine(l, p) +{ + r = split(l, tp) + + p[0] = tp[2] + p[1] = remove_brackets(tp[3]) +} + +function find_length(f) +{ + if (0) + printf "find_length " f "\n" > "/dev/stderr" + + if (f ~ /0x1/) + return 1 + else if (f ~ /0x3/) + return 2 + else if (f ~ /0x7/) + return 3 + else if (f ~ /0xf/) + return 4 + + printf "unknown legnth " f "\n" > "/dev/stderr" + exit +} + +function find_shift(s) +{ + id = index(s, "<") + if (id <= 0) { + printf "cannot find shift " s "\n" > "/dev/stderr" + exit + } + + return substr(s, id+2) +} + + +BEGIN { + if (ARGC < 2) { + print "too few arguments" > "/dev/stderr" + exit + } + +# read the header file and find the mask values that we will need +# to replace and create an associative array of values + + while (getline line < ARGV[1] > 0) { + if (line ~ /\#define.*_MASK/ && + !(line ~ /S5PC100_EPLL_MASK/) && + !(line ~ /USB_SIG_MASK/)) { + splitdefine(line, fields) + name = fields[0] + if (0) + printf "MASK " line "\n" > "/dev/stderr" + dmask[name,0] = find_length(fields[1]) + dmask[name,1] = find_shift(fields[1]) + if (0) + printf "=> '" name "' LENGTH=" dmask[name,0] " SHIFT=" dmask[name,1] "\n" > "/dev/stderr" + } else { + } + } + + delete ARGV[1] +} + +/clksrc_clk.*=.*{/ { + shift="" + mask="" + divshift="" + reg_div="" + reg_src="" + indent=1 + + print $0 + + for(; indent >= 1;) { + if ((getline line) <= 0) { + printf "unexpected end of file" > "/dev/stderr" + exit 1; + } + + if (line ~ /\.shift/) { + shift = extract_value(line) + } else if (line ~ /\.mask/) { + mask = extract_value(line) + } else if (line ~ /\.reg_divider/) { + reg_div = extract_value(line) + } else if (line ~ /\.reg_source/) { + reg_src = extract_value(line) + } else if (line ~ /\.divider_shift/) { + divshift = extract_value(line) + } else if (line ~ /{/) { + indent++ + print line + } else if (line ~ /}/) { + indent-- + + if (indent == 0) { + if (0) { + printf "shift '" shift "' ='" dmask[shift,0] "'\n" > "/dev/stderr" + printf "mask '" mask "'\n" > "/dev/stderr" + printf "dshft '" divshift "'\n" > "/dev/stderr" + printf "rdiv '" reg_div "'\n" > "/dev/stderr" + printf "rsrc '" reg_src "'\n" > "/dev/stderr" + } + + generated = mask + sub(reg_src, reg_div, generated) + + if (0) { + printf "/* rsrc " reg_src " */\n" + printf "/* rdiv " reg_div " */\n" + printf "/* shift " shift " */\n" + printf "/* mask " mask " */\n" + printf "/* generated " generated " */\n" + } + + if (reg_div != "") { + printf "\t.reg_div = { " + printf ".reg = " reg_div ", " + printf ".shift = " dmask[generated,1] ", " + printf ".size = " dmask[generated,0] ", " + printf "},\n" + } + + printf "\t.reg_src = { " + printf ".reg = " reg_src ", " + printf ".shift = " dmask[mask,1] ", " + printf ".size = " dmask[mask,0] ", " + + printf "},\n" + + } + + print line + } else { + print line + } + + if (0) + printf indent ":" line "\n" > "/dev/stderr" + } +} + +// && ! /clksrc_clk.*=.*{/ { print $0 } -- GitLab From 35accd2f6639a9245488f2f389e3c6372c7641e4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 13:10:59 +0900 Subject: [PATCH 059/370] ARM: S5PC1XX: Remove definitions deleted by previous clksrc changes Remove the definitions we've deleted in the previous updates to the clksrc_clk for arch/arm/plat-s5pc1xx/include/plat/regs-clock.h. Added comments about the removal to the clock header since we only need these defines in one place (and they've now been removed there) we get rid of them from the header. Signed-off-by: Ben Dooks --- .../plat-s5pc1xx/include/plat/regs-clock.h | 119 +----------------- 1 file changed, 6 insertions(+), 113 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index c5cc86e92d658..24dec4e525388 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h @@ -61,73 +61,10 @@ #define S5PC100_EPLL_MASK 0xffffffff #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) -/* CLKSRC0 */ -#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) -#define S5PC100_CLKSRC0_APLL_SHIFT (0) -#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) -#define S5PC100_CLKSRC0_MPLL_SHIFT (4) -#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) -#define S5PC100_CLKSRC0_EPLL_SHIFT (8) -#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) -#define S5PC100_CLKSRC0_HPLL_SHIFT (12) -#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) -#define S5PC100_CLKSRC0_AMMUX_SHIFT (16) -#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) -#define S5PC100_CLKSRC0_HREF_SHIFT (20) -#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) -#define S5PC100_CLKSRC0_ONENAND_SHIFT (24) - - -/* CLKSRC1 */ -#define S5PC100_CLKSRC1_UART_MASK (0x1<<0) -#define S5PC100_CLKSRC1_UART_SHIFT (0) -#define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) -#define S5PC100_CLKSRC1_SPI0_SHIFT (4) -#define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) -#define S5PC100_CLKSRC1_SPI1_SHIFT (8) -#define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) -#define S5PC100_CLKSRC1_SPI2_SHIFT (12) -#define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) -#define S5PC100_CLKSRC1_IRDA_SHIFT (16) -#define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) -#define S5PC100_CLKSRC1_UHOST_SHIFT (20) -#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) +/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ +#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) -/* CLKSRC2 */ -#define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) -#define S5PC100_CLKSRC2_MMC0_SHIFT (0) -#define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) -#define S5PC100_CLKSRC2_MMC1_SHIFT (4) -#define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) -#define S5PC100_CLKSRC2_MMC2_SHIFT (8) -#define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) -#define S5PC100_CLKSRC2_LCD_SHIFT (12) -#define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) -#define S5PC100_CLKSRC2_FIMC0_SHIFT (16) -#define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) -#define S5PC100_CLKSRC2_FIMC1_SHIFT (20) -#define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) -#define S5PC100_CLKSRC2_FIMC2_SHIFT (24) -#define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) -#define S5PC100_CLKSRC2_MIXER_SHIFT (28) - -/* CLKSRC3 */ -#define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) -#define S5PC100_CLKSRC3_PWI_SHIFT (0) -#define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) -#define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) -#define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) -#define S5PC100_CLKSRC3_I2SD2_SHIFT (8) -#define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) -#define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) -#define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) -#define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) -#define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) -#define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) -#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) -#define S5PC100_CLKSRC3_SPDIF_SHIFT (24) - /* CLKDIV0 */ #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) #define S5PC100_CLKDIV0_APLL_SHIFT (0) @@ -140,7 +77,7 @@ #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) #define S5PC100_CLKDIV0_SECSS_SHIFT (16) -/* CLKDIV1 */ +/* CLKDIV1 (OneNAND clock only used in one place, removed) */ #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) #define S5PC100_CLKDIV1_APLL2_SHIFT (0) #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) @@ -151,56 +88,12 @@ #define S5PC100_CLKDIV1_D1_SHIFT (12) #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) -#define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) -#define S5PC100_CLKDIV1_ONENAND_SHIFT (20) #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) #define S5PC100_CLKDIV1_CAM_SHIFT (24) -/* CLKDIV2 */ -#define S5PC100_CLKDIV2_UART_MASK (0x7<<0) -#define S5PC100_CLKDIV2_UART_SHIFT (0) -#define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) -#define S5PC100_CLKDIV2_SPI0_SHIFT (4) -#define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) -#define S5PC100_CLKDIV2_SPI1_SHIFT (8) -#define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) -#define S5PC100_CLKDIV2_SPI2_SHIFT (12) -#define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) -#define S5PC100_CLKDIV2_IRDA_SHIFT (16) -#define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) -#define S5PC100_CLKDIV2_UHOST_SHIFT (20) - -/* CLKDIV3 */ -#define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) -#define S5PC100_CLKDIV3_MMC0_SHIFT (0) -#define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) -#define S5PC100_CLKDIV3_MMC1_SHIFT (4) -#define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) -#define S5PC100_CLKDIV3_MMC2_SHIFT (8) -#define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) -#define S5PC100_CLKDIV3_LCD_SHIFT (12) -#define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) -#define S5PC100_CLKDIV3_FIMC0_SHIFT (16) -#define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) -#define S5PC100_CLKDIV3_FIMC1_SHIFT (20) -#define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) -#define S5PC100_CLKDIV3_FIMC2_SHIFT (24) -#define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) -#define S5PC100_CLKDIV3_HDMI_SHIFT (28) - -/* CLKDIV4 */ -#define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) -#define S5PC100_CLKDIV4_PWI_SHIFT (0) -#define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) -#define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) -#define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) -#define S5PC100_CLKDIV4_I2SD2_SHIFT (8) -#define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) -#define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) -#define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) -#define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) -#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) -#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) +/* CLKDIV2 => removed in clksrc update */ +/* CLKDIV3 => removed in clksrc update, or not needed */ +/* CLKDIV4 => removed in clksrc update, or not needed */ /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ #define S5PC100_CLKGATE_D00_INTC (1<<0) -- GitLab From 47101ec73901183520de724fb5f9062c014236bb Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 7 Jan 2010 14:41:38 +0900 Subject: [PATCH 060/370] ARM: S5PC1XX: Move to using standard timer IRQ handling code Move to using the standard VIC/Timer IRQ handling code added previously to avoid duplicating code. Thanks to Marek Szyprowski for pointing out dual Kconfig change. Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/include/mach/tick.h | 2 +- arch/arm/plat-s5pc1xx/Kconfig | 1 + arch/arm/plat-s5pc1xx/include/plat/irqs.h | 19 +++-- arch/arm/plat-s5pc1xx/irq.c | 88 ++--------------------- 4 files changed, 22 insertions(+), 88 deletions(-) diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index d3de0f3591ae1..f338c9eec7176 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h @@ -21,7 +21,7 @@ static inline u32 s3c24xx_ostimer_pending(void) { u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); - return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0)); + return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); } #define TICK_MAX (0xffffffff) diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index 5d97b1c3cef73..256f0f9f1ddfb 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -12,6 +12,7 @@ config PLAT_S5PC1XX select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index ef8736366f0d3..409c804315e87 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h @@ -88,11 +88,11 @@ #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) -#define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) -#define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) -#define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) -#define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) -#define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) +#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21) +#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22) +#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23) +#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24) +#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25) #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) @@ -171,8 +171,15 @@ #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) +#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x)) +#define IRQ_TIMER0 IRQ_TIMER(0) +#define IRQ_TIMER1 IRQ_TIMER(1) +#define IRQ_TIMER2 IRQ_TIMER(2) +#define IRQ_TIMER3 IRQ_TIMER(3) +#define IRQ_TIMER4 IRQ_TIMER(4) + /* External interrupt */ -#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) +#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6) #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index e44fd04ef3335..ae233bdeb7e24 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c @@ -20,77 +20,9 @@ #include #include -#include +#include #include -/* Timer interrupt handling */ - -static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) -{ - generic_handle_irq(sub_irq); -} - -static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER0); -} - -static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER1); -} - -static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER2); -} - -static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER3); -} - -static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER4); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~(1 << (irq - IRQ_TIMER0)); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= 1 << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_ack(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= (1 << 5) << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .mask = s3c_irq_timer_mask, - .unmask = s3c_irq_timer_unmask, - .ack = s3c_irq_timer_ack, -}; - struct uart_irq { void __iomem *regs; unsigned int base_irq; @@ -229,7 +161,7 @@ static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) void __init s5pc1xx_init_irq(u32 *vic_valid, int num) { int i; - int uart, irq; + int uart; printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -240,17 +172,11 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num) /* add the timer sub-irqs */ - set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); - set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); - set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); - set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); - set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); - - for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { - set_irq_chip(irq, &s3c_irq_timer); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) s5pc1xx_uart_irq(&uart_irqs[uart]); -- GitLab From be97162d47b2e067f9d21097650f2f0405dacc9f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 14:13:58 +0900 Subject: [PATCH 061/370] ARM: S5PC1XX: Use common UART IRQ handling code Use the common UART IRQ handling code for the S5PC100 system. Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/Kconfig | 1 + arch/arm/plat-s5pc1xx/irq.c | 116 +--------------------------------- 2 files changed, 4 insertions(+), 113 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index 256f0f9f1ddfb..c7ccdf22eefaa 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -12,6 +12,7 @@ config PLAT_S5PC1XX select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_UART select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index ae233bdeb7e24..bfc524827819f 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c @@ -21,18 +21,13 @@ #include #include +#include #include -struct uart_irq { - void __iomem *regs; - unsigned int base_irq; - unsigned int parent_irq; -}; - /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ -static struct uart_irq uart_irqs[] = { +static struct s3c_uart_irq uart_irqs[] = { [0] = { .regs = (void *)S3C_VA_UART0, .base_irq = IRQ_S3CUART_BASE0, @@ -55,113 +50,9 @@ static struct uart_irq uart_irqs[] = { }, }; -static inline void __iomem *s3c_irq_uart_base(unsigned int irq) -{ - struct uart_irq *uirq = get_irq_chip_data(irq); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -/* UART interrupt registers, not worth adding to seperate include header */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 - -static void s3c_irq_uart_mask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) -{ - struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; - u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); - int base = uirq->base_irq; - - if (pend & (1 << 0)) - generic_handle_irq(base); - if (pend & (1 << 1)) - generic_handle_irq(base + 1); - if (pend & (1 << 2)) - generic_handle_irq(base + 2); - if (pend & (1 << 3)) - generic_handle_irq(base + 3); -} - -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .mask = s3c_irq_uart_mask, - .unmask = s3c_irq_uart_unmask, - .mask_ack = s3c_irq_uart_maskack, - .ack = s3c_irq_uart_ack, -}; - -static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) -{ - void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; - - /* mask all interrupts at the start. */ - __raw_writel(0xf, reg_base + S3C64XX_UINTM); - - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -} - void __init s5pc1xx_init_irq(u32 *vic_valid, int num) { int i; - int uart; printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -178,8 +69,7 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num) s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); - for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) - s5pc1xx_uart_irq(&uart_irqs[uart]); + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } -- GitLab From 209fecd1b8e65b8046efbbc8314d449e53c4c6b6 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 15:29:17 +0900 Subject: [PATCH 062/370] ARM: S5P6440: Add new CPU initialization support This patch adds Samsung's S5P6440 CPU support. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/cpu.c | 114 ++++++++++++++++++ .../mach-s5p6440/include/mach/debug-macro.S | 37 ++++++ .../mach-s5p6440/include/mach/entry-macro.S | 16 +++ .../arm/mach-s5p6440/include/mach/gpio-core.h | 19 +++ arch/arm/mach-s5p6440/include/mach/gpio.h | 80 ++++++++++++ arch/arm/mach-s5p6440/include/mach/hardware.h | 18 +++ arch/arm/mach-s5p6440/include/mach/map.h | 94 +++++++++++++++ arch/arm/mach-s5p6440/include/mach/memory.h | 19 +++ arch/arm/mach-s5p6440/include/mach/system.h | 26 ++++ .../mach-s5p6440/include/mach/uncompress.h | 24 ++++ arch/arm/plat-s3c/include/plat/cpu.h | 3 + arch/arm/plat-s5p/cpu.c | 90 ++++++++++++++ arch/arm/plat-s5p/include/plat/s5p6440.h | 37 ++++++ arch/arm/plat-s5p/s5p6440-init.c | 50 ++++++++ arch/arm/plat-s5p/setup-i2c0.c | 25 ++++ 15 files changed, 652 insertions(+) create mode 100644 arch/arm/mach-s5p6440/cpu.c create mode 100644 arch/arm/mach-s5p6440/include/mach/debug-macro.S create mode 100644 arch/arm/mach-s5p6440/include/mach/entry-macro.S create mode 100644 arch/arm/mach-s5p6440/include/mach/gpio-core.h create mode 100644 arch/arm/mach-s5p6440/include/mach/gpio.h create mode 100644 arch/arm/mach-s5p6440/include/mach/hardware.h create mode 100644 arch/arm/mach-s5p6440/include/mach/map.h create mode 100644 arch/arm/mach-s5p6440/include/mach/memory.h create mode 100644 arch/arm/mach-s5p6440/include/mach/system.h create mode 100644 arch/arm/mach-s5p6440/include/mach/uncompress.h create mode 100644 arch/arm/plat-s5p/cpu.c create mode 100644 arch/arm/plat-s5p/include/plat/s5p6440.h create mode 100644 arch/arm/plat-s5p/s5p6440-init.c create mode 100644 arch/arm/plat-s5p/setup-i2c0.c diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c new file mode 100644 index 0000000000000..1794131aeacb5 --- /dev/null +++ b/arch/arm/mach-s5p6440/cpu.c @@ -0,0 +1,114 @@ +/* linux/arch/arm/mach-s5p6440/cpu.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +static void s5p6440_idle(void) +{ + unsigned long val; + + if (!need_resched()) { + val = __raw_readl(S5P_PWR_CFG); + val &= ~(0x3<<5); + val |= (0x1<<5); + __raw_writel(val, S5P_PWR_CFG); + + cpu_do_idle(); + } + local_irq_enable(); +} + +/* s5p6440_map_io + * + * register the standard cpu IO areas +*/ + +void __init s5p6440_map_io(void) +{ + /* initialize any device information early */ +} + +void __init s5p6440_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5p6440_register_clocks(); + s5p6440_setup_clocks(); +} + +void __init s5p6440_init_irq(void) +{ + /* S5P6440 supports only 2 VIC */ + u32 vic[2]; + + /* + * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)] + * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22] + */ + vic[0] = 0xff800ae7; + vic[1] = 0xffbf23e5; + + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +static struct sysdev_class s5p6440_sysclass = { + .name = "s5p6440-core", +}; + +static struct sys_device s5p6440_sysdev = { + .cls = &s5p6440_sysclass, +}; + +static int __init s5p6440_core_init(void) +{ + return sysdev_class_register(&s5p6440_sysclass); +} + +core_initcall(s5p6440_core_init); + +int __init s5p6440_init(void) +{ + printk(KERN_INFO "S5P6440: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5p6440_idle; + + return sysdev_register(&s5p6440_sysdev); +} diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S new file mode 100644 index 0000000000000..f3a5d1635be5b --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/debug-macro.S @@ -0,0 +1,37 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include +#include + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S5P_PA_UART + ldrne \rx, = (S5P_VA_UART + S5P_PA_UART & 0xfffff) +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p6440/include/mach/entry-macro.S new file mode 100644 index 0000000000000..e65f1b9672626 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/entry-macro.S @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Low-level IRQ helper macros for the Samsung S5P6440 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include + +#include diff --git a/arch/arm/mach-s5p6440/include/mach/gpio-core.h b/arch/arm/mach-s5p6440/include/mach/gpio-core.h new file mode 100644 index 0000000000000..ff7fb3094188f --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/gpio-core.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/gpio-core.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIO core support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_CORE_H +#define __ASM_ARCH_GPIO_CORE_H __FILE__ + +/* currently we just include the platform support */ +#include + +#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h new file mode 100644 index 0000000000000..21783834f2a2b --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/gpio.h @@ -0,0 +1,80 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S5P6440_GPIO_A_NR (6) +#define S5P6440_GPIO_B_NR (7) +#define S5P6440_GPIO_C_NR (8) +#define S5P6440_GPIO_F_NR (2) +#define S5P6440_GPIO_G_NR (7) +#define S5P6440_GPIO_H_NR (10) +#define S5P6440_GPIO_I_NR (16) +#define S5P6440_GPIO_J_NR (12) +#define S5P6440_GPIO_N_NR (16) +#define S5P6440_GPIO_P_NR (8) +#define S5P6440_GPIO_R_NR (15) + +/* GPIO bank numbers */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ +#define S5P6440_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + S5P6440_GPIO_A_START = 0, + S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A), + S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B), + S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C), + S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F), + S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G), + S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H), + S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I), + S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J), + S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N), + S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P), +}; + +/* S5P6440 GPIO number definitions. */ +#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr)) +#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr)) +#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr)) +#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr)) +#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr)) +#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr)) +#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr)) +#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr)) +#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr)) +#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr)) +#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr)) + +/* the end of the S5P6440 specific gpios */ +#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1) +#define S3C_GPIO_END S5P6440_GPIO_END + +/* define the number of gpios we need to the one after the GPR() range */ +#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p6440/include/mach/hardware.h new file mode 100644 index 0000000000000..be8b26e875db5 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h new file mode 100644 index 0000000000000..b3703293cc3be --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -0,0 +1,94 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/map.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include + +/* SYSCON */ +#define S5P6440_PA_SYSCON (0xE0100000) +#define S5P_PA_SYSCON S5P6440_PA_SYSCON +#define S5P_VA_SYSCON S3C_VA_SYS + +#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0) +#define S5P_PA_CLK S5P6440_PA_CLK +#define S5P_VA_CLK (S5P_VA_SYSCON + 0x0) + +/* GPIO */ +#define S5P6440_PA_GPIO (0xE0308000) +#define S5P_PA_GPIO S5P6440_PA_GPIO +#define S5P_VA_GPIO S3C_ADDR(0x00500000) + +/* VIC0 */ +#define S5P6440_PA_VIC0 (0xE4000000) +#define S5P_PA_VIC0 S5P6440_PA_VIC0 +#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define VA_VIC0 S5P_VA_VIC0 + +/* VIC1 */ +#define S5P6440_PA_VIC1 (0xE4100000) +#define S5P_PA_VIC1 S5P6440_PA_VIC1 +#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define VA_VIC1 S5P_VA_VIC1 + +/* Timer */ +#define S5P6440_PA_TIMER (0xEA000000) +#define S5P_PA_TIMER S5P6440_PA_TIMER +#define S5P_VA_TIMER S3C_VA_TIMER + +/* RTC */ +#define S5P6440_PA_RTC (0xEA100000) +#define S5P_PA_RTC S5P6440_PA_RTC +#define S5P_VA_RTC S3C_ADDR(0x00600000) + +/* WDT */ +#define S5P6440_PA_WDT (0xEA200000) +#define S5P_PA_WDT S5P6440_PA_WDT +#define S5p_VA_WDT S3C_VA_WATCHDOG + +/* UART */ +#define S5P6440_PA_UART (0xEC000000) +#define S5P_PA_UART S5P6440_PA_UART +#define S5P_VA_UART S3C_VA_UART + +#define S5P_PA_UART0 (S5P_PA_UART + 0x0) +#define S5P_PA_UART1 (S5P_PA_UART + 0x400) +#define S5P_PA_UART2 (S5P_PA_UART + 0x800) +#define S5P_PA_UART3 (S5P_PA_UART + 0xC00) +#define S5P_UART_OFFSET (0x400) + +#define S5P_VA_UARTx(x) (S5P_VA_UART + (S5P_PA_UART & 0xfffff) \ + + ((x) * S5P_UART_OFFSET)) + +#define S5P_VA_UART0 S5P_VA_UARTx(0) +#define S5P_VA_UART1 S5P_VA_UARTx(1) +#define S5P_VA_UART2 S5P_VA_UARTx(2) +#define S5P_VA_UART3 S5P_VA_UARTx(3) +#define S5P_SZ_UART SZ_256 + +/* I2C */ +#define S5P6440_PA_IIC0 (0xEC104000) +#define S5P_PA_IIC0 S5P6440_PA_IIC0 +#define S5p_VA_IIC0 S3C_ADDR(0x00700000) + +/* SDRAM */ +#define S5P6440_PA_SDRAM (0x20000000) +#define S5P_PA_SDRAM S5P6440_PA_SDRAM + +/* compatibiltiy defines. */ +#define S3C_PA_UART S5P_PA_UART +#define S3C_UART_OFFSET S5P_UART_OFFSET +#define S3C_PA_TIMER S5P_PA_TIMER +#define S3C_PA_IIC S5P_PA_IIC0 + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p6440/include/mach/memory.h new file mode 100644 index 0000000000000..d62910c71b566 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/memory.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/memory.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x20000000) +#define CONSISTENT_DMA_SIZE SZ_8M + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h new file mode 100644 index 0000000000000..d2dd817da66a7 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/system.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/system.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode, const char *cmd) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h new file mode 100644 index 0000000000000..7c1f600d65c0b --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/uncompress.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index d1131ca11e97e..676db94656749 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -48,9 +48,12 @@ extern void s3c_init_cpu(unsigned long idcode, extern void s3c24xx_init_irq(void); extern void s3c64xx_init_irq(u32 vic0, u32 vic1); +extern void s5p_init_irq(u32 *vic, u32 num_vic); extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); +extern void s5p_init_io(struct map_desc *mach_desc, + int size, void __iomem *cpuid_addr); extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c new file mode 100644 index 0000000000000..0895a77a28359 --- /dev/null +++ b/arch/arm/plat-s5p/cpu.c @@ -0,0 +1,90 @@ +/* linux/arch/arm/plat-s5p/cpu.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P CPU Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* table of supported CPUs */ + +static const char name_s5p6440[] = "S5P6440"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = 0x56440100, + .idmask = 0xffffff00, + .map_io = s5p6440_map_io, + .init_clocks = s5p6440_init_clocks, + .init_uarts = s5p6440_init_uarts, + .init = s5p6440_init, + .name = name_s5p6440, + }, +}; + +/* minimal IO mapping */ + +#define UART_OFFS (S5P_PA_UART & 0xfffff) + +static struct map_desc s5p_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSCON, + .pfn = __phys_to_pfn(S5P_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)(S5P_VA_UART + UART_OFFS), + .pfn = __phys_to_pfn(S5P_PA_UART), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_VIC0, + .pfn = __phys_to_pfn(S5P_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_VIC1, + .pfn = __phys_to_pfn(S5P_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_TIMER, + .pfn = __phys_to_pfn(S5P_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GPIO, + .pfn = __phys_to_pfn(S5P_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +/* read cpu identification code */ + +void __init s5p_init_io(struct map_desc *mach_desc, + int size, void __iomem *cpuid_addr) +{ + unsigned long idcode; + + /* initialize the io descriptors we need for initialization */ + iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); + if (mach_desc) + iotable_init(mach_desc, size); + + idcode = __raw_readl(cpuid_addr); + s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); +} diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h new file mode 100644 index 0000000000000..a4cd75afeb3bf --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6440.h @@ -0,0 +1,37 @@ +/* arch/arm/plat-s5p/include/plat/s5p6440.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p6440 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + /* Common init code for S5P6440 related SoCs */ + +extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5p6440_register_clocks(void); +extern void s5p6440_setup_clocks(void); + +#ifdef CONFIG_CPU_S5P6440 + +extern int s5p6440_init(void); +extern void s5p6440_init_irq(void); +extern void s5p6440_map_io(void); +extern void s5p6440_init_clocks(int xtal); + +#define s5p6440_init_uarts s5p6440_common_init_uarts + +#else +#define s5p6440_init_clocks NULL +#define s5p6440_init_uarts NULL +#define s5p6440_map_io NULL +#define s5p6440_init NULL +#endif + +/* S5P6440 timer */ + +extern struct sys_timer s5p6440_timer; diff --git a/arch/arm/plat-s5p/s5p6440-init.c b/arch/arm/plat-s5p/s5p6440-init.c new file mode 100644 index 0000000000000..90178256cc281 --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-init.c @@ -0,0 +1,50 @@ +/* linux/arch/arm/plat-s5p/s5p6440-init.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = { + [0] = { + .name = "pclk_low", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "uclk1", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, +}; + +/* uart registration process */ +void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + struct s3c2410_uartcfg *tcfg = cfg; + u32 ucnt; + + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + if (!tcfg->clocks) { + tcfg->clocks = s5p6440_serial_clocks; + tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks); + } + } + + s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/plat-s5p/setup-i2c0.c b/arch/arm/plat-s5p/setup-i2c0.c new file mode 100644 index 0000000000000..67a66e02a97a6 --- /dev/null +++ b/arch/arm/plat-s5p/setup-i2c0.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/plat-s5p/setup-i2c0.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include + +struct platform_device; /* don't need the contents */ + +#include + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + /* Will be populated later */ +} -- GitLab From 1a0e8a52ad56075663d8e120e2468fc96fb6fa6c Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:13:37 +0900 Subject: [PATCH 063/370] ARM: S5P6440: Add Clock and PLL support This patch adds clock and pll support for S5P6440. This patch are based on Harald Welte's patches and Ben's plat-samsung. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- .../mach-s5p6440/include/mach/regs-clock.h | 130 ++++ arch/arm/plat-s5p/clock.c | 136 ++++ arch/arm/plat-s5p/include/plat/pll.h | 83 +++ arch/arm/plat-s5p/include/plat/s5p-clock.h | 38 + arch/arm/plat-s5p/s5p6440-clock.c | 698 ++++++++++++++++++ arch/arm/plat-samsung/include/plat/clock.h | 1 + 6 files changed, 1086 insertions(+) create mode 100644 arch/arm/mach-s5p6440/include/mach/regs-clock.h create mode 100644 arch/arm/plat-s5p/clock.c create mode 100644 arch/arm/plat-s5p/include/plat/pll.h create mode 100644 arch/arm/plat-s5p/include/plat/s5p-clock.h create mode 100644 arch/arm/plat-s5p/s5p6440-clock.c diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h new file mode 100644 index 0000000000000..b7af28342bc47 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-clock.h @@ -0,0 +1,130 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include + +#define S5P_CLKREG(x) (S5P_VA_CLK + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x04) +#define S5P_EPLL_LOCK S5P_CLKREG(0x08) +#define S5P_APLL_CON S5P_CLKREG(0x0C) +#define S5P_MPLL_CON S5P_CLKREG(0x10) +#define S5P_EPLL_CON S5P_CLKREG(0x14) +#define S5P_EPLL_CON_K S5P_CLKREG(0x18) +#define S5P_CLK_SRC0 S5P_CLKREG(0x1C) +#define S5P_CLK_DIV0 S5P_CLKREG(0x20) +#define S5P_CLK_DIV1 S5P_CLKREG(0x24) +#define S5P_CLK_DIV2 S5P_CLKREG(0x28) +#define S5P_CLK_OUT S5P_CLKREG(0x2C) +#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30) +#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34) +#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38) +#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C) +#define S5P_CLK_DIV3 S5P_CLKREG(0x40) +#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44) +#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48) +#define S5P_AHB_CON0 S5P_CLKREG(0x100) +#define S5P_CLK_SRC1 S5P_CLKREG(0x10C) +#define S5P_SWRESET S5P_CLKREG(0x114) +#define S5P_SYS_ID S5P_CLKREG(0x118) +#define S5P_SYS_OTHERS S5P_CLKREG(0x11C) +#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C) +#define S5P_PWR_CFG S5P_CLKREG(0x804) +#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808) +#define S5P_NORMAL_CFG S5P_CLKREG(0x810) +#define S5P_STOP_CFG S5P_CLKREG(0x814) +#define S5P_SLEEP_CFG S5P_CLKREG(0x818) +#define S5P_OSC_FREQ S5P_CLKREG(0x820) +#define S5P_OSC_STABLE S5P_CLKREG(0x824) +#define S5P_PWR_STABLE S5P_CLKREG(0x828) +#define S5P_MTC_STABLE S5P_CLKREG(0x830) +#define S5P_OTHERS S5P_CLKREG(0x900) +#define S5P_RST_STAT S5P_CLKREG(0x904) +#define S5P_WAKEUP_STAT S5P_CLKREG(0x908) +#define S5P_SLPEN S5P_CLKREG(0x930) +#define S5P_INFORM0 S5P_CLKREG(0xA00) +#define S5P_INFORM1 S5P_CLKREG(0xA04) +#define S5P_INFORM2 S5P_CLKREG(0xA08) +#define S5P_INFORM3 S5P_CLKREG(0xA0C) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_PCLK_MASK (0xf << 12) +#define S5P_CLKDIV0_PCLK_SHIFT (12) +#define S5P_CLKDIV0_HCLK_MASK (0xf << 8) +#define S5P_CLKDIV0_HCLK_SHIFT (8) +#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S5P_CLKDIV0_ARM_MASK (0xf << 0) +#define S5P_CLKDIV0_ARM_SHIFT (0) + +/* CLKDIV3 */ +#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12) +#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12) +#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8) +#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8) + +/* HCLK0 GATE Registers */ +#define S5P_CLKCON_HCLK0_USB (1<<20) +#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19) +#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18) +#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17) +#define S5P_CLKCON_HCLK0_POST0 (1<<5) + +/* HCLK1 GATE Registers */ +#define S5P_CLKCON_HCLK1_DISPCON (1<<1) + +/* PCLK GATE Registers */ +#define S5P_CLKCON_PCLK_IIS2 (1<<26) +#define S5P_CLKCON_PCLK_SPI1 (1<<22) +#define S5P_CLKCON_PCLK_SPI0 (1<<21) +#define S5P_CLKCON_PCLK_GPIO (1<<18) +#define S5P_CLKCON_PCLK_IIC0 (1<<17) +#define S5P_CLKCON_PCLK_TSADC (1<<12) +#define S5P_CLKCON_PCLK_PWM (1<<7) +#define S5P_CLKCON_PCLK_RTC (1<<6) +#define S5P_CLKCON_PCLK_WDT (1<<5) +#define S5P_CLKCON_PCLK_UART3 (1<<4) +#define S5P_CLKCON_PCLK_UART2 (1<<3) +#define S5P_CLKCON_PCLK_UART1 (1<<2) +#define S5P_CLKCON_PCLK_UART0 (1<<1) + +/* SCLK0 GATE Registers */ +#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29) +#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28) +#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27) +#define S5P_CLKCON_SCLK0_MMC2 (1<<26) +#define S5P_CLKCON_SCLK0_MMC1 (1<<25) +#define S5P_CLKCON_SCLK0_MMC0 (1<<24) +#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23) +#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22) +#define S5P_CLKCON_SCLK0_SPI1 (1<<21) +#define S5P_CLKCON_SCLK0_SPI0 (1<<20) +#define S5P_CLKCON_SCLK0_UART (1<<5) + +/* SCLK1 GATE Registers */ + +/* MEM0 GATE Registers */ +#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2) + +/*OTHERS Resgister */ +#define S5P_OTHERS_USB_SIG_MASK (1<<16) +#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6) + +/* Compatibility defines */ +#define ARM_CLK_DIV S5P_CLK_DIV0 +#define ARM_DIV_RATIO_SHIFT 0 +#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c new file mode 100644 index 0000000000000..3d3c0f1934fc4 --- /dev/null +++ b/arch/arm/plat-s5p/clock.c @@ -0,0 +1,136 @@ +/* linux/arch/arm/plat-s5p/clock.c + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Common clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * clk_ext_xtal_mux. +*/ +struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", + .id = -1, +}; + +/* 48MHz USB Phy clock output */ +struct clk clk_48m = { + .name = "clk_48m", + .id = -1, + .rate = 48000000, +}; + +/* APLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_apll = { + .name = "fout_apll", + .id = -1, +}; + +/* MPLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_mpll = { + .name = "fout_mpll", + .id = -1, +}; + +/* EPLL clock output */ +struct clk clk_fout_epll = { + .name = "fout_epll", + .id = -1, + .ctrlbit = (1 << 31), +}; + +/* ARM clock */ +struct clk clk_arm = { + .name = "armclk", + .id = -1, + .rate = 0, + .ctrlbit = 0, +}; + +/* Possible clock sources for APLL Mux */ +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +struct clksrc_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +/* Possible clock sources for MPLL Mux */ +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +struct clksrc_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +/* Possible clock sources for EPLL Mux */ +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +struct clksrc_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + con = enable ? (con | ctrlbit) : (con & ~ctrlbit); + __raw_writel(con, reg); + return 0; +} + +static struct clk *s5p_clks[] __initdata = { + &clk_ext_xtal_mux, + &clk_48m, + &clk_fout_apll, + &clk_fout_mpll, + &clk_fout_epll, + &clk_arm, +}; + +void __init s5p_register_clocks(unsigned long xtal_freq) +{ + int ret; + + clk_ext_xtal_mux.rate = xtal_freq; + + ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register s5p clocks\n"); +} diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h new file mode 100644 index 0000000000000..d48325bb29e22 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -0,0 +1,83 @@ +/* arch/arm/plat-s5p/include/plat/pll.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P PLL code + * + * Based on arch/arm/plat-s3c64xx/include/plat/pll.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define PLL45XX_MDIV_MASK (0x3FF) +#define PLL45XX_PDIV_MASK (0x3F) +#define PLL45XX_SDIV_MASK (0x7) +#define PLL45XX_MDIV_SHIFT (16) +#define PLL45XX_PDIV_SHIFT (8) +#define PLL45XX_SDIV_SHIFT (0) + +#include + +enum pll45xx_type_t { + pll_4500, + pll_4502, + pll_4508 +}; + +static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, + enum pll45xx_type_t pll_type) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; + pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; + sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; + + if (pll_type == pll_4508) + sdiv = sdiv - 1; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define PLL90XX_MDIV_MASK (0xFF) +#define PLL90XX_PDIV_MASK (0x3F) +#define PLL90XX_SDIV_MASK (0x7) +#define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_MDIV_SHIFT (16) +#define PLL90XX_PDIV_SHIFT (8) +#define PLL90XX_SDIV_SHIFT (0) +#define PLL90XX_KDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, + u32 pll_con, u32 pll_conk) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK; + pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK; + sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; + kdiv = pll_conk & PLL90XX_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h new file mode 100644 index 0000000000000..e1a7444b88298 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h @@ -0,0 +1,38 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_CLOCK_H +#define __ASM_PLAT_S5P_CLOCK_H __FILE__ + +#include + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux + +extern struct clk clk_ext_xtal_mux; +extern struct clk clk_48m; +extern struct clk clk_fout_apll; +extern struct clk clk_fout_mpll; +extern struct clk clk_fout_epll; +extern struct clk clk_arm; + +extern struct clksrc_sources clk_src_apll; +extern struct clksrc_sources clk_src_mpll; +extern struct clksrc_sources clk_src_epll; + +extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable); +extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); + +#endif /* __ASM_PLAT_S5P_CLOCK_H */ diff --git a/arch/arm/plat-s5p/s5p6440-clock.c b/arch/arm/plat-s5p/s5p6440-clock.c new file mode 100644 index 0000000000000..2f412f8c1212a --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-clock.c @@ -0,0 +1,698 @@ +/* linux/arch/arm/plat-s5p/s5p6440-clock.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* APLL Mux output clock */ +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static int s5p6440_epll_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; + + if (enable) + __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); + else + __raw_writel(epll_con, S5P_EPLL_CON); + + return 0; +} + +static unsigned long s5p6440_epll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static u32 epll_div[][5] = { + { 36000000, 0, 48, 1, 4 }, + { 48000000, 0, 32, 1, 3 }, + { 60000000, 0, 40, 1, 3 }, + { 72000000, 0, 48, 1, 3 }, + { 84000000, 0, 28, 1, 2 }, + { 96000000, 0, 32, 1, 2 }, + { 32768000, 45264, 43, 1, 4 }, + { 45158000, 6903, 30, 1, 3 }, + { 49152000, 50332, 32, 1, 3 }, + { 67738000, 10398, 45, 1, 3 }, + { 73728000, 9961, 49, 1, 3 } +}; + +static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + if (clk->rate == rate) /* Return if nothing changed */ + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + epll_con_k = __raw_readl(S5P_EPLL_CON_K); + + epll_con_k &= ~(PLL90XX_KDIV_MASK); + epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); + epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | + (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | + (epll_div[i][4] << PLL90XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + __raw_writel(epll_con_k, S5P_EPLL_CON_K); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops s5p6440_epll_ops = { + .get_rate = s5p6440_epll_get_rate, + .set_rate = s5p6440_epll_set_rate, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, +}; + +static struct clk clk_h_low = { + .name = "hclk_low", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .ops = &clk_ops_def_setrate, +}; + +static struct clk clk_p_low = { + .name = "pclk_low", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .ops = &clk_ops_def_setrate, +}; + +enum perf_level { + L0 = 532*1000, + L1 = 266*1000, + L2 = 133*1000, +}; + +static const u32 clock_table[][3] = { + /*{ARM_CLK, DIVarm, DIVhclk}*/ + {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)}, + {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)}, + {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)}, +}; + +static unsigned long s5p6440_armclk_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv; + + /* divisor mask starts at bit0, so no need to shift */ + clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK; + + return rate / (clkdiv + 1); +} + +static unsigned long s5p6440_armclk_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 iter; + + for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) { + if (rate > clock_table[iter][0]) + return clock_table[iter-1][0]; + } + + return clock_table[ARRAY_SIZE(clock_table) - 1][0]; +} + +static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 round_tmp; + u32 iter; + u32 clk_div0_tmp; + u32 cur_rate = clk->ops->get_rate(clk); + unsigned long flags; + + round_tmp = clk->ops->round_rate(clk, rate); + if (round_tmp == cur_rate) + return 0; + + + for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) { + if (round_tmp == clock_table[iter][0]) + break; + } + + if (iter >= ARRAY_SIZE(clock_table)) + iter = ARRAY_SIZE(clock_table) - 1; + + local_irq_save(flags); + if (cur_rate > round_tmp) { + /* Frequency Down */ + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); + clk_div0_tmp |= clock_table[iter][1]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & + ~(S5P_CLKDIV0_HCLK_MASK); + clk_div0_tmp |= clock_table[iter][2]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + + } else { + /* Frequency Up */ + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & + ~(S5P_CLKDIV0_HCLK_MASK); + clk_div0_tmp |= clock_table[iter][2]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); + clk_div0_tmp |= clock_table[iter][1]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + } + local_irq_restore(flags); + + clk->rate = clock_table[iter][0]; + + return 0; +} + +static struct clk_ops s5p6440_clkarm_ops = { + .get_rate = s5p6440_armclk_get_rate, + .set_rate = s5p6440_armclk_set_rate, + .round_rate = s5p6440_armclk_round_rate, +}; + +static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + + if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) + rate /= 2; + + return rate; +} + +static struct clk clk_dout_mpll = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, + .ops = &(struct clk_ops) { + .get_rate = s5p6440_clk_doutmpll_get_rate, + }, +}; + +int s5p6440_clk48m_ctrl(struct clk *clk, int enable) +{ + unsigned long flags; + u32 val; + + /* can't rely on clock lock, this register has other usages */ + local_irq_save(flags); + + val = __raw_readl(S5P_OTHERS); + if (enable) + val |= S5P_OTHERS_USB_SIG_MASK; + else + val &= ~S5P_OTHERS_USB_SIG_MASK; + + __raw_writel(val, S5P_OTHERS); + + local_irq_restore(flags); + + return 0; +} + +static int s5p6440_pclk_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable); +} + +static int s5p6440_hclk0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable); +} + +static int s5p6440_hclk1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable); +} + +static int s5p6440_sclk_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); +} + +static int s5p6440_mem_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); +} + +/* + * The following clocks will be disabled during clock initialization. It is + * recommended to keep the following clocks disabled until the driver requests + * for enabling the clock. + */ +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + .enable = s5p6440_mem_ctrl, + .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_TSADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_IIC0, + }, { + .name = "i2s_v40", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_IIS2, + }, { + .name = "spi", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_SPI0, + }, { + .name = "spi", + .id = 1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_SPI1, + }, { + .name = "sclk_spi_48", + .id = 0, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48, + }, { + .name = "sclk_spi_48", + .id = 1, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48, + }, { + .name = "mmc_48m", + .id = 0, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48, + }, { + .name = "mmc_48m", + .id = 1, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48, + }, { + .name = "mmc_48m", + .id = 2, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48, + }, { + .name = "otg", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_USB + }, { + .name = "post", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_POST0 + }, { + .name = "lcd", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_WDT, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_PWM, + } +}; + +/* + * The following clocks will be enabled during clock initialization. + */ +static struct clk init_clocks[] = { + { + .name = "gpio", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_GPIO, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART3, + } +}; + +static struct clk clk_iis_cd_v40 = { + .name = "iis_cdclk_v40", + .id = -1, +}; + +static struct clk clk_pcm_cd = { + .name = "pcm_cdclk", + .id = -1, +}; + +static struct clk *clkset_spi_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, +}; + +static struct clksrc_sources clkset_spi_mmc = { + .sources = clkset_spi_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S5P_CLKCON_SCLK0_MMC0, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S5P_CLKCON_SCLK0_MMC1, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S5P_CLKCON_SCLK0_MMC2, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S5P_CLKCON_SCLK0_UART, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "spi_epll", + .id = 0, + .ctrlbit = S5P_CLKCON_SCLK0_SPI0, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "spi_epll", + .id = 1, + .ctrlbit = S5P_CLKCON_SCLK0_SPI1, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, + } +}; + +/* Clock initialisation code */ +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, +}; + +void __init_or_cpufreq s5p6440_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long hclk_low; + unsigned long pclk; + unsigned long pclk_low; + unsigned long epll; + unsigned long apll; + unsigned long mpll; + unsigned int ptr; + u32 clkdiv0; + u32 clkdiv3; + + /* Set S5P6440 functions for clk_fout_epll */ + clk_fout_epll.enable = s5p6440_epll_enable; + clk_fout_epll.ops = &s5p6440_epll_ops; + + /* Set S5P6440 functions for arm clock */ + clk_arm.parent = &clk_mout_apll.clk; + clk_arm.ops = &s5p6440_clkarm_ops; + clk_48m.enable = s5p6440_clk48m_ctrl; + + clkdiv0 = __raw_readl(S5P_CLK_DIV0); + clkdiv3 = __raw_readl(S5P_CLK_DIV3); + + xtal_clk = clk_get(NULL, "ext_xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON), + __raw_readl(S5P_EPLL_CON_K)); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); + + printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ + " E=%ld.%ldMHz\n", + print_mhz(apll), print_mhz(mpll), print_mhz(epll)); + + fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); + hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); + pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); + + if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { + /* Asynchronous mode */ + hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); + } else { + /* Synchronous mode */ + hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); + } + + pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); + + printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ + " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", + print_mhz(hclk), print_mhz(hclk_low), + print_mhz(pclk), print_mhz(pclk_low)); + + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + + clk_f.rate = fclk; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_h_low.rate = hclk_low; + clk_p_low.rate = pclk_low; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); +} + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_mout_epll.clk, + &clk_mout_mpll.clk, + &clk_dout_mpll, + &clk_iis_cd_v40, + &clk_pcm_cd, + &clk_p_low, + &clk_h_low, +}; + +void __init s5p6440_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register %u clocks\n", ret); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 22e011497502c..ba9a1cdd3a28a 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -95,6 +95,7 @@ extern void s3c_register_clocks(struct clk *clk, int nr_clks); extern int s3c24xx_register_baseclocks(unsigned long xtal); extern void s3c64xx_register_clocks(void); +extern void s5p_register_clocks(unsigned long xtal_freq); extern void s3c24xx_setup_clocks(unsigned long fclk, unsigned long hclk, -- GitLab From b7db51be43bc8f9943324a00b80e5d034de0a733 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:14:40 +0900 Subject: [PATCH 064/370] ARM: S5P6440: Add IRQ support This patch adds IRQ support for S5P6440 CPU. Signed-off-by: Adityapratap Sharma Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/include/mach/irqs.h | 111 ++++++++++++++++++ arch/arm/mach-s5p6440/include/mach/regs-irq.h | 19 +++ arch/arm/plat-s5p/include/plat/irqs.h | 83 +++++++++++++ arch/arm/plat-s5p/irq.c | 73 ++++++++++++ 4 files changed, 286 insertions(+) create mode 100644 arch/arm/mach-s5p6440/include/mach/irqs.h create mode 100644 arch/arm/mach-s5p6440/include/mach/regs-irq.h create mode 100644 arch/arm/plat-s5p/include/plat/irqs.h create mode 100644 arch/arm/plat-s5p/irq.c diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h new file mode 100644 index 0000000000000..a4b9b40d18f24 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/irqs.h @@ -0,0 +1,111 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - IRQ definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_S5P_IRQS_H +#define __ASM_ARCH_S5P_IRQS_H __FILE__ + +#include + +/* VIC0 */ + +#define IRQ_EINT0_3 S5P_IRQ_VIC0(0) +#define IRQ_EINT4_11 S5P_IRQ_VIC0(1) +#define IRQ_RTC_TIC S5P_IRQ_VIC0(2) +#define IRQ_IIC1 S5P_IRQ_VIC0(5) +#define IRQ_I2SV40 S5P_IRQ_VIC0(6) +#define IRQ_GPS S5P_IRQ_VIC0(7) +#define IRQ_POST0 S5P_IRQ_VIC0(9) +#define IRQ_2D S5P_IRQ_VIC0(11) +#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) +#define IRQ_WDT S5P_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) +#define IRQ_DISPCON0 S5P_IRQ_VIC0(29) +#define IRQ_DISPCON1 S5P_IRQ_VIC0(30) +#define IRQ_DISPCON2 S5P_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_15 S5P_IRQ_VIC1(0) +#define IRQ_PCM0 S5P_IRQ_VIC1(2) +#define IRQ_UART0 S5P_IRQ_VIC1(5) +#define IRQ_UART1 S5P_IRQ_VIC1(6) +#define IRQ_UART2 S5P_IRQ_VIC1(7) +#define IRQ_UART3 S5P_IRQ_VIC1(8) +#define IRQ_DMA0 S5P_IRQ_VIC1(9) +#define IRQ_NFC S5P_IRQ_VIC1(13) +#define IRQ_SPI0 S5P_IRQ_VIC1(16) +#define IRQ_SPI1 S5P_IRQ_VIC1(17) +#define IRQ_IIC S5P_IRQ_VIC1(18) +#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) +#define IRQ_FIMGVG S5P_IRQ_VIC1(20) +#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) +#define IRQ_PMUIRQ S5P_IRQ_VIC1(23) +#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) +#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S5P_IRQ_VIC1(26) +#define IRQ_DSI S5P_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) +#define IRQ_TSI S5P_IRQ_VIC1(29) +#define IRQ_PENDN S5P_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S5P_IRQ_VIC1(31) + +/* + * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined + * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place + * after the pair of VICs. + */ + +#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) + +#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) +#define IRQ_EINT(x) S5P_EINT(x) + +/* + * Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +/* Actually, #6 and #7 are missing in the EINT_GROUP1 */ +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ +#define IRQ_EINT_GROUP8_NR (11) + +#define IRQ_EINT_GROUP_BASE S5P_EINT(16) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) + +#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) + +#endif /* __ASM_ARCH_S5P_IRQS_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p6440/include/mach/regs-irq.h new file mode 100644 index 0000000000000..a961f4beeb0c2 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-irq.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include +#include + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h new file mode 100644 index 0000000000000..5d7937dddad2a --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -0,0 +1,83 @@ +/* linux/arch/arm/plat-s5p/include/plat/irqs.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_IRQS_H +#define __ASM_PLAT_S5P_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S5P_IRQ_OFFSET (32) + +#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) + +#define S5P_VIC0_BASE S5P_IRQ(0) +#define S5P_VIC1_BASE S5P_IRQ(32) + +#define IRQ_VIC0_BASE S5P_VIC0_BASE +#define IRQ_VIC1_BASE S5P_VIC1_BASE + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S5P_UART_BASE0 (16) +#define IRQ_S5P_UART_BASE1 (20) +#define IRQ_S5P_UART_BASE2 (24) +#define IRQ_S5P_UART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) + +#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) + +/* S3C compatibilty defines */ +#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 +#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 +#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 +#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 + +/* VIC based IRQs */ + +#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) +#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) + +#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x)) + +#define IRQ_TIMER0 S5P_TIMER_IRQ(0) +#define IRQ_TIMER1 S5P_TIMER_IRQ(1) +#define IRQ_TIMER2 S5P_TIMER_IRQ(2) +#define IRQ_TIMER3 S5P_TIMER_IRQ(3) +#define IRQ_TIMER4 S5P_TIMER_IRQ(4) + +#endif /* __ASM_PLAT_S5P_IRQS_H */ diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c new file mode 100644 index 0000000000000..eada40d0847d4 --- /dev/null +++ b/arch/arm/plat-s5p/irq.c @@ -0,0 +1,73 @@ +/* arch/arm/plat-s5p/irq.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000)) +#define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32)) + +/* + * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] + * are consecutive when looking up the interrupt in the demux routines. + */ +static struct s3c_uart_irq uart_irqs[] = { + [0] = { + .regs = S5P_VA_UART0, + .base_irq = IRQ_S5P_UART_BASE0, + .parent_irq = IRQ_UART0, + }, + [1] = { + .regs = S5P_VA_UART1, + .base_irq = IRQ_S5P_UART_BASE1, + .parent_irq = IRQ_UART1, + }, + [2] = { + .regs = S5P_VA_UART2, + .base_irq = IRQ_S5P_UART_BASE2, + .parent_irq = IRQ_UART2, + }, + [3] = { + .regs = S5P_VA_UART3, + .base_irq = IRQ_S5P_UART_BASE3, + .parent_irq = IRQ_UART3, + }, +}; + +void __init s5p_init_irq(u32 *vic, u32 num_vic) +{ + int irq; + + /* initialize the VICs */ + for (irq = 0; irq < num_vic; irq++) + vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0); + + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); +} -- GitLab From 5f3545f64a44b2b2dac34141dba23d18cdf40a92 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:15:39 +0900 Subject: [PATCH 065/370] ARM: S5P6440: Add Timer support This patch adds timer support for S5P6440 CPU. Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- .../arm/mach-s5p6440/include/mach/pwm-clock.h | 62 +++++++++++++++++++ arch/arm/mach-s5p6440/include/mach/tick.h | 24 +++++++ 2 files changed, 86 insertions(+) create mode 100644 arch/arm/mach-s5p6440/include/mach/pwm-clock.h create mode 100644 arch/arm/mach-s5p6440/include/mach/tick.h diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h new file mode 100644 index 0000000000000..c4bb7c5554777 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h @@ -0,0 +1,62 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - pwm clock and timer support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @cfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C2410_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << (1 + tcfg1); +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 0; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div) - 1; +} + +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p6440/include/mach/tick.h new file mode 100644 index 0000000000000..0815aeb4f2cf7 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/tick.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/tick.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Timer tick support definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(S5P_VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_TICK_H */ -- GitLab From c4ffccddd54b669cc9683f2c69e31035e916a1a0 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:19:36 +0900 Subject: [PATCH 066/370] ARM: S5P6440: Add new Kconfig and Makefiles This patch adds the Kconfig and Makefile for the new S5P6440 machine and platform directories. It also updates arch/arm Kconfig and Makefiles to include the support for the new S5P6440 CPU. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 13 +++++++++- arch/arm/Makefile | 2 ++ arch/arm/mach-s5p6440/Kconfig | 23 +++++++++++++++++ arch/arm/mach-s5p6440/Makefile | 19 +++++++++++++++ arch/arm/mach-s5p6440/Makefile.boot | 2 ++ arch/arm/plat-s5p/Kconfig | 38 +++++++++++++++++++++++++++++ arch/arm/plat-s5p/Makefile | 24 ++++++++++++++++++ 7 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-s5p6440/Kconfig create mode 100644 arch/arm/mach-s5p6440/Makefile create mode 100644 arch/arm/mach-s5p6440/Makefile.boot create mode 100644 arch/arm/plat-s5p/Kconfig create mode 100644 arch/arm/plat-s5p/Makefile diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c2238cd474c78..3bc5169f0f822 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -633,6 +633,14 @@ config ARCH_S3C64XX help Samsung S3C64XX series based systems +config ARCH_S5P6440 + bool "Samsung S5P6440" + select CPU_V6 + select GENERIC_GPIO + select HAVE_CLK + help + Samsung S5P6440 CPU based systems + config ARCH_S5PC1XX bool "Samsung S5PC1XX" select GENERIC_GPIO @@ -778,6 +786,7 @@ source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" +source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" if ARCH_S3C2410 @@ -794,6 +803,8 @@ source "arch/arm/mach-s3c6400/Kconfig" source "arch/arm/mach-s3c6410/Kconfig" endif +source "arch/arm/mach-s5p6440/Kconfig" + source "arch/arm/plat-stmp3xxx/Kconfig" if ARCH_S5PC1XX @@ -1074,7 +1085,7 @@ source kernel/Kconfig.preempt config HZ int default 128 if ARCH_L7200 - default 200 if ARCH_EBSA110 || ARCH_S3C2410 + default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default 100 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e9da08483b3cd..bbcd512ccf7e0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -161,6 +161,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 +machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark @@ -184,6 +185,7 @@ plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung +plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig new file mode 100644 index 0000000000000..3aa246244dcf4 --- /dev/null +++ b/arch/arm/mach-s5p6440/Kconfig @@ -0,0 +1,23 @@ +# arch/arm/mach-s5p6440/Kconfig +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +if ARCH_S5P6440 + +config CPU_S5P6440 + bool + select CPU_S5P6440_INIT + select CPU_S5P6440_CLOCK + help + Enable S5P6440 CPU support + +config MACH_SMDK6440 + bool "SMDK6440" + select CPU_S5P6440 + help + Machine support for the Samsung SMDK6440 + +endif diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile new file mode 100644 index 0000000000000..a3ffda96e87b1 --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile @@ -0,0 +1,19 @@ +# arch/arm/mach-s5p6440/Makefile +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S5P6440 system + +obj-$(CONFIG_CPU_S5P6440) += cpu.o + +# machine support + +obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p6440/Makefile.boot new file mode 100644 index 0000000000000..ff90aa13bd674 --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig new file mode 100644 index 0000000000000..7e08b40644143 --- /dev/null +++ b/arch/arm/plat-s5p/Kconfig @@ -0,0 +1,38 @@ +# arch/arm/plat-s5p/Kconfig +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +config PLAT_S5P + bool + depends on ARCH_S5P6440 + default y + select PLAT_S3C + select ARM_VIC + select NO_IOPORT + select ARCH_REQUIRE_GPIOLIB + select S3C_GPIO_TRACK + select PLAT_SAMSUNG + select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_IRQ_UART + help + Base platform code for Samsung's S5P series SoC. + +if (PLAT_S5P && ARCH_S5P6440) + +# Configuration options shared by all S5P64XX implementations + +config CPU_S5P6440_INIT + bool + help + Initialisation code for the S5P6440. + +config CPU_S5P6440_CLOCK + bool + help + Clock support code for the S5P6440. + +endif diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile new file mode 100644 index 0000000000000..92b6474505423 --- /dev/null +++ b/arch/arm/plat-s5p/Makefile @@ -0,0 +1,24 @@ +# arch/arm/plat-s5p/Makefile +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := dummy.o +obj- := + +# Core files + +obj-y += dev-uart.o +obj-y += cpu.o +obj-y += clock.o +obj-y += irq.o +obj-y += setup-i2c0.o + +# CPU support + +obj-$(CONFIG_CPU_S5P6440_INIT) += s5p6440-init.o +obj-$(CONFIG_CPU_S5P6440_CLOCK) += s5p6440-clock.o -- GitLab From d25168ea9308e19c7000f0c997eedec87c5d6298 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:22:00 +0900 Subject: [PATCH 067/370] ARM: S5P6440: Add Board support file This patch adds Samsung's SMDK6440 board support file. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/mach-smdk6440.c | 111 ++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 arch/arm/mach-s5p6440/mach-smdk6440.c diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c new file mode 100644 index 0000000000000..760ea5424a785 --- /dev/null +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -0,0 +1,111 @@ +/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S3C2440_UFCON_TXTRIG16 | \ + S3C2410_UFCON_RXTRIG8) + +static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, +}; + +static struct platform_device *smdk6440_devices[] __initdata = { +}; + +static void __init smdk6440_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_SYS_ID); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); +} + +static void __init smdk6440_machine_init(void) +{ + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); +} + +MACHINE_START(SMDK6440, "SMDK6440") + /* Maintainer: Kukjin Kim */ + .phys_io = S5P_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S5P_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + + .init_irq = s5p6440_init_irq, + .map_io = smdk6440_map_io, + .init_machine = smdk6440_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END -- GitLab From 62a6156e88b2e89eafed30aefc97ff4979393c1c Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:23:04 +0900 Subject: [PATCH 068/370] ARM: S5P6440: Add configuration file This patch adds Samsung's S5P6440 default configuration file. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/configs/s5p6440_defconfig | 969 +++++++++++++++++++++++++++++ 1 file changed, 969 insertions(+) create mode 100644 arch/arm/configs/s5p6440_defconfig diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig new file mode 100644 index 0000000000000..279a15e53114c --- /dev/null +++ b/arch/arm/configs/s5p6440_defconfig @@ -0,0 +1,969 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc2 +# Sat Jan 9 16:33:55 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +CONFIG_ARCH_S5P6440=y +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SAMSUNG=y +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_PLAT_S3C=y + +# +# Boot options +# +CONFIG_S3C_BOOT_ERROR_RESET=y +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y + +# +# Power management +# +CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +CONFIG_PLAT_S5P=y +CONFIG_CPU_S5P6440_INIT=y +CONFIG_CPU_S5P6440_CLOCK=y +CONFIG_CPU_S5P6440=y +CONFIG_MACH_SMDK6440=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S5P6440=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set +CONFIG_DEBUG_S3C_UART=1 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y -- GitLab From 501dae90b3ae4dd3d8efdacfcb072c3d65eb5a33 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:23:53 +0900 Subject: [PATCH 069/370] ARM: S5P6440: Add serial port support This patch adds UART serial port support for S5P6440 CPU. Most of the serial support of Samsung's 6400 CPU is reused for 6440 CPU. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/devs.h | 1 + arch/arm/plat-s5p/dev-uart.c | 165 ++++++++++++++++++++++++++ drivers/serial/Kconfig | 8 +- 3 files changed, 170 insertions(+), 4 deletions(-) create mode 100644 arch/arm/plat-s5p/dev-uart.c diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index c1c20b023917e..8a4153b49f40b 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -18,6 +18,7 @@ struct s3c24xx_uart_resources { extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; +extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c new file mode 100644 index 0000000000000..af726f47385ee --- /dev/null +++ b/arch/arm/plat-s5p/dev-uart.c @@ -0,0 +1,165 @@ +/* linux/arch/arm/plat-s5p/dev-uart.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P UART resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + + /* Serial port registrations */ + +static struct resource s5p_uart0_resource[] = { + [0] = { + .start = S5P_PA_UART0, + .end = S5P_PA_UART0 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX0, + .end = IRQ_S5P_UART_RX0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX0, + .end = IRQ_S5P_UART_TX0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR0, + .end = IRQ_S5P_UART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s5p_uart1_resource[] = { + [0] = { + .start = S5P_PA_UART1, + .end = S5P_PA_UART1 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX1, + .end = IRQ_S5P_UART_RX1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX1, + .end = IRQ_S5P_UART_TX1, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR1, + .end = IRQ_S5P_UART_ERR1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart2_resource[] = { + [0] = { + .start = S5P_PA_UART2, + .end = S5P_PA_UART2 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX2, + .end = IRQ_S5P_UART_RX2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX2, + .end = IRQ_S5P_UART_TX2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR2, + .end = IRQ_S5P_UART_ERR2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart3_resource[] = { + [0] = { + .start = S5P_PA_UART3, + .end = S5P_PA_UART3 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX3, + .end = IRQ_S5P_UART_RX3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX3, + .end = IRQ_S5P_UART_TX3, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR3, + .end = IRQ_S5P_UART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { + [0] = { + .resources = s5p_uart0_resource, + .nr_resources = ARRAY_SIZE(s5p_uart0_resource), + }, + [1] = { + .resources = s5p_uart1_resource, + .nr_resources = ARRAY_SIZE(s5p_uart1_resource), + }, + [2] = { + .resources = s5p_uart2_resource, + .nr_resources = ARRAY_SIZE(s5p_uart2_resource), + }, + [3] = { + .resources = s5p_uart3_resource, + .nr_resources = ARRAY_SIZE(s5p_uart3_resource), + }, +}; + +/* uart devices */ + +static struct platform_device s5p_uart_device0 = { + .id = 0, +}; + +static struct platform_device s5p_uart_device1 = { + .id = 1, +}; + +static struct platform_device s5p_uart_device2 = { + .id = 2, +}; + +static struct platform_device s5p_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { + &s5p_uart_device0, + &s5p_uart_device1, + &s5p_uart_device2, + &s5p_uart_device3, +}; + +struct platform_device *s3c24xx_uart_devs[4] = { +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9ff47db0b2ced..d7d687f0d201b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 default 3 help Select the number of available UART ports for the Samsung S3C @@ -526,11 +526,11 @@ config SERIAL_S3C24A0 Serial port support for the Samsung S3C24A0 SoC config SERIAL_S3C6400 - tristate "Samsung S3C6400/S3C6410 Serial port support" - depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410) + tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) default y help - Serial port support for the Samsung S3C6400 and S3C6410 + Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 SoCs config SERIAL_S5PC100 -- GitLab From b813248c614b07642adbf1d7b577d0466003b339 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 23 Nov 2009 00:13:39 +0000 Subject: [PATCH 070/370] ARM: S3C: Rename s3c_device_usb to s3c_device_ohci Prepare for the forthcoming device changes by renaming s3c_device_usb to s3c_device_ohci as this is what the device represents. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/mach-amlm5900.c | 2 +- arch/arm/mach-s3c2410/mach-bast.c | 2 +- arch/arm/mach-s3c2410/mach-h1940.c | 2 +- arch/arm/mach-s3c2410/mach-n30.c | 2 +- arch/arm/mach-s3c2410/mach-otom.c | 2 +- arch/arm/mach-s3c2410/mach-qt2410.c | 2 +- arch/arm/mach-s3c2410/mach-smdk2410.c | 2 +- arch/arm/mach-s3c2410/mach-tct_hammer.c | 2 +- arch/arm/mach-s3c2410/mach-vr1000.c | 2 +- arch/arm/mach-s3c2410/usb-simtec.c | 2 +- arch/arm/mach-s3c2412/mach-jive.c | 2 +- arch/arm/mach-s3c2412/mach-smdk2413.c | 2 +- arch/arm/mach-s3c2412/mach-vstms.c | 2 +- arch/arm/mach-s3c2440/mach-anubis.c | 2 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 2 +- arch/arm/mach-s3c2440/mach-mini2440.c | 2 +- arch/arm/mach-s3c2440/mach-nexcoder.c | 2 +- arch/arm/mach-s3c2440/mach-rx3715.c | 2 +- arch/arm/mach-s3c2440/mach-smdk2440.c | 2 +- arch/arm/mach-s3c2442/mach-gta02.c | 4 ++-- arch/arm/mach-s3c6410/mach-hmt.c | 2 +- arch/arm/mach-s3c6410/mach-smdk6410.c | 2 +- arch/arm/plat-s3c/include/plat/devs.h | 2 +- arch/arm/plat-samsung/dev-usb.c | 4 ++-- 24 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 06a84adfb13fe..7047317ed7f42 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -153,7 +153,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { &s3c_device_adc, &s3c_device_wdt, &s3c_device_i2c0, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_usbgadget, &s3c_device_sdi, diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 97162fdd05906..02b1b6220cbac 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -584,7 +584,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = { // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 static struct platform_device *bast_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 1e34abe1a19e8..3f9217d0abf7d 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -272,7 +272,7 @@ static struct platform_device h1940_lcd_powerdev = { static struct platform_device *h1940_devices[] __initdata = { &s3c_device_ts, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 0405712c22634..684710f881427 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -322,7 +322,7 @@ static struct platform_device *n30_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_usbgadget, &n30_button_device, &n30_blue_led, diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index f6c7261a4a12b..d8c7f2efc1a7b 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -92,7 +92,7 @@ static struct platform_device otom_device_nor = { /* Standard OTOM devices */ static struct platform_device *otom11_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index ab092bcda393a..92a4ec375d82a 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -246,7 +246,7 @@ static struct platform_device qt2410_spi = { /* Board devices */ static struct platform_device *qt2410_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index c49126ccb1d59..452223042201a 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -87,7 +87,7 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = { }; static struct platform_device *smdk2410_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c index 8fdb0430bd480..929164a8e9b14 100644 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c @@ -129,7 +129,7 @@ static struct platform_device *tct_hammer_devices[] __initdata = { &s3c_device_adc, &s3c_device_wdt, &s3c_device_i2c0, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_usbgadget, &s3c_device_sdi, diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 0d61fb5771706..9051f0d311239 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -334,7 +334,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = { /* devices for this board */ static struct platform_device *vr1000_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 6b9d0d83a6f90..199bb4ffe689d 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -127,6 +127,6 @@ int usb_simtec_init(void) gpio_direction_output(S3C2410_GPB(4), 1); gpio_direction_input(S3C2410_GPG(10)); - s3c_device_usb.dev.platform_data = &usb_simtec_info; + s3c_device_ohci.dev.platform_data = &usb_simtec_info; return 0; } diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index c9fa3fca486c7..14f4798291aa6 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -468,7 +468,7 @@ static struct i2c_board_info jive_i2c_devs[] __initdata = { /* The platform devices being used. */ static struct platform_device *jive_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 9a5e43419722e..437c087eb71b4 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -104,7 +104,7 @@ static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = { static struct platform_device *smdk2413_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, //&s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index a6ba591b26bb3..3ca9265b69971 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -121,7 +121,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = { }; static struct platform_device *vstms_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 62a4c3eba97f1..b73f78a9da5cf 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -409,7 +409,7 @@ static struct platform_device anubis_device_sm501 = { /* Standard Anubis devices */ static struct platform_device *anubis_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_adc, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index aa69290e04c6a..0defde6de38f8 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -203,7 +203,7 @@ static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { }; static struct platform_device *at2440evb_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_adc, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 2068e9096a434..347eb6d53fc35 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -506,7 +506,7 @@ static struct i2c_board_info mini2440_i2c_devs[] __initdata = { }; static struct platform_device *mini2440_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, /* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index d43edede590e9..86a243b3e37d9 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -106,7 +106,7 @@ static struct platform_device nexcoder_device_nor = { /* Standard Nexcoder devices */ static struct platform_device *nexcoder_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index a952a13afb1f9..1e836e506f8b7 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -176,7 +176,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = { }; static struct platform_device *rx3715_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index ec13e748ccc59..df3e9a3be82fd 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -150,7 +150,7 @@ static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = { }; static struct platform_device *smdk2440_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index 0b4a3a03071f2..825800bf5506e 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -565,7 +565,7 @@ static void __init gta02_map_io(void) /* These are the guys that don't need to be children of PMU. */ static struct platform_device *gta02_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_sdi, &s3c_device_usbgadget, @@ -623,7 +623,7 @@ static void __init gta02_machine_init(void) INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); #endif - s3c_device_usb.dev.platform_data = >a02_usb_info; + s3c_device_ohci.dev.platform_data = >a02_usb_info; s3c24xx_udc_set_platdata(>a02_udc_cfg); s3c_nand_set_platdata(>a02_nand_info); diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c index cdd4b5378552a..284886c26a285 100644 --- a/arch/arm/mach-s3c6410/mach-hmt.c +++ b/arch/arm/mach-s3c6410/mach-hmt.c @@ -233,7 +233,7 @@ static struct platform_device *hmt_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_nand, &s3c_device_fb, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_timer[1], &hmt_backlight_device, &hmt_leds_device, diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 8969fe73b83ff..e2811fca00a5f 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -235,7 +235,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_fb, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_usb_hsotg, #ifdef CONFIG_REGULATOR diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 8a4153b49f40b..543a351bce786 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -34,7 +34,7 @@ extern struct platform_device s3c64xx_device_pcm1; extern struct platform_device s3c_device_ts; extern struct platform_device s3c_device_fb; -extern struct platform_device s3c_device_usb; +extern struct platform_device s3c_device_ohci; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c index 2ee85abed6d9a..431ae5dfd3fb7 100644 --- a/arch/arm/plat-samsung/dev-usb.c +++ b/arch/arm/plat-samsung/dev-usb.c @@ -36,7 +36,7 @@ static struct resource s3c_usb_resource[] = { static u64 s3c_device_usb_dmamask = 0xffffffffUL; -struct platform_device s3c_device_usb = { +struct platform_device s3c_device_ohci = { .name = "s3c2410-ohci", .id = -1, .num_resources = ARRAY_SIZE(s3c_usb_resource), @@ -47,4 +47,4 @@ struct platform_device s3c_device_usb = { } }; -EXPORT_SYMBOL(s3c_device_usb); +EXPORT_SYMBOL(s3c_device_ohci); -- GitLab From 0f61628e37e121b7786bff2653fc25a321e82ec4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 29 Nov 2009 14:34:56 +0000 Subject: [PATCH 071/370] ARM: S3C2412: Fixup commented out device in SMDK2413 The SMDK2413 has a commented out device that does not have any setup data for it, so remove it for now. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2412/mach-smdk2413.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 437c087eb71b4..0392065af1af8 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -105,7 +105,6 @@ static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = { static struct platform_device *smdk2413_devices[] __initdata = { &s3c_device_ohci, - //&s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, -- GitLab From 206090913d0d6ad3506e3e2693a696fc1626993e Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Tue, 12 Jan 2010 01:40:14 +0100 Subject: [PATCH 072/370] ARM: S3C64XX: Add S3C64XX RTC platform driver Add S3C64XX RTC platform driver Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 1 + arch/arm/plat-s3c64xx/Makefile | 1 + arch/arm/plat-s3c64xx/dev-rtc.c | 43 ++++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 arch/arm/plat-s3c64xx/dev-rtc.c diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index d4cd3abe3cba7..0552716d6bb2a 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -42,6 +42,7 @@ #define S3C64XX_PA_FB (0x77100000) #define S3C64XX_PA_USB_HSOTG (0x7C000000) #define S3C64XX_PA_WATCHDOG (0x7E004000) +#define S3C64XX_PA_RTC (0x7E005000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_AC97 (0x7F001000) #define S3C64XX_PA_IIS0 (0x7F002000) diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index b85b4359e935f..e66dbd7ce9d68 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -13,6 +13,7 @@ obj- := # Core files obj-y += dev-uart.o +obj-y += dev-rtc.o obj-y += cpu.o obj-y += irq.o obj-y += irq-eint.o diff --git a/arch/arm/plat-s3c64xx/dev-rtc.c b/arch/arm/plat-s3c64xx/dev-rtc.c new file mode 100644 index 0000000000000..b9e7a05f0129c --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-rtc.c @@ -0,0 +1,43 @@ +/* linux/arch/arm/plat-s3c64xx/dev-rtc.c + * + * Copyright 2009 by Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include + +static struct resource s3c_rtc_resource[] = { + [0] = { + .start = S3C64XX_PA_RTC, + .end = S3C64XX_PA_RTC + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTC_TIC, + .end = IRQ_RTC_TIC, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device s3c_device_rtc = { + .name = "s3c64xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, +}; +EXPORT_SYMBOL(s3c_device_rtc); -- GitLab From 71269364a8d5ea42ecc6cbc7b687e5d45cbabe0e Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Wed, 6 Jan 2010 15:33:44 +0900 Subject: [PATCH 073/370] ARM: S3C64XX: Add I2S resources in platform code Define resources needed by the I2S drivers in platform code. Audio cfg_gpio callback and IORESOURCE_DMA are added. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/dev-audio.c | 91 ++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index a21a88fbb7e33..cdba3a77ea192 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c @@ -3,7 +3,6 @@ * Copyright 2009 Wolfson Microelectronics * Mark Brown * - * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -20,16 +19,69 @@ #include #include +#include #include #include +#include #include +static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK); + s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI); + s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0); + break; + case 1: + s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK); + s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); + s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0); + default: + printk(KERN_DEBUG "Invalid I2S Controller number!"); + return -EINVAL; + } + + return 0; +} + +static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S0_V40_DO); + s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S1_V40_DO); + s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S2_V40_DO); + s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); + + return 0; +} + static struct resource s3c64xx_iis0_resource[] = { [0] = { .start = S3C64XX_PA_IIS0, .end = S3C64XX_PA_IIS0 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_I2S0_OUT, + .end = DMACH_I2S0_OUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_IN, + .end = DMACH_I2S0_IN, + .flags = IORESOURCE_DMA, + }, +}; + +struct s3c_audio_pdata s3c_i2s0_pdata = { + .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; struct platform_device s3c64xx_device_iis0 = { @@ -37,6 +89,9 @@ struct platform_device s3c64xx_device_iis0 = { .id = 0, .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), .resource = s3c64xx_iis0_resource, + .dev = { + .platform_data = &s3c_i2s0_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iis0); @@ -46,6 +101,20 @@ static struct resource s3c64xx_iis1_resource[] = { .end = S3C64XX_PA_IIS1 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_I2S1_OUT, + .end = DMACH_I2S1_OUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_IN, + .end = DMACH_I2S1_IN, + .flags = IORESOURCE_DMA, + }, +}; + +struct s3c_audio_pdata s3c_i2s1_pdata = { + .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; struct platform_device s3c64xx_device_iis1 = { @@ -53,6 +122,9 @@ struct platform_device s3c64xx_device_iis1 = { .id = 1, .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), .resource = s3c64xx_iis1_resource, + .dev = { + .platform_data = &s3c_i2s1_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iis1); @@ -62,6 +134,20 @@ static struct resource s3c64xx_iisv4_resource[] = { .end = S3C64XX_PA_IISV4 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_HSI_I2SV40_TX, + .end = DMACH_HSI_I2SV40_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_HSI_I2SV40_RX, + .end = DMACH_HSI_I2SV40_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct s3c_audio_pdata s3c_i2sv4_pdata = { + .cfg_gpio = s3c64xx_i2sv4_cfg_gpio, }; struct platform_device s3c64xx_device_iisv4 = { @@ -69,6 +155,9 @@ struct platform_device s3c64xx_device_iisv4 = { .id = -1, .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), .resource = s3c64xx_iisv4_resource, + .dev = { + .platform_data = &s3c_i2sv4_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iisv4); -- GitLab From 3929e1e76d9116856a4c7a00fcce0539dd8507a0 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Thu, 14 Jan 2010 00:30:31 +0100 Subject: [PATCH 074/370] ARM: SAMSUNG: Move S3C24XX ADC driver to plat-samsung Move S3C24XX ADC driver to plat-samsung Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/configs/mini2440_defconfig | 2 +- arch/arm/configs/s3c2410_defconfig | 2 +- arch/arm/plat-s3c24xx/Kconfig | 7 ------- arch/arm/plat-s3c24xx/Makefile | 1 - arch/arm/plat-samsung/Kconfig | 9 +++++++++ arch/arm/plat-samsung/Makefile | 4 ++++ arch/arm/{plat-s3c24xx => plat-samsung}/adc.c | 4 ++-- arch/arm/{plat-s3c => plat-samsung}/include/plat/adc.h | 4 ++-- 8 files changed, 19 insertions(+), 14 deletions(-) rename arch/arm/{plat-s3c24xx => plat-samsung}/adc.c (99%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/adc.h (92%) diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index d2a90eb844a9d..4c46644b6f18d 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -184,7 +184,7 @@ CONFIG_S3C24XX_PWM=y CONFIG_S3C24XX_GPIO_EXTRA=0 CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set -CONFIG_S3C24XX_ADC=y +CONFIG_S3C_ADC=y CONFIG_PLAT_S3C=y CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y CONFIG_CPU_LLSERIAL_S3C2440=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 2f10dae027963..9697e97677ecc 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -187,7 +187,7 @@ CONFIG_S3C24XX_GPIO_EXTRA128=y CONFIG_PM_SIMTEC=y CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set -CONFIG_S3C24XX_ADC=y +CONFIG_S3C_ADC=y CONFIG_MACH_SMDK=y CONFIG_PLAT_S3C=y CONFIG_CPU_LLSERIAL_S3C2410=y diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 342647eb91d8d..a806f359ceb67 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -117,13 +117,6 @@ config S3C2410_DMA_DEBUG Enable debugging output for the DMA code. This option sends info to the kernel log, at priority KERN_DEBUG. -config S3C24XX_ADC - bool "ADC common driver support" - help - Core support for the ADC block found in the S3C24XX SoC systems - for drivers such as the touchscreen and hwmon to use to share - this resource. - # SPI default pin configuration code config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 5dee8c12e8b43..e0100266d0393 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o obj-$(CONFIG_S3C2410_DMA) += dma.o -obj-$(CONFIG_S3C24XX_ADC) += adc.o obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index faec4b8c626c8..e6c122967355e 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -74,6 +74,15 @@ config SAMSUNG_GPIO_EXTRA provides. This allows expanding the GPIO space for use with GPIO expanders. +# ADC driver + +config S3C_ADC + bool "ADC common driver support" + help + Core support for the ADC block found in the Samsung SoC systems + for drivers such as the touchscreen and hwmon to use to share + this resource. + # device definitions to compile in config S3C_DEV_HSMMC diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index aeb7e12d1f637..ee310384b90fb 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -20,6 +20,10 @@ obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o +# ADC + +obj-$(CONFIG_S3C_ADC) += adc.o + # devices obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-samsung/adc.c similarity index 99% rename from arch/arm/plat-s3c24xx/adc.c rename to arch/arm/plat-samsung/adc.c index ce47627f3368f..a8843dd5e1e7b 100644 --- a/arch/arm/plat-s3c24xx/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -1,10 +1,10 @@ -/* arch/arm/plat-s3c24xx/adc.c +/* arch/arm/plat-samsung/adc.c * * Copyright (c) 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks , * - * S3C24XX ADC device core + * Samsung ADC device core * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h similarity index 92% rename from arch/arm/plat-s3c/include/plat/adc.h rename to arch/arm/plat-samsung/include/plat/adc.h index 5f3b1cd53b908..e8382c7be10b9 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -1,10 +1,10 @@ -/* arch/arm/plat-s3c/include/plat/adc.h +/* arch/arm/plat-samsung/include/plat/adc.h * * Copyright (c) 2008 Simtec Electronics * http://armlinux.simnte.co.uk/ * Ben Dooks * - * S3C24XX ADC driver information + * S3C ADC driver information * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as -- GitLab From bcedfa98d97e02e95bb023ab93675dbe63c508ef Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Thu, 14 Jan 2010 00:30:34 +0100 Subject: [PATCH 075/370] ARM: S3C64XX: Add S3C64XX support to the generic Samsung ADC driver Add S3C64XX support to the generic Samsung ADC driver Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 1 + arch/arm/plat-s3c/include/plat/regs-adc.h | 3 ++ arch/arm/plat-s3c64xx/Makefile | 4 ++ arch/arm/plat-s3c64xx/dev-adc.c | 46 +++++++++++++++++++++++ arch/arm/plat-samsung/adc.c | 27 ++++++++++++- 5 files changed, 79 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-s3c64xx/dev-adc.c diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index d4cd3abe3cba7..5a35f24fcb80e 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -42,6 +42,7 @@ #define S3C64XX_PA_FB (0x77100000) #define S3C64XX_PA_USB_HSOTG (0x7C000000) #define S3C64XX_PA_WATCHDOG (0x7E004000) +#define S3C64XX_PA_ADC (0x7E00B000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_AC97 (0x7F001000) #define S3C64XX_PA_IIS0 (0x7F002000) diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-s3c/include/plat/regs-adc.h index 4323cccc86cd9..f43c8dab39e4c 100644 --- a/arch/arm/plat-s3c/include/plat/regs-adc.h +++ b/arch/arm/plat-s3c/include/plat/regs-adc.h @@ -19,6 +19,9 @@ #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) +#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) +#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) +#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) /* ADCCON Register Bits */ diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index b85b4359e935f..80600176cf2ac 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -35,6 +35,10 @@ obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_S3C64XX_DMA) += dma.o +# ADC support + +obj-$(CONFIG_S3C_ADC) += dev-adc.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o diff --git a/arch/arm/plat-s3c64xx/dev-adc.c b/arch/arm/plat-s3c64xx/dev-adc.c new file mode 100644 index 0000000000000..fafef9b6bcfa4 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-adc.c @@ -0,0 +1,46 @@ +/* linux/arch/arm/plat-s3c64xx/dev-adc.c + * + * Copyright 2010 Maurus Cuelenaere + * + * S3C64xx series device definition for ADC device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +static struct resource s3c_adc_resource[] = { + [0] = { + .start = S3C64XX_PA_ADC, + .end = S3C64XX_PA_ADC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_ADC, + .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_adc = { + .name = "s3c64xx-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index a8843dd5e1e7b..120b7902fc2fd 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -37,6 +37,11 @@ * action is required. */ +enum s3c_cpu_type { + TYPE_S3C24XX, + TYPE_S3C64XX +}; + struct s3c_adc_client { struct platform_device *pdev; struct list_head pend; @@ -262,7 +267,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) if (!client) { dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); - return IRQ_HANDLED; + goto exit; } data0 = readl(adc->regs + S3C2410_ADCDAT0); @@ -289,6 +294,11 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) local_irq_restore(flags); } +exit: + if (platform_get_device_id(client->pdev)->driver_data == TYPE_S3C64XX) { + /* Clear ADC interrupt */ + writel(0, adc->regs + S3C64XX_ADCCLRINT); + } return IRQ_HANDLED; } @@ -410,9 +420,22 @@ static int s3c_adc_resume(struct platform_device *pdev) #define s3c_adc_resume NULL #endif +static struct platform_device_id s3c_adc_driver_ids[] = { + { + .name = "s3c24xx-adc", + .driver_data = TYPE_S3C24XX, + }, { + .name = "s3c64xx-adc", + .driver_data = TYPE_S3C64XX, + }, + { } +}; +MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); + static struct platform_driver s3c_adc_driver = { + .id_table = s3c_adc_driver_ids, .driver = { - .name = "s3c24xx-adc", + .name = "s3c-adc", .owner = THIS_MODULE, }, .probe = s3c_adc_probe, -- GitLab From a7c9194cdc9a858bbf5a4cdae289e28dea149aeb Mon Sep 17 00:00:00 2001 From: Andy Green Date: Tue, 29 Dec 2009 14:40:23 +0000 Subject: [PATCH 076/370] ARM: S3C64XX: Add SROM register definitions This introduces a platform file for s3c64xx that defines the SROM unit registers that control chip select characteristics. Signed-off-by: Andy Green Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 12 ++++ .../arm/plat-s3c64xx/include/plat/regs-srom.h | 59 +++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 arch/arm/plat-s3c64xx/include/plat/regs-srom.h diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index c33810ed21b35..0d6044090566a 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -17,6 +17,18 @@ #include +/* + * Post-mux Chip Select Regions Xm0CSn_ + * These may be used by SROM, NAND or CF depending on settings + */ + +#define S3C64XX_PA_XM0CSN0 (0x10000000) +#define S3C64XX_PA_XM0CSN1 (0x18000000) +#define S3C64XX_PA_XM0CSN2 (0x20000000) +#define S3C64XX_PA_XM0CSN3 (0x28000000) +#define S3C64XX_PA_XM0CSN4 (0x30000000) +#define S3C64XX_PA_XM0CSN5 (0x38000000) + /* HSMMC units */ #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h new file mode 100644 index 0000000000000..756731b36297c --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h @@ -0,0 +1,59 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h + * + * Copyright 2009 Andy Green + * + * S3C64XX SROM definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_SROM_H +#define __PLAT_REGS_SROM_H __FILE__ + +#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) + +#define S3C64XX_SROM_BW S3C64XX_SROMREG(0) +#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) +#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) +#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) +#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) +#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) +#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) + +/* + * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 + */ + +#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 +#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 +#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 +#define S3C64XX_SROM_BW__CS_MASK 0xf + +#define S3C64XX_SROM_BW__NCS0__SHIFT 0 +#define S3C64XX_SROM_BW__NCS1__SHIFT 4 +#define S3C64XX_SROM_BW__NCS2__SHIFT 8 +#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc +#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 + +/* + * applies to same to BCS0 - BCS4 + */ + +#define S3C64XX_SROM_BCX__PMC__SHIFT 0 +#define S3C64XX_SROM_BCX__PMC__MASK 3 +#define S3C64XX_SROM_BCX__TACP__SHIFT 4 +#define S3C64XX_SROM_BCX__TACP__MASK 0xf +#define S3C64XX_SROM_BCX__TCAH__SHIFT 8 +#define S3C64XX_SROM_BCX__TCAH__MASK 0xf +#define S3C64XX_SROM_BCX__TCOH__SHIFT 12 +#define S3C64XX_SROM_BCX__TCOH__MASK 0xf +#define S3C64XX_SROM_BCX__TACC__SHIFT 16 +#define S3C64XX_SROM_BCX__TACC__MASK 0x1f +#define S3C64XX_SROM_BCX__TCOS__SHIFT 24 +#define S3C64XX_SROM_BCX__TCOS__MASK 0xf +#define S3C64XX_SROM_BCX__TACS__SHIFT 28 +#define S3C64XX_SROM_BCX__TACS__MASK 0xf + +#endif /* _PLAT_REGS_SROM_H */ -- GitLab From f01fdac005d44e6c36af5b5eb841c4804570f0ad Mon Sep 17 00:00:00 2001 From: Andy Green Date: Tue, 29 Dec 2009 14:40:36 +0000 Subject: [PATCH 077/370] ARM: SMDK6410: Add nC1 chipselect SROM setup Since the mach-smdk6410.c file claims it can start up the smsc9115 ethernet device on the board, it should take care about configuring the necessary chip select nCS1 so it can see the chip. The select defaults to 8-bit mode so without config the Ethernet doesn't work. This patch uses the new SROM definitions to set nCS1 to the state found in the Samsung U-Boot port for 6410. It may be more conservative that it needs to be since those settings were marked as for CS8900A also using this chip select. But this change is enough to get the ethernet working when booted with Qi. Signed-off-by: Andy Green Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6410/mach-smdk6410.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 8969fe73b83ff..e7bae539af430 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -156,8 +157,8 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { static struct resource smdk6410_smsc911x_resources[] = { [0] = { - .start = 0x18000000, - .end = 0x18000000 + SZ_64K - 1, + .start = S3C64XX_PA_XM0CSN1, + .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -430,10 +431,32 @@ static void __init smdk6410_map_io(void) static void __init smdk6410_machine_init(void) { + u32 cs1; + s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); s3c_fb_set_platdata(&smdk6410_lcd_pdata); + /* configure nCS1 width to 16 bits */ + + cs1 = __raw_readl(S3C64XX_SROM_BW) & + ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | + (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << + S3C64XX_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S3C64XX_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + + __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | + (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | + (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | + (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | + (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); + gpio_request(S3C64XX_GPN(5), "LCD power"); gpio_request(S3C64XX_GPF(13), "LCD power"); gpio_request(S3C64XX_GPF(15), "LCD power"); -- GitLab From 810f613c03a1614c71a2b27859e91ae155bd659f Mon Sep 17 00:00:00 2001 From: Andy Green Date: Tue, 29 Dec 2009 14:40:30 +0000 Subject: [PATCH 078/370] ARM: S3C64XX: Add virtual mapping for S3C64XX SROM area This adds the physical address of the SROM unit, and applies a virtual mapping for it to the S3C_VA_MEM slot. Signed-off-by: Andy Green Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 2 ++ arch/arm/plat-s3c64xx/cpu.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 0d6044090566a..3e17adf3a89ba 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -50,6 +50,8 @@ #define S3C_VA_UART2 S3C_VA_UARTx(2) #define S3C_VA_UART3 S3C_VA_UARTx(3) +#define S3C64XX_PA_SROM (0x70000000) + #define S3C64XX_PA_NAND (0x70200000) #define S3C64XX_PA_FB (0x77100000) #define S3C64XX_PA_USB_HSOTG (0x7C000000) diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index c0e6f2a45154a..bc7ca1812e32d 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -72,6 +72,11 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_MEM, + .pfn = __phys_to_pfn(S3C64XX_PA_SROM), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), .pfn = __phys_to_pfn(S3C_PA_UART), -- GitLab From a4e946947b966d018f3f712d5c7ca2932c2aadd2 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Tue, 29 Dec 2009 14:40:43 +0000 Subject: [PATCH 079/370] ARM: SMDK6410: Add comments on ethernet connectivity LAN9115 Ethernet only works on SMDK6410 if certain switches are set in specific ways. Document the requirement. Signed-off-by: Andy Green Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6410/mach-smdk6410.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index e7bae539af430..eb5de981c094e 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -155,6 +155,16 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, }; +/* + * Configuring Ethernet on SMDK6410 + * + * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6. + * The constant address below corresponds to nCS1 + * + * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet" + * 2) CFG6 needs to be switched to "LAN9115" side + */ + static struct resource smdk6410_smsc911x_resources[] = { [0] = { .start = S3C64XX_PA_XM0CSN1, -- GitLab From a0de298a0eee7f9004a8e512c12c7b40d66c9934 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 13:24:01 +0900 Subject: [PATCH 080/370] ARM: S5PC1XX: Register pd0 and hd0 clocks, remove unecessary dummy_enable The clk_hd0 and clk_pd0 where given a local dummy_enable call due to not being registered with the clock code, which they really should have been. Register these two clocks and remove the clk_dummy_enable as this is done by the default clock registration code. Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/clock.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index aec0305174aa1..387f23190c3c9 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -64,18 +64,12 @@ struct clk clk_54m = { .rate = 54000000, }; -static int clk_dummy_enable(struct clk *clk, int enable) -{ - return 0; -} - struct clk clk_hd0 = { .name = "hclkd0", .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, - .enable = clk_dummy_enable, .ops = &clk_ops_def_setrate, }; @@ -86,7 +80,6 @@ struct clk clk_pd0 = { .parent = NULL, .ctrlbit = 0, .ops = &clk_ops_def_setrate, - .enable = clk_dummy_enable, }; static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) @@ -680,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = { static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, + &clk_pd0, + &clk_hd0, &clk_27m, &clk_48m, &clk_54m, -- GitLab From b8792dbff6ed93c5a77f71917d4a0c5efa12eee1 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 18 Jan 2010 14:30:16 +0900 Subject: [PATCH 081/370] ARM: SAMSUNG: Add check to ensure that clksrc_clk does have multiple clock sources Adds a additional check in s3c_set_clksrc function to ensure that the clksrc_clk does have a choice of multiple clock sources. In addition to this, a check is added to ensure that a parent is assigned to the clksrc_clk in case it does not have a choice of parent clocks. Signed-off-by: Thomas Abraham Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock-clksrc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 33c633a8be8de..98c6b8859f493 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -129,11 +129,16 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce) { struct clksrc_sources *srcs = clk->sources; u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); - u32 clksrc = 0; + u32 clksrc; - if (clk->reg_src.reg) - clksrc = __raw_readl(clk->reg_src.reg); + if (!clk->reg_src.reg) { + if (!clk->clk.parent) + printk(KERN_ERR "%s: no parent clock specified\n", + clk->clk.name); + return; + } + clksrc = __raw_readl(clk->reg_src.reg); clksrc &= mask; clksrc >>= clk->reg_src.shift; -- GitLab From f3b464cca94c4a8f54fbc11ec5af8b143fd1750b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 15:37:25 +0900 Subject: [PATCH 082/370] ARM: SAMSUNG: Fix clksrc-clk's checks for bad register settings The WARN_ON() was only checking the first clock in the array, instead of being executed for each clksrc clock being registered. Since this is an array of clocks, WARN_ON() does not provide a lot of useful information about the problem, so change to using printk(KERN_ERR) to report the problem to the console. As a note, we still try and register the clock even if these problems are present just in case and to avoid changing the behaviour of the registration process. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock-clksrc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 98c6b8859f493..656c70e0400a0 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -177,9 +177,11 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) { int ret; - WARN_ON(!clksrc->reg_div.reg && !clksrc->reg_src.reg); - for (; size > 0; size--, clksrc++) { + if (!clksrc->reg_div.reg && !clksrc->reg_src.reg) + printk(KERN_ERR "%s: clock %s has no registers set\n", + __func__, clksrc->clk.name); + /* fill in the default functions */ if (!clksrc->clk.ops) { -- GitLab From f9e011b6b305d38445bbd4a1e7a8814e056de37b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 15:57:42 +0900 Subject: [PATCH 083/370] ARM: SAMSUNG: Fix bug in clksrc-clk round_rate call. The call has been assuming all clksrc-clks' divider size is 4 bits, but this may not be the case anymore. Use the reg_div.size parameter to calculate the maximum value it can take and check against that. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock-clksrc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 656c70e0400a0..ae8b8507663f5 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -60,7 +60,7 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) rate = clk_round_rate(clk, rate); div = clk_get_rate(clk->parent) / rate; - if (div > 16) + if (div > (1 << sclk->reg_div.size)) return -EINVAL; val = __raw_readl(reg); @@ -102,7 +102,9 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) static unsigned long s3c_roundrate_clksrc(struct clk *clk, unsigned long rate) { + struct clksrc_clk *sclk = to_clksrc(clk); unsigned long parent_rate = clk_get_rate(clk->parent); + int max_div = 1 << sclk->reg_div.size; int div; if (rate >= parent_rate) @@ -114,8 +116,8 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk, if (div == 0) div = 1; - if (div > 16) - div = 16; + if (div > max_div) + div = max_div; rate = parent_rate / div; } -- GitLab From 10f9f743f661d200a7a0006e65688cf28c2f01d9 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 18 Jan 2010 16:15:07 +0900 Subject: [PATCH 084/370] ARM: S3C64XX: SPI: Add SPI controller register base Added SPI controller register base. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 3e17adf3a89ba..801c1c0f3a951 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -64,6 +64,8 @@ #define S3C64XX_PA_IIS1 (0x7F003000) #define S3C64XX_PA_TIMER (0x7F006000) #define S3C64XX_PA_IIC0 (0x7F004000) +#define S3C64XX_PA_SPI0 (0x7F00B000) +#define S3C64XX_PA_SPI1 (0x7F00C000) #define S3C64XX_PA_PCM0 (0x7F009000) #define S3C64XX_PA_PCM1 (0x7F00A000) #define S3C64XX_PA_IISV4 (0x7F00D000) -- GitLab From 87315a802a8aab9d986858fcf2230726c1b5c598 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 18 Jan 2010 16:15:08 +0900 Subject: [PATCH 085/370] ARM: S3C64XX: SPI: Define SPI-48M clock sources Defined special 48MHz clock sources for SPI-0,1. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/clock.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index ae5883c00e7ad..2989c3a2e94d3 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -140,6 +140,18 @@ static struct clk init_clocks_disable[] = { .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, + }, { + .name = "spi_48m", + .id = 0, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, + }, { + .name = "spi_48m", + .id = 1, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, }, { .name = "48m", .id = 0, -- GitLab From 398ccccb770e6ed3e138925404f0746cbe57c5a1 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 18 Jan 2010 17:45:52 +0900 Subject: [PATCH 086/370] ARM: S3C64XX: SPI: Header for passing platform data We need a way to pass controller specific information to the SPI driver. For that purpose new headers are made. SPI Controller is assumed 'type-s3c64xx' and can be defined for newer SoCs. Hence, that part is placed under plat-samsung to be shared across newer SoCs. SoC specific part - spi source clocks, will be placed under plat-/include/plat/ Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- .../plat-s3c64xx/include/plat/spi-clocks.h | 18 +++++ .../plat-samsung/include/plat/s3c64xx-spi.h | 67 +++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/arm/plat-s3c64xx/include/plat/spi-clocks.h create mode 100644 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h new file mode 100644 index 0000000000000..524bdae3f6255 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S3C64XX_PLAT_SPI_CLKS_H +#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ + +#define S3C64XX_SPI_SRCCLK_PCLK 0 +#define S3C64XX_SPI_SRCCLK_SPIBUS 1 +#define S3C64XX_SPI_SRCCLK_48M 2 + +#endif /* __S3C64XX_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h new file mode 100644 index 0000000000000..d177241493156 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -0,0 +1,67 @@ +/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S3C64XX_PLAT_SPI_H +#define __S3C64XX_PLAT_SPI_H + +/** + * struct s3c64xx_spi_csinfo - ChipSelect description + * @fb_delay: Slave specific feedback delay. + * Refer to FB_CLK_SEL register definition in SPI chapter. + * @line: Custom 'identity' of the CS line. + * @set_level: CS line control. + * + * This is per SPI-Slave Chipselect information. + * Allocate and initialize one in machine init code and make the + * spi_board_info.controller_data point to it. + */ +struct s3c64xx_spi_csinfo { + u8 fb_delay; + unsigned line; + void (*set_level)(unsigned line_id, int lvl); +}; + +/** + * struct s3c64xx_spi_info - SPI Controller defining structure + * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. + * @src_clk_name: Platform name of the corresponding clock. + * @num_cs: Number of CS this controller emulates. + * @cfg_gpio: Configure pins for this SPI controller. + * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 + * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number + * @high_speed: If the controller supports HIGH_SPEED_EN bit + */ +struct s3c64xx_spi_info { + int src_clk_nr; + char *src_clk_name; + + int num_cs; + + int (*cfg_gpio)(struct platform_device *pdev); + + /* Following two fields are for future compatibility */ + int fifo_lvl_mask; + int rx_lvl_offset; + int high_speed; +}; + +/** + * s3c64xx_spi_set_info - SPI Controller configure callback by the board + * initialization code. + * @cntrlr: SPI controller number the configuration is for. + * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. + * @num_cs: Number of elements in the 'cs' array. + * + * Call this from machine init code for each SPI Controller that + * has some chips attached to it. + */ +extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); + +#endif /* __S3C64XX_PLAT_SPI_H */ -- GitLab From 6a2b4111643127a28944d673995810a82582c5a1 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 18 Jan 2010 17:32:02 +0900 Subject: [PATCH 087/370] ARM: S3C64XX: SPI: Define SPI controller devices Platform devices for SPI Controller of S3C64XX are defined and exported for machines to include. Also, controller setup helper functions are defined for machine code to set runtime configuration of the controller and the bus. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/devs.h | 3 + arch/arm/plat-s3c64xx/Makefile | 1 + arch/arm/plat-s3c64xx/dev-spi.c | 180 ++++++++++++++++++++++++++ 3 files changed, 184 insertions(+) create mode 100644 arch/arm/plat-s3c64xx/dev-spi.c diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 8a4153b49f40b..f4a7e57bab2bd 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -29,6 +29,9 @@ extern struct platform_device s3c64xx_device_iis0; extern struct platform_device s3c64xx_device_iis1; extern struct platform_device s3c64xx_device_iisv4; +extern struct platform_device s3c64xx_device_spi0; +extern struct platform_device s3c64xx_device_spi1; + extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index b241f3695560f..80255a5e17891 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o +obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c new file mode 100644 index 0000000000000..6b6d7af066242 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-spi.c @@ -0,0 +1,180 @@ +/* linux/arch/arm/plat-s3c64xx/dev-spi.c + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +static char *spi_src_clks[] = { + [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", + [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus", + [S3C64XX_SPI_SRCCLK_48M] = "spi_48m", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0); + s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO); + s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO); + s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP); + break; + + case 1: + s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1); + s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1); + s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1); + s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s3c64xx_spi0_resource[] = { + [0] = { + .start = S3C64XX_PA_SPI0, + .end = S3C64XX_PA_SPI0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { + .cfg_gpio = s3c64xx_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s3c64xx_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), + .resource = s3c64xx_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c64xx_spi0_pdata, + }, +}; +EXPORT_SYMBOL(s3c64xx_device_spi0); + +static struct resource s3c64xx_spi1_resource[] = { + [0] = { + .start = S3C64XX_PA_SPI1, + .end = S3C64XX_PA_SPI1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI1_TX, + .end = DMACH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI1_RX, + .end = DMACH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { + .cfg_gpio = s3c64xx_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, +}; + +struct platform_device s3c64xx_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), + .resource = s3c64xx_spi1_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c64xx_spi1_pdata, + }, +}; +EXPORT_SYMBOL(s3c64xx_device_spi1); + +void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + s3c64xx_spi0_pdata.num_cs = num_cs; + s3c64xx_spi0_pdata.src_clk_nr = src_clk_nr; + s3c64xx_spi0_pdata.src_clk_name = spi_src_clks[src_clk_nr]; + break; + case 1: + s3c64xx_spi1_pdata.num_cs = num_cs; + s3c64xx_spi1_pdata.src_clk_nr = src_clk_nr; + s3c64xx_spi1_pdata.src_clk_name = spi_src_clks[src_clk_nr]; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } +} -- GitLab From 0a6361316d6493b9dcbdda9a6a4586c3ccbfd008 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 12 Jan 2010 15:15:28 +0900 Subject: [PATCH 088/370] ARM: SAMSUNG: Make UART device code common Move s3c24xx_uart_devs, s3c24xx_uart_src and the platform devices to a common entry in plat-samsung since they are the same in all the current implementations. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/devs.c | 28 -------------------- arch/arm/plat-s3c64xx/dev-uart.c | 29 --------------------- arch/arm/plat-s5p/dev-uart.c | 28 -------------------- arch/arm/plat-s5pc1xx/dev-uart.c | 29 --------------------- arch/arm/plat-samsung/Makefile | 1 + arch/arm/plat-samsung/dev-uart.c | 44 ++++++++++++++++++++++++++++++++ 6 files changed, 45 insertions(+), 114 deletions(-) create mode 100644 arch/arm/plat-samsung/dev-uart.c diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 7f686a31e6723..38c358c14aa20 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -112,34 +112,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { }, }; -/* yart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - /* LCD Controller */ static struct resource s3c_lcd_resource[] = { diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c index 62c11a6fc7ba3..f797f748b9990 100644 --- a/arch/arm/plat-s3c64xx/dev-uart.c +++ b/arch/arm/plat-s3c64xx/dev-uart.c @@ -145,32 +145,3 @@ struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), }, }; - -/* uart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c index af726f47385ee..23c75316d4917 100644 --- a/arch/arm/plat-s5p/dev-uart.c +++ b/arch/arm/plat-s5p/dev-uart.c @@ -135,31 +135,3 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { .nr_resources = ARRAY_SIZE(s5p_uart3_resource), }, }; - -/* uart devices */ - -static struct platform_device s5p_uart_device0 = { - .id = 0, -}; - -static struct platform_device s5p_uart_device1 = { - .id = 1, -}; - -static struct platform_device s5p_uart_device2 = { - .id = 2, -}; - -static struct platform_device s5p_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s5p_uart_device0, - &s5p_uart_device1, - &s5p_uart_device2, - &s5p_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c index f749bc5407b54..586c95c60bfe8 100644 --- a/arch/arm/plat-s5pc1xx/dev-uart.c +++ b/arch/arm/plat-s5pc1xx/dev-uart.c @@ -143,32 +143,3 @@ struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), }, }; - -/* uart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index aeb7e12d1f637..f834e42d95daf 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o +obj-y += dev-uart.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c new file mode 100644 index 0000000000000..3776cd9524501 --- /dev/null +++ b/arch/arm/plat-samsung/dev-uart.c @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-samsung/dev-uart.c + * originally from arch/arm/plat-s3c24xx/devs.c + *x + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Base S3C24XX platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include + +/* uart devices */ + +static struct platform_device s3c24xx_uart_device0 = { + .id = 0, +}; + +static struct platform_device s3c24xx_uart_device1 = { + .id = 1, +}; + +static struct platform_device s3c24xx_uart_device2 = { + .id = 2, +}; + +static struct platform_device s3c24xx_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { + &s3c24xx_uart_device0, + &s3c24xx_uart_device1, + &s3c24xx_uart_device2, + &s3c24xx_uart_device3, +}; + +struct platform_device *s3c24xx_uart_devs[4] = { +}; -- GitLab From f126752043c67003de6d34b14160f87ba0323c98 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 Jan 2010 14:59:46 +0900 Subject: [PATCH 089/370] ARM: SAMSUNG: Add platform data registration for OHCI Add a platform data helper for the OHCI device Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/usb-simtec.c | 4 ++-- arch/arm/mach-s3c2442/mach-gta02.c | 5 ++--- arch/arm/plat-s3c/include/plat/usb-control.h | 2 ++ arch/arm/plat-samsung/dev-usb.c | 21 +++++++++++++++++++- 4 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 199bb4ffe689d..29bd3d987bec8 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -91,7 +91,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) } } -static struct s3c2410_hcd_info usb_simtec_info = { +static struct s3c2410_hcd_info usb_simtec_info __initdata = { .port[0] = { .flags = S3C_HCDFLG_USED }, @@ -127,6 +127,6 @@ int usb_simtec_init(void) gpio_direction_output(S3C2410_GPB(4), 1); gpio_direction_input(S3C2410_GPG(10)); - s3c_device_ohci.dev.platform_data = &usb_simtec_info; + s3c_ohci_set_platdata(&usb_simtec_info); return 0; } diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index 825800bf5506e..45799c608d8f0 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -544,7 +544,7 @@ static struct platform_device gta02_bl_dev = { /* USB */ -static struct s3c2410_hcd_info gta02_usb_info = { +static struct s3c2410_hcd_info gta02_usb_info __initdata = { .port[0] = { .flags = S3C_HCDFLG_USED, }, @@ -623,9 +623,8 @@ static void __init gta02_machine_init(void) INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); #endif - s3c_device_ohci.dev.platform_data = >a02_usb_info; - s3c24xx_udc_set_platdata(>a02_udc_cfg); + s3c_ohci_set_platdata(>a02_usb_info); s3c_nand_set_platdata(>a02_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/plat-s3c/include/plat/usb-control.h b/arch/arm/plat-s3c/include/plat/usb-control.h index 822c87fe948eb..a6a57bf796bd3 100644 --- a/arch/arm/plat-s3c/include/plat/usb-control.h +++ b/arch/arm/plat-s3c/include/plat/usb-control.h @@ -38,4 +38,6 @@ static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int port } } +extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info); + #endif /*__ASM_ARCH_USBCONTROL_H */ diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c index 431ae5dfd3fb7..88165657fa536 100644 --- a/arch/arm/plat-samsung/dev-usb.c +++ b/arch/arm/plat-samsung/dev-usb.c @@ -19,7 +19,7 @@ #include #include - +#include static struct resource s3c_usb_resource[] = { [0] = { @@ -48,3 +48,22 @@ struct platform_device s3c_device_ohci = { }; EXPORT_SYMBOL(s3c_device_ohci); + +/** + * s3c_ohci_set_platdata - initialise OHCI device platform data + * @info: The platform data. + * + * This call copies the @info passed in and sets the device .platform_data + * field to that copy. The @info is copied so that the original can be marked + * __initdata. + */ +void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) +{ + struct s3c2410_hcd_info *npd; + + npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_ohci.dev.platform_data = npd; +} -- GitLab From 3cd2fff59fc924752611301f4ca7e8484f5744a5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 15 Jan 2010 15:09:20 +0900 Subject: [PATCH 090/370] ARM: MINI2440: Remove commented out devices from device array There's no point in having these in until there is proper support for them, so remove as they only confuse the device changing script. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-mini2440.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 347eb6d53fc35..65ea3b5ee4fd1 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -508,7 +508,6 @@ static struct i2c_board_info mini2440_i2c_devs[] __initdata = { static struct platform_device *mini2440_devices[] __initdata = { &s3c_device_ohci, &s3c_device_wdt, -/* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_usbgadget, @@ -522,8 +521,6 @@ static struct platform_device *mini2440_devices[] __initdata = { &s3c_device_sdi, &s3c_device_iis, &mini2440_audio, -/* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ - /* remaining devices are optional */ }; static void __init mini2440_map_io(void) -- GitLab From 22c810ab3e25d16e6f128384d107b933b6fd8fff Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 16:24:22 +0900 Subject: [PATCH 091/370] ARM: S3C24XX: Add mci platform data set call s3c24xx_mci_set_platdata(). Add a s3c24xx_mci_set_platdata() call for all the machine files that have platform data for the MCI driver. This brings the MCI device into line with the other devices with __initdata and a specific call to ensure the right structure type is being passed. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/mach-h1940.c | 5 ++--- arch/arm/mach-s3c2440/mach-at2440evb.c | 5 ++--- arch/arm/mach-s3c2440/mach-mini2440.c | 3 +-- arch/arm/plat-s3c24xx/devs.c | 13 +++++++++++++ arch/arm/plat-s3c24xx/include/plat/mci.h | 9 +++++++++ 5 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 3f9217d0abf7d..fbedd07609417 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -196,7 +196,7 @@ static struct platform_device h1940_device_bluetooth = { .id = -1, }; -static struct s3c24xx_mci_pdata h1940_mmc_cfg = { +static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { .gpio_detect = S3C2410_GPF(5), .gpio_wprotect = S3C2410_GPH(8), .set_power = NULL, @@ -311,12 +311,11 @@ static void __init h1940_init(void) u32 tmp; s3c24xx_fb_set_platdata(&h1940_fb_info); + s3c24xx_mci_set_platdata(&h1940_mmc_cfg); s3c24xx_udc_set_platdata(&h1940_udc_cfg); s3c24xx_ts_set_platdata(&h1940_ts_cfg); s3c_i2c0_set_platdata(NULL); - s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg; - /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 0defde6de38f8..84725791e6bfe 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -165,7 +165,7 @@ static struct platform_device at2440evb_device_eth = { }, }; -static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { +static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = { .gpio_detect = S3C2410_GPG(10), }; @@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = { static void __init at2440evb_map_io(void) { - s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; - s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); @@ -226,6 +224,7 @@ static void __init at2440evb_map_io(void) static void __init at2440evb_init(void) { s3c24xx_fb_set_platdata(&at2440evb_fb_info); + s3c24xx_mci_set_platdata(&at2440evb_mci_pdata); s3c_nand_set_platdata(&at2440evb_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 65ea3b5ee4fd1..571b17683d96f 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -528,8 +528,6 @@ static void __init mini2440_map_io(void) s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); - - s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; } /* @@ -675,6 +673,7 @@ static void __init mini2440_init(void) } s3c24xx_udc_set_platdata(&mini2440_udc_cfg); + s3c24xx_mci_set_platdata(&mini2440_mmc_cfg); s3c_nand_set_platdata(&mini2440_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 38c358c14aa20..986d4e5408f57 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -351,6 +352,18 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); +void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) +{ + struct s3c24xx_mci_pdata *npd; + + npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory to copy pdata", __func__); + + s3c_device_sdi.dev.platform_data = npd; +} + + /* SPI (0) */ static struct resource s3c_spi0_resource[] = { diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h index 36aaa10fad063..2ac2b21ec490b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/mci.h +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h @@ -40,4 +40,13 @@ struct s3c24xx_mci_pdata { unsigned short vdd); }; +/** + * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device + * @pdata: The platform data + * + * Copy the platform data supplied by @pdata so that this can be marked + * __initdata. + */ +extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata); + #endif /* _ARCH_NCI_H */ -- GitLab From 51fe52229e3765dc56b8d2dd5df656fbf8a20500 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 14 Jan 2010 15:05:38 +0900 Subject: [PATCH 092/370] ARM: SAMSUNG: serial: Modify console initialization. This patch modifies s3c24xx_serial_initconsole function to accept multiple platform UART information structures. This is required on platforms that have differences among the instances of UART ports. As an example, the FIFO sizes could be different for each UART instance and hence multiple platform UART information structures would be needed. This patch also modifies the s3c24xx_console_init macro since it wraps the call to the s3c24xx_serial_initconsole function. Signed-off-by: Thomas Abraham Signed-off-by: Ben Dooks --- drivers/serial/samsung.c | 6 +++--- drivers/serial/samsung.h | 19 ++++++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 52e3df113ec01..6982243736d1e 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -1374,7 +1374,7 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, * data. */ -static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) +static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info) { struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; struct platform_device **platdev_ptr; @@ -1385,7 +1385,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) platdev_ptr = s3c24xx_uart_devs; for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { - s3c24xx_serial_init_port(ptr, info, *platdev_ptr); + s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr); } return 0; @@ -1451,7 +1451,7 @@ static struct console s3c24xx_serial_console = { }; int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *info) + struct s3c24xx_uart_info **info) { struct platform_device *dev = s3c24xx_uart_devs[0]; diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index 1fb22343df423..0ac06a07d25ff 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h @@ -75,19 +75,24 @@ extern int s3c24xx_serial_probe(struct platform_device *dev, extern int __devexit s3c24xx_serial_remove(struct platform_device *dev); extern int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *uart); + struct s3c24xx_uart_info **uart); extern int s3c24xx_serial_init(struct platform_driver *drv, struct s3c24xx_uart_info *info); #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE -#define s3c24xx_console_init(__drv, __inf) \ -static int __init s3c_serial_console_init(void) \ -{ \ - return s3c24xx_serial_initconsole(__drv, __inf); \ -} \ - \ +#define s3c24xx_console_init(__drv, __inf) \ +static int __init s3c_serial_console_init(void) \ +{ \ + struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \ + int i; \ + \ + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \ + uinfo[i] = __inf; \ + return s3c24xx_serial_initconsole(__drv, uinfo); \ +} \ + \ console_initcall(s3c_serial_console_init) #else -- GitLab From 1f323cfda5feee4e9c1fc09ededaee849f906468 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 19 Jan 2010 15:30:54 +0900 Subject: [PATCH 093/370] ARM: SAMSUNG: Move GPIO common functions to plat-samsung This patch moves GPIO common functions (from plat-s3c64xx) into plat-samsung. and adds the config option to build the plat-samsung/gpiolib for Samsung SoCs. Signed-off-by: Adityapratap Sharma Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/gpio-core.h | 28 +++ arch/arm/plat-s3c64xx/Kconfig | 1 + arch/arm/plat-s3c64xx/gpiolib.c | 162 +---------------- arch/arm/plat-samsung/Kconfig | 7 + arch/arm/plat-samsung/Makefile | 1 + arch/arm/plat-samsung/gpiolib.c | 197 +++++++++++++++++++++ 6 files changed, 236 insertions(+), 160 deletions(-) create mode 100644 arch/arm/plat-samsung/gpiolib.c diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h index 32af612767aa2..94fed584d5aef 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h @@ -11,6 +11,11 @@ * published by the Free Software Foundation. */ +#define GPIOCON_OFF (0x00) +#define GPIODAT_OFF (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + /* Define the core gpiolib support functions that the s3c platforms may * need to extend or change depending on the hardware and the s3c chip * selected at build or found at run time. @@ -80,6 +85,29 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * and any other necessary functions. */ +/** + * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependant on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a seperate set of function + * (samsung_gpiolib_add_4bit2_chips)for each case. + */ +extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); +extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, + int nr_chips); + +extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); +extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); + #ifdef CONFIG_S3C_GPIO_TRACK extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 0fba1f956b8a2..37b4519fb832a 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -22,6 +22,7 @@ config PLAT_S3C64XX select S3C_GPIO_CFG_S3C64XX select S3C_DEV_NAND select USB_ARCH_HAS_OHCI + select SAMSUNG_GPIOLIB_4BIT help Base platform code for any Samsung S3C64XX device diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 778560457277c..265e23b6de8e7 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -49,150 +49,6 @@ * [2] BANK has two control registers, GPxCON0 and GPxCON1 */ -#define OFF_GPCON (0x00) -#define OFF_GPDAT (0x04) - -#define con_4bit_shift(__off) ((__off) * 4) - -#if 1 -#define gpio_dbg(x...) do { } while(0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. -*/ - -static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + OFF_GPCON); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + OFF_GPDAT); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + OFF_GPDAT); - __raw_writel(con, base + OFF_GPCON); - __raw_writel(dat, base + OFF_GPDAT); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -/* The next set of routines are for the case where the GPIO configuration - * registers are 4 bits per GPIO but there is more than one register (the - * bank has more than 8 GPIOs. - * - * This case is the similar to the 4 bit case, but the registers are as - * follows: - * - * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x08: Data register, 1 bit per gpio - * bit n: data bit n - * - * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we - * store the 'base + 0x4' address so that these routines see the data - * register at ourchip->base + 0x04. -*/ - -static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); - - return 0; - -} - -static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + OFF_GPDAT); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + OFF_GPDAT); - __raw_writel(con, regcon); - __raw_writel(dat, base + OFF_GPDAT); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -399,20 +255,6 @@ static struct s3c_gpio_chip gpio_2bit[] = { }, }; -static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; - chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; - chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) { chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); @@ -432,10 +274,10 @@ static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, static __init int s3c64xx_gpiolib_init(void) { s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), - s3c64xx_gpiolib_add_4bit); + samsung_gpiolib_add_4bit); s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), - s3c64xx_gpiolib_add_4bit2); + samsung_gpiolib_add_4bit2); s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), s3c64xx_gpiolib_add_2bit); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index e6c122967355e..6484b5bf82c3e 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -33,6 +33,13 @@ config SAMSUNG_IRQ_UART # options for gpio configuration support +config SAMSUNG_GPIOLIB_4BIT + bool + help + GPIOlib file contains the 4 bit modification functions for gpio + configuration. GPIOlib shall be compiled only for S3C64XX and S5P + series of processors. + config S3C_GPIO_CFG_S3C24XX bool help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index ceac416d80b89..1fc8d471c6ee3 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -15,6 +15,7 @@ obj-y += clock.o obj-y += pwm-clock.o obj-y += gpio-config.o +obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c new file mode 100644 index 0000000000000..3419b67f42214 --- /dev/null +++ b/arch/arm/plat-samsung/gpiolib.c @@ -0,0 +1,197 @@ +/* arch/arm/plat-samsung/gpiolib.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * SAMSUNG - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef DEBUG_GPIO +#define gpio_dbg(x...) do { } while (0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG x) +#endif + +/* The samsung_gpiolib_4bit routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of + * the output. +*/ + +int samsung_gpiolib_4bit_input(struct gpio_chip *chip, unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + GPIOCON_OFF); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +int samsung_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, base + GPIOCON_OFF); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* The next set of routines are for the case where the GPIO configuration + * registers are 4 bits per GPIO but there is more than one register (the + * bank has more than 8 GPIOs. + * + * This case is the similar to the 4 bit case, but the registers are as + * follows: + * + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x08: Data register, 1 bit per gpio + * bit n: data bit n + * + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we + * store the 'base + 0x4' address so that these routines see the data + * register at ourchip->base + 0x04. +*/ + +int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); + + return 0; +} + +int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned con_offset = offset; + + if (con_offset > 7) + con_offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = samsung_gpiolib_4bit_input; + chip->chip.direction_output = samsung_gpiolib_4bit_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = samsung_gpiolib_4bit2_input; + chip->chip.direction_output = samsung_gpiolib_4bit2_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + samsung_gpiolib_add_4bit(chip); + s3c_gpiolib_add(chip); + } +} + +void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + samsung_gpiolib_add_4bit2(chip); + s3c_gpiolib_add(chip); + } +} -- GitLab From 42d828d46f526605c84ebdb5a987fd25fe09a3c9 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 19 Jan 2010 15:31:17 +0900 Subject: [PATCH 094/370] ARM: S5P6440: Add S5P6440 GPIO support This patch adds Samsung's S5P6440 GPIO support. Signed-off-by: Adityapratap Sharma Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/Makefile | 2 +- .../arm/mach-s5p6440/include/mach/regs-gpio.h | 54 +++ arch/arm/mach-s5p6440/s5p6440-gpio.c | 322 ++++++++++++++++++ arch/arm/plat-s5p/Kconfig | 4 + 4 files changed, 381 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-s5p6440/include/mach/regs-gpio.h create mode 100644 arch/arm/mach-s5p6440/s5p6440-gpio.c diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index a3ffda96e87b1..a79b13011edc1 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile @@ -12,7 +12,7 @@ obj- := # Core support for S5P6440 system -obj-$(CONFIG_CPU_S5P6440) += cpu.o +obj-$(CONFIG_CPU_S5P6440) += cpu.o s5p6440-gpio.o # machine support diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h new file mode 100644 index 0000000000000..82ff753913da7 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIO register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +#include + +/* Base addresses for each of the banks */ +#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) +#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) +#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) +#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) +#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) +#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) +#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) +#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) +#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) +#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) +#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) +#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) +#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) +#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) +#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) +#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) + +/* for LCD */ +#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) +#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) + +/* These set of macros are not really useful for the + * GPF/GPI/GPJ/GPN/GPP, + * useful for others set of GPIO's (4 bit) + */ +#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) + * */ +#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5p6440/s5p6440-gpio.c b/arch/arm/mach-s5p6440/s5p6440-gpio.c new file mode 100644 index 0000000000000..742264c29f2a5 --- /dev/null +++ b/arch/arm/mach-s5p6440/s5p6440-gpio.c @@ -0,0 +1,322 @@ +/* arch/arm/mach-s5p6440/s5p6440-gpio.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GPIO bank summary: +* +* Bank GPIOs Style SlpCon ExtInt Group +* A 6 4Bit Yes 1 +* B 7 4Bit Yes 1 +* C 8 4Bit Yes 2 +* F 2 2Bit Yes 4 [1] +* G 7 4Bit Yes 5 +* H 10 4Bit[2] Yes 6 +* I 16 2Bit Yes None +* J 12 2Bit Yes None +* N 16 2Bit No IRQ_EINT +* P 8 2Bit Yes 8 +* R 15 4Bit[2] Yes 8 +* +* [1] BANKF pins 14,15 do not form part of the external interrupt sources +* [2] BANK has two control registers, GPxCON0 and GPxCON1 +*/ + +static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + switch (offset) { + case 6: + offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + offset -= 7; + break; + } + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + return 0; +} + +static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned con_offset = offset; + + switch (con_offset) { + case 6: + con_offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + con_offset -= 7; + break; + } + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + return 0; +} + +int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift; + u32 con; + + switch (off) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + shift = (off & 7) * 4; + reg -= 4; + break; + case 6: + shift = ((off + 1) & 7) * 4; + reg -= 4; + default: + shift = ((off + 1) & 7) * 4; + break; + } + + if (s3c_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0xf << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { + { + .cfg_eint = 0, + }, { + .cfg_eint = 7, + }, { + .cfg_eint = 3, + .set_config = s5p6440_gpio_setcfg_4bit_rbank, + }, { + .cfg_eint = 0, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, { + .cfg_eint = 2, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { + { + .base = S5P6440_GPA_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPA(0), + .ngpio = S5P6440_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S5P6440_GPB_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPB(0), + .ngpio = S5P6440_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S5P6440_GPC_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPC(0), + .ngpio = S5P6440_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5P6440_GPG_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPG(0), + .ngpio = S5P6440_GPIO_G_NR, + .label = "GPG", + }, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { + { + .base = S5P6440_GPH_BASE + 0x4, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPH(0), + .ngpio = S5P6440_GPIO_H_NR, + .label = "GPH", + }, + }, +}; + +static struct s3c_gpio_chip gpio_rbank_4bit2[] = { + { + .base = S5P6440_GPR_BASE + 0x4, + .config = &s5p6440_gpio_cfgs[2], + .chip = { + .base = S5P6440_GPR(0), + .ngpio = S5P6440_GPIO_R_NR, + .label = "GPR", + }, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { + { + .base = S5P6440_GPF_BASE, + .config = &s5p6440_gpio_cfgs[5], + .chip = { + .base = S5P6440_GPF(0), + .ngpio = S5P6440_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P6440_GPI_BASE, + .config = &s5p6440_gpio_cfgs[3], + .chip = { + .base = S5P6440_GPI(0), + .ngpio = S5P6440_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P6440_GPJ_BASE, + .config = &s5p6440_gpio_cfgs[3], + .chip = { + .base = S5P6440_GPJ(0), + .ngpio = S5P6440_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P6440_GPN_BASE, + .config = &s5p6440_gpio_cfgs[4], + .chip = { + .base = S5P6440_GPN(0), + .ngpio = S5P6440_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P6440_GPP_BASE, + .config = &s5p6440_gpio_cfgs[5], + .chip = { + .base = S5P6440_GPP(0), + .ngpio = S5P6440_GPIO_P_NR, + .label = "GPP", + }, + }, +}; + +void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chipcfg++) { + if (!chipcfg->set_config) + chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; + if (!chipcfg->set_pull) + chipcfg->set_pull = s3c_gpio_setpull_updown; + if (!chipcfg->get_pull) + chipcfg->get_pull = s3c_gpio_getpull_updown; + } +} + +static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; + chip->chip.direction_output = + s5p6440_gpiolib_rbank_4bit2_output; + s3c_gpiolib_add(chip); + } +} + +static int __init s5p6440_gpiolib_init(void) +{ + struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; + int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); + + s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, + ARRAY_SIZE(s5p6440_gpio_cfgs)); + + for (; nr_chips > 0; nr_chips--, chips++) + s3c_gpiolib_add(chips); + + samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, + ARRAY_SIZE(s5p6440_gpio_4bit)); + + samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, + ARRAY_SIZE(s5p6440_gpio_4bit2)); + + s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, + ARRAY_SIZE(gpio_rbank_4bit2)); + + return 0; +} +arch_initcall(s5p6440_gpiolib_init); diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 7e08b40644143..e7c31e7060e58 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -14,6 +14,10 @@ config PLAT_S5P select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK + select SAMSUNG_GPIOLIB_4BIT + select S3C_GPIO_CFG_S3C64XX + select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX select PLAT_SAMSUNG select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER -- GitLab From 67866fb38680d85cbd13c7bb468fb89f16e026d1 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 10:47:45 +0900 Subject: [PATCH 095/370] ARM: SAMSUNG: Move pm-gpio into plat-samsung Move the pm-gpio code into plat-samsung. Note, this should be changed later to properly compile the 4bit code if the 4bit settings are enabled. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 1 - arch/arm/plat-samsung/Makefile | 4 ++++ arch/arm/{plat-s3c => plat-samsung}/pm-gpio.c | 0 3 files changed, 4 insertions(+), 1 deletion(-) rename arch/arm/{plat-s3c => plat-samsung}/pm-gpio.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index ea4a001f67935..ac12ba526f776 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_S3C_DMA) += dma.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o # PWM support diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 1fc8d471c6ee3..94fe6ea362be2 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -37,3 +37,7 @@ obj-y += dev-uart.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o + +# PM support + +obj-$(CONFIG_PM) += pm-gpio.o diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c similarity index 100% rename from arch/arm/plat-s3c/pm-gpio.c rename to arch/arm/plat-samsung/pm-gpio.c -- GitLab From 4f2b617aff8147338faa0d5ed7b57636076671bf Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 11:22:38 +0900 Subject: [PATCH 096/370] ARM: SAMSUNG: Move gpiolib support in gpio.c to plat-samsung Move the gpio.c code containing the core gpiolib and GPIO support to plat-samsung from plat-s3c as it is used by all current Samsung SoCs. Note, we didn't move this to gpiolib.c as it contains code that is not strictly for gpiolib support and the 4bit code is already called gpiolib.c so make the change easier by not renaming both files in one go. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 1 - arch/arm/plat-samsung/Makefile | 1 + arch/arm/{plat-s3c => plat-samsung}/gpio.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/{plat-s3c => plat-samsung}/gpio.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index ac12ba526f776..20cb335aa75b2 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -13,7 +13,6 @@ obj- := obj-y += init.o obj-y += time.o -obj-y += gpio.o # DMA support diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 94fe6ea362be2..27d5bfb60b2eb 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -13,6 +13,7 @@ obj- := obj-y += clock.o obj-y += pwm-clock.o +obj-y += gpio.o obj-y += gpio-config.o obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-samsung/gpio.c similarity index 100% rename from arch/arm/plat-s3c/gpio.c rename to arch/arm/plat-samsung/gpio.c -- GitLab From 16e2c7c59f0a4debcb110648025bef11958aa3cd Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Jan 2010 18:00:55 +0900 Subject: [PATCH 097/370] ARM: SAMSUNG: Move GPIO headers to plat-samsung Move the GPIO and GPIO configuration headers into arch/arm/plat-samsung as they are common to all the Samsung SoCs. Signed-off-by: Ben Dooks --- .../{plat-s3c => plat-samsung}/include/plat/gpio-cfg-helpers.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/gpio-cfg.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/gpio-core.h | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/gpio-cfg-helpers.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/gpio-cfg.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/gpio-core.h (100%) diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h rename to arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/gpio-cfg.h rename to arch/arm/plat-samsung/include/plat/gpio-cfg.h diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/gpio-core.h rename to arch/arm/plat-samsung/include/plat/gpio-core.h -- GitLab From e856bb1f8dfcd924a973102a244b81920752648e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 19 Jan 2010 17:14:46 +0900 Subject: [PATCH 098/370] ARM: SAMSUNG: Remove empty gpio-core.h and use central plat/gpio-core.h Rename mach-s3c2410/include/mach/gpio-core.h to mach/gpio-track.h so that it can be included by when needed. Eliminate all other empty gpio-core.h files and just include the as necessary. Signed-off-by: Ben Dooks --- .../mach/{gpio-core.h => gpio-track.h} | 1 - .../arm/mach-s3c6400/include/mach/gpio-core.h | 21 ------------------- .../arm/mach-s5p6440/include/mach/gpio-core.h | 19 ----------------- .../arm/mach-s5pc100/include/mach/gpio-core.h | 21 ------------------- arch/arm/plat-s3c24xx/gpiolib.c | 2 +- arch/arm/plat-s3c64xx/gpiolib.c | 2 +- arch/arm/plat-s5pc1xx/gpio-config.c | 2 +- arch/arm/plat-s5pc1xx/gpiolib.c | 2 +- arch/arm/plat-samsung/gpio-config.c | 2 +- arch/arm/plat-samsung/gpio.c | 2 +- .../arm/plat-samsung/include/plat/gpio-core.h | 2 ++ arch/arm/plat-samsung/pm-gpio.c | 2 +- 12 files changed, 9 insertions(+), 69 deletions(-) rename arch/arm/mach-s3c2410/include/mach/{gpio-core.h => gpio-track.h} (96%) delete mode 100644 arch/arm/mach-s3c6400/include/mach/gpio-core.h delete mode 100644 arch/arm/mach-s5p6440/include/mach/gpio-core.h delete mode 100644 arch/arm/mach-s5pc100/include/mach/gpio-core.h diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h similarity index 96% rename from arch/arm/mach-s3c2410/include/mach/gpio-core.h rename to arch/arm/mach-s3c2410/include/mach/gpio-track.h index f8b879a7973c6..acb2591038087 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h @@ -15,7 +15,6 @@ #ifndef __ASM_ARCH_GPIO_CORE_H #define __ASM_ARCH_GPIO_CORE_H __FILE__ -#include #include extern struct s3c_gpio_chip s3c24xx_gpios[]; diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h deleted file mode 100644 index d89aae68b0a50..0000000000000 --- a/arch/arm/mach-s3c6400/include/mach/gpio-core.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s3c6400/include/mach/gpio-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -/* currently we just include the platform support */ -#include - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/gpio-core.h b/arch/arm/mach-s5p6440/include/mach/gpio-core.h deleted file mode 100644 index ff7fb3094188f..0000000000000 --- a/arch/arm/mach-s5p6440/include/mach/gpio-core.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-s5p6440/include/mach/gpio-core.h - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P6440 - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -/* currently we just include the platform support */ -#include - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h deleted file mode 100644 index ad28d8ec8a781..0000000000000 --- a/arch/arm/mach-s5pc100/include/mach/gpio-core.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s5pc100/include/mach/gpio-core.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min - * - * S5PC100 - GPIO core support - * - * Based on mach-s3c6400/include/mach/gpio-core.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -/* currently we just include the platform support */ -#include - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 6d7a961d3269e..4f0f11a6a6778 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 265e23b6de8e7..b6e3f55321fa6 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -18,8 +18,8 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c index bba675df9c751..a4f67e80a150f 100644 --- a/arch/arm/plat-s5pc1xx/gpio-config.c +++ b/arch/arm/plat-s5pc1xx/gpio-config.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c index facb410e7a71c..1ffc57ac293d0 100644 --- a/arch/arm/plat-s5pc1xx/gpiolib.c +++ b/arch/arm/plat-s5pc1xx/gpiolib.c @@ -17,8 +17,8 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 456969b6fa0d6..44a84e8965468 100644 --- a/arch/arm/plat-samsung/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c index 5ff24e0f9f89c..28d2ab8a08db7 100644 --- a/arch/arm/plat-samsung/gpio.c +++ b/arch/arm/plat-samsung/gpio.c @@ -16,7 +16,7 @@ #include #include -#include +#include #ifdef CONFIG_S3C_GPIO_TRACK struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 94fed584d5aef..49ff406a7066c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -118,6 +118,8 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) #else /* machine specific code should provide s3c_gpiolib_getchip */ +#include + static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index cfd326a8b6936..69a4c7f02e253 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -19,7 +19,7 @@ #include #include -#include +#include #include /* PM GPIO helpers */ -- GitLab From af1519408a0d40f312e8f103504cd292cc49d927 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 19 Jan 2010 11:21:39 +0900 Subject: [PATCH 099/370] ARM: S5P6440: Add IO descriptor for ChipID block. This patch adds the IO descriptor for ChipID block in S5P6440. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/include/mach/map.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index b3703293cc3be..dc922d6e11ff6 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -15,6 +15,11 @@ #include +/* Chip ID */ +#define S5P6440_PA_CHIPID (0xE0000000) +#define S5P_PA_CHIPID S5P6440_PA_CHIPID +#define S5P_VA_CHIPID S3C_ADDR(0x00700000) + /* SYSCON */ #define S5P6440_PA_SYSCON (0xE0100000) #define S5P_PA_SYSCON S5P6440_PA_SYSCON -- GitLab From a0c814afcfc2c840698372bd402b669b659ee1c5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 23 Nov 2009 23:32:31 +0000 Subject: [PATCH 100/370] ARM: SAMSUNG: Add initial documentation directory and overview Start Documentation/arm/Samsung and add an initial overview file which whilst is not complete, is better than nothing. Signed-off-by: Ben Dooks --- Documentation/arm/Samsung/Overview.txt | 86 ++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/arm/Samsung/Overview.txt diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt new file mode 100644 index 0000000000000..7cced1fea9c3f --- /dev/null +++ b/Documentation/arm/Samsung/Overview.txt @@ -0,0 +1,86 @@ + Samsung ARM Linux Overview + ========================== + +Introduction +------------ + + The Samsung range of ARM SoCs spans many similar devices, from the initial + ARM9 through to the newest ARM cores. This document shows an overview of + the current kernel support, how to use it and where to find the code + that supports this. + + The currently supported SoCs are: + + - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list + - S3C64XX: S3C6400 and S3C6410 + - S5PC6440 + + S5PC100 and S5PC110 support is currently being merged + + +S3C24XX Systems +--------------- + + There is still documentation in Documnetation/arm/Samsung-S3C24XX/ which + deals with the architecture and drivers specific to these devices. + + See Documentation/arm/Samsung-S3C24XX/Overview.txt for more information + on the implementation details and specific support. + + +Configuration +------------- + + A number of configurations are supplied, as there is no current way of + unifying all the SoCs into one kernel. + + s5p6440_defconfig - S5P6440 specific default configuration + s5pc100_defconfig - S5PC100 specific default configuration + + +Layout +------ + + The directory layout is currently being restructured, and consists of + several platform directories and then the machine specific directories + of the CPUs being built for. + + plat-samsung provides the base for all the implementations, and is the + last in the line of include directories that are processed for the build + specific information. It contains the base clock, GPIO and device definitions + to get the system running. + + plat-s3c is the s3c24xx/s3c64xx platform directory, although it is currently + involved in other builds this will be phased out once the relevant code is + moved elsewhere. + + plat-s3c24xx is for s3c24xx specific builds, see the S3C24XX docs. + + plat-s3c64xx is for the s3c64xx specific bits, see the S3C24XX docs. + + plat-s5p is for s5p specific builds, more to be added. + + + [ to finish ] + + +Port Contributors +----------------- + + Ben Dooks (BJD) + Vincent Sanders + Herbert Potzl + Arnaud Patard (RTP) + Roc Wu + Klaus Fetscher + Dimitry Andric + Shannon Holland + Guillaume Gourat (NexVision) + Christer Weinigel (wingel) (Acer N30) + Lucas Correia Villa Real (S3C2400 port) + + +Document Author +--------------- + +Copyright 2009-2010 Ben Dooks -- GitLab From 6890556c140469622497bea98cf49bf93f92f922 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 20 Jan 2010 11:09:28 +0900 Subject: [PATCH 101/370] ARM: SAMSUNG: Move more support into plat-samsung Move header files which are not likely to be touched in any further support addition out of plat-s3c's include directory into plat-samsung. Signed-off-by: Ben Dooks --- arch/arm/{plat-s3c => plat-samsung}/include/plat/dma-core.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/hwmon.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/iic-core.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/iic.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/nand.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-ac97.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-adc.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-iic.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-irqtype.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-nand.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-rtc.h | 0 .../{plat-s3c => plat-samsung}/include/plat/regs-s3c2412-iis.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-sdhci.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-timer.h | 0 .../{plat-s3c => plat-samsung}/include/plat/regs-usb-hsotg-phy.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-usb-hsotg.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-watchdog.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/sdhci.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/udc-hs.h | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/watchdog-reset.h | 0 20 files changed, 0 insertions(+), 0 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/dma-core.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/hwmon.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/iic-core.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/iic.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/nand.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-ac97.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-adc.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-iic.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-irqtype.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-nand.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-rtc.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-s3c2412-iis.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-sdhci.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-timer.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-usb-hsotg-phy.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-usb-hsotg.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-watchdog.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/sdhci.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/udc-hs.h (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/watchdog-reset.h (100%) diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/dma-core.h rename to arch/arm/plat-samsung/include/plat/dma-core.h diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/hwmon.h rename to arch/arm/plat-samsung/include/plat/hwmon.h diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/iic-core.h rename to arch/arm/plat-samsung/include/plat/iic-core.h diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/iic.h rename to arch/arm/plat-samsung/include/plat/iic.h diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/nand.h rename to arch/arm/plat-samsung/include/plat/nand.h diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-ac97.h rename to arch/arm/plat-samsung/include/plat/regs-ac97.h diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-adc.h rename to arch/arm/plat-samsung/include/plat/regs-adc.h diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-iic.h rename to arch/arm/plat-samsung/include/plat/regs-iic.h diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-irqtype.h rename to arch/arm/plat-samsung/include/plat/regs-irqtype.h diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-nand.h rename to arch/arm/plat-samsung/include/plat/regs-nand.h diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-rtc.h rename to arch/arm/plat-samsung/include/plat/regs-rtc.h diff --git a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h rename to arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-sdhci.h rename to arch/arm/plat-samsung/include/plat/regs-sdhci.h diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-timer.h rename to arch/arm/plat-samsung/include/plat/regs-timer.h diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h rename to arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h rename to arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/regs-watchdog.h rename to arch/arm/plat-samsung/include/plat/regs-watchdog.h diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/sdhci.h rename to arch/arm/plat-samsung/include/plat/sdhci.h diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/udc-hs.h rename to arch/arm/plat-samsung/include/plat/udc-hs.h diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/watchdog-reset.h rename to arch/arm/plat-samsung/include/plat/watchdog-reset.h -- GitLab From 106cc6aa73f594015fc8b99f7c70d1b7cf23f19a Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 20 Jan 2010 12:22:24 +0900 Subject: [PATCH 102/370] ARM: SAMSUNG: Move pmw.c to plat-samsung Move the PWM driver support to plat-samsung, as these PWM blocks are close enough across the current range to be supported by this driver. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 4 ---- arch/arm/plat-samsung/Makefile | 4 ++++ arch/arm/{plat-s3c => plat-samsung}/pwm.c | 0 3 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/pwm.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 20cb335aa75b2..095bc97cd6ce2 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -22,7 +22,3 @@ obj-$(CONFIG_S3C_DMA) += dma.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o - -# PWM support - -obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 27d5bfb60b2eb..f31e64f3a1c30 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -42,3 +42,7 @@ obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o # PM support obj-$(CONFIG_PM) += pm-gpio.o + +# PWM support + +obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-s3c/pwm.c b/arch/arm/plat-samsung/pwm.c similarity index 100% rename from arch/arm/plat-s3c/pwm.c rename to arch/arm/plat-samsung/pwm.c -- GitLab From 8005745d6eea79da8ee2e7fe978d14e412aa3353 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 20 Jan 2010 12:29:25 +0900 Subject: [PATCH 103/370] ARM: SAMSUNG: Move pm-check.c to plat-samsung Move the pm-check.c file to plat-samsung for all Samsung SoC users, and update Kconfig names to make them SAMSUNG_ instead of S3C2410_ Sed expresions used to make the change: s/S3C2410_PM_DEBUG/SAMSUNG_PM_DEBUG/g s/S3C2410_PM_CHECK/SAMSUNG_PM_CHECK/g Signed-off-by: Ben Dooks --- arch/arm/configs/mini2440_defconfig | 4 +- arch/arm/configs/s3c2410_defconfig | 4 +- arch/arm/plat-s3c/Kconfig | 44 ------------------ arch/arm/plat-s3c/Makefile | 1 - arch/arm/plat-s3c/include/plat/pm.h | 4 +- arch/arm/plat-s3c/pm.c | 6 +-- arch/arm/plat-samsung/Kconfig | 45 +++++++++++++++++++ arch/arm/plat-samsung/Makefile | 1 + .../arm/{plat-s3c => plat-samsung}/pm-check.c | 8 ++-- 9 files changed, 59 insertions(+), 58 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/pm-check.c (95%) diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 4c46644b6f18d..ff44bd1615c04 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -199,8 +199,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y # # Power management # -# CONFIG_S3C2410_PM_DEBUG is not set -# CONFIG_S3C2410_PM_CHECK is not set +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_SAMSUNG_PM_CHECK is not set CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C_GPIO_SPACE=0 diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 9697e97677ecc..8e94c3caeb8c7 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -203,8 +203,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y # # Power management # -# CONFIG_S3C2410_PM_DEBUG is not set -# CONFIG_S3C2410_PM_CHECK is not set +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_SAMSUNG_PM_CHECK is not set CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_DEV_HSMMC=y diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 454cc39b7adc1..2367908c4f626 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -59,50 +59,6 @@ config S3C_BOOT_UART_FORCE_FIFO Say Y here to force the UART FIFOs on during the kernel uncompressor -comment "Power management" - -config S3C2410_PM_DEBUG - bool "S3C2410 PM Suspend debug" - depends on PM - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See - for more information. - -config S3C_PM_DEBUG_LED_SMDK - bool "SMDK LED suspend/resume debugging" - depends on PM && (MACH_SMDK6410) - help - Say Y here to enable the use of the SMDK LEDs on the baseboard - for debugging of the state of the suspend and resume process. - - Note, this currently only works for S3C64XX based SMDK boards. - -config S3C2410_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on PM && CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - - Note, this can take several seconds depending on memory size - and CPU speed. - - See - -config S3C2410_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on PM && S3C2410_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but wil identify any - faults with better precision. - - See config S3C_LOWLEVEL_UART_PORT int "S3C UART to use for low-level messages" diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 095bc97cd6ce2..89dbdb0adebf1 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -21,4 +21,3 @@ obj-$(CONFIG_S3C_DMA) += dma.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index 7a797192fcf35..2543bd227f2d6 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h @@ -111,7 +111,7 @@ extern int s3c24xx_irq_resume(struct sys_device *dev); /* PM debug functions */ -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG /** * s3c_pm_dbg() - low level debug function for use in suspend/resume. * @msg: The message to print. @@ -141,7 +141,7 @@ static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } /* suspend memory checking */ -#ifdef CONFIG_S3C2410_PM_CHECK +#ifdef CONFIG_SAMSUNG_PM_CHECK extern void s3c_pm_check_prepare(void); extern void s3c_pm_check_restore(void); extern void s3c_pm_check_cleanup(void); diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index 767470601e5c3..e5eef126791b3 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c @@ -41,7 +41,7 @@ unsigned long s3c_pm_flags; * resume before the console layer is available. */ -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG extern void printascii(const char *); void s3c_pm_dbg(const char *fmt, ...) @@ -65,13 +65,13 @@ static inline void s3c_pm_debug_init(void) #else #define s3c_pm_debug_init() do { } while(0) -#endif /* CONFIG_S3C2410_PM_DEBUG */ +#endif /* CONFIG_SAMSUNG_PM_DEBUG */ /* Save the UART configurations if we are configured for debug. */ unsigned char pm_uart_udivslot; -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 6484b5bf82c3e..1c2fe91c23e93 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -132,4 +132,49 @@ config S3C_DEV_NAND help Compile in platform device definition for NAND controller +comment "Power management" + +config SAMSUNG_PM_DEBUG + bool "S3C2410 PM Suspend debug" + depends on PM + help + Say Y here if you want verbose debugging from the PM Suspend and + Resume code. See + for more information. + +config S3C_PM_DEBUG_LED_SMDK + bool "SMDK LED suspend/resume debugging" + depends on PM && (MACH_SMDK6410) + help + Say Y here to enable the use of the SMDK LEDs on the baseboard + for debugging of the state of the suspend and resume process. + + Note, this currently only works for S3C64XX based SMDK boards. + +config SAMSUNG_PM_CHECK + bool "S3C2410 PM Suspend Memory CRC" + depends on PM && CRC32 + help + Enable the PM code's memory area checksum over sleep. This option + will generate CRCs of all blocks of memory, and store them before + going to sleep. The blocks are then checked on resume for any + errors. + + Note, this can take several seconds depending on memory size + and CPU speed. + + See + +config SAMSUNG_PM_CHECK_CHUNKSIZE + int "S3C2410 PM Suspend CRC Chunksize (KiB)" + depends on PM && SAMSUNG_PM_CHECK + default 64 + help + Set the chunksize in Kilobytes of the CRC for checking memory + corruption over suspend and resume. A smaller value will mean that + the CRC data block will take more memory, but wil identify any + faults with better precision. + + See + endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index f31e64f3a1c30..c8c8caec8cde0 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o # PM support obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o # PWM support diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-samsung/pm-check.c similarity index 95% rename from arch/arm/plat-s3c/pm-check.c rename to arch/arm/plat-samsung/pm-check.c index 8eb1f439861c3..0b5bb774192a5 100644 --- a/arch/arm/plat-s3c/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -20,8 +20,8 @@ #include -#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 -#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value +#if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 +#error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value #endif /* suspend checking code... @@ -29,12 +29,12 @@ * this next area does a set of crc checks over all the installed * memory, so the system can verify if the resume was ok. * - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, + * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, * increasing it will mean that the area corrupted will be less easy to spot, * and reducing the size will cause the CRC save area to grow */ -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) +#define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024) static u32 crc_size; /* size needed for the crc block */ static u32 *crcs; /* allocated over suspend/resume */ -- GitLab From 9fca878623378e7dd6da8e7135a561c17bc1112b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 19 Jan 2010 15:26:56 +0000 Subject: [PATCH 104/370] ARM: SMDK6410: Set up interrupt range for WM835x on 1190-EV1 PMIC board The WM835x driver won't actually use this yet but it will in the future when the changes converting it to genirq are merged. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6410/mach-smdk6410.c | 1 + arch/arm/plat-s3c64xx/include/plat/irqs.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 5376880cdd89d..eba345fadffeb 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -399,6 +399,7 @@ static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { .init = smdk6410_wm8350_init, .irq_high = 1, + .irq_base = IRQ_BOARD_START, }; #endif diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index 176fe15a61d60..a22758194e6d2 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -198,7 +198,11 @@ * interrupt controllers). */ #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) +#ifdef CONFIG_SMDK6410_WM1190_EV1 +#define IRQ_BOARD_NR 64 +#else #define IRQ_BOARD_NR 16 +#endif #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) -- GitLab From 1c24522c05f25b89cc4df5a875d8a005a774f570 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 20 Jan 2010 12:05:55 +0000 Subject: [PATCH 105/370] ARM: S3C64XX: Fix dev-audio build As reported when the patch was posted commit 71269364 ("ARM: S3C64XX: Add I2S resources in platform code") uses pin names for the IISv4 data output pins which are not present in mainline, causing dev-audio to fail to build. Fix this by using the defines which are actually present in the kernel source. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/dev-audio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index cdba3a77ea192..5b89344779f05 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c @@ -51,9 +51,9 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) { - s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S0_V40_DO); - s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S1_V40_DO); - s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S2_V40_DO); + s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); + s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); + s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); -- GitLab From 8dcdd6e6bb09ba1915668b45a0ee730e820d0de1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 20 Jan 2010 13:06:04 +0000 Subject: [PATCH 106/370] ARM: S3C64XX: Staticise audio platform data It's not exported. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/dev-audio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index 5b89344779f05..f6b7bfb519d7b 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c @@ -80,7 +80,7 @@ static struct resource s3c64xx_iis0_resource[] = { }, }; -struct s3c_audio_pdata s3c_i2s0_pdata = { +static struct s3c_audio_pdata s3c_i2s0_pdata = { .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; @@ -113,7 +113,7 @@ static struct resource s3c64xx_iis1_resource[] = { }, }; -struct s3c_audio_pdata s3c_i2s1_pdata = { +static struct s3c_audio_pdata s3c_i2s1_pdata = { .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; @@ -146,7 +146,7 @@ static struct resource s3c64xx_iisv4_resource[] = { }, }; -struct s3c_audio_pdata s3c_i2sv4_pdata = { +static struct s3c_audio_pdata s3c_i2sv4_pdata = { .cfg_gpio = s3c64xx_i2sv4_cfg_gpio, }; -- GitLab From 46f2b478b21bdb5bb588317c971a77df13702660 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 20 Jan 2010 13:06:05 +0000 Subject: [PATCH 107/370] ARM: SAMSUNG: Staticise gpiolib implementation functions They are not exported, they are referenced via vtables. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/gpiolib.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c index 3419b67f42214..8a8ba8bc1d963 100644 --- a/arch/arm/plat-samsung/gpiolib.c +++ b/arch/arm/plat-samsung/gpiolib.c @@ -44,7 +44,8 @@ * the output. */ -int samsung_gpiolib_4bit_input(struct gpio_chip *chip, unsigned int offset) +static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, + unsigned int offset) { struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); void __iomem *base = ourchip->base; @@ -59,8 +60,8 @@ int samsung_gpiolib_4bit_input(struct gpio_chip *chip, unsigned int offset) return 0; } -int samsung_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned int offset, int value) +static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned int offset, int value) { struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); void __iomem *base = ourchip->base; @@ -106,9 +107,10 @@ int samsung_gpiolib_4bit_output(struct gpio_chip *chip, * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we * store the 'base + 0x4' address so that these routines see the data * register at ourchip->base + 0x04. -*/ + */ -int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned int offset) +static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, + unsigned int offset) { struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); void __iomem *base = ourchip->base; @@ -129,8 +131,8 @@ int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned int offset) return 0; } -int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned int offset, int value) +static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) { struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); void __iomem *base = ourchip->base; -- GitLab From bd548e5ef21ac2ff18b262a905543d7a2340fb87 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Thu, 21 Jan 2010 01:37:28 +0100 Subject: [PATCH 108/370] ARM: S3C64XX: Fix typo in s3c-hsotg platform data ARM: S3C64XX: Fix typo in s3c-hsotg platform data Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/include/plat/udc-hs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h index dd04db0431090..a22a4f2eea944 100644 --- a/arch/arm/plat-samsung/include/plat/udc-hs.h +++ b/arch/arm/plat-samsung/include/plat/udc-hs.h @@ -12,7 +12,7 @@ * published by the Free Software Foundation. */ -enum s3c_hostg_dmamode { +enum s3c_hsotg_dmamode { S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ S3C_HSOTG_DMA_ONLY, /* always use DMA */ S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ @@ -24,6 +24,6 @@ enum s3c_hostg_dmamode { * @is_osc: The clock source is an oscillator, not a crystal */ struct s3c_hsotg_plat { - enum s3c_hostg_dmamode dma; + enum s3c_hsotg_dmamode dma; unsigned int is_osc : 1; }; -- GitLab From 75497d96b2094d325594b46d5e5f12b2396c4d51 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 21 Jan 2010 13:31:38 +0900 Subject: [PATCH 109/370] ARM: S3C64XX: Tidy up common code in s3c64xx_spi_set_info() The s3c64xx_spi_set_info() sets one of two platform data structures depending on which controller is being specified. Change to taking a pointer to the relevant platform data structure and then having one set of code to place the data into the area being pointed to. Cc: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/dev-spi.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c index 6b6d7af066242..ca10388d7ed15 100644 --- a/arch/arm/plat-s3c64xx/dev-spi.c +++ b/arch/arm/plat-s3c64xx/dev-spi.c @@ -18,6 +18,7 @@ #include #include + #include #include #include @@ -154,6 +155,8 @@ EXPORT_SYMBOL(s3c64xx_device_spi1); void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) { + struct s3c64xx_spi_info *pd; + /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { @@ -163,18 +166,18 @@ void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) switch (cntrlr) { case 0: - s3c64xx_spi0_pdata.num_cs = num_cs; - s3c64xx_spi0_pdata.src_clk_nr = src_clk_nr; - s3c64xx_spi0_pdata.src_clk_name = spi_src_clks[src_clk_nr]; + pd = &s3c64xx_spi0_pdata; break; case 1: - s3c64xx_spi1_pdata.num_cs = num_cs; - s3c64xx_spi1_pdata.src_clk_nr = src_clk_nr; - s3c64xx_spi1_pdata.src_clk_name = spi_src_clks[src_clk_nr]; + pd = &s3c64xx_spi1_pdata; break; default: printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", __func__, cntrlr); return; } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; } -- GitLab From 3a3b585aa4ecad21ae91cfa9e5f387d64a15a312 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 19 Jan 2010 11:34:58 +0900 Subject: [PATCH 110/370] ARM: S3C6400: Update s3c6400_defconfig for bigger initrds for SMDK6410 The Samsung initrd for SMDK6410 is now bigger than the original initrds that where used. Increase the command-line size and the size of the ramdisk that it is unpacked into. Also change the default init to /linuxrc to avoid problems with the current SMDK ramdisk image failing to run /bin/bash. Signed-off-by: Ben Dooks --- arch/arm/configs/s3c6400_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index f56e50fab79b1..c018435668491 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -256,7 +256,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M" +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set -- GitLab From 1725c679a08902ce04419b274d22254155ce707c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 19 Jan 2010 13:16:50 +0900 Subject: [PATCH 111/370] ARM: S3C64XX: Update s3c6400_defconfig for current kernel Update the s3c6400_defconfig with one from the current kernel which has been build and run tested on an SMDK6410. Signed-off-by: Ben Dooks --- arch/arm/configs/s3c6400_defconfig | 358 +++++++++++++++++++++-------- 1 file changed, 263 insertions(+), 95 deletions(-) diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index c018435668491..5e7d4c1b8fc1f 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -1,14 +1,11 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.28-rc3 -# Mon Nov 3 10:10:30 2008 +# Linux kernel version: 2.6.33-rc4 +# Tue Jan 19 13:12:40 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y -# CONFIG_GENERIC_TIME is not set -# CONFIG_GENERIC_CLOCKEVENTS is not set -CONFIG_MMU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -18,13 +15,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -34,13 +31,30 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_CGROUPS is not set # CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set @@ -50,8 +64,13 @@ CONFIG_NAMESPACES=y # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y @@ -62,32 +81,38 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -95,11 +120,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_BLOCK=y -CONFIG_LBD=y -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_LSF=y +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -107,33 +129,62 @@ CONFIG_LSF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -141,35 +192,62 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set CONFIG_ARCH_S3C64XX=y +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SAMSUNG=y +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +# CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_I2C1=y +CONFIG_S3C_DEV_FB=y +CONFIG_S3C_DEV_USB_HOST=y +CONFIG_S3C_DEV_USB_HSOTG=y +CONFIG_S3C_DEV_NAND=y CONFIG_PLAT_S3C64XX=y CONFIG_CPU_S3C6400_INIT=y CONFIG_CPU_S3C6400_CLOCK=y +# CONFIG_S3C64XX_DMA is not set CONFIG_S3C64XX_SETUP_I2C0=y CONFIG_S3C64XX_SETUP_I2C1=y +CONFIG_S3C64XX_SETUP_FB_24BPP=y +CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y CONFIG_PLAT_S3C=y # # Boot options # CONFIG_S3C_BOOT_ERROR_RESET=y +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y # # Power management @@ -177,17 +255,16 @@ CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_GPIO_TRACK=y -CONFIG_S3C_GPIO_PULL_UPDOWN=y -CONFIG_S3C_GPIO_CFG_S3C24XX=y -CONFIG_S3C_GPIO_CFG_S3C64XX=y -CONFIG_S3C_DEV_HSMMC=y -CONFIG_S3C_DEV_HSMMC1=y -CONFIG_S3C_DEV_I2C1=y +# CONFIG_MACH_SMDK6400 is not set CONFIG_CPU_S3C6410=y CONFIG_S3C6410_SETUP_SDHCI=y +# CONFIG_MACH_ANW6410 is not set CONFIG_MACH_SMDK6410=y CONFIG_SMDK6410_SD_CH0=y # CONFIG_SMDK6410_SD_CH1 is not set +# CONFIG_SMDK6410_WM1190_EV1 is not set +# CONFIG_MACH_NCP is not set +# CONFIG_MACH_HMT is not set # # Processor Type @@ -196,7 +273,7 @@ CONFIG_CPU_V6=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v6=y CONFIG_CPU_ABRT_EV6=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_V6=y CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y @@ -212,8 +289,10 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set -# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 # # Bus support @@ -229,13 +308,15 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -243,13 +324,14 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options @@ -263,6 +345,7 @@ CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x5100 # # CPU Power Management # +# CONFIG_CPU_FREQ is not set # CONFIG_CPU_IDLE is not set # @@ -300,6 +383,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -314,14 +398,32 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y -# CONFIG_EEPROM_93CX6 is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -334,6 +436,7 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set +# CONFIG_PHONE is not set # # Input device support @@ -341,6 +444,7 @@ CONFIG_HAVE_IDE=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -357,27 +461,33 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set # CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -390,6 +500,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -423,16 +534,18 @@ CONFIG_SERIAL_S3C6400=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_HELPER_AUTO=y @@ -443,6 +556,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set CONFIG_I2C_S3C2410=y @@ -463,32 +577,33 @@ CONFIG_I2C_S3C2410=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set -CONFIG_EEPROM_AT24=y -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_TPS65010 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set # CONFIG_GPIO_SYSFS is not set +# +# Memory mapped GPIO expanders: +# + # # I2C GPIO expanders: # # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -497,10 +612,19 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set @@ -509,17 +633,21 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -530,16 +658,24 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set @@ -549,15 +685,14 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -568,28 +703,22 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -612,17 +741,15 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -CONFIG_HID_DEBUG=y # CONFIG_HIDRAW is not set # CONFIG_HID_PID is not set # # Special HID drivers # -# CONFIG_HID_COMPAT is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB is not set @@ -631,9 +758,13 @@ CONFIG_USB_ARCH_HAS_HCD=y # # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# CONFIG_MMC=y CONFIG_MMC_DEBUG=y CONFIG_MMC_UNSAFE_RESUME=y @@ -650,22 +781,24 @@ CONFIG_SDIO_UART=y # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PLTFM is not set CONFIG_MMC_SDHCI_S3C=y +# CONFIG_MMC_SDHCI_S3C_DMA is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # -# Voltage and Current regulators +# TI VLYNQ # -# CONFIG_REGULATOR is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -674,6 +807,7 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y @@ -683,9 +817,12 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -695,6 +832,11 @@ CONFIG_INOTIFY_USER=y # CONFIG_FUSE_FS is not set CONFIG_GENERIC_ACL=y +# +# Caches +# +# CONFIG_FSCACHE is not set + # # CD-ROM/DVD Filesystems # @@ -719,10 +861,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -731,12 +870,17 @@ CONFIG_TMPFS_POSIX_ACL=y # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set @@ -755,6 +899,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -763,12 +908,16 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_PI_LIST=y # CONFIG_RT_MUTEX_TESTER is not set @@ -787,34 +936,43 @@ CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y - -# -# Tracers -# +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set CONFIG_DEBUG_S3C_UART=0 # @@ -823,13 +981,19 @@ CONFIG_DEBUG_S3C_UART=0 # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" # CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -838,6 +1002,10 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_PLIST=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y -- GitLab From 0647aee035245e0e5ea39ae17cf909b7099f988d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 20 Jan 2010 15:09:40 +0900 Subject: [PATCH 112/370] ARM: S5P6440: Add HSMMC and OTG base addresses to map.h Add the HSOTG and HSMMC block addresses to the map.h file. Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/include/mach/map.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index dc922d6e11ff6..4a73e73c9428a 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -66,6 +66,14 @@ #define S5P_PA_UART S5P6440_PA_UART #define S5P_VA_UART S3C_VA_UART +/* HS USB OtG */ +#define S5P6440_PA_HSOTG (0xED100000) + +/* HSMMC */ +#define S5P6440_PA_HSMMC0 (0xED800000) +#define S5P6440_PA_HSMMC1 (0xED900000) +#define S5P6440_PA_HSMMC2 (0xEDA00000) + #define S5P_PA_UART0 (S5P_PA_UART + 0x0) #define S5P_PA_UART1 (S5P_PA_UART + 0x400) #define S5P_PA_UART2 (S5P_PA_UART + 0x800) -- GitLab From 501d70383aa9ffc78b41aa7e74f6b0254c7c731c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 21 Sep 2009 09:30:09 +0200 Subject: [PATCH 113/370] arm/at91: Don't disable irqs in set_next_event and set_mode callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit on AT91 the timer irq is shared, so the handler might be entered without irqs being disabled. Though this should not happen as the timer irq is registered early, there have been some reports on the mailing list. To make debugging that problem easier next time it pops up a WARN_ON_ONCE is added to the handler if irqs are not off. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-at91/at91rm9200_time.c | 20 ++++++-------------- arch/arm/mach-at91/at91sam926x_time.c | 11 ++++++----- 2 files changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 309f3511aa203..2500f41d8d2db 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -58,6 +58,12 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) { u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; + /* + * irqs should be disabled here, but as the irq is shared they are only + * guaranteed to be off if the timer irq is registered first. + */ + WARN_ON_ONCE(!irqs_disabled()); + /* simulate "oneshot" timer with alarm */ if (sr & AT91_ST_ALMS) { clkevt.event_handler(&clkevt); @@ -132,24 +138,11 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) static int clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) { - unsigned long flags; u32 alm; int status = 0; BUG_ON(delta < 2); - /* Use "raw" primitives so we behave correctly on RT kernels. */ - raw_local_irq_save(flags); - - /* - * According to Thomas Gleixner irqs are already disabled here. Simply - * removing raw_local_irq_save above (and the matching - * raw_local_irq_restore) was not accepted. See - * http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174 - * So for now (2008-11-20) just warn once if irqs were not disabled ... - */ - WARN_ON_ONCE(!raw_irqs_disabled_flags(flags)); - /* The alarm IRQ uses absolute time (now+delta), not the relative * time (delta) in our calling convention. Like all clockevents * using such "match" hardware, we have a race to defend against. @@ -169,7 +162,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) alm += delta; at91_sys_write(AT91_ST_RTAR, alm); - raw_local_irq_restore(flags); return status; } diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 4bd56aee4370b..608a63240b64b 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -62,16 +62,12 @@ static struct clocksource pit_clk = { static void pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* update clocksource counter, then enable the IRQ */ - raw_local_irq_save(flags); + /* update clocksource counter */ pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_ONESHOT: BUG(); @@ -100,6 +96,11 @@ static struct clock_event_device pit_clkevt = { */ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) { + /* + * irqs should be disabled here, but as the irq is shared they are only + * guaranteed to be off if the timer irq is registered first. + */ + WARN_ON_ONCE(!irqs_disabled()); /* The PIT interrupt may be disabled, and is shared */ if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) -- GitLab From a602f0f2f04f150fa1f7312b9e601e8e1a5afe10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 17 Dec 2009 12:43:29 +0100 Subject: [PATCH 114/370] arm/{pxa,sa1100,nomadik}: Don't disable irqs in set_next_event and set_mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These functions are called with irqs already off. This commit removes the calls to raw_local_irq_save and raw_local_irq_restore on platforms that don't have to use a shared interrupt for their timekeeping. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-pxa/time.c | 10 +--------- arch/arm/mach-sa1100/time.c | 8 +------- arch/arm/plat-nomadik/timer.c | 9 +-------- 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 750c448db6722..293e40aeaf29d 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -76,14 +76,12 @@ pxa_ost0_interrupt(int irq, void *dev_id) static int pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) { - unsigned long flags, next, oscr; + unsigned long next, oscr; - raw_local_irq_save(flags); OIER |= OIER_E0; next = OSCR + delta; OSMR0 = next; oscr = OSCR; - raw_local_irq_restore(flags); return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; } @@ -91,23 +89,17 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) static void pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long irqflags; - switch (mode) { case CLOCK_EVT_MODE_ONESHOT: - raw_local_irq_save(irqflags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(irqflags); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* initializing, released, or preparing for suspend */ - raw_local_irq_save(irqflags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(irqflags); break; case CLOCK_EVT_MODE_RESUME: diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index b9cbb56d6e9d9..74b6e0e570b64 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -35,14 +35,12 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) static int sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) { - unsigned long flags, next, oscr; + unsigned long next, oscr; - raw_local_irq_save(flags); OIER |= OIER_E0; next = OSCR + delta; OSMR0 = next; oscr = OSCR; - raw_local_irq_restore(flags); return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; } @@ -50,16 +48,12 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) static void sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - raw_local_irq_save(flags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_RESUME: diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 62f18ad43a282..fa7cb3a57cbf6 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -49,24 +49,17 @@ static struct clocksource nmdk_clksrc = { static void nmdk_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* enable interrupts -- and count current value? */ - raw_local_irq_save(flags); + /* count current value? */ writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_ONESHOT: BUG(); /* Not supported, yet */ /* FALLTHROUGH */ case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: - /* disable irq */ - raw_local_irq_save(flags); writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_RESUME: break; -- GitLab From d85127319cc36c38eb99615c52531c6ef2f11369 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 22 Jan 2010 10:50:42 +0900 Subject: [PATCH 115/370] ARM: S5PV210: Add serial port support This patch adds UART serial port support for S5PV210. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/regs-serial.h | 30 ++++ drivers/serial/Kconfig | 9 +- drivers/serial/Makefile | 1 + drivers/serial/s5pv210.c | 154 +++++++++++++++++++ 4 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/s5pv210.c diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 85d8904e7f240..60d6604185ea3 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -194,6 +194,36 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 +/* Following are specific to S5PV210 and S5P6442 */ +#define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_PCLK (0<<10) +#define S5PV210_UCON_UCLK (1<<10) + +#define S5PV210_UFCON_TXTRIG0 (0<<8) +#define S5PV210_UFCON_TXTRIG4 (1<<8) +#define S5PV210_UFCON_TXTRIG8 (2<<8) +#define S5PV210_UFCON_TXTRIG16 (3<<8) +#define S5PV210_UFCON_TXTRIG32 (4<<8) +#define S5PV210_UFCON_TXTRIG64 (5<<8) +#define S5PV210_UFCON_TXTRIG128 (6<<8) +#define S5PV210_UFCON_TXTRIG256 (7<<8) + +#define S5PV210_UFCON_RXTRIG1 (0<<4) +#define S5PV210_UFCON_RXTRIG4 (1<<4) +#define S5PV210_UFCON_RXTRIG8 (2<<4) +#define S5PV210_UFCON_RXTRIG16 (3<<4) +#define S5PV210_UFCON_RXTRIG32 (4<<4) +#define S5PV210_UFCON_RXTRIG64 (5<<4) +#define S5PV210_UFCON_RXTRIG128 (6<<4) +#define S5PV210_UFCON_RXTRIG256 (7<<4) + +#define S5PV210_UFSTAT_TXFULL (1<<24) +#define S5PV210_UFSTAT_RXFULL (1<<8) +#define S5PV210_UFSTAT_TXMASK (255<<16) +#define S5PV210_UFSTAT_TXSHIFT (16) +#define S5PV210_UFSTAT_RXMASK (255<<0) +#define S5PV210_UFSTAT_RXSHIFT (0) + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index d7d687f0d201b..ebdd2b984d16e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S5PV210 || ARCH_S3C64XX || CPU_S3C2443 default 3 help Select the number of available UART ports for the Samsung S3C @@ -540,6 +540,13 @@ config SERIAL_S5PC100 help Serial port support for the Samsung S5PC100 SoCs +config SERIAL_S5PV210 + tristate "Samsung S5PV210 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S5PV210 + default y + help + Serial port support for Samsung's S5P Family of SoC's + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5548fe7df61d2..6aa4723b74eec 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o +obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_MUX) += mux.o diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c new file mode 100644 index 0000000000000..8dc03837617b7 --- /dev/null +++ b/drivers/serial/s5pv210.c @@ -0,0 +1,154 @@ +/* linux/drivers/serial/s5pv210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on drivers/serial/s3c6400.c + * + * Driver for Samsung S5PV210 SoC UARTs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "samsung.h" + +static int s5pv210_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "pclk") == 0) + ucon &= ~S5PV210_UCON_CLKMASK; + else if (strcmp(clk->name, "uclk1") == 0) + ucon |= S5PV210_UCON_CLKMASK; + else { + printk(KERN_ERR "unknown clock source %s\n", clk->name); + return -EINVAL; + } + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + + +static int s5pv210_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + u32 ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + + switch (ucon & S5PV210_UCON_CLKMASK) { + case S5PV210_UCON_PCLK: + clk->name = "pclk"; + break; + case S5PV210_UCON_UCLK: + clk->name = "uclk1"; + break; + } + + return 0; +} + +static int s5pv210_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + ucon &= S5PV210_UCON_CLKMASK; + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +#define S5PV210_UART_DEFAULT_INFO(fifo_size) \ + .name = "Samsung S5PV210 UART0", \ + .type = PORT_S3C6400, \ + .fifosize = fifo_size, \ + .has_divslot = 1, \ + .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ + .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ + .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ + .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ + .get_clksrc = s5pv210_serial_getsource, \ + .set_clksrc = s5pv210_serial_setsource, \ + .reset_port = s5pv210_serial_resetport + +static struct s3c24xx_uart_info s5p_port_fifo256 = { + S5PV210_UART_DEFAULT_INFO(256), +}; + +static struct s3c24xx_uart_info s5p_port_fifo64 = { + S5PV210_UART_DEFAULT_INFO(64), +}; + +static struct s3c24xx_uart_info s5p_port_fifo16 = { + S5PV210_UART_DEFAULT_INFO(16), +}; + +static struct s3c24xx_uart_info *s5p_uart_inf[] = { + [0] = &s5p_port_fifo256, + [1] = &s5p_port_fifo64, + [2] = &s5p_port_fifo16, + [3] = &s5p_port_fifo16, +}; + +/* device management */ +static int s5p_serial_probe(struct platform_device *pdev) +{ + return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]); +} + +static struct platform_driver s5p_serial_drv = { + .probe = s5p_serial_probe, + .remove = __devexit_p(s3c24xx_serial_remove), + .driver = { + .name = "s5pv210-uart", + .owner = THIS_MODULE, + }, +}; + +static int __init s5pv210_serial_console_init(void) +{ + return s3c24xx_serial_initconsole(&s5p_serial_drv, s5p_uart_inf); +} + +console_initcall(s5pv210_serial_console_init); + +static int __init s5p_serial_init(void) +{ + return s3c24xx_serial_init(&s5p_serial_drv, *s5p_uart_inf); +} + +static void __exit s5p_serial_exit(void) +{ + platform_driver_unregister(&s5p_serial_drv); +} + +module_init(s5p_serial_init); +module_exit(s5p_serial_exit); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:s5pv210-uart"); +MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support"); +MODULE_AUTHOR("Thomas Abraham "); -- GitLab From f6b56704f78b2667fc8f61d2f398931fbc032b62 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Fri, 22 Jan 2010 23:29:16 +0100 Subject: [PATCH 116/370] ARM: SAMSUNG: Fix null pointer dereference in ADC driver ARM: SAMSUNG: Fix null pointer dereference in ADC driver Use struct adc_device instead of relying on client (which could be NULL) when checking for SoC type. Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 120b7902fc2fd..c7659b7378b1f 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -295,7 +295,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) } exit: - if (platform_get_device_id(client->pdev)->driver_data == TYPE_S3C64XX) { + if (platform_get_device_id(adc->pdev)->driver_data == TYPE_S3C64XX) { /* Clear ADC interrupt */ writel(0, adc->regs + S3C64XX_ADCCLRINT); } -- GitLab From ab5d97db1c6ced3e95c00d097931471707032b1f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 25 Jan 2010 10:39:23 +0900 Subject: [PATCH 117/370] ARM: SAMSUNG: Fix bad use of __initdata for s3c_register_clocks() Functions should be marked __init, not __initdata. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 0c746ae7b2a63..e9cdbe47beb63 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -344,7 +344,7 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) * Call s3c24xx_register_clock() on the @clkp array given, printing an * error if it fails to register the clock (unlikely). */ -void __initdata s3c_register_clocks(struct clk *clkp, int nr_clks) +void __init s3c_register_clocks(struct clk *clkp, int nr_clks) { int ret; -- GitLab From 431107ea5b680a24a4d01fbd3a178a3eb932f378 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 10:11:04 +0900 Subject: [PATCH 118/370] ARM: S3C64XX: Merge mach-s3c6400 and mach-s3c6410 As per discussions with Russell King on linux-arm-kernel, it appears that both mach-s3c6400 and mach-s3c6410 are so close together that they should simply be merged into mach-s3c64xx. Note, this patch does not eliminate any of the bits that are still common, it is simply a move of the two directories together, any further common code will be eliminated or moved in further patches. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 3 +- arch/arm/Makefile | 2 +- arch/arm/mach-s3c6400/Kconfig | 30 ------------------- arch/arm/mach-s3c6400/Makefile | 23 -------------- arch/arm/mach-s3c6410/Makefile | 26 ---------------- .../{mach-s3c6410 => mach-s3c64xx}/Kconfig | 30 +++++++++++++++++-- arch/arm/mach-s3c64xx/Makefile | 29 ++++++++++++++++++ .../Makefile.boot | 0 .../include/mach/debug-macro.S | 0 .../include/mach/dma.h | 0 .../include/mach/entry-macro.S | 0 .../include/mach/gpio.h | 0 .../include/mach/hardware.h | 0 .../include/mach/irqs.h | 0 .../include/mach/map.h | 0 .../include/mach/memory.h | 0 .../include/mach/pwm-clock.h | 0 .../include/mach/regs-clock.h | 0 .../include/mach/regs-fb.h | 0 .../include/mach/regs-irq.h | 0 .../include/mach/system.h | 0 .../include/mach/tick.h | 0 .../include/mach/uncompress.h | 0 .../mach-anw6410.c | 2 +- .../{mach-s3c6410 => mach-s3c64xx}/mach-hmt.c | 0 .../{mach-s3c6410 => mach-s3c64xx}/mach-ncp.c | 2 +- .../mach-smdk6400.c | 2 +- .../mach-smdk6410.c | 2 +- .../{mach-s3c6400 => mach-s3c64xx}/s3c6400.c | 2 +- .../cpu.c => mach-s3c64xx/s3c6410.c} | 2 +- .../setup-sdhci-s3c6400.c} | 2 +- .../setup-sdhci-s3c6410.c} | 2 +- 32 files changed, 67 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/mach-s3c6400/Kconfig delete mode 100644 arch/arm/mach-s3c6400/Makefile delete mode 100644 arch/arm/mach-s3c6410/Makefile rename arch/arm/{mach-s3c6410 => mach-s3c64xx}/Kconfig (84%) create mode 100644 arch/arm/mach-s3c64xx/Makefile rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/Makefile.boot (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/debug-macro.S (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/dma.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/entry-macro.S (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/gpio.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/hardware.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/irqs.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/map.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/memory.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/pwm-clock.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/regs-clock.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/regs-fb.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/regs-irq.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/system.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/tick.h (100%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/include/mach/uncompress.h (100%) rename arch/arm/{mach-s3c6410 => mach-s3c64xx}/mach-anw6410.c (99%) rename arch/arm/{mach-s3c6410 => mach-s3c64xx}/mach-hmt.c (100%) rename arch/arm/{mach-s3c6410 => mach-s3c64xx}/mach-ncp.c (98%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/mach-smdk6400.c (98%) rename arch/arm/{mach-s3c6410 => mach-s3c64xx}/mach-smdk6410.c (99%) rename arch/arm/{mach-s3c6400 => mach-s3c64xx}/s3c6400.c (98%) rename arch/arm/{mach-s3c6410/cpu.c => mach-s3c64xx/s3c6410.c} (98%) rename arch/arm/{mach-s3c6400/setup-sdhci.c => mach-s3c64xx/setup-sdhci-s3c6400.c} (97%) rename arch/arm/{mach-s3c6410/setup-sdhci.c => mach-s3c64xx/setup-sdhci-s3c6410.c} (97%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3bc5169f0f822..685ff7effff9e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,8 +799,7 @@ source "arch/arm/mach-s3c2443/Kconfig" endif if ARCH_S3C64XX -source "arch/arm/mach-s3c6400/Kconfig" -source "arch/arm/mach-s3c6410/Kconfig" +source "arch/arm/mach-s3c64xx/Kconfig" endif source "arch/arm/mach-s5p6440/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bbcd512ccf7e0..ecf963d61aed5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -160,7 +160,7 @@ machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 -machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 +machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig deleted file mode 100644 index a250bf68709f2..0000000000000 --- a/arch/arm/mach-s3c6400/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2008 Openmoko, Inc. -# Simtec Electronics, Ben Dooks -# -# Licensed under GPLv2 - -# Configuration options for the S3C6410 CPU - -config CPU_S3C6400 - bool - select CPU_S3C6400_INIT - select CPU_S3C6400_CLOCK - help - Enable S3C6400 CPU support - -config S3C6400_SETUP_SDHCI - bool - help - Internal configuration for default SDHCI - setup for S3C6400. - -# S36400 Macchine support - -config MACH_SMDK6400 - bool "SMDK6400" - select CPU_S3C6400 - select S3C_DEV_HSMMC - select S3C_DEV_NAND - select S3C6400_SETUP_SDHCI - help - Machine support for the Samsung SMDK6400 diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile deleted file mode 100644 index df1ce4aa03e5e..0000000000000 --- a/arch/arm/mach-s3c6400/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# arch/arm/mach-s3c6400/Makefile -# -# Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -# Core support for S3C6400 system - -obj-$(CONFIG_CPU_S3C6400) += s3c6400.o - -# setup support - -obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o - -# Machine support - -obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile deleted file mode 100644 index 3e48c3dbf9734..0000000000000 --- a/arch/arm/mach-s3c6410/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# arch/arm/plat-s3c6410/Makefile -# -# Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -# Core support for S3C6410 system - -obj-$(CONFIG_CPU_S3C6410) += cpu.o - -# Helper and device support - -obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o - -# machine support - -obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o -obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o -obj-$(CONFIG_MACH_NCP) += mach-ncp.o -obj-$(CONFIG_MACH_HMT) += mach-hmt.o diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c64xx/Kconfig similarity index 84% rename from arch/arm/mach-s3c6410/Kconfig rename to arch/arm/mach-s3c64xx/Kconfig index 162f4561f80f1..551bb3faa3ac6 100644 --- a/arch/arm/mach-s3c6410/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -1,10 +1,17 @@ # Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics +# Simtec Electronics, Ben Dooks # # Licensed under GPLv2 # Configuration options for the S3C6410 CPU +config CPU_S3C6400 + bool + select CPU_S3C6400_INIT + select CPU_S3C6400_CLOCK + help + Enable S3C6400 CPU support + config CPU_S3C6410 bool select CPU_S3C6400_INIT @@ -12,12 +19,31 @@ config CPU_S3C6410 help Enable S3C6410 CPU support +config S3C6400_SETUP_SDHCI + bool + help + Internal configuration for default SDHCI + setup for S3C6400. + config S3C6410_SETUP_SDHCI bool select S3C64XX_SETUP_SDHCI_GPIO help Internal helper functions for S3C6410 based SDHCI systems +# S36400 Macchine support + +config MACH_SMDK6400 + bool "SMDK6400" + select CPU_S3C6400 + select S3C_DEV_HSMMC + select S3C_DEV_NAND + select S3C6400_SETUP_SDHCI + help + Machine support for the Samsung SMDK6400 + +# S3C6410 machine support + config MACH_ANW6410 bool "A&W6410" select CPU_S3C6410 @@ -58,7 +84,7 @@ config SMDK6410_SD_CH0 at least some SMDK6410 boards come with the resistors fitted so that the card detects for channels 0 and 1 are the same. - + config SMDK6410_SD_CH1 bool "Use channel 1 only" depends on MACH_SMDK6410 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile new file mode 100644 index 0000000000000..24a3bc33da1e7 --- /dev/null +++ b/arch/arm/mach-s3c64xx/Makefile @@ -0,0 +1,29 @@ +# arch/arm/mach-s3c64xx/Makefile +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S3C6400 system + +obj-$(CONFIG_CPU_S3C6400) += s3c6400.o +obj-$(CONFIG_CPU_S3C6410) += s3c6410.o + +# setup support + +obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci-s3c6400.o +obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci-s3c6410.o + +# Machine support + +obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o +obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o +obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o +obj-$(CONFIG_MACH_NCP) += mach-ncp.o +obj-$(CONFIG_MACH_HMT) += mach-hmt.o diff --git a/arch/arm/mach-s3c6400/Makefile.boot b/arch/arm/mach-s3c64xx/Makefile.boot similarity index 100% rename from arch/arm/mach-s3c6400/Makefile.boot rename to arch/arm/mach-s3c64xx/Makefile.boot diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/debug-macro.S rename to arch/arm/mach-s3c64xx/include/mach/debug-macro.S diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/dma.h rename to arch/arm/mach-s3c64xx/include/mach/dma.h diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/entry-macro.S rename to arch/arm/mach-s3c64xx/include/mach/entry-macro.S diff --git a/arch/arm/mach-s3c6400/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/gpio.h rename to arch/arm/mach-s3c64xx/include/mach/gpio.h diff --git a/arch/arm/mach-s3c6400/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/hardware.h rename to arch/arm/mach-s3c64xx/include/mach/hardware.h diff --git a/arch/arm/mach-s3c6400/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/irqs.h rename to arch/arm/mach-s3c64xx/include/mach/irqs.h diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/map.h rename to arch/arm/mach-s3c64xx/include/mach/map.h diff --git a/arch/arm/mach-s3c6400/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/memory.h rename to arch/arm/mach-s3c64xx/include/mach/memory.h diff --git a/arch/arm/mach-s3c6400/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/pwm-clock.h rename to arch/arm/mach-s3c64xx/include/mach/pwm-clock.h diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/regs-clock.h rename to arch/arm/mach-s3c64xx/include/mach/regs-clock.h diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/regs-fb.h rename to arch/arm/mach-s3c64xx/include/mach/regs-fb.h diff --git a/arch/arm/mach-s3c6400/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/regs-irq.h rename to arch/arm/mach-s3c64xx/include/mach/regs-irq.h diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/system.h rename to arch/arm/mach-s3c64xx/include/mach/system.h diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/tick.h rename to arch/arm/mach-s3c64xx/include/mach/tick.h diff --git a/arch/arm/mach-s3c6400/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h similarity index 100% rename from arch/arm/mach-s3c6400/include/mach/uncompress.h rename to arch/arm/mach-s3c64xx/include/mach/uncompress.h diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c similarity index 99% rename from arch/arm/mach-s3c6410/mach-anw6410.c rename to arch/arm/mach-s3c64xx/mach-anw6410.c index 661cca63de257..49032a85f6f85 100644 --- a/arch/arm/mach-s3c6410/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/mach-anw6410.c +/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c similarity index 100% rename from arch/arm/mach-s3c6410/mach-hmt.c rename to arch/arm/mach-s3c64xx/mach-hmt.c diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c similarity index 98% rename from arch/arm/mach-s3c6410/mach-ncp.c rename to arch/arm/mach-s3c64xx/mach-ncp.c index 55e9bbfaf68b3..9be92ddd21767 100644 --- a/arch/arm/mach-s3c6410/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-s3c6410/mach-ncp.c + * linux/arch/arm/mach-s3c64xx/mach-ncp.c * * Copyright (C) 2008-2009 Samsung Electronics * diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c similarity index 98% rename from arch/arm/mach-s3c6400/mach-smdk6400.c rename to arch/arm/mach-s3c64xx/mach-smdk6400.c index ab19285389a7e..ba8a052a61421 100644 --- a/arch/arm/mach-s3c6400/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c +/* linux/arch/arm/mach-s3c64xx/mach-smdk6400.c * * Copyright 2008 Simtec Electronics * Ben Dooks diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c similarity index 99% rename from arch/arm/mach-s3c6410/mach-smdk6410.c rename to arch/arm/mach-s3c64xx/mach-smdk6410.c index eba345fadffeb..6e6ff354da429 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c +/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c similarity index 98% rename from arch/arm/mach-s3c6400/s3c6400.c rename to arch/arm/mach-s3c64xx/s3c6400.c index d876ee5036710..884858a78d496 100644 --- a/arch/arm/mach-s3c6400/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/cpu.c +/* linux/arch/arm/mach-s3c64xx/cpu.c * * Copyright 2009 Simtec Electronics * Ben Dooks diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c64xx/s3c6410.c similarity index 98% rename from arch/arm/mach-s3c6410/cpu.c rename to arch/arm/mach-s3c64xx/s3c6410.c index 522c08691952e..dd55c6a74ed55 100644 --- a/arch/arm/mach-s3c6410/cpu.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/cpu.c +/* linux/arch/arm/mach-s3c64xx/s3c6410.c * * Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c similarity index 97% rename from arch/arm/mach-s3c6400/setup-sdhci.c rename to arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c index 1039937403be1..ec96a5863c0cb 100644 --- a/arch/arm/mach-s3c6400/setup-sdhci.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/setup-sdhci.c +/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c * * Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c similarity index 97% rename from arch/arm/mach-s3c6410/setup-sdhci.c rename to arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c index 816d2d9f9ef8a..8d714a1f6dc7c 100644 --- a/arch/arm/mach-s3c6410/setup-sdhci.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c6410/setup-sdhci.c +/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c * * Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics -- GitLab From 97ce9d6938d58e7846dc0365c720c13ebe64547e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 10:18:14 +0900 Subject: [PATCH 119/370] ARM: S3C64XX: Remove useless IO descriptor from S3C6410 The iotable in arch/arm/mach-s3c64xx/s3c6410.c is currently empty and therefore can be removed from the build. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/s3c6410.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index dd55c6a74ed55..185f15cbb701f 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -41,20 +41,8 @@ #include #include -/* Initial IO mappings */ - -static struct map_desc s3c6410_iodesc[] __initdata = { -}; - -/* s3c6410_map_io - * - * register the standard cpu IO areas -*/ - void __init s3c6410_map_io(void) { - iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); - /* initialise device information early */ s3c6410_default_sdhci0(); s3c6410_default_sdhci1(); -- GitLab From 2f6c2ac1d945ffc2e343103bdcfccbdb2e2de805 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 10:38:52 +0900 Subject: [PATCH 120/370] ARM: S3C64XX: Squash SDHCI setup into one file Squash the SDHCI setup for both the S3C6400 and S3C6410 into one file and make the S3C6410 case use the S3C6400 code. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 17 ++--- arch/arm/mach-s3c64xx/Makefile | 3 +- arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c | 68 ------------------- .../{setup-sdhci-s3c6400.c => setup-sdhci.c} | 13 +++- arch/arm/plat-samsung/include/plat/sdhci.h | 43 ++++++------ 5 files changed, 37 insertions(+), 107 deletions(-) delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c rename arch/arm/mach-s3c64xx/{setup-sdhci-s3c6400.c => setup-sdhci.c} (81%) diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 551bb3faa3ac6..ce32e4997d763 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -19,17 +19,12 @@ config CPU_S3C6410 help Enable S3C6410 CPU support -config S3C6400_SETUP_SDHCI - bool - help - Internal configuration for default SDHCI - setup for S3C6400. - -config S3C6410_SETUP_SDHCI - bool +config S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_SDHCI_GPIO + bool help - Internal helper functions for S3C6410 based SDHCI systems + Internal configuration for default SDHCI setup for S3C6400 and + S3C6410 SoCs. # S36400 Macchine support @@ -38,7 +33,7 @@ config MACH_SMDK6400 select CPU_S3C6400 select S3C_DEV_HSMMC select S3C_DEV_NAND - select S3C6400_SETUP_SDHCI + select S3C64XX_SETUP_SDHCI help Machine support for the Samsung SMDK6400 @@ -61,7 +56,7 @@ config MACH_SMDK6410 select S3C_DEV_FB select S3C_DEV_USB_HOST select S3C_DEV_USB_HSOTG - select S3C6410_SETUP_SDHCI + select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_FB_24BPP help diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 24a3bc33da1e7..21ddf6b29280d 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -17,8 +17,7 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o # setup support -obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci-s3c6400.o -obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci-s3c6410.o +obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o # Machine support diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c deleted file mode 100644 index 8d714a1f6dc7c..0000000000000 --- a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c6410_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not successfully used yet */ -}; - - -void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything acording to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} - diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c b/arch/arm/mach-s3c64xx/setup-sdhci.c similarity index 81% rename from arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c rename to arch/arm/mach-s3c64xx/setup-sdhci.c index ec96a5863c0cb..1a942037c4eff 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci.c @@ -5,7 +5,7 @@ * Ben Dooks * http://armlinux.simtec.co.uk/ * - * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) + * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -26,7 +26,7 @@ /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ -char *s3c6400_hsmmc_clksrcs[4] = { +char *s3c64xx_hsmmc_clksrcs[4] = { [0] = "hsmmc", [1] = "hsmmc", [2] = "mmc_bus", @@ -61,3 +61,12 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, writel(ctrl3, r + S3C_SDHCI_CONTROL3); } +void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); + + s3c6400_setup_sdhci_cfg_card(dev, r, ios, card); +} diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 53198673b6bde..7d07cd7aa4f20 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -78,8 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); /* S3C6400 SDHCI setup */ -#ifdef CONFIG_S3C6400_SETUP_SDHCI -extern char *s3c6400_hsmmc_clksrcs[4]; +#ifdef CONFIG_S3C64XX_SETUP_SDHCI +extern char *s3c64xx_hsmmc_clksrcs[4]; #ifdef CONFIG_S3C_DEV_HSMMC extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, @@ -89,7 +89,7 @@ extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, static inline void s3c6400_default_sdhci0(void) { - s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; } @@ -101,7 +101,7 @@ static inline void s3c6400_default_sdhci0(void) { } #ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s3c6400_default_sdhci1(void) { - s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; } @@ -112,7 +112,7 @@ static inline void s3c6400_default_sdhci1(void) { } #ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s3c6400_default_sdhci2(void) { - s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; } @@ -120,27 +120,19 @@ static inline void s3c6400_default_sdhci2(void) static inline void s3c6400_default_sdhci2(void) { } #endif /* CONFIG_S3C_DEV_HSMMC2 */ -#else -static inline void s3c6400_default_sdhci0(void) { } -static inline void s3c6400_default_sdhci1(void) { } -#endif /* CONFIG_S3C6400_SETUP_SDHCI */ - /* S3C6410 SDHCI setup */ -#ifdef CONFIG_S3C6410_SETUP_SDHCI -extern char *s3c6410_hsmmc_clksrcs[4]; - -extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); +extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); #ifdef CONFIG_S3C_DEV_HSMMC static inline void s3c6410_default_sdhci0(void) { - s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; + s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; } #else static inline void s3c6410_default_sdhci0(void) { } @@ -149,9 +141,9 @@ static inline void s3c6410_default_sdhci0(void) { } #ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s3c6410_default_sdhci1(void) { - s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; + s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; } #else static inline void s3c6410_default_sdhci1(void) { } @@ -160,9 +152,9 @@ static inline void s3c6410_default_sdhci1(void) { } #ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s3c6410_default_sdhci2(void) { - s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; + s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; } #else static inline void s3c6410_default_sdhci2(void) { } @@ -171,7 +163,10 @@ static inline void s3c6410_default_sdhci2(void) { } #else static inline void s3c6410_default_sdhci0(void) { } static inline void s3c6410_default_sdhci1(void) { } -#endif /* CONFIG_S3C6410_SETUP_SDHCI */ +static inline void s3c6400_default_sdhci0(void) { } +static inline void s3c6400_default_sdhci1(void) { } + +#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ /* S5PC100 SDHCI setup */ -- GitLab From 8428d47a36a35c457a1147c3e8aa61c1be343604 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 25 Jan 2010 10:44:10 +0900 Subject: [PATCH 121/370] ARM: SAMSUNG: Add documentation to the clock registration calls. Add some kerneldoc documentation to the s3c24xx_register_clock and the s3c24xx_register_clocks() call. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index e9cdbe47beb63..4b95b39200361 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -307,6 +307,12 @@ struct clk s3c24xx_uclk = { /* initialise the clock system */ +/** + * s3c24xx_register_clock() - register a clock + * @clk: The clock to register + * + * Add the specified clock to the list of clocks known by the system. + */ int s3c24xx_register_clock(struct clk *clk) { if (clk->enable == NULL) @@ -324,6 +330,14 @@ int s3c24xx_register_clock(struct clk *clk) return 0; } +/** + * s3c24xx_register_clocks() - register an array of clock pointers + * @clks: Pointer to an array of struct clk pointers + * @nr_clks: The number of clocks in the @clks array. + * + * Call s3c24xx_register_clock() for all the clock pointers contained + * in the @clks list. Returns the number of failures. + */ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) { int fails = 0; -- GitLab From 50ee2d35a592ead260527244af5160c7fa6189ea Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 25 Jan 2010 10:46:51 +0900 Subject: [PATCH 122/370] ARM: SAMSUNG: Add error printing to s3c24xx_register_clocks Add an error print to s3c24xx_register_clocks to provide more useful information when failing to register the clock. I belive this was originally left out due to the possibility of a problem with low-level debugging code. However, if the low-level debug code is not functional by now there will be a whole other set of problems being presented to the system. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/clock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 4b95b39200361..1b25c9d8c4034 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -343,8 +343,12 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) int fails = 0; for (; nr_clks > 0; nr_clks--, clks++) { - if (s3c24xx_register_clock(*clks) < 0) + if (s3c24xx_register_clock(*clks) < 0) { + struct clk *clk = *clks; + printk(KERN_ERR "%s: failed to register %p: %s\n", + __func__, clk, clk->name); fails++; + } } return fails; -- GitLab From 4e41db871e0ea46b08eb3cdf887153c853e3ee3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Jan 2010 18:23:04 +0100 Subject: [PATCH 123/370] mx2/mx3: debug-macro.S needs deprecated symbols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/kernel/debug.S:147: Error: constant expression expected -- `ldrne r3,=(((UART1_BASE_ADDR)-AIPI_BASE_ADDR)+AIPI_BASE_ADDR_VIRT)' arch/arm/kernel/debug.S:163: Error: constant expression expected -- `ldrne r3,=(((UART1_BASE_ADDR)-AIPI_BASE_ADDR)+AIPI_BASE_ADDR_VIRT)' when compiling for mx2 with CONFIG_DEBUG_LL=y. A similar error exists on mx3 and is fixed by this commit, too. These were introduced by aae7019382896cf1075a93acc564e42601bc44a2. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/debug-macro.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 15b2b148a105c..21e0f077268cd 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,6 +10,7 @@ * published by the Free Software Foundation. * */ +#define IMX_NEEDS_DEPRECATED_SYMBOLS #ifdef CONFIG_ARCH_MX1 #include -- GitLab From 70c91a384918736afee13104eea059cc7c8728a1 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 26 Jan 2010 14:00:40 +0300 Subject: [PATCH 124/370] ARM: IMX31: configure pins iomux for SDHC setup on litekit board. This patch adds SDHC support, and corrects current pins setup. Added irq handling on card removal. Signed-off-by: Vladimir Zapolskiy Cc: Daniel Mack Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite-db.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 694611d6b0576..ccd874225c3b6 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = { MX31_PIN_CSPI1_SS0__SS0, MX31_PIN_CSPI1_SS1__SS1, MX31_PIN_CSPI1_SS2__SS2, + /* SDHC1 */ + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, }; /* UART */ @@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = { static int gpio_det, gpio_wp; #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + PAD_CTL_ODE_CMOS) static int mxc_mmc1_get_ro(struct device *dev) { - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); + return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6)); } static int mxc_mmc1_init(struct device *dev, @@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev, gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); ret = gpio_request(gpio_det, "MMC detect"); if (ret) @@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev, gpio_direction_input(gpio_wp); ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC detect", data); if (ret) goto exit_free_wp; @@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) { gpio_free(gpio_det); gpio_free(gpio_wp); - free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); + free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); } static struct imxmmc_platform_data mmc_pdata = { -- GitLab From e96b234b7e9d24e50528287b881ca229b7f094b8 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 25 Jan 2010 14:24:04 +0900 Subject: [PATCH 125/370] ARM: S5P6440: Move CPU specific code in plat-s5p to machine directory The s5p6440-clock.c and s5p6440-init.c code in the plat-s5p is specific to s5p6440 SoC based systems. So these files are being moved to the machine directory of s5p6440. And these files are renamed in the machine directory. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/Kconfig | 2 -- arch/arm/mach-s5p6440/Makefile | 2 +- .../s5p6440-clock.c => mach-s5p6440/clock.c} | 2 +- arch/arm/mach-s5p6440/{s5p6440-gpio.c => gpio.c} | 2 +- .../s5p6440-init.c => mach-s5p6440/init.c} | 4 +++- arch/arm/plat-s5p/Kconfig | 16 ---------------- arch/arm/plat-s5p/Makefile | 5 ----- 7 files changed, 6 insertions(+), 27 deletions(-) rename arch/arm/{plat-s5p/s5p6440-clock.c => mach-s5p6440/clock.c} (99%) rename arch/arm/mach-s5p6440/{s5p6440-gpio.c => gpio.c} (99%) rename arch/arm/{plat-s5p/s5p6440-init.c => mach-s5p6440/init.c} (94%) diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index 3aa246244dcf4..4c29ff8b07de0 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig @@ -9,8 +9,6 @@ if ARCH_S5P6440 config CPU_S5P6440 bool - select CPU_S5P6440_INIT - select CPU_S5P6440_CLOCK help Enable S5P6440 CPU support diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index a79b13011edc1..1ad894b1d3ab8 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile @@ -12,7 +12,7 @@ obj- := # Core support for S5P6440 system -obj-$(CONFIG_CPU_S5P6440) += cpu.o s5p6440-gpio.o +obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o # machine support diff --git a/arch/arm/plat-s5p/s5p6440-clock.c b/arch/arm/mach-s5p6440/clock.c similarity index 99% rename from arch/arm/plat-s5p/s5p6440-clock.c rename to arch/arm/mach-s5p6440/clock.c index 2f412f8c1212a..b2672e16e7aa6 100644 --- a/arch/arm/plat-s5p/s5p6440-clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/s5p6440-clock.c +/* linux/arch/arm/mach-s5p6440/clock.c * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/mach-s5p6440/s5p6440-gpio.c b/arch/arm/mach-s5p6440/gpio.c similarity index 99% rename from arch/arm/mach-s5p6440/s5p6440-gpio.c rename to arch/arm/mach-s5p6440/gpio.c index 742264c29f2a5..b0ea741177ad1 100644 --- a/arch/arm/mach-s5p6440/s5p6440-gpio.c +++ b/arch/arm/mach-s5p6440/gpio.c @@ -1,4 +1,4 @@ -/* arch/arm/mach-s5p6440/s5p6440-gpio.c +/* arch/arm/mach-s5p6440/gpio.c * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/plat-s5p/s5p6440-init.c b/arch/arm/mach-s5p6440/init.c similarity index 94% rename from arch/arm/plat-s5p/s5p6440-init.c rename to arch/arm/mach-s5p6440/init.c index 90178256cc281..a1f3727e40214 100644 --- a/arch/arm/plat-s5p/s5p6440-init.c +++ b/arch/arm/mach-s5p6440/init.c @@ -1,8 +1,10 @@ -/* linux/arch/arm/plat-s5p/s5p6440-init.c +/* linux/arch/arm/mach-s5p6440/init.c * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * + * S5P6440 - Init support + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index e7c31e7060e58..fca6dade9fd9c 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -24,19 +24,3 @@ config PLAT_S5P select SAMSUNG_IRQ_UART help Base platform code for Samsung's S5P series SoC. - -if (PLAT_S5P && ARCH_S5P6440) - -# Configuration options shared by all S5P64XX implementations - -config CPU_S5P6440_INIT - bool - help - Initialisation code for the S5P6440. - -config CPU_S5P6440_CLOCK - bool - help - Clock support code for the S5P6440. - -endif diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 92b6474505423..a7c54b332d275 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -17,8 +17,3 @@ obj-y += cpu.o obj-y += clock.o obj-y += irq.o obj-y += setup-i2c0.o - -# CPU support - -obj-$(CONFIG_CPU_S5P6440_INIT) += s5p6440-init.o -obj-$(CONFIG_CPU_S5P6440_CLOCK) += s5p6440-clock.o -- GitLab From 81317960466ebd37fd958aa07993e3fea461dbe4 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 27 Jan 2010 16:57:07 +0900 Subject: [PATCH 126/370] ARM: S5P6440: Move common memory map definitions for S5P 1. Moved common memory map definitions for S5P such as S5P_VA_XXX into plat-s5p/include/mach/map-s5p.h from mach-s5p6440/include/mach. 2. Removed unnecessary definitions in the map.h and irq.c 3. Removed the unnecessary support for unaligned UART address 4. Renamed S5P_VA_VICx definitions as VA_VICx 5. Moved the definitons of VIC_BASE to plat-s5p/include/plat/irqs.h Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- .../mach-s5p6440/include/mach/debug-macro.S | 4 +- arch/arm/mach-s5p6440/include/mach/map.h | 65 ++++--------------- .../mach-s5p6440/include/mach/regs-clock.h | 2 +- arch/arm/mach-s5p6440/include/mach/tick.h | 2 +- arch/arm/mach-s5p6440/mach-smdk6440.c | 4 +- arch/arm/plat-s5p/cpu.c | 19 +++--- arch/arm/plat-s5p/include/plat/irqs.h | 2 + arch/arm/plat-s5p/include/plat/map-s5p.h | 32 +++++++++ arch/arm/plat-s5p/irq.c | 5 +- 9 files changed, 65 insertions(+), 70 deletions(-) create mode 100644 arch/arm/plat-s5p/include/plat/map-s5p.h diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S index f3a5d1635be5b..48cdb0da026c1 100644 --- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S +++ b/arch/arm/mach-s5p6440/include/mach/debug-macro.S @@ -22,8 +22,8 @@ .macro addruart, rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 - ldreq \rx, = S5P_PA_UART - ldrne \rx, = (S5P_VA_UART + S5P_PA_UART & 0xfffff) + ldreq \rx, = S3C_PA_UART + ldrne \rx, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) #endif diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 4a73e73c9428a..8924e5a4d6a63 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -14,94 +14,55 @@ #define __ASM_ARCH_MAP_H __FILE__ #include +#include -/* Chip ID */ #define S5P6440_PA_CHIPID (0xE0000000) #define S5P_PA_CHIPID S5P6440_PA_CHIPID -#define S5P_VA_CHIPID S3C_ADDR(0x00700000) -/* SYSCON */ #define S5P6440_PA_SYSCON (0xE0100000) -#define S5P_PA_SYSCON S5P6440_PA_SYSCON -#define S5P_VA_SYSCON S3C_VA_SYS - #define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0) -#define S5P_PA_CLK S5P6440_PA_CLK -#define S5P_VA_CLK (S5P_VA_SYSCON + 0x0) +#define S5P_PA_SYSCON S5P6440_PA_SYSCON -/* GPIO */ #define S5P6440_PA_GPIO (0xE0308000) #define S5P_PA_GPIO S5P6440_PA_GPIO -#define S5P_VA_GPIO S3C_ADDR(0x00500000) -/* VIC0 */ #define S5P6440_PA_VIC0 (0xE4000000) #define S5P_PA_VIC0 S5P6440_PA_VIC0 -#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) -#define VA_VIC0 S5P_VA_VIC0 -/* VIC1 */ #define S5P6440_PA_VIC1 (0xE4100000) #define S5P_PA_VIC1 S5P6440_PA_VIC1 -#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) -#define VA_VIC1 S5P_VA_VIC1 -/* Timer */ #define S5P6440_PA_TIMER (0xEA000000) #define S5P_PA_TIMER S5P6440_PA_TIMER -#define S5P_VA_TIMER S3C_VA_TIMER -/* RTC */ #define S5P6440_PA_RTC (0xEA100000) #define S5P_PA_RTC S5P6440_PA_RTC -#define S5P_VA_RTC S3C_ADDR(0x00600000) -/* WDT */ #define S5P6440_PA_WDT (0xEA200000) #define S5P_PA_WDT S5P6440_PA_WDT -#define S5p_VA_WDT S3C_VA_WATCHDOG -/* UART */ #define S5P6440_PA_UART (0xEC000000) -#define S5P_PA_UART S5P6440_PA_UART -#define S5P_VA_UART S3C_VA_UART -/* HS USB OtG */ +#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0) +#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400) +#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800) +#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00) + +#define S5P_SZ_UART SZ_256 + +#define S5P6440_PA_IIC0 (0xEC104000) + #define S5P6440_PA_HSOTG (0xED100000) -/* HSMMC */ #define S5P6440_PA_HSMMC0 (0xED800000) #define S5P6440_PA_HSMMC1 (0xED900000) #define S5P6440_PA_HSMMC2 (0xEDA00000) -#define S5P_PA_UART0 (S5P_PA_UART + 0x0) -#define S5P_PA_UART1 (S5P_PA_UART + 0x400) -#define S5P_PA_UART2 (S5P_PA_UART + 0x800) -#define S5P_PA_UART3 (S5P_PA_UART + 0xC00) -#define S5P_UART_OFFSET (0x400) - -#define S5P_VA_UARTx(x) (S5P_VA_UART + (S5P_PA_UART & 0xfffff) \ - + ((x) * S5P_UART_OFFSET)) - -#define S5P_VA_UART0 S5P_VA_UARTx(0) -#define S5P_VA_UART1 S5P_VA_UARTx(1) -#define S5P_VA_UART2 S5P_VA_UARTx(2) -#define S5P_VA_UART3 S5P_VA_UARTx(3) -#define S5P_SZ_UART SZ_256 - -/* I2C */ -#define S5P6440_PA_IIC0 (0xEC104000) -#define S5P_PA_IIC0 S5P6440_PA_IIC0 -#define S5p_VA_IIC0 S3C_ADDR(0x00700000) - -/* SDRAM */ #define S5P6440_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5P6440_PA_SDRAM /* compatibiltiy defines. */ -#define S3C_PA_UART S5P_PA_UART -#define S3C_UART_OFFSET S5P_UART_OFFSET -#define S3C_PA_TIMER S5P_PA_TIMER -#define S3C_PA_IIC S5P_PA_IIC0 +#define S3C_PA_UART S5P6440_PA_UART +#define S3C_PA_IIC S5P6440_PA_IIC0 #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h index b7af28342bc47..c783ecc9f1930 100644 --- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h +++ b/arch/arm/mach-s5p6440/include/mach/regs-clock.h @@ -15,7 +15,7 @@ #include -#define S5P_CLKREG(x) (S5P_VA_CLK + (x)) +#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) #define S5P_APLL_LOCK S5P_CLKREG(0x00) #define S5P_MPLL_LOCK S5P_CLKREG(0x04) diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p6440/include/mach/tick.h index 0815aeb4f2cf7..2f25c7f079700 100644 --- a/arch/arm/mach-s5p6440/include/mach/tick.h +++ b/arch/arm/mach-s5p6440/include/mach/tick.h @@ -15,7 +15,7 @@ static inline u32 s3c24xx_ostimer_pending(void) { - u32 pend = __raw_readl(S5P_VA_VIC0 + VIC_RAW_STATUS); + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); } diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index 760ea5424a785..3ae88f2c7c77a 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -100,8 +100,8 @@ static void __init smdk6440_machine_init(void) MACHINE_START(SMDK6440, "SMDK6440") /* Maintainer: Kukjin Kim */ - .phys_io = S5P_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S5P_VA_UART) >> 18) & 0xfffc, + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = s5p6440_init_irq, diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 0895a77a28359..ee9c6b302dedf 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -37,31 +37,34 @@ static struct cpu_table cpu_ids[] __initdata = { /* minimal IO mapping */ -#define UART_OFFS (S5P_PA_UART & 0xfffff) - static struct map_desc s5p_iodesc[] __initdata = { { - .virtual = (unsigned long)S5P_VA_SYSCON, + .virtual = (unsigned long)S5P_VA_CHIPID, + .pfn = __phys_to_pfn(S5P_PA_CHIPID), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_SYS, .pfn = __phys_to_pfn(S5P_PA_SYSCON), .length = SZ_64K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)(S5P_VA_UART + UART_OFFS), - .pfn = __phys_to_pfn(S5P_PA_UART), + .virtual = (unsigned long)S3C_VA_UART, + .pfn = __phys_to_pfn(S3C_PA_UART), .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_VIC0, + .virtual = (unsigned long)VA_VIC0, .pfn = __phys_to_pfn(S5P_PA_VIC0), .length = SZ_16K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_VIC1, + .virtual = (unsigned long)VA_VIC1, .pfn = __phys_to_pfn(S5P_PA_VIC1), .length = SZ_16K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_TIMER, + .virtual = (unsigned long)S3C_VA_TIMER, .pfn = __phys_to_pfn(S5P_PA_TIMER), .length = SZ_16K, .type = MT_DEVICE, diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 5d7937dddad2a..878acfe3690f6 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -29,6 +29,8 @@ #define S5P_VIC0_BASE S5P_IRQ(0) #define S5P_VIC1_BASE S5P_IRQ(32) +#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) + #define IRQ_VIC0_BASE S5P_VIC0_BASE #define IRQ_VIC1_BASE S5P_VIC1_BASE diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h new file mode 100644 index 0000000000000..51d9cb5a3e2bf --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_MAP_S5P_H +#define __ASM_PLAT_MAP_S5P_H __FILE__ + +#define S5P_VA_CHIPID S3C_ADDR(0x00700000) +#define S5P_VA_GPIO S3C_ADDR(0x00500000) +#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) +#define S5P_VA_SROMC S3C_ADDR(0x01100000) + +#define S5P_VA_UART0 (S3C_VA_UART + 0x0) +#define S5P_VA_UART1 (S3C_VA_UART + 0x400) +#define S5P_VA_UART2 (S3C_VA_UART + 0x800) +#define S5P_VA_UART3 (S3C_VA_UART + 0xC00) + +#define S3C_UART_OFFSET (0x400) + +#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) +#define VA_VIC0 VA_VIC(0) +#define VA_VIC1 VA_VIC(1) + +#endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index eada40d0847d4..11535a5f534e6 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -25,9 +25,6 @@ #include #include -#define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000)) -#define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32)) - /* * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. @@ -61,7 +58,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) /* initialize the VICs */ for (irq = 0; irq < num_vic; irq++) - vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0); + vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); -- GitLab From 87aef30eb3c5dac0491c83fe3b90bc61f1df24ec Mon Sep 17 00:00:00 2001 From: Atul Dahiya Date: Fri, 29 Jan 2010 09:08:28 +0900 Subject: [PATCH 127/370] ARM: S5P: Change S5P_TIMER_IRQ based to 11 for SAMSUNG S5P series. Currently, S5P_TIMER_IRQ is based at the end of VICs. This patch changes the S5P_TIMER_IRQ base from end of VICs to 11 in ISA IRQ space. No of VICs varies between SOCs. This causes an exception on S5P6442. Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5p/include/plat/irqs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 878acfe3690f6..101038d499440 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -74,7 +74,7 @@ #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) -#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x)) +#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) #define IRQ_TIMER0 S5P_TIMER_IRQ(0) #define IRQ_TIMER1 S5P_TIMER_IRQ(1) -- GitLab From dcbabbc1fce2c32e4cfe0e18a2651226a72ecaae Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 27 Jan 2010 15:00:48 +0200 Subject: [PATCH 128/370] mx25: add support for the DryIce rtc Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 2 ++ arch/arm/mach-mx25/devices.c | 19 +++++++++++++++++++ arch/arm/mach-mx25/devices.h | 1 + arch/arm/plat-mxc/include/mach/mx25.h | 2 ++ 4 files changed, 24 insertions(+) diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 6acc88bcdc403..744b52a613fc7 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -182,6 +182,7 @@ DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); +DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -214,6 +215,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) }; int __init mx25_clocks_init(void) diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index dd4069725ef5a..b0b75fc99058f 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -458,3 +458,22 @@ struct platform_device mxc_nand_device = { .num_resources = ARRAY_SIZE(mxc_nand_resources), .resource = mxc_nand_resources, }; + +static struct resource mx25_rtc_resources[] = { + { + .start = MX25_DRYICE_BASE_ADDR, + .end = MX25_DRYICE_BASE_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_DRYICE, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mx25_rtc_device = { + .name = "imxdi_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(mx25_rtc_resources), + .resource = mx25_rtc_resources, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index 8f5530062b435..37e6a08214470 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -19,3 +19,4 @@ extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; extern struct platform_device mxc_nand_device; +extern struct platform_device mx25_rtc_device; diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 021d208e86bc0..61052a33979c9 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -32,7 +32,9 @@ #define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_NFC_BASE_ADDR 0xbb000000 +#define MX25_DRYICE_BASE_ADDR 0x53ffc000 +#define MX25_INT_DRYICE 25 #define MX25_INT_FEC 57 #define MX25_INT_NANDFC 33 -- GitLab From 1eaa4f2762899d2f3c54ba7a4fee564e255ad0a5 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 27 Jan 2010 15:00:49 +0200 Subject: [PATCH 129/370] mx25pdk: platform code for the DryIce RTC module Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/mx25pdk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c index 232f9caa7dd90..f4e8b984af725 100644 --- a/arch/arm/mach-mx25/mx25pdk.c +++ b/arch/arm/mach-mx25/mx25pdk.c @@ -91,6 +91,7 @@ static void __init mx25pdk_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_usbh2, NULL); mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); + mxc_register_device(&mx25_rtc_device, NULL); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); -- GitLab From 4ec07bba6945290c48dcc5b789cbd7adeabd7695 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 15:02:58 +0900 Subject: [PATCH 130/370] ARM: S3C2443: Use common clock gate code Add common clock gate code for each of the S3C2443 clock gate code. Whether to move this elsewhere will be decided later. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 48 ++++++++++------------------------- 1 file changed, 13 insertions(+), 35 deletions(-) diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 3eb8b935d64c2..5d061ea0c5137 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -53,55 +53,33 @@ * set the correct muxing at initialisation */ -static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) +static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_HCLKCON); + u32 ctrlbit = clk->ctrlbit; + u32 con = __raw_readl(reg); if (enable) - clkcon |= clocks; + con |= ctrlbit; else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_HCLKCON); + con &= ~ctrlbit; + __raw_writel(con, reg); return 0; } -static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_PCLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_PCLKCON); + return s3c2443_gate(S3C2443_HCLKCON, clk, enable); +} - return 0; +static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +{ + return s3c2443_gate(S3C2443_PCLKCON, clk, enable); } static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_SCLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_SCLKCON); - - return 0; + return s3c2443_gate(S3C2443_SCLKCON, clk, enable); } static unsigned long s3c2443_roundrate_clksrc(struct clk *clk, -- GitLab From 7d58289fc315258b4829a29d21c540eb35dd6feb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 11 Jan 2010 11:37:24 +0100 Subject: [PATCH 131/370] mx1: prefix SOC specific defines with MX1_ and deprecate old names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are defined only if the cpp symbol IMX_NEEDS_DEPRECATED_SYMBOLS exists, which is defined (for now) for all files below arch/arm/mach-mx1. This was done earlier for mx2 and mx3, too. USBD_INT0 is for now defined unconditionally to prevent breaking drivers/usb/gadget/imx_udc. While at it use IMX_IO_ADDRESS to define MX1_IO_ADDRESS which adds a cast to the IO_ADDRESS macro fixing many warnings like arch/arm/mach-mx1/generic.c:51: warning: passing argument 1 of 'mxc_init_irq' makes pointer from integer without a cast . Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx1/Makefile | 1 + arch/arm/plat-mxc/include/mach/mx1.h | 387 ++++++++++++++++++--------- 2 files changed, 261 insertions(+), 127 deletions(-) diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index 297d17210e116..fc2ddf82441b6 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile @@ -4,6 +4,7 @@ # Object file lists. +EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-y += generic.o clock.o devices.o # Support for CMOS sensor interface diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b652a9c25865b..5eba7e6785dec 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -17,148 +17,281 @@ /* * Memory map */ -#define IMX_IO_PHYS 0x00200000 -#define IMX_IO_SIZE 0x00100000 -#define IMX_IO_BASE VMALLOC_END +#define MX1_IO_BASE_ADDR 0x00200000 +#define MX1_IO_SIZE SZ_1M +#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END -#define IMX_CS0_PHYS 0x10000000 -#define IMX_CS0_SIZE 0x02000000 +#define MX1_CS0_PHYS 0x10000000 +#define MX1_CS0_SIZE 0x02000000 -#define IMX_CS1_PHYS 0x12000000 -#define IMX_CS1_SIZE 0x01000000 +#define MX1_CS1_PHYS 0x12000000 +#define MX1_CS1_SIZE 0x01000000 -#define IMX_CS2_PHYS 0x13000000 -#define IMX_CS2_SIZE 0x01000000 +#define MX1_CS2_PHYS 0x13000000 +#define MX1_CS2_SIZE 0x01000000 -#define IMX_CS3_PHYS 0x14000000 -#define IMX_CS3_SIZE 0x01000000 +#define MX1_CS3_PHYS 0x14000000 +#define MX1_CS3_SIZE 0x01000000 -#define IMX_CS4_PHYS 0x15000000 -#define IMX_CS4_SIZE 0x01000000 +#define MX1_CS4_PHYS 0x15000000 +#define MX1_CS4_SIZE 0x01000000 -#define IMX_CS5_PHYS 0x16000000 -#define IMX_CS5_SIZE 0x01000000 +#define MX1_CS5_PHYS 0x16000000 +#define MX1_CS5_SIZE 0x01000000 /* * Register BASEs, based on OFFSETs */ -#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) -#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) -#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) -#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) -#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) -#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) -#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) -#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) -#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) -#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) -#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) -#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) -#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) -#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) -#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) -#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) -#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) -#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) -#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) -#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) -#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) -#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) -#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) -#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) -#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) -#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) -#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) -#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) -#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) +#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) +#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) +#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) +#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) +#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) +#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) +#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) +#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) +#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) +#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) +#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) +#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) +#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) +#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) +#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) +#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) +#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) +#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) +#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) +#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) +#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) +#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) +#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) +#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) +#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) +#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) - -/* define macros needed for entry-macro.S */ -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define MX1_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX1_IO)) /* fixed interrput numbers */ -#define INT_SOFTINT 0 -#define CSI_INT 6 -#define DSPA_MAC_INT 7 -#define DSPA_INT 8 -#define COMP_INT 9 -#define MSHC_XINT 10 -#define GPIO_INT_PORTA 11 -#define GPIO_INT_PORTB 12 -#define GPIO_INT_PORTC 13 -#define LCDC_INT 14 -#define SIM_INT 15 -#define SIM_DATA_INT 16 -#define RTC_INT 17 -#define RTC_SAMINT 18 -#define UART2_MINT_PFERR 19 -#define UART2_MINT_RTS 20 -#define UART2_MINT_DTR 21 -#define UART2_MINT_UARTC 22 -#define UART2_MINT_TX 23 -#define UART2_MINT_RX 24 -#define UART1_MINT_PFERR 25 -#define UART1_MINT_RTS 26 -#define UART1_MINT_DTR 27 -#define UART1_MINT_UARTC 28 -#define UART1_MINT_TX 29 -#define UART1_MINT_RX 30 -#define VOICE_DAC_INT 31 -#define VOICE_ADC_INT 32 -#define PEN_DATA_INT 33 -#define PWM_INT 34 -#define SDHC_INT 35 -#define I2C_INT 39 -#define CSPI_INT 41 -#define SSI_TX_INT 42 -#define SSI_TX_ERR_INT 43 -#define SSI_RX_INT 44 -#define SSI_RX_ERR_INT 45 -#define TOUCH_INT 46 -#define USBD_INT0 47 -#define USBD_INT1 48 -#define USBD_INT2 49 -#define USBD_INT3 50 -#define USBD_INT4 51 -#define USBD_INT5 52 -#define USBD_INT6 53 -#define BTSYS_INT 55 -#define BTTIM_INT 56 -#define BTWUI_INT 57 -#define TIM2_INT 58 -#define TIM1_INT 59 -#define DMA_ERR 60 -#define DMA_INT 61 -#define GPIO_INT_PORTD 62 -#define WDT_INT 63 +#define MX1_INT_SOFTINT 0 +#define MX1_CSI_INT 6 +#define MX1_DSPA_MAC_INT 7 +#define MX1_DSPA_INT 8 +#define MX1_COMP_INT 9 +#define MX1_MSHC_XINT 10 +#define MX1_GPIO_INT_PORTA 11 +#define MX1_GPIO_INT_PORTB 12 +#define MX1_GPIO_INT_PORTC 13 +#define MX1_LCDC_INT 14 +#define MX1_SIM_INT 15 +#define MX1_SIM_DATA_INT 16 +#define MX1_RTC_INT 17 +#define MX1_RTC_SAMINT 18 +#define MX1_UART2_MINT_PFERR 19 +#define MX1_UART2_MINT_RTS 20 +#define MX1_UART2_MINT_DTR 21 +#define MX1_UART2_MINT_UARTC 22 +#define MX1_UART2_MINT_TX 23 +#define MX1_UART2_MINT_RX 24 +#define MX1_UART1_MINT_PFERR 25 +#define MX1_UART1_MINT_RTS 26 +#define MX1_UART1_MINT_DTR 27 +#define MX1_UART1_MINT_UARTC 28 +#define MX1_UART1_MINT_TX 29 +#define MX1_UART1_MINT_RX 30 +#define MX1_VOICE_DAC_INT 31 +#define MX1_VOICE_ADC_INT 32 +#define MX1_PEN_DATA_INT 33 +#define MX1_PWM_INT 34 +#define MX1_SDHC_INT 35 +#define MX1_I2C_INT 39 +#define MX1_CSPI_INT 41 +#define MX1_SSI_TX_INT 42 +#define MX1_SSI_TX_ERR_INT 43 +#define MX1_SSI_RX_INT 44 +#define MX1_SSI_RX_ERR_INT 45 +#define MX1_TOUCH_INT 46 +#define MX1_USBD_INT0 47 +#define MX1_USBD_INT1 48 +#define MX1_USBD_INT2 49 +#define MX1_USBD_INT3 50 +#define MX1_USBD_INT4 51 +#define MX1_USBD_INT5 52 +#define MX1_USBD_INT6 53 +#define MX1_BTSYS_INT 55 +#define MX1_BTTIM_INT 56 +#define MX1_BTWUI_INT 57 +#define MX1_TIM2_INT 58 +#define MX1_TIM1_INT 59 +#define MX1_DMA_ERR 60 +#define MX1_DMA_INT 61 +#define MX1_GPIO_INT_PORTD 62 +#define MX1_WDT_INT 63 /* DMA */ -#define DMA_REQ_UART3_T 2 -#define DMA_REQ_UART3_R 3 -#define DMA_REQ_SSI2_T 4 -#define DMA_REQ_SSI2_R 5 -#define DMA_REQ_CSI_STAT 6 -#define DMA_REQ_CSI_R 7 -#define DMA_REQ_MSHC 8 -#define DMA_REQ_DSPA_DCT_DOUT 9 -#define DMA_REQ_DSPA_DCT_DIN 10 -#define DMA_REQ_DSPA_MAC 11 -#define DMA_REQ_EXT 12 -#define DMA_REQ_SDHC 13 -#define DMA_REQ_SPI1_R 14 -#define DMA_REQ_SPI1_T 15 -#define DMA_REQ_SSI_T 16 -#define DMA_REQ_SSI_R 17 -#define DMA_REQ_ASP_DAC 18 -#define DMA_REQ_ASP_ADC 19 -#define DMA_REQ_USP_EP(x) (20 + (x)) -#define DMA_REQ_SPI2_R 26 -#define DMA_REQ_SPI2_T 27 -#define DMA_REQ_UART2_T 28 -#define DMA_REQ_UART2_R 29 -#define DMA_REQ_UART1_T 30 -#define DMA_REQ_UART1_R 31 +#define MX1_DMA_REQ_UART3_T 2 +#define MX1_DMA_REQ_UART3_R 3 +#define MX1_DMA_REQ_SSI2_T 4 +#define MX1_DMA_REQ_SSI2_R 5 +#define MX1_DMA_REQ_CSI_STAT 6 +#define MX1_DMA_REQ_CSI_R 7 +#define MX1_DMA_REQ_MSHC 8 +#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 +#define MX1_DMA_REQ_DSPA_DCT_DIN 10 +#define MX1_DMA_REQ_DSPA_MAC 11 +#define MX1_DMA_REQ_EXT 12 +#define MX1_DMA_REQ_SDHC 13 +#define MX1_DMA_REQ_SPI1_R 14 +#define MX1_DMA_REQ_SPI1_T 15 +#define MX1_DMA_REQ_SSI_T 16 +#define MX1_DMA_REQ_SSI_R 17 +#define MX1_DMA_REQ_ASP_DAC 18 +#define MX1_DMA_REQ_ASP_ADC 19 +#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) +#define MX1_DMA_REQ_SPI2_R 26 +#define MX1_DMA_REQ_SPI2_T 27 +#define MX1_DMA_REQ_UART2_T 28 +#define MX1_DMA_REQ_UART2_R 29 +#define MX1_DMA_REQ_UART1_T 30 +#define MX1_DMA_REQ_UART1_R 31 + +/* + * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS + * to not break drivers/usb/gadget/imx_udc. Should go + * away after this driver uses the new name. + */ +#define USBD_INT0 MX1_USBD_INT0 + +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS +/* these should go away */ +#define IMX_IO_PHYS MX1_IO_BASE_ADDR +#define IMX_IO_SIZE MX1_IO_SIZE +#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT +#define IMX_CS0_PHYS MX1_CS0_PHYS +#define IMX_CS0_SIZE MX1_CS0_SIZE +#define IMX_CS1_PHYS MX1_CS1_PHYS +#define IMX_CS1_SIZE MX1_CS1_SIZE +#define IMX_CS2_PHYS MX1_CS2_PHYS +#define IMX_CS2_SIZE MX1_CS2_SIZE +#define IMX_CS3_PHYS MX1_CS3_PHYS +#define IMX_CS3_SIZE MX1_CS3_SIZE +#define IMX_CS4_PHYS MX1_CS4_PHYS +#define IMX_CS4_SIZE MX1_CS4_SIZE +#define IMX_CS5_PHYS MX1_CS5_PHYS +#define IMX_CS5_SIZE MX1_CS5_SIZE +#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR +#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR +#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR +#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR +#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR +#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR +#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR +#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR +#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR +#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR +#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR +#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR +#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR +#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR +#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR +#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR +#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR +#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR +#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR +#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR +#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR +#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR +#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR +#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR +#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR +#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR +#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR +#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR +#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) +#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define INT_SOFTINT MX1_INT_SOFTINT +#define CSI_INT MX1_CSI_INT +#define DSPA_MAC_INT MX1_DSPA_MAC_INT +#define DSPA_INT MX1_DSPA_INT +#define COMP_INT MX1_COMP_INT +#define MSHC_XINT MX1_MSHC_XINT +#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA +#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB +#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC +#define LCDC_INT MX1_LCDC_INT +#define SIM_INT MX1_SIM_INT +#define SIM_DATA_INT MX1_SIM_DATA_INT +#define RTC_INT MX1_RTC_INT +#define RTC_SAMINT MX1_RTC_SAMINT +#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR +#define UART2_MINT_RTS MX1_UART2_MINT_RTS +#define UART2_MINT_DTR MX1_UART2_MINT_DTR +#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC +#define UART2_MINT_TX MX1_UART2_MINT_TX +#define UART2_MINT_RX MX1_UART2_MINT_RX +#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR +#define UART1_MINT_RTS MX1_UART1_MINT_RTS +#define UART1_MINT_DTR MX1_UART1_MINT_DTR +#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC +#define UART1_MINT_TX MX1_UART1_MINT_TX +#define UART1_MINT_RX MX1_UART1_MINT_RX +#define VOICE_DAC_INT MX1_VOICE_DAC_INT +#define VOICE_ADC_INT MX1_VOICE_ADC_INT +#define PEN_DATA_INT MX1_PEN_DATA_INT +#define PWM_INT MX1_PWM_INT +#define SDHC_INT MX1_SDHC_INT +#define I2C_INT MX1_I2C_INT +#define CSPI_INT MX1_CSPI_INT +#define SSI_TX_INT MX1_SSI_TX_INT +#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT +#define SSI_RX_INT MX1_SSI_RX_INT +#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT +#define TOUCH_INT MX1_TOUCH_INT +#define USBD_INT1 MX1_USBD_INT1 +#define USBD_INT2 MX1_USBD_INT2 +#define USBD_INT3 MX1_USBD_INT3 +#define USBD_INT4 MX1_USBD_INT4 +#define USBD_INT5 MX1_USBD_INT5 +#define USBD_INT6 MX1_USBD_INT6 +#define BTSYS_INT MX1_BTSYS_INT +#define BTTIM_INT MX1_BTTIM_INT +#define BTWUI_INT MX1_BTWUI_INT +#define TIM2_INT MX1_TIM2_INT +#define TIM1_INT MX1_TIM1_INT +#define DMA_ERR MX1_DMA_ERR +#define DMA_INT MX1_DMA_INT +#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD +#define WDT_INT MX1_WDT_INT +#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T +#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R +#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T +#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R +#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT +#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R +#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC +#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT +#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN +#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC +#define DMA_REQ_EXT MX1_DMA_REQ_EXT +#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC +#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R +#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T +#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T +#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R +#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC +#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC +#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) +#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R +#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T +#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T +#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R +#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T +#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R +#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ #endif /* ifndef __MACH_MX1_H__ */ -- GitLab From 66ac2f28b658f1938035966cafc42501758b4324 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Jan 2010 17:55:16 +0100 Subject: [PATCH 132/370] mx25: deprecate UART1_BASE_ADDR and UART2_BASE_ADDR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx25.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 61052a33979c9..4ef9d5332b4a8 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -27,8 +27,8 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) -#define UART1_BASE_ADDR 0x43f90000 -#define UART2_BASE_ADDR 0x43f94000 +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX25_UART2_BASE_ADDR 0x43f94000 #define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_NFC_BASE_ADDR 0xbb000000 @@ -38,4 +38,9 @@ #define MX25_INT_FEC 57 #define MX25_INT_NANDFC 33 +#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) +#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR +#endif + #endif /* ifndef __MACH_MX25_H__ */ -- GitLab From 5cbcccb370355d4cd8534796bf32ac8bb04627cc Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:06:46 +0900 Subject: [PATCH 133/370] ARM: S3C24XX: Merge s3c2442 and s3c2440 machines into mach-s3c2440 Move the pair of machines in arch/arm/mach-s3c2442 into the mach-s3c2440 directory as the S3C2440 and S3C2442 are very close. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/Kconfig | 20 +++++++++++++++-- arch/arm/mach-s3c2440/Makefile | 1 + .../include/mach/gta02.h | 0 .../mach-gta02.c | 0 arch/arm/mach-s3c2442/Kconfig | 22 ------------------- arch/arm/mach-s3c2442/Makefile | 2 -- 6 files changed, 19 insertions(+), 26 deletions(-) rename arch/arm/{mach-s3c2442 => mach-s3c2440}/include/mach/gta02.h (100%) rename arch/arm/{mach-s3c2442 => mach-s3c2440}/mach-gta02.c (100%) diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 80879358eb2f0..5486929dc3d0c 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -21,8 +21,7 @@ config S3C2440_DMA help Support for S3C2440 specific DMA code5A - -menu "S3C2440 Machines" +menu "S3C2440 and S3C2442 Machines" config MACH_ANUBIS bool "Simtec Electronics ANUBIS" @@ -37,6 +36,18 @@ config MACH_ANUBIS Say Y here if you are using the Simtec Electronics ANUBIS development system +config MACH_NEO1973_GTA02 + bool "Openmoko GTA02 / Freerunner phone" + select CPU_S3C2442 + select MFD_PCF50633 + select PCF50633_GPIO + select I2C + select POWER_SUPPLY + select MACH_NEO1973 + select S3C2410_PWM + help + Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone + config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" select CPU_S3C2440 @@ -99,6 +110,11 @@ config SMDK2440_CPU2440 select S3C2440_XTAL_16934400 select CPU_S3C2440 +config SMDK2440_CPU2442 + bool "SMDM2440 with S3C2442 CPU module" + depends on ARCH_S3C2440 + select CPU_S3C2442 + config MACH_AT2440EVB bool "Avantech AT2440EVB development board" select CPU_S3C2440 diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index 5f32245318856..e51497ca12ea7 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o # extra machine support diff --git a/arch/arm/mach-s3c2442/include/mach/gta02.h b/arch/arm/mach-s3c2440/include/mach/gta02.h similarity index 100% rename from arch/arm/mach-s3c2442/include/mach/gta02.h rename to arch/arm/mach-s3c2440/include/mach/gta02.h diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c similarity index 100% rename from arch/arm/mach-s3c2442/mach-gta02.c rename to arch/arm/mach-s3c2440/mach-gta02.c diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index 8d3811852fc7e..4832cd6ccfbcb 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -13,25 +13,3 @@ config CPU_S3C2442 select CPU_LLSERIAL_S3C2440 help Support for S3C2442 Samsung Mobile CPU based systems. - - -menu "S3C2442 Machines" - -config SMDK2440_CPU2442 - bool "SMDM2440 with S3C2442 CPU module" - depends on ARCH_S3C2440 - select CPU_S3C2442 - -config MACH_NEO1973_GTA02 - bool "Openmoko GTA02 / Freerunner phone" - select CPU_S3C2442 - select MFD_PCF50633 - select PCF50633_GPIO - select I2C - select POWER_SUPPLY - select MACH_NEO1973 - select S3C2410_PWM - help - Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone - -endmenu diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile index 2a19113a57697..2a909c6c57987 100644 --- a/arch/arm/mach-s3c2442/Makefile +++ b/arch/arm/mach-s3c2442/Makefile @@ -12,7 +12,5 @@ obj- := obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C2442) += clock.o -obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o - # Machine support -- GitLab From 491547d43bc2393de914b5ad18b6f5219107f918 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:13:35 +0900 Subject: [PATCH 134/370] ARM: S3C2442: Merge s3c2442.c and clock.c Merge s3c2442.c and clock.c as the s3c242.c does not contain much and the clock parts are always built for s3c2442 anyway. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2442/Makefile | 1 - arch/arm/mach-s3c2442/clock.c | 153 -------------------------------- arch/arm/mach-s3c2442/s3c2442.c | 153 +++++++++++++++++++++++++++++--- 3 files changed, 142 insertions(+), 165 deletions(-) delete mode 100644 arch/arm/mach-s3c2442/clock.c diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile index 2a909c6c57987..7e31ccdc83de3 100644 --- a/arch/arm/mach-s3c2442/Makefile +++ b/arch/arm/mach-s3c2442/Makefile @@ -10,7 +10,6 @@ obj-n := obj- := obj-$(CONFIG_CPU_S3C2442) += s3c2442.o -obj-$(CONFIG_CPU_S3C2442) += clock.o # Machine support diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c deleted file mode 100644 index d9b692a124802..0000000000000 --- a/arch/arm/mach-s3c2442/clock.c +++ /dev/null @@ -1,153 +0,0 @@ -/* linux/arch/arm/mach-s3c2442/clock.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2442 Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -/* S3C2442 extended clock support */ - -static unsigned long s3c2442_camif_upll_round(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - - if (div == 3) - return parent_rate / 3; - - /* note, we remove the +/- 1 calculations for the divisor */ - - div /= 2; - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / (div * 2); -} - -static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - rate = s3c2442_camif_upll_round(clk, rate); - - camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; - - if (rate == parent_rate) { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; - } else if ((parent_rate / rate) == 3) { - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; - } else { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= (((parent_rate / rate) / 2) - 1); - } - - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -/* Extra S3C2442 clocks */ - -static struct clk s3c2442_clk_cam = { - .name = "camif", - .id = -1, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static struct clk s3c2442_clk_cam_upll = { - .name = "camif-upll", - .id = -1, - .ops = &(struct clk_ops) { - .set_rate = s3c2442_camif_upll_setrate, - .round_rate = s3c2442_camif_upll_round, - }, -}; - -static int s3c2442_clk_add(struct sys_device *sysdev) -{ - struct clk *clock_upll; - struct clk *clock_h; - struct clk *clock_p; - - clock_p = clk_get(NULL, "pclk"); - clock_h = clk_get(NULL, "hclk"); - clock_upll = clk_get(NULL, "upll"); - - if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); - return -EINVAL; - } - - s3c2442_clk_cam.parent = clock_h; - s3c2442_clk_cam_upll.parent = clock_upll; - - s3c24xx_register_clock(&s3c2442_clk_cam); - s3c24xx_register_clock(&s3c2442_clk_cam_upll); - - clk_disable(&s3c2442_clk_cam); - - return 0; -} - -static struct sysdev_driver s3c2442_clk_driver = { - .add = s3c2442_clk_add, -}; - -static __init int s3c2442_clk_init(void) -{ - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); -} - -arch_initcall(s3c2442_clk_init); diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2442/s3c2442.c index 4663bdc7fff6f..188ad1e57dc03 100644 --- a/arch/arm/mach-s3c2442/s3c2442.c +++ b/arch/arm/mach-s3c2442/s3c2442.c @@ -1,27 +1,158 @@ /* linux/arch/arm/mach-s3c2442/s3c2442.c * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks + * Copyright (c) 2004-2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks * - * Samsung S3C2442 Mobile CPU support + * S3C2442 core and lock support * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include +#include #include -#include -#include #include -#include -#include -#include +#include +#include +#include #include +#include +#include +#include +#include +#include -#include +#include +#include +#include + +#include + +#include #include +/* S3C2442 extended clock support */ + +static unsigned long s3c2442_camif_upll_round(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + div = parent_rate / rate; + + if (div == 3) + return parent_rate / 3; + + /* note, we remove the +/- 1 calculations for the divisor */ + + div /= 2; + + if (div < 1) + div = 1; + else if (div > 16) + div = 16; + + return parent_rate / (div * 2); +} + +static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + + rate = s3c2442_camif_upll_round(clk, rate); + + camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; + + if (rate == parent_rate) { + camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; + } else if ((parent_rate / rate) == 3) { + camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; + camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; + } else { + camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; + camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; + camdivn |= (((parent_rate / rate) / 2) - 1); + } + + __raw_writel(camdivn, S3C2440_CAMDIVN); + + return 0; +} + +/* Extra S3C2442 clocks */ + +static struct clk s3c2442_clk_cam = { + .name = "camif", + .id = -1, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2440_CLKCON_CAMERA, +}; + +static struct clk s3c2442_clk_cam_upll = { + .name = "camif-upll", + .id = -1, + .ops = &(struct clk_ops) { + .set_rate = s3c2442_camif_upll_setrate, + .round_rate = s3c2442_camif_upll_round, + }, +}; + +static int s3c2442_clk_add(struct sys_device *sysdev) +{ + struct clk *clock_upll; + struct clk *clock_h; + struct clk *clock_p; + + clock_p = clk_get(NULL, "pclk"); + clock_h = clk_get(NULL, "hclk"); + clock_upll = clk_get(NULL, "upll"); + + if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { + printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); + return -EINVAL; + } + + s3c2442_clk_cam.parent = clock_h; + s3c2442_clk_cam_upll.parent = clock_upll; + + s3c24xx_register_clock(&s3c2442_clk_cam); + s3c24xx_register_clock(&s3c2442_clk_cam_upll); + + clk_disable(&s3c2442_clk_cam); + + return 0; +} + +static struct sysdev_driver s3c2442_clk_driver = { + .add = s3c2442_clk_add, +}; + +static __init int s3c2442_clk_init(void) +{ + return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); +} + +arch_initcall(s3c2442_clk_init); + + static struct sys_device s3c2442_sysdev = { .cls = &s3c2442_sysclass, }; -- GitLab From 1f51bbfd5905b8c860cc95ae10c20e0844d0ade8 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:27:08 +0900 Subject: [PATCH 135/370] ARM: S3C2440: Fix SMDK2440 SoC selection Fix the entries for SMDK2440 should have allowed for S3C2440 or S3C2440 SoC selection but this depended on ARCH_S3C2440 which has not been around for a while. Remove the dependency to allow this to be selected. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 5486929dc3d0c..45cab7af5cdeb 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -105,14 +105,12 @@ config MACH_NEXCODER_2440 config SMDK2440_CPU2440 bool "SMDK2440 with S3C2440 CPU module" - depends on ARCH_S3C2440 default y if ARCH_S3C2440 select S3C2440_XTAL_16934400 select CPU_S3C2440 config SMDK2440_CPU2442 bool "SMDM2440 with S3C2442 CPU module" - depends on ARCH_S3C2440 select CPU_S3C2442 config MACH_AT2440EVB -- GitLab From 916ee9249a7f19d8eb18cc9ee16ca495a517ab34 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:31:32 +0900 Subject: [PATCH 136/370] ARM: S3C244X: Move S3C2442 code into S3C2440 Move the remaining S3C2442 code into mach-s3c2440 as there is only one file currently in there and these two SoCs are very similar. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/Kconfig | 12 ++++++++++++ arch/arm/mach-s3c2440/Makefile | 2 ++ arch/arm/{mach-s3c2442 => mach-s3c2440}/s3c2442.c | 0 arch/arm/mach-s3c2442/Kconfig | 11 ----------- 4 files changed, 14 insertions(+), 11 deletions(-) rename arch/arm/{mach-s3c2442 => mach-s3c2440}/s3c2442.c (100%) diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 45cab7af5cdeb..f496385e1c751 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -15,6 +15,18 @@ config CPU_S3C2440 help Support for S3C2440 Samsung Mobile CPU based systems. +config CPU_S3C2442 + bool + depends on ARCH_S3C2410 + select CPU_ARM920T + select S3C2410_CLOCK + select S3C2410_GPIO + select S3C2410_PM if PM + select CPU_S3C244X + select CPU_LLSERIAL_S3C2440 + help + Support for S3C2442 Samsung Mobile CPU based systems. + config S3C2440_DMA bool depends on ARCH_S3C2410 && CPU_S3C24405B diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index e51497ca12ea7..e8412b35dcb03 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -10,6 +10,8 @@ obj-n := obj- := obj-$(CONFIG_CPU_S3C2440) += s3c2440.o dsc.o +obj-$(CONFIG_CPU_S3C2442) += s3c2442.o + obj-$(CONFIG_CPU_S3C2440) += irq.o obj-$(CONFIG_CPU_S3C2440) += clock.o obj-$(CONFIG_S3C2440_DMA) += dma.o diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c similarity index 100% rename from arch/arm/mach-s3c2442/s3c2442.c rename to arch/arm/mach-s3c2440/s3c2442.c diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index 4832cd6ccfbcb..29ef0669e9595 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -2,14 +2,3 @@ # # Licensed under GPLv2 -config CPU_S3C2442 - bool - depends on ARCH_S3C2410 - select CPU_ARM920T - select S3C2410_CLOCK - select S3C2410_GPIO - select S3C2410_PM if PM - select CPU_S3C244X - select CPU_LLSERIAL_S3C2440 - help - Support for S3C2442 Samsung Mobile CPU based systems. -- GitLab From 70556b143ae4cf404a73c2461a6bf7fef3fefbf7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:37:50 +0900 Subject: [PATCH 137/370] ARM: S3C24XX: Remove old mach-s3c2442 Remove the old mach-s3c2442 directory now all is merged into mach-s3c2440 and remove it from the arch/arm build process. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 1 - arch/arm/Makefile | 2 +- arch/arm/mach-s3c2442/Kconfig | 4 ---- arch/arm/mach-s3c2442/Makefile | 15 --------------- 4 files changed, 1 insertion(+), 21 deletions(-) delete mode 100644 arch/arm/mach-s3c2442/Kconfig delete mode 100644 arch/arm/mach-s3c2442/Makefile diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3bc5169f0f822..63f726f594f26 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -794,7 +794,6 @@ source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" source "arch/arm/mach-s3c2412/Kconfig" source "arch/arm/mach-s3c2440/Kconfig" -source "arch/arm/mach-s3c2442/Kconfig" source "arch/arm/mach-s3c2443/Kconfig" endif diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bbcd512ccf7e0..893bcfc777082 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -158,7 +158,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_RPC) := rpc -machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 +machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 machine-$(CONFIG_ARCH_S5P6440) := s5p6440 diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig deleted file mode 100644 index 29ef0669e9595..0000000000000 --- a/arch/arm/mach-s3c2442/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile deleted file mode 100644 index 7e31ccdc83de3..0000000000000 --- a/arch/arm/mach-s3c2442/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# arch/arm/mach-s3c2442/Makefile -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_CPU_S3C2442) += s3c2442.o - -# Machine support - -- GitLab From 58bac7b8ded70c39bcd5f7037091051c277618aa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:47:41 +0900 Subject: [PATCH 138/370] ARM: S3C24XX: Move S3C2440/S3C2442 plat-s3c24xx support to mach-s3c2440 Remove the old common S3C2440 and S3C2442 SoC support from plat-s3c24xx into mach-s3c2440 now this directory is serving both SoCs. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/Kconfig | 42 +++++++++++++++++++ arch/arm/mach-s3c2440/Makefile | 8 ++++ .../s3c244x-clock.c | 0 .../s3c244x-irq.c | 0 .../{plat-s3c24xx => mach-s3c2440}/s3c244x.c | 2 +- arch/arm/plat-s3c24xx/Kconfig | 41 ------------------ arch/arm/plat-s3c24xx/Makefile | 7 ---- arch/arm/plat-s3c24xx/cpu.c | 2 +- .../plat-s3c24xx/{ => include/plat}/s3c244x.h | 2 +- 9 files changed, 53 insertions(+), 51 deletions(-) rename arch/arm/{plat-s3c24xx => mach-s3c2440}/s3c244x-clock.c (100%) rename arch/arm/{plat-s3c24xx => mach-s3c2440}/s3c244x-irq.c (100%) rename arch/arm/{plat-s3c24xx => mach-s3c2440}/s3c244x.c (99%) rename arch/arm/plat-s3c24xx/{ => include/plat}/s3c244x.h (92%) diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index f496385e1c751..7f465265cf04a 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -27,6 +27,48 @@ config CPU_S3C2442 help Support for S3C2442 Samsung Mobile CPU based systems. +config CPU_S3C244X + bool + depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) + help + Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. + + + +config S3C2440_CPUFREQ + bool "S3C2440/S3C2442 CPU Frequency scaling support" + depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) + select S3C2410_CPUFREQ_UTILS + default y + help + CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. + +config S3C2440_XTAL_12000000 + bool + help + Indicate that the build needs to support 12MHz system + crystal. + +config S3C2440_XTAL_16934400 + bool + help + Indicate that the build needs to support 16.9344MHz system + crystal. + +config S3C2440_PLL_12000000 + bool + depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 + default y if CPU_FREQ_S3C24XX_PLL + help + PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. + +config S3C2440_PLL_16934400 + bool + depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 + default y if CPU_FREQ_S3C24XX_PLL + help + PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. + config S3C2440_DMA bool depends on ARCH_S3C2410 && CPU_S3C24405B diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index e8412b35dcb03..c85ba32d8956d 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -16,6 +16,14 @@ obj-$(CONFIG_CPU_S3C2440) += irq.o obj-$(CONFIG_CPU_S3C2440) += clock.o obj-$(CONFIG_S3C2440_DMA) += dma.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o +obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o + +obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o +obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o + # Machine support obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c similarity index 100% rename from arch/arm/plat-s3c24xx/s3c244x-clock.c rename to arch/arm/mach-s3c2440/s3c244x-clock.c diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c similarity index 100% rename from arch/arm/plat-s3c24xx/s3c244x-irq.c rename to arch/arm/mach-s3c2440/s3c244x-irq.c diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c similarity index 99% rename from arch/arm/plat-s3c24xx/s3c244x.c rename to arch/arm/mach-s3c2440/s3c244x.c index 12623a474b548..46e13db03e798 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -39,7 +39,7 @@ #include #include -#include "s3c244x.h" +#include #include #include #include diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index a806f359ceb67..0cc5760b668a1 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -27,46 +27,6 @@ config S3C24XX_DCLK help Clock code for supporting DCLK/CLKOUT on S3C24XX architectures -config CPU_S3C244X - bool - depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) - help - Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. - -config S3C2440_CPUFREQ - bool "S3C2440/S3C2442 CPU Frequency scaling support" - depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - select S3C2410_CPUFREQ_UTILS - default y - help - CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. - -config S3C2440_XTAL_12000000 - bool - help - Indicate that the build needs to support 12MHz system - crystal. - -config S3C2440_XTAL_16934400 - bool - help - Indicate that the build needs to support 16.9344MHz system - crystal. - -config S3C2440_PLL_12000000 - bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if CPU_FREQ_S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. - -config S3C2440_PLL_16934400 - bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if CPU_FREQ_S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. - config S3C24XX_PWM bool "PWM device support" select HAVE_PWM @@ -74,7 +34,6 @@ config S3C24XX_PWM Support for exporting the PWM timer blocks via the pwm device system. - # gpio configurations config S3C24XX_GPIO_EXTRA diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index e0100266d0393..c2237c41141f9 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -25,13 +25,6 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o # Architecture dependant builds -obj-$(CONFIG_CPU_S3C244X) += s3c244x.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o -obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o -obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o -obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o - obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += irq-pm.o diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 4af9dd9487930..6ecf87af96022 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -49,7 +49,7 @@ #include #include #include -#include "s3c244x.h" +#include #include #include #include diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h similarity index 92% rename from arch/arm/plat-s3c24xx/s3c244x.h rename to arch/arm/plat-s3c24xx/include/plat/s3c244x.h index 6aab5eaae2b46..8da0904c41ab3 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/s3c244x.h +/* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks -- GitLab From 84c9b7271a0af08c4e5fce3901a0ad3d952036bc Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 16:54:21 +0900 Subject: [PATCH 139/370] ARM: S3C244X: Merge plat-s3c24xx s3c2440.h and s3c2442.h into s3c244x.h Merge these two headers into one, these two SoCs are so similar. Note, correct fault in mach-smdk2443.h including the wrong header. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/dsc.c | 2 +- arch/arm/mach-s3c2440/mach-nexcoder.c | 2 +- arch/arm/mach-s3c2440/mach-smdk2440.c | 2 +- arch/arm/mach-s3c2440/s3c2440.c | 2 +- arch/arm/mach-s3c2440/s3c244x.c | 1 - arch/arm/mach-s3c2443/mach-smdk2443.c | 2 +- arch/arm/plat-s3c24xx/cpu.c | 2 -- arch/arm/plat-s3c24xx/include/plat/s3c2440.h | 17 ----------------- arch/arm/plat-s3c24xx/include/plat/s3c2442.h | 17 ----------------- arch/arm/plat-s3c24xx/include/plat/s3c244x.h | 12 ++++++++++++ 10 files changed, 17 insertions(+), 42 deletions(-) delete mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2440.h delete mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2442.h diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c index 5540442727713..9ea66e31f6263 100644 --- a/arch/arm/mach-s3c2440/dsc.c +++ b/arch/arm/mach-s3c2440/dsc.c @@ -28,7 +28,7 @@ #include #include -#include +#include int s3c2440_set_dsc(unsigned int pin, unsigned int value) { diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index 86a243b3e37d9..342041593f22f 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -41,7 +41,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index df3e9a3be82fd..3ac3d636d615e 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index ac1f7ea5f405f..2b68f7ea45ae9 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -29,9 +29,9 @@ #include #include -#include #include #include +#include static struct sys_device s3c2440_sysdev = { .cls = &s3c2440_sysclass, diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c index 46e13db03e798..5e4a97e765334 100644 --- a/arch/arm/mach-s3c2440/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -38,7 +38,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index 039a462431050..d65afdee59c5e 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 6ecf87af96022..9ca64df35bf60 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -50,8 +50,6 @@ #include #include #include -#include -#include #include /* table of supported CPUs */ diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2440.h b/arch/arm/plat-s3c24xx/include/plat/s3c2440.h deleted file mode 100644 index 107853bf94813..0000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2440.h +++ /dev/null @@ -1,17 +0,0 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2440 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); -#else -#define s3c2440_init NULL -#endif diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2442.h b/arch/arm/plat-s3c24xx/include/plat/s3c2442.h deleted file mode 100644 index 451a23a2092aa..0000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2442.h +++ /dev/null @@ -1,17 +0,0 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2442 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); -#else -#define s3c2442_init NULL -#endif diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h index 8da0904c41ab3..307248d1ccbbd 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h @@ -23,3 +23,15 @@ extern void s3c244x_init_clocks(int xtal); #define s3c244x_init_uarts NULL #define s3c244x_map_io NULL #endif + +#ifdef CONFIG_CPU_S3C2440 +extern int s3c2440_init(void); +#else +#define s3c2440_init NULL +#endif + +#ifdef CONFIG_CPU_S3C2442 +extern int s3c2442_init(void); +#else +#define s3c2442_init NULL +#endif -- GitLab From 8ac5b7c5ec8d46ad273d37aaa0d6e1f9cd2b01d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 13 Jan 2010 17:58:04 +0100 Subject: [PATCH 140/370] imx: WARN in clk_disable if the clock isn't enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King --- arch/arm/plat-mxc/clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 9e8fbd57495cc..323ff8ccc8771 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk) __clk_disable(clk->parent); __clk_disable(clk->secondary); + WARN_ON(!clk->usecount); if (!(--clk->usecount) && clk->disable) clk->disable(clk); } -- GitLab From 9ea07ec05e8030f6b4e12c4a41a9d633c0ccb618 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 13 Jan 2010 18:07:11 +0100 Subject: [PATCH 141/370] mxc91231: use MXC91231_IO_ADDRESS instead of MXC91231_AIPS1_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apart from MXC91231_IO_ADDRESS itself this was the only usage of MXC91231_AIPS1_IO_ADDRESS. Now MXC91231_IO_ADDRESS can be recoded with IMX_IO_ADDRESS and all helper macros can go away. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Cc: Russell King Cc: Fabio Estevam Cc: Daniel Schaeffer Cc: Alberto Panizzo Cc: Ivo Clarysse --- arch/arm/plat-mxc/include/mach/debug-macro.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 21e0f077268cd..916d4fcb2ef2d 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -51,7 +51,7 @@ #endif #include #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) +#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 -- GitLab From 08f9bf167c2729b46920fdef459787667ee68130 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 14 Jan 2010 22:04:49 +0100 Subject: [PATCH 142/370] mxc91231: redefine MXC91231_IO_ADDRESS using IMX_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This simplifies the macro and makes is similar to the other ..._IO_ADDRESS macros defined for imx SOCs. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mxc91231.h | 58 ++++------------------- 1 file changed, 10 insertions(+), 48 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 81484d1ef2327..5182b986b7851 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -184,60 +184,22 @@ #define MXC91231_CS4_BASE_ADDR 0xB4000000 #define MXC91231_CS5_BASE_ADDR 0xB6000000 -/* Is given address belongs to the specified memory region? */ -#define ADDRESS_IN_REGION(addr, start, size) \ - (((addr) >= (start)) && ((addr) < (start)+(size))) - -/* Is given address belongs to the specified named `module'? */ -#define MXC91231_IS_MODULE(addr, module) \ - ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \ - MXC91231_ ## module ## _SIZE) /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ - -#define MXC91231_IO_ADDRESS(x) \ - (void __iomem *) \ - (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \ - 0xDEADBEEF) - - -/* - * define the address mapping macros: in physical address order + * it returns 0. */ -#define MXC91231_L2CC_IO_ADDRESS(x) \ - (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT) - -#define MXC91231_AIPS1_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT) - -#define MXC91231_SPBA0_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT) - -#define MXC91231_SPBA1_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT) - -#define MXC91231_AIPS2_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT) - -#define MXC91231_ROMP_IO_ADDRESS(x) \ - (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT) - -#define MXC91231_AVIC_IO_ADDRESS(x) \ - (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT) -#define MXC91231_X_MEMC_IO_ADDRESS(x) \ - (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) +#define MXC91231_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS2)) /* * Interrupt numbers -- GitLab From 7fc06d8c24fb7915d9cebc9aad7d3b40d8a6ef0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 15 Jan 2010 10:13:30 +0100 Subject: [PATCH 143/370] imx2x: convert serial.c to use soc-prefixed constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the file compilable for a kernel that supports both imx21 and imx27. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/Makefile | 1 - arch/arm/mach-mx2/serial.c | 48 +++++++++++++++++++------------------- 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index a9c94e39e3212..e8910903b24ff 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -7,7 +7,6 @@ obj-y := generic.o devices.o serial.o CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_serial.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX21) += clock_imx21.o diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c index 40a485cdc10e8..1c0c835b22526 100644 --- a/arch/arm/mach-mx2/serial.c +++ b/arch/arm/mach-mx2/serial.c @@ -26,12 +26,12 @@ static struct resource uart0[] = { { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0x0B5, + .start = MX2x_UART1_BASE_ADDR, + .end = MX2x_UART1_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART1, - .end = MXC_INT_UART1, + .start = MX2x_INT_UART1, + .end = MX2x_INT_UART1, .flags = IORESOURCE_IRQ, }, }; @@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = { static struct resource uart1[] = { { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0x0B5, + .start = MX2x_UART2_BASE_ADDR, + .end = MX2x_UART2_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART2, - .end = MXC_INT_UART2, + .start = MX2x_INT_UART2, + .end = MX2x_INT_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = { static struct resource uart2[] = { { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + 0x0B5, + .start = MX2x_UART3_BASE_ADDR, + .end = MX2x_UART3_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, + .start = MX2x_INT_UART3, + .end = MX2x_INT_UART3, .flags = IORESOURCE_IRQ, }, }; @@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = { static struct resource uart3[] = { { - .start = UART4_BASE_ADDR, - .end = UART4_BASE_ADDR + 0x0B5, + .start = MX2x_UART4_BASE_ADDR, + .end = MX2x_UART4_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART4, - .end = MXC_INT_UART4, + .start = MX2x_INT_UART4, + .end = MX2x_INT_UART4, .flags = IORESOURCE_IRQ, }, }; @@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = { #ifdef CONFIG_MACH_MX27 static struct resource uart4[] = { { - .start = UART5_BASE_ADDR, - .end = UART5_BASE_ADDR + 0x0B5, + .start = MX27_UART5_BASE_ADDR, + .end = MX27_UART5_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART5, - .end = MXC_INT_UART5, + .start = MX27_INT_UART5, + .end = MX27_INT_UART5, .flags = IORESOURCE_IRQ, }, }; @@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = { static struct resource uart5[] = { { - .start = UART6_BASE_ADDR, - .end = UART6_BASE_ADDR + 0x0B5, + .start = MX27_UART6_BASE_ADDR, + .end = MX27_UART6_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART6, - .end = MXC_INT_UART6, + .start = MX27_INT_UART6, + .end = MX27_INT_UART6, .flags = IORESOURCE_IRQ, }, }; -- GitLab From 34101237d975ba37d19cbfe9318984af78332816 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 29 Jan 2010 17:36:05 +0100 Subject: [PATCH 144/370] imx: define per SOC ..._PHYS_OFFSET and use these in favour of PHYS_OFFSET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a further step in allowing to build a kernel image for more than one imx SOC. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx1/mach-mx1ads.c | 4 +-- arch/arm/mach-mx2/mach-cpuimx27.c | 2 +- arch/arm/mach-mx2/mach-imx27lite.c | 2 +- arch/arm/mach-mx2/mach-mx21ads.c | 2 +- arch/arm/mach-mx2/mach-mx27_3ds.c | 2 +- arch/arm/mach-mx2/mach-mx27ads.c | 2 +- arch/arm/mach-mx2/mach-mxt_td60.c | 2 +- arch/arm/mach-mx2/mach-pca100.c | 2 +- arch/arm/mach-mx2/mach-pcm038.c | 2 +- arch/arm/mach-mx25/mx25pdk.c | 2 +- arch/arm/mach-mx3/mach-armadillo5x0.c | 2 +- arch/arm/mach-mx3/mach-kzm_arm11_01.c | 2 +- arch/arm/mach-mx3/mach-mx31_3ds.c | 2 +- arch/arm/mach-mx3/mach-mx31ads.c | 2 +- arch/arm/mach-mx3/mach-mx31lilly.c | 2 +- arch/arm/mach-mx3/mach-mx31lite.c | 2 +- arch/arm/mach-mx3/mach-mx31moboard.c | 2 +- arch/arm/mach-mx3/mach-mx35pdk.c | 2 +- arch/arm/mach-mx3/mach-pcm037.c | 2 +- arch/arm/mach-mx3/mach-pcm043.c | 2 +- arch/arm/mach-mx3/mach-qong.c | 2 +- arch/arm/mach-mxc91231/magx-zn5.c | 2 +- arch/arm/plat-mxc/include/mach/memory.h | 36 ++++++++++++++----------- 23 files changed, 44 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c index a39433afb5123..69831aa274ff0 100644 --- a/arch/arm/mach-mx1/mach-mx1ads.c +++ b/arch/arm/mach-mx1/mach-mx1ads.c @@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, @@ -157,7 +157,7 @@ MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c index 8e4f3d08e32ca..92fd1bf7a6380 100644 --- a/arch/arm/mach-mx2/mach-cpuimx27.c +++ b/arch/arm/mach-mx2/mach-cpuimx27.c @@ -226,7 +226,7 @@ static struct sys_timer eukrea_cpuimx27_timer = { MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = eukrea_cpuimx27_init, diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c index ca6ab1265f3ee..621c2c1046ea3 100644 --- a/arch/arm/mach-mx2/mach-imx27lite.c +++ b/arch/arm/mach-mx2/mach-imx27lite.c @@ -87,7 +87,7 @@ static struct sys_timer mx27lite_timer = { MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27lite_init, diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c index eb4a6e855595b..d5eb8065df3e1 100644 --- a/arch/arm/mach-mx2/mach-mx21ads.c +++ b/arch/arm/mach-mx2/mach-mx21ads.c @@ -286,7 +286,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX21_AIPI_BASE_ADDR, .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX21_PHYS_OFFSET + 0x100, .map_io = mx21ads_map_io, .init_irq = mx21_init_irq, .init_machine = mx21ads_board_init, diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c index 595fea46b6f7a..8c975f6514ad0 100644 --- a/arch/arm/mach-mx2/mach-mx27_3ds.c +++ b/arch/arm/mach-mx2/mach-mx27_3ds.c @@ -87,7 +87,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27pdk_init, diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c index 385fc1c9ad389..808ca271a8292 100644 --- a/arch/arm/mach-mx2/mach-mx27ads.c +++ b/arch/arm/mach-mx2/mach-mx27ads.c @@ -336,7 +336,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") /* maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27ads_map_io, .init_irq = mx27_init_irq, .init_machine = mx27ads_board_init, diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c index 9ed4e492fc73e..df954d879cc34 100644 --- a/arch/arm/mach-mx2/mach-mxt_td60.c +++ b/arch/arm/mach-mx2/mach-mxt_td60.c @@ -286,7 +286,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mxt_td60_board_init, diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index 55dbf5a64e006..9279b42b24b58 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -235,7 +235,7 @@ static struct sys_timer pca100_timer = { MACHINE_START(PCA100, "phyCARD-i.MX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pca100_init, diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 9636bb82f1e9c..e055d9dd61014 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -328,7 +328,7 @@ static struct sys_timer pcm038_timer = { MACHINE_START(PCM038, "phyCORE-i.MX27") .phys_io = MX27_AIPI_BASE_ADDR, .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pcm038_init, diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c index f4e8b984af725..10be38eb82a88 100644 --- a/arch/arm/mach-mx25/mx25pdk.c +++ b/arch/arm/mach-mx25/mx25pdk.c @@ -110,7 +110,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX25_AIPS1_BASE_ADDR, .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX25_PHYS_OFFSET + 0x100, .map_io = mx25_map_io, .init_irq = mx25_init_irq, .init_machine = mx25pdk_init, diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 1fed146324f50..3d72b0b897059 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -408,7 +408,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .timer = &armadillo5x0_timer, diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 2484dddca549b..f085d5d1a6de7 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -265,7 +265,7 @@ static struct sys_timer kzm_timer = { MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = kzm_map_io, .init_irq = mx31_init_irq, .init_machine = kzm_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 88af58514a761..b88c18ad76981 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -258,7 +258,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31pdk_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 59de37887f337..2f02df212b665 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -537,7 +537,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31ads_map_io, .init_irq = mx31ads_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 9225cb72dd01b..80847b04c063a 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -197,7 +197,7 @@ static struct sys_timer mx31lilly_timer = { MACHINE_START(LILLY1131, "INCO startec LILLY-1131") .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mx31lilly_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 8589e3d1dada2..2b6d114008774 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -289,7 +289,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31lite_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 63f991f8817ff..fe18cd513cd7c 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -571,7 +571,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c index 2d11bf053c785..bcac84d4dca4b 100644 --- a/arch/arm/mach-mx3/mach-mx35pdk.c +++ b/arch/arm/mach-mx3/mach-mx35pdk.c @@ -108,7 +108,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") /* Maintainer: Freescale Semiconductor, Inc */ .phys_io = MX35_AIPS1_BASE_ADDR, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index d9bd7d2b0ade5..21f54811a630c 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -638,7 +638,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 1212194fb9c2e..25942b8e8bed7 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -250,7 +250,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ .phys_io = MX35_AIPS1_BASE_ADDR, .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index fdb819ae0e60d..e5b5b8323a179 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -275,7 +275,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ .phys_io = MX31_AIPS1_BASE_ADDR, .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c index 7dbe4ca12efd5..69816ba82930e 100644 --- a/arch/arm/mach-mxc91231/magx-zn5.c +++ b/arch/arm/mach-mxc91231/magx-zn5.c @@ -55,7 +55,7 @@ struct sys_timer zn5_timer = { MACHINE_START(MAGX_ZN5, "Motorola Zn5") .phys_io = MXC91231_AIPS1_BASE_ADDR, .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MXC91231_PHYS_OFFSET + 0x100, .map_io = mxc91231_map_io, .init_irq = mxc91231_init_irq, .timer = &zn5_timer, diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index d3afafdcc0e5d..002eb91ab235c 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,21 +11,27 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#if defined CONFIG_ARCH_MX1 -#define PHYS_OFFSET UL(0x08000000) -#elif defined CONFIG_ARCH_MX2 -#ifdef CONFIG_MACH_MX21 -#define PHYS_OFFSET UL(0xC0000000) -#endif -#ifdef CONFIG_MACH_MX27 -#define PHYS_OFFSET UL(0xA0000000) -#endif -#elif defined CONFIG_ARCH_MX3 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MX25 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MXC91231 -#define PHYS_OFFSET UL(0x90000000) +#define MX1_PHYS_OFFSET UL(0x08000000) +#define MX21_PHYS_OFFSET UL(0xc0000000) +#define MX25_PHYS_OFFSET UL(0x80000000) +#define MX27_PHYS_OFFSET UL(0xa0000000) +#define MX3x_PHYS_OFFSET UL(0x80000000) +#define MXC91231_PHYS_OFFSET UL(0x90000000) + +#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) +# if defined CONFIG_ARCH_MX1 +# define PHYS_OFFSET MX1_PHYS_OFFSET +# elif defined CONFIG_MACH_MX21 +# define PHYS_OFFSET MX21_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX25 +# define PHYS_OFFSET MX25_PHYS_OFFSET +# elif defined CONFIG_MACH_MX27 +# define PHYS_OFFSET MX27_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX3 +# define PHYS_OFFSET MX3x_PHYS_OFFSET +# elif defined CONFIG_ARCH_MXC91231 +# define PHYS_OFFSET MXC91231_PHYS_OFFSET +# endif #endif #if defined(CONFIG_MX1_VIDEO) -- GitLab From e27bf72465f4d867a2aea33cad5e9e255c4d92ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 30 Jan 2010 16:23:51 +0100 Subject: [PATCH 145/370] imx/mx25: rename files defining a machine to mach-$mach.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx25/Makefile | 2 +- arch/arm/mach-mx25/{mx25pdk.c => mach-mx25pdk.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/mach-mx25/{mx25pdk.c => mach-mx25pdk.c} (100%) diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index fe23836a9f3d8..10cebc5ced8c0 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,3 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c similarity index 100% rename from arch/arm/mach-mx25/mx25pdk.c rename to arch/arm/mach-mx25/mach-mx25pdk.c -- GitLab From 2848552cef6a14fe4e54e676a61a340c8fd023b3 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 27 Jan 2010 18:13:59 +0900 Subject: [PATCH 146/370] ARM: SAMSUNG: Add DMA masks to hsotg device Add the required DMA masks to the hs-otg device definition to allow DMA to work with it. Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/dev-usb-hsotg.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/plat-samsung/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c index e2f604b51c866..33a844ab69170 100644 --- a/arch/arm/plat-samsung/dev-usb-hsotg.c +++ b/arch/arm/plat-samsung/dev-usb-hsotg.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -33,9 +34,15 @@ static struct resource s3c_usb_hsotg_resources[] = { }, }; +static u64 s3c_hsotg_dmamask = DMA_BIT_MASK(32); + struct platform_device s3c_device_usb_hsotg = { .name = "s3c-hsotg", .id = -1, .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources), .resource = s3c_usb_hsotg_resources, + .dev = { + .dma_mask = &s3c_hsotg_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, }; -- GitLab From 4b4c662571bb3a19d6bacb4433886ec35c7093fa Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Thu, 28 Jan 2010 17:14:49 +0900 Subject: [PATCH 147/370] ARM: S3C64XX: SPI: Make platform device compilation selectable The SPI controller platform devices should be compiled in independent of the driver support, otherwise we might end up with dev-spi built as kernel module. Change this to make every machine select if it has some SPI device and wants to build device definitions. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/Makefile | 4 +++- arch/arm/plat-samsung/Kconfig | 6 ++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 80255a5e17891..e60bde304d868 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -40,6 +40,9 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o obj-$(CONFIG_S3C_ADC) += dev-adc.o +# SPI support +obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o @@ -47,4 +50,3 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o -obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 1c2fe91c23e93..72da6461db128 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -132,6 +132,12 @@ config S3C_DEV_NAND help Compile in platform device definition for NAND controller +config S3C64XX_DEV_SPI + bool + help + Compile in platform device definitions for S3C64XX's type + SPI controllers. + comment "Power management" config SAMSUNG_PM_DEBUG -- GitLab From 21030403209f0c253d462492f881c613bd8eeda2 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 27 Jan 2010 16:38:08 +0000 Subject: [PATCH 148/370] ARM: S3C2412: SoC has the fractional baud rate register The S3C2412 has a fractional baud rate register, this patch adds the corresponding flag to the UART definition to allow generation of more precise baud rates for the various clock combinations. Signed-off-by: Michel Pollet Signed-off-by: Ben Dooks --- drivers/serial/s3c2412.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c index ce75e28e36ef5..1700b1a2fb7e0 100644 --- a/drivers/serial/s3c2412.c +++ b/drivers/serial/s3c2412.c @@ -102,6 +102,7 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = { .name = "Samsung S3C2412 UART", .type = PORT_S3C2412, .fifosize = 64, + .has_divslot = 1, .rx_fifomask = S3C2440_UFSTAT_RXMASK, .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, .rx_fifofull = S3C2440_UFSTAT_RXFULL, -- GitLab From 3bd9377e8761cb7f1000b3075763df779ab9aeca Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 10:52:02 +0900 Subject: [PATCH 149/370] ARM: SAMSUNG: Add SERIAL_SAMSUNG_UARTS_4 Kconfig option Add SERIAL_SAMSUNG_UARTS_4 to mop up the number of cases currently using four Samsung compatible UARTS. Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ebdd2b984d16e..1d47c770c3b8e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -455,11 +455,18 @@ config SERIAL_SAMSUNG provide all of these ports, depending on how the serial port pins are configured. +config SERIAL_SAMSUNG_UARTS_4 + bool + depends on ARM && PLAT_SAMSUNG + default y if CPU_S3C2443 + help + Internal node for the common case of 4 Samsung compatible UARTs + config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S5PV210 || ARCH_S3C64XX || CPU_S3C2443 + default 4 if SERIAL_SAMSUNG_UARTS_4 default 3 help Select the number of available UART ports for the Samsung S3C @@ -526,8 +533,9 @@ config SERIAL_S3C24A0 Serial port support for the Samsung S3C24A0 SoC config SERIAL_S3C6400 - tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" + tristate "Samsung S3C6400/S3C6410/S5P6440 Seria port support" depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 @@ -536,6 +544,7 @@ config SERIAL_S3C6400 config SERIAL_S5PC100 tristate "Samsung S5PC100 Serial port support" depends on SERIAL_SAMSUNG && CPU_S5PC100 + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for the Samsung S5PC100 SoCs @@ -543,6 +552,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" depends on SERIAL_SAMSUNG && CPU_S5PV210 + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for Samsung's S5P Family of SoC's -- GitLab From 1de203adf6210b9dd81d907ea8cda587bc61cf4c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 10:53:35 +0900 Subject: [PATCH 150/370] ARM: SAMSUNG: Use PLAT_SAMSUNG instead of PLAT_S3C As part of the development process, it is hoped PLAT_S3C is either removed from all of the PLAT_SAMSUNG derived platforms or removed entirely. It is also better to use PLAT_SAMSUNG as this is the current base of all Samsung devices. Change the two places that use PLAT_S3C to use PLAT_SAMSUNG Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1d47c770c3b8e..b2157c36566dc 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on ARM && PLAT_S3C + depends on ARM && PLAT_SAMSUNG select SERIAL_CORE help Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, @@ -464,7 +464,7 @@ config SERIAL_SAMSUNG_UARTS_4 config SERIAL_SAMSUNG_UARTS int - depends on ARM && PLAT_S3C + depends on ARM && PLAT_SAMSUNG default 2 if ARCH_S3C2400 default 4 if SERIAL_SAMSUNG_UARTS_4 default 3 -- GitLab From cf9814eb6d83f066d5db63f4144598e9c6ca2951 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 13:03:34 +0900 Subject: [PATCH 151/370] ARM: S3C64XX: Make audio device code built unconditionally Making the code depend on CONFIG_SND_S3C24XX_SOC means that if the ASoC code is build modularily, the boards will fail to link due to the device code also being built as a module. As per Mark Brown's suggestions, just compile this always as it is expected many machines will have audio. Also move the obj-y line out of the device setup area into a new area just for devices. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index e60bde304d868..33a73f3e9f01b 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -43,10 +43,13 @@ obj-$(CONFIG_S3C_ADC) += dev-adc.o # SPI support obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o +# Device support +obj-y += dev-audio.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o + -- GitLab From 91492b4a04586e7cb191c72de9d1b22545a3ce16 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Sat, 30 Jan 2010 18:01:48 +0100 Subject: [PATCH 152/370] ARM: SAMSUNG: Add support for 12bit ADC The S3C64XX SoC series support 12bit ADC data, enable this and mask the data accordingly. Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/adc.c | 24 +++++++++++++++---- arch/arm/plat-samsung/include/plat/regs-adc.h | 1 + 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index c7659b7378b1f..81caf21357219 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -262,6 +262,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) { struct adc_device *adc = pw; struct s3c_adc_client *client = adc->cur; + enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; unsigned long flags; unsigned data0, data1; @@ -276,9 +277,17 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) client->nr_samples--; + if (cpu == TYPE_S3C64XX) { + /* S3C64XX ADC resolution is 12-bit */ + data0 &= 0xfff; + data1 &= 0xfff; + } else { + data0 &= 0x3ff; + data1 &= 0x3ff; + } + if (client->convert_cb) - (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff, - &client->nr_samples); + (client->convert_cb)(client, data0, data1, &client->nr_samples); if (client->nr_samples > 0) { /* fire another conversion for this */ @@ -295,7 +304,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) } exit: - if (platform_get_device_id(adc->pdev)->driver_data == TYPE_S3C64XX) { + if (cpu == TYPE_S3C64XX) { /* Clear ADC interrupt */ writel(0, adc->regs + S3C64XX_ADCCLRINT); } @@ -308,6 +317,7 @@ static int s3c_adc_probe(struct platform_device *pdev) struct adc_device *adc; struct resource *regs; int ret; + unsigned tmp; adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL); if (adc == NULL) { @@ -354,8 +364,12 @@ static int s3c_adc_probe(struct platform_device *pdev) clk_enable(adc->clk); - writel(adc->prescale | S3C2410_ADCCON_PRSCEN, - adc->regs + S3C2410_ADCCON); + tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; + if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) { + /* Enable 12-bit ADC resolution */ + tmp |= S3C64XX_ADCCON_RESSEL; + } + writel(tmp, adc->regs + S3C2410_ADCCON); dev_info(dev, "attached adc driver\n"); diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index f43c8dab39e4c..7554c4fcddb9d 100644 --- a/arch/arm/plat-samsung/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h @@ -25,6 +25,7 @@ /* ADCCON Register Bits */ +#define S3C64XX_ADCCON_RESSEL (1<<16) #define S3C2410_ADCCON_ECFLG (1<<15) #define S3C2410_ADCCON_PRSCEN (1<<14) #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) -- GitLab From 5c17ef878fa25e04b1e8f1d8f5fa8b267753472c Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 3 Feb 2010 20:19:00 +0100 Subject: [PATCH 153/370] MX1/MX2: -EINVAL overwritten in second iteration in mxc_gpio_setup_multiple_pins() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the `ret = gpio_request()' below in the loop, the initial -EINVAL value of ret is overwritten. Signed-off-by: Roel Kluin Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/iomux-mx1-mx2.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c index a37163ce280b3..25023ac2f53b9 100644 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c @@ -116,14 +116,16 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, int i; unsigned gpio; unsigned mode; - int ret = -EINVAL; + int ret; for (i = 0; i < count; i++) { gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); - if (gpio >= (GPIO_PORT_MAX + 1) * 32) + if (gpio >= (GPIO_PORT_MAX + 1) * 32) { + ret = -EINVAL; goto setup_error; + } ret = gpio_request(gpio, label); if (ret) -- GitLab From ba593e5966440deec8684863e0cba9b502c4a377 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:40:59 +0100 Subject: [PATCH 154/370] fsl_mx3_udc: Add i.MX35 support The i.MX35 works fine with this driver, but we do not have the usb_ahb clock. Signed-off-by: Sascha Hauer Cc: Guennadi Liakhovetski --- drivers/usb/gadget/fsl_mx3_udc.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c index 4bc2bf3d602e3..20a802ecaa158 100644 --- a/drivers/usb/gadget/fsl_mx3_udc.c +++ b/drivers/usb/gadget/fsl_mx3_udc.c @@ -17,6 +17,8 @@ #include #include +#include + static struct clk *mxc_ahb_clk; static struct clk *mxc_usb_clk; @@ -28,14 +30,16 @@ int fsl_udc_clk_init(struct platform_device *pdev) pdata = pdev->dev.platform_data; - mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); - if (IS_ERR(mxc_ahb_clk)) - return PTR_ERR(mxc_ahb_clk); + if (!cpu_is_mx35()) { + mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); + if (IS_ERR(mxc_ahb_clk)) + return PTR_ERR(mxc_ahb_clk); - ret = clk_enable(mxc_ahb_clk); - if (ret < 0) { - dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); - goto eenahb; + ret = clk_enable(mxc_ahb_clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); + goto eenahb; + } } /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ @@ -50,6 +54,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) if (pdata->phy_mode != FSL_USB2_PHY_ULPI && (freq < 59999000 || freq > 60001000)) { dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); + ret = -EINVAL; goto eclkrate; } @@ -66,9 +71,11 @@ int fsl_udc_clk_init(struct platform_device *pdev) clk_put(mxc_usb_clk); mxc_usb_clk = NULL; egusb: - clk_disable(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_disable(mxc_ahb_clk); eenahb: - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_put(mxc_ahb_clk); return ret; } @@ -90,6 +97,8 @@ void fsl_udc_clk_release(void) clk_disable(mxc_usb_clk); clk_put(mxc_usb_clk); } - clk_disable(mxc_ahb_clk); - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) { + clk_disable(mxc_ahb_clk); + clk_put(mxc_ahb_clk); + } } -- GitLab From 84ab80616b0eb5fac4d1970f10ea1b3cf75280e1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:45:11 +0100 Subject: [PATCH 155/370] i.MX ehci platform support: Some fixes - The SIC mask is only 2bits wide, not 4 - MX31_OTG_PM_BIT and MX31_H1_PM_BIT use negative logic - clear MX31_H1_DT_BIT and MX31_H2_DT_BIT so that they can be cleared, not only set. - return -EINVAL if called with an invalid controller number Signed-off-by: Sascha Hauer Cc: Daniel Mack --- arch/arm/plat-mxc/ehci.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 8df03f36295cd..586b55dc2ab1f 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -25,16 +25,16 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 #define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) +#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) #define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) +#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) #define MX31_H2_PM_BIT (1 << 16) #define MX31_H2_DT_BIT (1 << 5) #define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) +#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) @@ -51,15 +51,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_OTG_PM_BIT; break; case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) @@ -67,7 +67,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) @@ -77,6 +77,8 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v |= MX31_H2_DT_BIT; break; + default: + return -EINVAL; } writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + -- GitLab From 9cf945cbef42a4524b6a58486bd8bfb96640e97f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:45:41 +0100 Subject: [PATCH 156/370] i.MX27: Add USB control register access support Signed-off-by: Sascha Hauer Cc: Daniel Mack --- arch/arm/plat-mxc/ehci.c | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 586b55dc2ab1f..816a9cc60e5d0 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -41,7 +41,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; - +#ifdef CONFIG_ARCH_MX3 if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); @@ -85,7 +85,52 @@ int mxc_set_usbcontrol(int port, unsigned int flags) USBCTRL_OTGBASE_OFFSET)); return 0; } +#endif /* CONFIG_ARCH_MX3 */ +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + /* On i.MX27 we can use the i.MX31 USBCTRL bits, they + * are identical + */ + v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_OTG_PM_BIT; + break; + case 1: /* H1 port */ + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H1_DT_BIT; + break; + case 2: /* H2 port */ + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H2_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H2_DT_BIT; + + break; + default: + return -EINVAL; + } + writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_MACH_MX27 */ printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); return -EINVAL; -- GitLab From d186f04c17d86e587e72bc402302df56a9b820f3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:34:48 +0100 Subject: [PATCH 157/370] i.MX35: Add USB control register access support Signed-off-by: Sascha Hauer Cc: Daniel Mack --- arch/arm/plat-mxc/ehci.c | 55 +++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc_ehci.h | 4 ++ 2 files changed, 59 insertions(+) diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 816a9cc60e5d0..cb0b638744824 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -38,6 +38,18 @@ #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#define MX35_OTG_SIC_SHIFT 29 +#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) +#define MX35_OTG_PM_BIT (1 << 24) + +#define MX35_H1_SIC_SHIFT 21 +#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) +#define MX35_H1_PM_BIT (1 << 8) +#define MX35_H1_IPPUE_UP_BIT (1 << 7) +#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX35_H1_TLL_BIT (1 << 5) +#define MX35_H1_USBTE_BIT (1 << 4) + int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; @@ -85,6 +97,49 @@ int mxc_set_usbcontrol(int port, unsigned int flags) USBCTRL_OTGBASE_OFFSET)); return 0; } + + if (cpu_is_mx35()) { + v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } #endif /* CONFIG_ARCH_MX3 */ #ifdef CONFIG_MACH_MX27 if (cpu_is_mx27()) { diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 8f796239393e7..4b9b8368c0c08 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -22,6 +22,10 @@ #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) #define MXC_EHCI_TTL_ENABLED (1 << 6) +#define MXC_EHCI_INTERNAL_PHY (1 << 7) +#define MXC_EHCI_IPPUE_DOWN (1 << 8) +#define MXC_EHCI_IPPUE_UP (1 << 9) + struct mxc_usbh_platform_data { int (*init)(struct platform_device *pdev); int (*exit)(struct platform_device *pdev); -- GitLab From eee7c497d250bbb2bfd0fdc2b41b9b6ff02148a2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 3 Feb 2010 17:13:29 +0100 Subject: [PATCH 158/370] i.MX27 pca100: Add USB support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/Kconfig | 1 + arch/arm/mach-mx2/mach-pca100.c | 103 ++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index 7bc797c1c3a2e..ca1278d5c845b 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -100,6 +100,7 @@ config MACH_IMX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" depends on MACH_MX27 + select MXC_ULPI if USB_ULPI help Include support for phyCARD-s (aka pca100) platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index 9279b42b24b58..cda52a6a32909 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -26,6 +26,9 @@ #include #include #include +#include +#include +#include #include #include @@ -41,9 +44,14 @@ #include #include #include +#include +#include #include "devices.h" +#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) +#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) + static int pca100_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, @@ -92,6 +100,34 @@ static int pca100_pins[] = { PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, + /* OTG */ + OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* USBH2 */ + USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; static struct imxuart_platform_data uart_pdata = { @@ -182,6 +218,50 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pca100_sdhc2_exit, }; +static int otg_phy_init(struct platform_device *pdev) +{ + gpio_set_value(OTG_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data otg_pdata = { + .init = otg_phy_init, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static int usbh2_phy_init(struct platform_device *pdev) +{ + gpio_set_value(USBH2_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data usbh2_pdata = { + .init = usbh2_phy_init, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init pca100_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pca100_otg_mode); + static void __init pca100_init(void) { int ret; @@ -220,6 +300,29 @@ static void __init pca100_init(void) mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); #endif + gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); + gpio_direction_output(OTG_PHY_CS_GPIO, 1); + gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); + gpio_direction_output(USBH2_PHY_CS_GPIO, 1); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) { + gpio_set_value(OTG_PHY_CS_GPIO, 0); + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } -- GitLab From 773f206b2f3745bde8ee17ec0f884c19db3917a5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 3 Feb 2010 17:13:41 +0100 Subject: [PATCH 159/370] i.MX27 pcm038: Add USB support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/Kconfig | 1 + arch/arm/mach-mx2/mach-pcm038.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index ca1278d5c845b..742fd4e6dcb92 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -37,6 +37,7 @@ config MACH_MX27ADS config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" depends on MACH_MX27 + select MXC_ULPI if USB_ULPI help Include support for phyCORE-i.MX27 (aka pcm038) platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index e055d9dd61014..5a0169cff20f8 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -40,6 +40,8 @@ #include #include #include +#include +#include #include "devices.h" @@ -96,6 +98,19 @@ static int pcm038_pins[] = { PC17_PF_SSI4_RXD, PC18_PF_SSI4_TXD, PC19_PF_SSI4_CLK, + /* USB host */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; /* @@ -277,6 +292,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { } }; +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, +}; + static void __init pcm038_init(void) { mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), @@ -309,6 +329,8 @@ static void __init pcm038_init(void) spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); + mxc_register_device(&mxc_usbh2, &usbh2_pdata); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #ifdef CONFIG_MACH_PCM970_BASEBOARD -- GitLab From ee14373cdc91fbc9ad8db0bf38e28d58f577b181 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 09:32:44 +0100 Subject: [PATCH 160/370] i.MX31 pcm037: Add USB support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Kconfig | 1 + arch/arm/mach-mx3/mach-pcm037.c | 137 +++++++++++++++++++++----------- 2 files changed, 93 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 28294416b0afb..2232b7b04b6d2 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -34,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" select ARCH_MX31 + select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 21f54811a630c..11f5315591693 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -33,6 +33,9 @@ #include #include #include +#include +#include +#include #include @@ -51,6 +54,8 @@ #include #include #include +#include +#include #include "devices.h" #include "pcm037.h" @@ -172,19 +177,7 @@ static unsigned int pcm037_pins[] = { MX31_PIN_CSI_VSYNC__CSI_VSYNC, /* GPIO */ IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), -}; - -static struct physmap_flash_data pcm037_flash_data = { - .width = 2, -}; - -static struct resource pcm037_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static int usbotg_pins[] = { + /* OTG */ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, @@ -197,39 +190,29 @@ static int usbotg_pins[] = { MX31_PIN_USBOTG_DIR__USBOTG_DIR, MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, + /* USB host 2 */ + IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), }; -/* USB OTG HS port */ -static int __init gpio_usbotg_hs_activate(void) -{ - int ret = mxc_iomux_setup_multiple_pins(usbotg_pins, - ARRAY_SIZE(usbotg_pins), "usbotg"); - - if (ret < 0) { - printk(KERN_ERR "Cannot set up OTG pins\n"); - return ret; - } - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - return 0; -} +static struct physmap_flash_data pcm037_flash_data = { + .width = 2, +}; -/* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, +static struct resource pcm037_flash_resource = { + .start = 0xa0000000, + .end = 0xa1ffffff, + .flags = IORESOURCE_MEM, }; static struct platform_device pcm037_flash = { @@ -561,16 +544,65 @@ static struct platform_device pcm970_sja1000 = { .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), }; +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init pcm037_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pcm037_otg_mode); + /* * Board specific initialization. */ static void __init mxc_board_init(void) { int ret; + u32 tmp; + + mxc_iomux_set_gpr(MUX_PGP_UH2, 1); mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), "pcm037"); +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ + | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ + mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ + if (pcm037_variant() == PCM037_EET) mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); @@ -608,8 +640,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); - if (!gpio_usbotg_hs_activate()) - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); /* CSI */ /* Camera power: default - off */ @@ -623,6 +653,23 @@ static void __init mxc_board_init(void) mxc_register_device(&mx3_camera, &camera_pdata); platform_device_register(&pcm970_sja1000); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } static void __init pcm037_timer_init(void) -- GitLab From cb2dc111b156eb41f61ed4e5b3a3a5df90526d9d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:32:53 +0100 Subject: [PATCH 161/370] i.MX27 pca100: Add USB support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Kconfig | 1 + arch/arm/mach-mx3/mach-pcm043.c | 53 +++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 2232b7b04b6d2..3872af1cf2c32 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -87,6 +87,7 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 + select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 25942b8e8bed7..a9741c2b379fc 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -28,6 +28,9 @@ #include #include #include +#include +#include +#include #include #include @@ -44,6 +47,8 @@ #include #include #include +#include +#include #include "devices.h" @@ -205,6 +210,9 @@ static struct pad_desc pcm043_pads[] = { MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, /* gpio */ MX35_PAD_ATA_CS0__GPIO2_6, + /* USB host */ + MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, + MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, }; static struct mxc_nand_platform_data pcm037_nand_board_info = { @@ -212,6 +220,37 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { .hw_ecc = 1, }; +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh1_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init pcm043_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pcm043_otg_mode); + /* * Board specific initialization. */ @@ -235,6 +274,20 @@ static void __init mxc_board_init(void) mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + mxc_register_device(&mxc_usbh1, &usbh1_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } static void __init pcm043_timer_init(void) -- GitLab From ef4a6777cf33c4a7a76e74ecd593f74a1df30b96 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 29 Jan 2010 14:56:58 -0800 Subject: [PATCH 162/370] mach-orion5x/common.c: remove unnecessary (void *) casts The (void *) cast is not needed when setting dev.platform_data to the address of the data. Remove the casts. Signed-off-by: H Hartley Sweeten Cc: Lennert Buytenhek Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index f87fa12538036..8dc2c76d22600 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -488,7 +488,7 @@ static struct platform_device orion5x_xor0_channel = { .dev = { .dma_mask = &orion5x_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&orion5x_xor0_data, + .platform_data = &orion5x_xor0_data, }, }; @@ -514,7 +514,7 @@ static struct platform_device orion5x_xor1_channel = { .dev = { .dma_mask = &orion5x_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&orion5x_xor1_data, + .platform_data = &orion5x_xor1_data, }, }; -- GitLab From 3e3e65fc425588a4a4b9143d7dfe40e52a2bf0be Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 29 Jan 2010 14:43:52 -0800 Subject: [PATCH 163/370] mach-kirkwood/common.c: remove unnecessary (void *) casts The (void *) cast is not needed when setting dev.platform_data to the address of the data. Remove the casts. Signed-off-by: H Hartley Sweeten Cc: Lennert Buytenhek Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 242dd07753433..f759ca2439252 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -656,7 +656,7 @@ static struct platform_device kirkwood_xor00_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor00_data, + .platform_data = &kirkwood_xor00_data, }, }; @@ -682,7 +682,7 @@ static struct platform_device kirkwood_xor01_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor01_data, + .platform_data = &kirkwood_xor01_data, }, }; @@ -755,7 +755,7 @@ static struct platform_device kirkwood_xor10_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor10_data, + .platform_data = &kirkwood_xor10_data, }, }; @@ -781,7 +781,7 @@ static struct platform_device kirkwood_xor11_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor11_data, + .platform_data = &kirkwood_xor11_data, }, }; -- GitLab From 639b9be60ec2045a0a59b2ea33479937c4b5acef Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 29 Jan 2010 15:30:53 -0700 Subject: [PATCH 164/370] mach-dove/common.c: remove unnecessary (void *) casts The (void *) cast is not needed when setting dev.platform_data to the address of the data. Remove the casts. Signed-off-by: H Hartley Sweeten Signed-off-by: Nicolas Pitre --- arch/arm/mach-dove/common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 806972a68c873..5da2cf402c81d 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -605,7 +605,7 @@ static struct platform_device dove_xor00_channel = { .dev = { .dma_mask = &dove_xor0_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor00_data, + .platform_data = &dove_xor00_data, }, }; @@ -631,7 +631,7 @@ static struct platform_device dove_xor01_channel = { .dev = { .dma_mask = &dove_xor0_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor01_data, + .platform_data = &dove_xor01_data, }, }; @@ -704,7 +704,7 @@ static struct platform_device dove_xor10_channel = { .dev = { .dma_mask = &dove_xor1_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor10_data, + .platform_data = &dove_xor10_data, }, }; @@ -730,7 +730,7 @@ static struct platform_device dove_xor11_channel = { .dev = { .dma_mask = &dove_xor1_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor11_data, + .platform_data = &dove_xor11_data, }, }; -- GitLab From b2fdb5660fccc060e47658baad8911a963397ced Mon Sep 17 00:00:00 2001 From: Alexander Clouter Date: Mon, 18 Jan 2010 23:38:19 +0000 Subject: [PATCH 165/370] [ARM] kirkwood: combine support for openrd base/client support Inspired by the mach-ep93xx flattening work, there is really not much difference between the OpenRD base and client board support so they should be merged together. Signed-off-by: Alexander Clouter Acked-by: Simon Kagstrom Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Kconfig | 11 ++ arch/arm/mach-kirkwood/Makefile | 2 +- arch/arm/mach-kirkwood/openrd-setup.c | 118 +++++++++++++++++++++ arch/arm/mach-kirkwood/openrd_base-setup.c | 96 ----------------- 4 files changed, 130 insertions(+), 97 deletions(-) create mode 100644 arch/arm/mach-kirkwood/openrd-setup.c delete mode 100644 arch/arm/mach-kirkwood/openrd_base-setup.c diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f6c6196a51fa4..4ac6f463eb037 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -46,12 +46,23 @@ config MACH_TS41X QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS devices. +config MACH_OPENRD + bool + config MACH_OPENRD_BASE bool "Marvell OpenRD Base Board" + select MACH_OPENRD help Say 'Y' here if you want your kernel to support the Marvell OpenRD Base Board. +config MACH_OPENRD_CLIENT + bool "Marvell OpenRD Client Board" + select MACH_OPENRD + help + Say 'Y' here if you want your kernel to support the + Marvell OpenRD Client Board. + config MACH_NETSPACE_V2 bool "LaCie Network Space v2 NAS Board" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index d4d7f53b0fb9d..df91d0789f182 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o -obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o +obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c new file mode 100644 index 0000000000000..ad3f1ec337968 --- /dev/null +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -0,0 +1,118 @@ +/* + * arch/arm/mach-kirkwood/openrd-setup.c + * + * Marvell OpenRD (Base|Client) Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + +static struct mtd_partition openrd_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct mv643xx_eth_platform_data openrd_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv643xx_eth_platform_data openrd_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(24), +}; + +static struct mv_sata_platform_data openrd_sata_data = { + .n_ports = 2, +}; + +static struct mvsdio_platform_data openrd_mvsdio_data = { + .gpio_card_detect = 29, /* MPP29 used as SD card detect */ +}; + +static unsigned int openrd_mpp_config[] __initdata = { + MPP29_GPIO, + 0 +}; + +static void __init openrd_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(openrd_mpp_config); + + kirkwood_uart0_init(); + kirkwood_nand_init(ARRAY_AND_SIZE(openrd_nand_parts), 25); + + kirkwood_ehci_init(); + + kirkwood_ge00_init(&openrd_ge00_data); + if (machine_is_openrd_client()) + kirkwood_ge01_init(&openrd_ge01_data); + kirkwood_sata_init(&openrd_sata_data); + kirkwood_sdio_init(&openrd_mvsdio_data); + + kirkwood_i2c_init(); +} + +static int __init openrd_pci_init(void) +{ + if (machine_is_openrd_base() || machine_is_openrd_client()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(openrd_pci_init); + +#ifdef CONFIG_MACH_OPENRD_BASE +MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") + /* Maintainer: Dhaval Vasa */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = openrd_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") + /* Maintainer: Dhaval Vasa */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = openrd_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-kirkwood/openrd_base-setup.c b/arch/arm/mach-kirkwood/openrd_base-setup.c deleted file mode 100644 index 77617c7222995..0000000000000 --- a/arch/arm/mach-kirkwood/openrd_base-setup.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-kirkwood/openrd_base-setup.c - * - * Marvell OpenRD Base Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -static struct mtd_partition openrd_base_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data openrd_base_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data openrd_base_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data openrd_base_mvsdio_data = { - .gpio_card_detect = 29, /* MPP29 used as SD card detect */ -}; - -static unsigned int openrd_base_mpp_config[] __initdata = { - MPP29_GPIO, - 0 -}; - -static void __init openrd_base_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(openrd_base_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(openrd_base_nand_parts), 25); - - kirkwood_ehci_init(); - - kirkwood_ge00_init(&openrd_base_ge00_data); - kirkwood_sata_init(&openrd_base_sata_data); - kirkwood_sdio_init(&openrd_base_mvsdio_data); - - kirkwood_i2c_init(); -} - -static int __init openrd_base_pci_init(void) -{ - if (machine_is_openrd_base()) - kirkwood_pcie_init(); - - return 0; - } -subsys_initcall(openrd_base_pci_init); - - -MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") - /* Maintainer: Dhaval Vasa */ - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = openrd_base_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END -- GitLab From 2d18638ec010a2ed1daa08b4774ed12108647a53 Mon Sep 17 00:00:00 2001 From: Zhu Qingsen Date: Thu, 4 Feb 2010 19:33:27 -0800 Subject: [PATCH 166/370] [ARM] Orion: Add Buffalo Linkstation LS-HGL support Signed-off-by: Zhu Qingsen Signed-off-by: Nicolas Pitre --- arch/arm/configs/orion5x_defconfig | 1 + arch/arm/mach-orion5x/Kconfig | 7 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/ls_hgl-setup.c | 276 +++++++++++++++++++++++++++ 4 files changed, 285 insertions(+) create mode 100644 arch/arm/mach-orion5x/ls_hgl-setup.c diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 85b05d3e279b6..eacc9e973e152 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -192,6 +192,7 @@ CONFIG_MACH_TS209=y CONFIG_MACH_TERASTATION_PRO2=y CONFIG_MACH_LINKSTATION_PRO=y CONFIG_MACH_LINKSTATION_MINI=y +CONFIG_MACH_LINKSTATION_LS_HGL=y CONFIG_MACH_TS409=y CONFIG_MACH_WRT350N_V2=y CONFIG_MACH_TS78XX=y diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c3d513cad5acf..905719a677ae3 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -57,6 +57,13 @@ config MACH_LINKSTATION_MINI Say 'Y' here if you want your kernel to support the Buffalo Linkstation Mini platform. +config MACH_LINKSTATION_LS_HGL + bool "Buffalo Linkstation LS-HGL" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Buffalo Linkstation LS-HGL platform. + config MACH_TS409 bool "QNAP TS-409" help diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 89772fcd65c70..eb6eabcb41e45 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_LINKSTATION_MINI) += lsmini-setup.o +obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c new file mode 100644 index 0000000000000..b9acd6bb382b9 --- /dev/null +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -0,0 +1,276 @@ +/* + * arch/arm/mach-orion5x/ls_hgl-setup.c + * + * Maintainer: Zhu Qingsen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" +#include "include/mach/system.h" + +/***************************************************************************** + * Linkstation LS-HGL Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define LS_HGL_NOR_BOOT_BASE 0xf4000000 +#define LS_HGL_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data ls_hgl_nor_flash_data = { + .width = 1, +}; + +static struct resource ls_hgl_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = LS_HGL_NOR_BOOT_BASE, + .end = LS_HGL_NOR_BOOT_BASE + LS_HGL_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device ls_hgl_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ls_hgl_nor_flash_data, + }, + .num_resources = 1, + .resource = &ls_hgl_nor_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data ls_hgl_eth_data = { + .phy_addr = 8, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +static struct i2c_board_info __initdata ls_hgl_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), +}; + +/***************************************************************************** + * LEDs attached to GPIO + ****************************************************************************/ + +#define LS_HGL_GPIO_LED_ALARM 2 +#define LS_HGL_GPIO_LED_INFO 3 +#define LS_HGL_GPIO_LED_FUNC 17 +#define LS_HGL_GPIO_LED_PWR 0 + + +static struct gpio_led ls_hgl_led_pins[] = { + { + .name = "alarm:red", + .gpio = LS_HGL_GPIO_LED_ALARM, + .active_low = 1, + }, { + .name = "info:amber", + .gpio = LS_HGL_GPIO_LED_INFO, + .active_low = 1, + }, { + .name = "func:blue:top", + .gpio = LS_HGL_GPIO_LED_FUNC, + .active_low = 1, + }, { + .name = "power:blue:bottom", + .gpio = LS_HGL_GPIO_LED_PWR, + }, +}; + +static struct gpio_led_platform_data ls_hgl_led_data = { + .leds = ls_hgl_led_pins, + .num_leds = ARRAY_SIZE(ls_hgl_led_pins), +}; + +static struct platform_device ls_hgl_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &ls_hgl_led_data, + }, +}; + +/**************************************************************************** + * GPIO Attached Keys + ****************************************************************************/ +#define LS_HGL_GPIO_KEY_FUNC 15 +#define LS_HGL_GPIO_KEY_POWER 8 +#define LS_HGL_GPIO_KEY_AUTOPOWER 10 + +#define LS_HGL_SW_POWER 0x00 +#define LS_HGL_SW_AUTOPOWER 0x01 + +static struct gpio_keys_button ls_hgl_buttons[] = { + { + .code = KEY_OPTION, + .gpio = LS_HGL_GPIO_KEY_FUNC, + .desc = "Function Button", + .active_low = 1, + }, { + .type = EV_SW, + .code = LS_HGL_SW_POWER, + .gpio = LS_HGL_GPIO_KEY_POWER, + .desc = "Power-on Switch", + .active_low = 1, + }, { + .type = EV_SW, + .code = LS_HGL_SW_AUTOPOWER, + .gpio = LS_HGL_GPIO_KEY_AUTOPOWER, + .desc = "Power-auto Switch", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data ls_hgl_button_data = { + .buttons = ls_hgl_buttons, + .nbuttons = ARRAY_SIZE(ls_hgl_buttons), +}; + +static struct platform_device ls_hgl_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ls_hgl_button_data, + }, +}; + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data ls_hgl_sata_data = { + .n_ports = 2, +}; + + +/***************************************************************************** + * Linkstation LS-HGL specific power off method: reboot + ****************************************************************************/ +/* + * On the Linkstation LS-HGL, the shutdown process is following: + * - Userland monitors key events until the power switch goes to off position + * - The board reboots + * - U-boot starts and goes into an idle mode waiting for the user + * to move the switch to ON position + */ + +static void ls_hgl_power_off(void) +{ + arch_reset(0, NULL); +} + + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +#define LS_HGL_GPIO_USB_POWER 9 +#define LS_HGL_GPIO_AUTO_POWER 10 +#define LS_HGL_GPIO_POWER 8 + +#define LS_HGL_GPIO_HDD_POWER 1 + +static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* LED_PWR */ + { 1, MPP_GPIO }, /* HDD_PWR */ + { 2, MPP_GPIO }, /* LED_ALARM */ + { 3, MPP_GPIO }, /* LED_INFO */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_GPIO }, /* FAN_LCK */ + { 7, MPP_GPIO }, /* INIT */ + { 8, MPP_GPIO }, /* POWER */ + { 9, MPP_GPIO }, /* USB_PWR */ + { 10, MPP_GPIO }, /* AUTO_POWER */ + { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_UNUSED }, + { 15, MPP_GPIO }, /* FUNC */ + { 16, MPP_UNUSED }, + { 17, MPP_GPIO }, /* LED_FUNC */ + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + +static void __init ls_hgl_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(ls_hgl_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&ls_hgl_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&ls_hgl_sata_data); + orion5x_uart0_init(); + orion5x_xor_init(); + + orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, + LS_HGL_NOR_BOOT_SIZE); + platform_device_register(&ls_hgl_nor_flash); + + platform_device_register(&ls_hgl_button_device); + + platform_device_register(&ls_hgl_leds); + + i2c_register_board_info(0, &ls_hgl_i2c_rtc, 1); + + /* enable USB power */ + gpio_set_value(LS_HGL_GPIO_USB_POWER, 1); + + /* register power-off method */ + pm_power_off = ls_hgl_power_off; + + pr_info("%s: finished\n", __func__); +} + +MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") + /* Maintainer: Zhu Qingsen */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = ls_hgl_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END -- GitLab From 1961528959aa523a351b49236f8627b30793ee80 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Feb 2010 00:20:24 -0500 Subject: [PATCH 167/370] [ARM] orion5x: fix some improper includes in Linkstation files ... and replace misuse of arch_reset() with arm_machine_restart(). Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/ls_hgl-setup.c | 8 ++++---- arch/arm/mach-orion5x/lsmini-setup.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index b9acd6bb382b9..8e569be6e2c7f 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -19,12 +18,13 @@ #include #include #include -#include #include +#include #include +#include +#include #include "common.h" #include "mpp.h" -#include "include/mach/system.h" /***************************************************************************** * Linkstation LS-HGL Info @@ -186,7 +186,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = { static void ls_hgl_power_off(void) { - arch_reset(0, NULL); + arm_machine_restart('h', NULL); } diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index c9bf6b81a80d9..c704f056de1e1 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -19,12 +18,13 @@ #include #include #include -#include #include +#include #include +#include +#include #include "common.h" #include "mpp.h" -#include "include/mach/system.h" /***************************************************************************** * Linkstation Mini Info @@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = { static void lsmini_power_off(void) { - arch_reset(0, NULL); + arm_machine_restart('h', NULL); } -- GitLab From f123560a07313218108d3cc652af99eaaf04d67f Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 4 Feb 2010 23:27:23 -0500 Subject: [PATCH 168/370] [ARM] Kirkwood: update defconfig Signed-off-by: Nicolas Pitre --- arch/arm/configs/kirkwood_defconfig | 126 +++++++++++++++++++++------- 1 file changed, 94 insertions(+), 32 deletions(-) diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 5fc44c94b0ada..4611d3ce451ac 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc6 -# Sat Nov 7 20:31:18 2009 +# Linux kernel version: 2.6.33-rc6 +# Thu Feb 4 23:08:54 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -32,6 +32,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -45,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -127,14 +134,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -163,6 +197,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set CONFIG_ARCH_KIRKWOOD=y # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -185,6 +220,7 @@ CONFIG_ARCH_KIRKWOOD=y # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # # Marvell Kirkwood Implementations @@ -195,7 +231,11 @@ CONFIG_MACH_RD88F6281=y CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_OPENRD=y CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_NETSPACE_V2=y CONFIG_PLAT_ORION=y # @@ -262,12 +302,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y @@ -398,15 +436,18 @@ CONFIG_NET_PKTGEN=m # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=1 # CONFIG_CFG80211_DEBUGFS is not set CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y +CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y # CONFIG_LIB80211_DEBUG is not set @@ -556,6 +597,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -606,7 +651,9 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -642,6 +689,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set @@ -696,15 +744,16 @@ CONFIG_SATA_MV=y # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_SCH is not set @@ -720,7 +769,7 @@ CONFIG_SATA_MV=y # # -# See the help texts for more information. +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -828,13 +877,6 @@ CONFIG_MV643XX_ETH=y # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_LIBERTAS=y -# CONFIG_LIBERTAS_USB is not set -CONFIG_LIBERTAS_SDIO=y -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_ATMEL is not set # CONFIG_AT76C50X_USB is not set @@ -846,19 +888,24 @@ CONFIG_LIBERTAS_SDIO=y # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set -# CONFIG_P54_COMMON is not set # CONFIG_ATH_COMMON is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set # CONFIG_IWLWIFI is not set -# CONFIG_HOSTAP is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set -# CONFIG_RT2X00 is not set +# CONFIG_IWM is not set +CONFIG_LIBERTAS=y +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=y +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set # CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set # CONFIG_WL12XX is not set -# CONFIG_IWM is not set +# CONFIG_ZD1211RW is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -881,6 +928,7 @@ CONFIG_LIBERTAS_SDIO=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -890,6 +938,7 @@ CONFIG_LIBERTAS_SDIO=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -933,6 +982,7 @@ CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -1018,11 +1068,6 @@ CONFIG_I2C_MV64XXX=y # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set -# -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - # # Other I2C/SMBus bus drivers # @@ -1032,7 +1077,6 @@ CONFIG_I2C_MV64XXX=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1048,6 +1092,8 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_GPIO is not set CONFIG_SPI_ORION=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set # # SPI Protocol Masters @@ -1074,10 +1120,12 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: # +# CONFIG_GPIO_CS5535 is not set # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_LANGWELL is not set @@ -1116,6 +1164,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set @@ -1123,6 +1172,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set # CONFIG_EZX_PCAP is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_AB4500_CORE is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -1305,6 +1356,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set CONFIG_MMC=y @@ -1344,6 +1396,7 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set # # LED Triggers @@ -1388,6 +1441,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set @@ -1417,7 +1471,9 @@ CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1684,7 +1740,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1692,7 +1750,11 @@ CONFIG_DEBUG_LL=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # -- GitLab From e233230f9c8f02d4c3a643ec5067ca21bc90ee9a Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Feb 2010 00:24:33 -0500 Subject: [PATCH 169/370] [ARM] orion5x: update defconfig Signed-off-by: Nicolas Pitre --- arch/arm/configs/orion5x_defconfig | 100 ++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 22 deletions(-) diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index eacc9e973e152..ee1ebd8dfa80d 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc6 -# Sat Nov 7 20:52:21 2009 +# Linux kernel version: 2.6.33-rc6 +# Thu Feb 4 23:30:00 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -32,6 +32,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -45,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -122,14 +129,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -158,6 +192,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -180,6 +215,7 @@ CONFIG_ARCH_ORION5X=y # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # # Orion Implementations @@ -269,12 +305,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y @@ -413,10 +447,6 @@ CONFIG_NET_PKTGEN=m # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set # @@ -555,6 +585,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -563,6 +597,7 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set @@ -570,6 +605,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # @@ -622,7 +658,9 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -658,6 +696,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set @@ -712,15 +751,16 @@ CONFIG_SATA_MV=y # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set @@ -737,7 +777,7 @@ CONFIG_SATA_MV=y # # -# See the help texts for more information. +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -843,8 +883,10 @@ CONFIG_MV643XX_ETH=y # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -867,6 +909,7 @@ CONFIG_WLAN=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -876,6 +919,7 @@ CONFIG_WLAN=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -993,11 +1037,6 @@ CONFIG_I2C_MV64XXX=y # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set -# -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - # # Other I2C/SMBus bus drivers # @@ -1007,7 +1046,6 @@ CONFIG_I2C_MV64XXX=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1034,10 +1072,12 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: # +# CONFIG_GPIO_CS5535 is not set # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_LANGWELL is not set @@ -1080,6 +1120,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -1105,6 +1146,7 @@ CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set @@ -1119,6 +1161,7 @@ CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -1141,11 +1184,13 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set +# CONFIG_MFD_88PM8607 is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -1317,6 +1362,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set # CONFIG_MMC is not set @@ -1333,6 +1379,7 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set # # LED Triggers @@ -1378,6 +1425,7 @@ CONFIG_RTC_DRV_PCF8563=y # CONFIG_RTC_DRV_PCF8583 is not set CONFIG_RTC_DRV_M41T80=y # CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_BQ32K is not set CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set @@ -1399,7 +1447,9 @@ CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_M48T86=y # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1687,7 +1737,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1695,7 +1747,11 @@ CONFIG_DEBUG_LL=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # -- GitLab From c793c1b0c8ea11b46caf5a532752214b27a2df42 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:14:49 +0000 Subject: [PATCH 170/370] ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/Kconfig | 7 + arch/arm/Makefile | 1 + arch/arm/mach-shmobile/Kconfig | 53 ++++ arch/arm/mach-shmobile/Makefile | 12 + arch/arm/mach-shmobile/Makefile.boot | 9 + arch/arm/mach-shmobile/board-g3evm.c | 127 +++++++++ arch/arm/mach-shmobile/clock-sh7367.c | 89 +++++++ arch/arm/mach-shmobile/include/mach/clkdev.h | 7 + arch/arm/mach-shmobile/include/mach/common.h | 11 + arch/arm/mach-shmobile/include/mach/dma.h | 1 + .../mach-shmobile/include/mach/entry-macro.S | 39 +++ arch/arm/mach-shmobile/include/mach/gpio.h | 1 + .../arm/mach-shmobile/include/mach/hardware.h | 7 + arch/arm/mach-shmobile/include/mach/io.h | 9 + arch/arm/mach-shmobile/include/mach/irqs.h | 10 + arch/arm/mach-shmobile/include/mach/memory.h | 7 + arch/arm/mach-shmobile/include/mach/system.h | 14 + arch/arm/mach-shmobile/include/mach/timex.h | 6 + .../mach-shmobile/include/mach/uncompress.h | 21 ++ arch/arm/mach-shmobile/include/mach/vmalloc.h | 6 + arch/arm/mach-shmobile/setup-sh7367.c | 241 ++++++++++++++++++ arch/arm/mach-shmobile/timer.c | 46 ++++ 22 files changed, 724 insertions(+) create mode 100644 arch/arm/mach-shmobile/Kconfig create mode 100644 arch/arm/mach-shmobile/Makefile create mode 100644 arch/arm/mach-shmobile/Makefile.boot create mode 100644 arch/arm/mach-shmobile/board-g3evm.c create mode 100644 arch/arm/mach-shmobile/clock-sh7367.c create mode 100644 arch/arm/mach-shmobile/include/mach/clkdev.h create mode 100644 arch/arm/mach-shmobile/include/mach/common.h create mode 100644 arch/arm/mach-shmobile/include/mach/dma.h create mode 100644 arch/arm/mach-shmobile/include/mach/entry-macro.S create mode 100644 arch/arm/mach-shmobile/include/mach/gpio.h create mode 100644 arch/arm/mach-shmobile/include/mach/hardware.h create mode 100644 arch/arm/mach-shmobile/include/mach/io.h create mode 100644 arch/arm/mach-shmobile/include/mach/irqs.h create mode 100644 arch/arm/mach-shmobile/include/mach/memory.h create mode 100644 arch/arm/mach-shmobile/include/mach/system.h create mode 100644 arch/arm/mach-shmobile/include/mach/timex.h create mode 100644 arch/arm/mach-shmobile/include/mach/uncompress.h create mode 100644 arch/arm/mach-shmobile/include/mach/vmalloc.h create mode 100644 arch/arm/mach-shmobile/setup-sh7367.c create mode 100644 arch/arm/mach-shmobile/timer.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 184a6bd548250..55764a1c8763d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -584,6 +584,11 @@ config ARCH_MSM interface to the ARM9 modem processor which runs the baseband stack and controls some vital subsystems (clock and power control, etc). +config ARCH_SHMOBILE + bool "Renesas SH-Mobile" + help + Support for Renesas's SH-Mobile ARM platforms + config ARCH_RPC bool "RiscPC" select ARCH_ACORN @@ -822,6 +827,8 @@ source "arch/arm/mach-s3c6400/Kconfig" source "arch/arm/mach-s3c6410/Kconfig" endif +source "arch/arm/mach-shmobile/Kconfig" + source "arch/arm/plat-stmp3xxx/Kconfig" if ARCH_S5PC1XX diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 356d702c08086..177775fe514db 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -165,6 +165,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark +machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_U300) := u300 diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig new file mode 100644 index 0000000000000..8f4eb13b58692 --- /dev/null +++ b/arch/arm/mach-shmobile/Kconfig @@ -0,0 +1,53 @@ +if ARCH_SHMOBILE + +comment "SH-Mobile System Type" + +config ARCH_SH7367 + bool "SH-Mobile G3 (SH7367)" + select CPU_V6 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + +comment "SH-Mobile Board Type" + +config MACH_G3EVM + bool "G3EVM board" + depends on ARCH_SH7367 + +comment "SH-Mobile System Configuration" + +menu "Memory configuration" + +config MEMORY_START + hex "Physical memory start address" + default "0x50000000" if MACH_G3EVM + default "0x00000000" + ---help--- + Tweak this only when porting to a new machine which does not + already have a defconfig. Changing it from the known correct + value on any of the known systems will only lead to disaster. + +config MEMORY_SIZE + hex "Physical memory size" + default "0x08000000" if MACH_G3EVM + default "0x04000000" + help + This sets the default memory size assumed by your kernel. It can + be overridden as normal by the 'mem=' argument on the kernel command + line. + +endmenu + +menu "Timer and clock configuration" + +config SH_TIMER_CMT + bool "CMT timer driver" + default y + help + This enables build of the CMT timer driver. + +endmenu + +endif diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile new file mode 100644 index 0000000000000..3eca521853d20 --- /dev/null +++ b/arch/arm/mach-shmobile/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for the linux kernel. +# + +# Common objects +obj-y := timer.o + +# CPU objects +obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o + +# Board objects +obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot new file mode 100644 index 0000000000000..1c08ee9de86a6 --- /dev/null +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -0,0 +1,9 @@ +__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ + $$[$(CONFIG_MEMORY_START) + 0x8000]') + + zreladdr-y := $(__ZRELADDR) + +# Unsupported legacy stuff +# +#params_phys-y (Instead: Pass atags pointer in r2) +#initrd_phys-y (Instead: Use compiled-in initramfs) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c new file mode 100644 index 0000000000000..b4b202718e4d6 --- /dev/null +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -0,0 +1,127 @@ +/* + * G3EVM board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *g3evm_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc g3evm_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init g3evm_map_io(void) +{ + iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); + + /* setup early devices and clocks here as well */ + sh7367_add_early_devices(); + sh7367_clock_init(); +} + +static void __init g3evm_init(void) +{ + sh7367_add_standard_devices(); + + platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); +} + +MACHINE_START(G3EVM, "g3evm") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = g3evm_map_io, + .init_irq = sh7367_init_irq, + .init_machine = g3evm_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c new file mode 100644 index 0000000000000..3b2e3f2fc7eaf --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -0,0 +1,89 @@ +/* + * Preliminary clock framework support for sh7367 + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +struct clk { + const char *name; + unsigned long rate; +}; + +#include + +int __clk_get(struct clk *clk) +{ + return 1; +} +EXPORT_SYMBOL(__clk_get); + +void __clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(__clk_put); + + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk ? clk->rate : 0; +} +EXPORT_SYMBOL(clk_get_rate); + +/* a static peripheral clock for now - enough to get sh-sci working */ +static struct clk peripheral_clk = { + .name = "peripheral_clk", + .rate = 48000000, +}; + +/* a static rclk for now - enough to get sh_cmt working */ +static struct clk r_clk = { + .name = "r_clk", + .rate = 32768, +}; + +static struct clk_lookup lookups[] = { + { + .clk = &peripheral_clk, + }, { + .clk = &r_clk, + } +}; + +void __init sh7367_clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + lookups[i].con_id = lookups[i].clk->name; + clkdev_add(&lookups[i]); + } +} diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h new file mode 100644 index 0000000000000..36d0163a857ab --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +int __clk_get(struct clk *clk); +void __clk_put(struct clk *clk); + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h new file mode 100644 index 0000000000000..d771afa79eb68 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -0,0 +1,11 @@ +#ifndef __ARCH_MACH_COMMON_H +#define __ARCH_MACH_COMMON_H + +extern struct sys_timer shmobile_timer; + +extern void sh7367_init_irq(void); +extern void sh7367_add_early_devices(void); +extern void sh7367_add_standard_devices(void); +extern void sh7367_clock_init(void); + +#endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h new file mode 100644 index 0000000000000..40a8c178f10d9 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S new file mode 100644 index 0000000000000..796b304050cca --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =INTFLGA + ldr \irqnr, [\base] + cmp \irqnr, #0 + beq 1000f + /* intevt to irq number */ + lsr \irqnr, \irqnr, #0x5 + subs \irqnr, \irqnr, #16 + +1000: + .endm diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h new file mode 100644 index 0000000000000..40a8c178f10d9 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h new file mode 100644 index 0000000000000..3f0ef194603ef --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/hardware.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_HARDWARE_H +#define __ASM_MACH_HARDWARE_H + +/* INTFLGA register - used by low level interrupt code in entry-macro.S */ +#define INTFLGA 0xe6980018 + +#endif /* __ASM_MACH_HARDWARE_H */ diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h new file mode 100644 index 0000000000000..7339fe46cb7ce --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/io.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_IO_H +#define __ASM_MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif /* __ASM_MACH_IO_H */ diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h new file mode 100644 index 0000000000000..5179b72e1ee3d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -0,0 +1,10 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#define NR_IRQS 512 +#define NR_IRQS_LEGACY 8 + +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h new file mode 100644 index 0000000000000..e188183f4dcee --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_MEMORY_H +#define __ASM_MACH_MEMORY_H + +#define PHYS_OFFSET UL(CONFIG_MEMORY_START) +#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) + +#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h new file mode 100644 index 0000000000000..76a687eeaa22d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/system.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + cpu_reset(0); +} + +#endif diff --git a/arch/arm/mach-shmobile/include/mach/timex.h b/arch/arm/mach-shmobile/include/mach/timex.h new file mode 100644 index 0000000000000..ae0d8d825c231 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/timex.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MACH_TIMEX_H +#define __ASM_MACH_TIMEX_H + +#define CLOCK_TICK_RATE 1193180 /* unused i8253 PIT value */ + +#endif /* __ASM_MACH_TIMEX_H */ diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h new file mode 100644 index 0000000000000..0bd7556b13879 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/uncompress.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_UNCOMPRESS_H +#define __ASM_MACH_UNCOMPRESS_H + +/* + * This does not append a newline + */ +static void putc(int c) +{ +} + +static inline void flush(void) +{ +} + +static void arch_decomp_setup(void) +{ +} + +#define arch_decomp_wdog() + +#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h new file mode 100644 index 0000000000000..fb3c4f1ab2522 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MACH_VMALLOC_H +#define __ASM_MACH_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x24000000) + +#endif /* __ASM_MACH_VMALLOC_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c new file mode 100644 index 0000000000000..840e5bcf2d68a --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -0,0 +1,241 @@ +/* + * sh7367 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7367_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &cmt10_device, +}; + +void __init sh7367_add_standard_devices(void) +{ + platform_add_devices(sh7367_early_devices, + ARRAY_SIZE(sh7367_early_devices)); +} + +#define SYMSTPCR2 0xe6158048 +#define SYMSTPCR2_CMT1 (1 << 29) + +void __init sh7367_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2); + + early_platform_add_devices(sh7367_early_devices, + ARRAY_SIZE(sh7367_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7367", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7367_init_irq(void) +{ + register_intc_controller(&intc_desc); +} diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c new file mode 100644 index 0000000000000..895794b543cdc --- /dev/null +++ b/arch/arm/mach-shmobile/timer.c @@ -0,0 +1,46 @@ +/* + * SH-Mobile Timer + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2002 - 2009 Paul Mundt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ +#include +#include + +static void __init shmobile_late_time_init(void) +{ + /* + * Make sure all compiled-in early timers register themselves. + * + * Run probe() for two "earlytimer" devices, these will be the + * clockevents and clocksource devices respectively. In the event + * that only a clockevents device is available, we -ENODEV on the + * clocksource and the jiffies clocksource is used transparently + * instead. No error handling is necessary here. + */ + early_platform_driver_register_all("earlytimer"); + early_platform_driver_probe("earlytimer", 2, 0); +} + +static void __init shmobile_timer_init(void) +{ + late_time_init = shmobile_late_time_init; +} + +struct sys_timer shmobile_timer = { + .init = shmobile_timer_init, +}; -- GitLab From f2aaf66df0858116b2fcdbbfe8126d4ff925ac61 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:07 +0000 Subject: [PATCH 171/370] ARM: mach-shmobile: SH-Mobile G4 support. This adds preliminary support for the SH7377 (SH-Mobile G4) CPU and the G4EVM reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 14 + arch/arm/mach-shmobile/Makefile | 2 + arch/arm/mach-shmobile/board-g4evm.c | 127 +++++++++ arch/arm/mach-shmobile/include/mach/common.h | 4 + arch/arm/mach-shmobile/setup-sh7377.c | 260 +++++++++++++++++++ 5 files changed, 407 insertions(+) create mode 100644 arch/arm/mach-shmobile/board-g4evm.c create mode 100644 arch/arm/mach-shmobile/setup-sh7377.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 8f4eb13b58692..160b2eef6d819 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -10,12 +10,24 @@ config ARCH_SH7367 select GENERIC_TIME select GENERIC_CLOCKEVENTS +config ARCH_SH7377 + bool "SH-Mobile G4 (SH7377)" + select CPU_V7 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + comment "SH-Mobile Board Type" config MACH_G3EVM bool "G3EVM board" depends on ARCH_SH7367 +config MACH_G4EVM + bool "G4EVM board" + depends on ARCH_SH7377 + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -23,6 +35,7 @@ menu "Memory configuration" config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM + default "0x40000000" if MACH_G4EVM default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -32,6 +45,7 @@ config MEMORY_START config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM + default "0x08000000" if MACH_G4EVM default "0x04000000" help This sets the default memory size assumed by your kernel. It can diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3eca521853d20..3f91268705a3e 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -7,6 +7,8 @@ obj-y := timer.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o +obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c new file mode 100644 index 0000000000000..0d2948f17766d --- /dev/null +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -0,0 +1,127 @@ +/* + * G4EVM board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *g4evm_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc g4evm_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init g4evm_map_io(void) +{ + iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); + + /* setup early devices and clocks here as well */ + sh7377_add_early_devices(); + sh7367_clock_init(); /* use g3 clocks for now */ +} + +static void __init g4evm_init(void) +{ + sh7377_add_standard_devices(); + + platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); +} + +MACHINE_START(G4EVM, "g4evm") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = g4evm_map_io, + .init_irq = sh7377_init_irq, + .init_machine = g4evm_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d771afa79eb68..3595d24b7c8bf 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,4 +8,8 @@ extern void sh7367_add_early_devices(void); extern void sh7367_add_standard_devices(void); extern void sh7367_clock_init(void); +extern void sh7377_init_irq(void); +extern void sh7377_add_early_devices(void); +extern void sh7377_add_standard_devices(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c new file mode 100644 index 0000000000000..e568124ce1972 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -0,0 +1,260 @@ +/* + * sh7377 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6cc0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 196, 196, 196, 196 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7377_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt10_device, +}; + +void __init sh7377_add_standard_devices(void) +{ + platform_add_devices(sh7377_early_devices, + ARRAY_SIZE(sh7377_early_devices)); +} + +#define SMSTPCR3 0xe615013c +#define SMSTPCR3_CMT1 (1 << 29) + +void __init sh7377_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); + + early_platform_add_devices(sh7377_early_devices, + ARRAY_SIZE(sh7377_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, SCIFA6, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), INTC_VECT(SCIFA6, 0x1a80), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { 0, 0, 0, 0, SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, + { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7377", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7377_init_irq(void) +{ + register_intc_controller(&intc_desc); +} -- GitLab From 2b7eda63e489a43575f776a1a32bcfbcd75b9476 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:14:58 +0000 Subject: [PATCH 172/370] ARM: mach-shmobile: SH-Mobile AP4 support. This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and the AP4EVB reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 14 ++ arch/arm/mach-shmobile/Makefile | 2 + arch/arm/mach-shmobile/board-ap4evb.c | 127 ++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 4 + arch/arm/mach-shmobile/setup-sh7372.c | 241 +++++++++++++++++++ 5 files changed, 388 insertions(+) create mode 100644 arch/arm/mach-shmobile/board-ap4evb.c create mode 100644 arch/arm/mach-shmobile/setup-sh7372.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 160b2eef6d819..06b3b6162ff7d 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -18,6 +18,14 @@ config ARCH_SH7377 select GENERIC_TIME select GENERIC_CLOCKEVENTS +config ARCH_SH7372 + bool "SH-Mobile AP4 (SH7372)" + select CPU_V7 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + comment "SH-Mobile Board Type" config MACH_G3EVM @@ -28,6 +36,10 @@ config MACH_G4EVM bool "G4EVM board" depends on ARCH_SH7377 +config MACH_AP4EVB + bool "AP4EVB board" + depends on ARCH_SH7372 + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -36,6 +48,7 @@ config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM default "0x40000000" if MACH_G4EVM + default "0x40000000" if MACH_AP4EVB default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -46,6 +59,7 @@ config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM default "0x08000000" if MACH_G4EVM + default "0x10000000" if MACH_AP4EVB default "0x04000000" help This sets the default memory size assumed by your kernel. It can diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3f91268705a3e..88893dbf71078 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,7 +8,9 @@ obj-y := timer.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o +obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c new file mode 100644 index 0000000000000..a8d815c962327 --- /dev/null +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -0,0 +1,127 @@ +/* + * AP4EVB board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *ap4evb_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc ap4evb_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init ap4evb_map_io(void) +{ + iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); + + /* setup early devices and clocks here as well */ + sh7372_add_early_devices(); + sh7367_clock_init(); /* use g3 clocks for now */ +} + +static void __init ap4evb_init(void) +{ + sh7372_add_standard_devices(); + + platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); +} + +MACHINE_START(AP4EVB, "ap4evb") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = ap4evb_map_io, + .init_irq = sh7372_init_irq, + .init_machine = ap4evb_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 3595d24b7c8bf..a12eb4d75f638 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -12,4 +12,8 @@ extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); extern void sh7377_add_standard_devices(void); +extern void sh7372_init_irq(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c new file mode 100644 index 0000000000000..db972e61c0711 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -0,0 +1,241 @@ +/* + * sh7372 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7372_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &cmt10_device, +}; + +void __init sh7372_add_standard_devices(void) +{ + platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); +} + +#define SMSTPCR3 0xe615013c +#define SMSTPCR3_CMT1 (1 << 29) + +void __init sh7372_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); + + early_platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7372", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7372_init_irq(void) +{ + register_intc_controller(&intc_desc); +} -- GitLab From 13d605de2ece8c8f7c17a88747d90b7931350ee5 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:15 +0000 Subject: [PATCH 173/370] sh: Build drivers/sh for ARM-based SH-Mobile CPUs. Build drivers/sh in the case of ARM-based SH-Mobile CPUs. Shared code for the interrupt controller (INTC) and the gpio/pinmux (PFC) is located there. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/Makefile b/drivers/Makefile index 6ee53c7a57a1c..e94cb1b796333 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_SGI_SN) += sn/ obj-y += firmware/ obj-$(CONFIG_CRYPTO) += crypto/ obj-$(CONFIG_SUPERH) += sh/ +obj-$(CONFIG_ARCH_SHMOBILE) += sh/ obj-$(CONFIG_GENERIC_TIME) += clocksource/ obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ -- GitLab From 65a5b28f0af00dddd785b516914739460562638f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:25 +0000 Subject: [PATCH 174/370] sh: Let INTC set IRQF_VALID on ARM platforms. Reuse the SuperH INTC code on ARM by using set_irq_flags() to set IRQF_VALID on ARM platforms. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/intc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index d5d7f23c19a5e..926013bece126 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c @@ -658,6 +658,10 @@ static void __init intc_register_irq(struct intc_desc *desc, if (desc->ack_regs) ack_handle[irq] = intc_ack_data(desc, d, enum_id); + +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif } static unsigned int __init save_reg(struct intc_desc_int *d, @@ -902,8 +906,12 @@ static unsigned int create_irq_on_node(unsigned int irq_want, int node) out_unlock: spin_unlock_irqrestore(&vector_lock, flags); - if (irq > 0) + if (irq > 0) { dynamic_irq_init(irq); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif + } return irq; } -- GitLab From 8a77b8d0744ab21b59a9413c41c6a3d6cb9b0b4f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:33 +0000 Subject: [PATCH 175/370] serial: sh-sci: Support ARM-based SH-Mobile CPUs. Add support for ARM-based SH-Mobile CPUs to the sh-sci driver. Also remove the SCLSR register that is missing on sh772x, sh7705 and SH-Mobile. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/serial/Kconfig | 2 +- drivers/serial/sh-sci.h | 22 ++++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9ff47db0b2ced..406ad918cbac4 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -996,7 +996,7 @@ config SERIAL_IP22_ZILOG_CONSOLE config SERIAL_SH_SCI tristate "SuperH SCI(F) serial port support" - depends on HAVE_CLK && (SUPERH || H8300) + depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) select SERIAL_CORE config SERIAL_SH_SCI_NR_UARTS diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index f7d2589926d22..fad67d33b0bdd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -30,7 +30,8 @@ */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define PORT_PTCR 0xA405011EUL # define PORT_PVCR 0xA4050122UL @@ -228,7 +229,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCIF_ORER 0x0200 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) # define SCIF_RFDC_MASK 0x007f @@ -261,7 +263,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) @@ -356,7 +359,7 @@ SCI_OUT(sci_size, sci_offset, value); \ } -#ifdef CONFIG_CPU_SH3 +#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ @@ -366,7 +369,8 @@ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -401,7 +405,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCxTDR, 0x20, 8) SCIF_FNS(SCxRDR, 0x24, 8) -SCIF_FNS(SCLSR, 0x24, 16) +SCIF_FNS(SCLSR, 0x00, 0) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) @@ -583,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) -- GitLab From d48d38e87c2ce56dcee030a8bcd5e9e1090c232f Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 8 Feb 2010 12:50:24 +0900 Subject: [PATCH 176/370] MAINTAINERS: Add entry for ARM-based SH-Mobile architecture. Signed-off-by: Paul Mundt --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 03f38c18f3236..9d7e056cb14cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -935,6 +935,16 @@ W: http://www.fluff.org/ben/linux/ S: Maintained F: arch/arm/mach-s3c6410/ +ARM/SHMOBILE ARM ARCHITECTURE +M: Paul Mundt +M: Magnus Damm +L: linux-sh@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git +W: http://oss.renesas.com +S: Supported +F: arch/arm/mach-shmobile/ +F: drivers/sh/ + ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- GitLab From 34bf0fc54a4634ebb0a992e8562191a01233e240 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 03:35:46 +0000 Subject: [PATCH 177/370] ARM: mach-shmobile: G3EVM, G4EVM and AP4EVB defconfigs Add defconfigs for G3EVM, G4EVM and AP4EVB. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/configs/ap4evb_defconfig | 779 ++++++++++++++++++++++++++++++ arch/arm/configs/g3evm_defconfig | 774 +++++++++++++++++++++++++++++ arch/arm/configs/g4evm_defconfig | 779 ++++++++++++++++++++++++++++++ 3 files changed, 2332 insertions(+) create mode 100644 arch/arm/configs/ap4evb_defconfig create mode 100644 arch/arm/configs/g3evm_defconfig create mode 100644 arch/arm/configs/g4evm_defconfig diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig new file mode 100644 index 0000000000000..261913d05b4a6 --- /dev/null +++ b/arch/arm/configs/ap4evb_defconfig @@ -0,0 +1,779 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:25:36 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +# CONFIG_ARCH_SH7367 is not set +# CONFIG_ARCH_SH7377 is not set +CONFIG_ARCH_SH7372=y + +# +# SH-Mobile Board Type +# +CONFIG_MACH_AP4EVB=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x10000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC0,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig new file mode 100644 index 0000000000000..d323ff7efa25d --- /dev/null +++ b/arch/arm/configs/g3evm_defconfig @@ -0,0 +1,774 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:20:01 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +CONFIG_ARCH_SH7367=y +# CONFIG_ARCH_SH7377 is not set +# CONFIG_ARCH_SH7372 is not set + +# +# SH-Mobile Board Type +# +CONFIG_MACH_G3EVM=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x50000000 +CONFIG_MEMORY_SIZE=0x08000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC1,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig new file mode 100644 index 0000000000000..ce8e05fe1a103 --- /dev/null +++ b/arch/arm/configs/g4evm_defconfig @@ -0,0 +1,779 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:21:35 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +# CONFIG_ARCH_SH7367 is not set +CONFIG_ARCH_SH7377=y +# CONFIG_ARCH_SH7372 is not set + +# +# SH-Mobile Board Type +# +CONFIG_MACH_G4EVM=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x08000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC4,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- GitLab From 68c94b40b31926f627573a7f656b903f6644744e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Feb 2010 22:04:32 +0100 Subject: [PATCH 178/370] arm/mx2: use cpp magic to create spi_imx devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the source shorter and easier to verify. While at it switch to use the SoC-prefixed constants. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 78 +++++++++++-------------------------- arch/arm/mach-mx2/devices.h | 2 + 2 files changed, 24 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 3d398ce09b310..ce164a315ee7f 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -46,65 +46,31 @@ * - i.MX21: 2 channel * - i.MX27: 3 channel */ -static struct resource mxc_spi_resources0[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource mxc_spi_resources2[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; -#endif - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; +#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_spi_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device mxc_spi_device ## n = { \ + .name = "spi_imx", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ + .resource = mxc_spi_resources ## n, \ + } -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; +DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); +DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); #ifdef CONFIG_MACH_MX27 -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; +DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); #endif /* diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 97306aa18f1c5..e13a352f0b8a2 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -25,6 +25,8 @@ extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_spi_device2; +#endif extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; -- GitLab From 2b84a3640ffdebbbea3ec004eae963e920c16e1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Feb 2010 14:11:02 +0100 Subject: [PATCH 179/370] arm/mx2: use cpp magic to create imx_gpt devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the source shorter and easier to verify. While at it switch to use the SoC-prefixed constants. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 118 ++++++++---------------------------- arch/arm/mach-mx2/devices.h | 2 + 2 files changed, 26 insertions(+), 94 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index ce164a315ee7f..6efd862426306 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -78,104 +78,34 @@ DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); * - i.MX21: 3 timers * - i.MX27: 6 timers */ - -/* We use gpt0 as system timer, so do not add a device for this one */ - -static struct resource timer1_resources[] = { - { - .start = GPT2_BASE_ADDR, - .end = GPT2_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT2, - .end = MXC_INT_GPT2, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ + static struct resource timer ## n ##_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_gpt ## n = { \ + .name = "imx_gpt", \ + .id = n, \ + .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ + .resource = timer ## n ## _resources, \ } -}; -struct platform_device mxc_gpt1 = { - .name = "imx_gpt", - .id = 1, - .num_resources = ARRAY_SIZE(timer1_resources), - .resource = timer1_resources, -}; - -static struct resource timer2_resources[] = { - { - .start = GPT3_BASE_ADDR, - .end = GPT3_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT3, - .end = MXC_INT_GPT3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt2 = { - .name = "imx_gpt", - .id = 2, - .num_resources = ARRAY_SIZE(timer2_resources), - .resource = timer2_resources, -}; +/* We use gpt1 as system timer, so do not add a device for this one */ +DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); +DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); #ifdef CONFIG_MACH_MX27 -static struct resource timer3_resources[] = { - { - .start = GPT4_BASE_ADDR, - .end = GPT4_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT4, - .end = MXC_INT_GPT4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt3 = { - .name = "imx_gpt", - .id = 3, - .num_resources = ARRAY_SIZE(timer3_resources), - .resource = timer3_resources, -}; - -static struct resource timer4_resources[] = { - { - .start = GPT5_BASE_ADDR, - .end = GPT5_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT5, - .end = MXC_INT_GPT5, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt4 = { - .name = "imx_gpt", - .id = 4, - .num_resources = ARRAY_SIZE(timer4_resources), - .resource = timer4_resources, -}; - -static struct resource timer5_resources[] = { - { - .start = GPT6_BASE_ADDR, - .end = GPT6_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT6, - .end = MXC_INT_GPT6, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt5 = { - .name = "imx_gpt", - .id = 5, - .num_resources = ARRAY_SIZE(timer5_resources), - .resource = timer5_resources, -}; +DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); +DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); +DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); #endif /* diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index e13a352f0b8a2..a0c6e1ad22d28 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -1,8 +1,10 @@ extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_gpt3; extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; +#endif extern struct platform_device mxc_wdt; extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device1; -- GitLab From 9309b2ba54d9082b8eb2ce641ad395cf5d9929f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Feb 2010 22:13:52 +0100 Subject: [PATCH 180/370] arm/mx2: use cpp magic to create imx-i2c devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the source shorter and easier to verify. While at it switch to use the SoC-prefixed constants. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 54 ++++++++++++++----------------------- arch/arm/mach-mx2/devices.h | 2 ++ 2 files changed, 22 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 6efd862426306..b32dfa045088d 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -213,44 +213,30 @@ struct platform_device mxc_fec_device = { }; #endif -static struct resource mxc_i2c_1_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_i2c_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_i2c_device ## n = { \ + .name = "imx-i2c", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ + .resource = mxc_i2c_resources ## n, \ } -}; -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; +DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); #ifdef CONFIG_MACH_MX27 -static struct resource mxc_i2c_2_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; +DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); #endif static struct resource mxc_pwm_resources[] = { diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index a0c6e1ad22d28..0dee0f5e681c4 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -18,7 +18,9 @@ extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; extern struct platform_device mxc_i2c_device0; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_i2c_device1; +#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; -- GitLab From ccd0e42c827666e91296b6395b7b7b04fb8c8803 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Feb 2010 10:46:56 +0100 Subject: [PATCH 181/370] arm/mx2: use cpp magic to create imx-mmc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the source shorter and easier to verify. While at it switch to use the SoC-prefixed constants. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 87 +++++++++++++------------------------ 1 file changed, 31 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index b32dfa045088d..71fd2c5e8a0dc 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -261,63 +261,38 @@ struct platform_device mxc_pwm_device = { /* * Resource definition for the MXC SDHC */ -static struct resource mxc_sdhc1_resources[] = { - { - .start = SDHC1_BASE_ADDR, - .end = SDHC1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC1, - .end = MXC_INT_SDHC1, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC1, - .end = DMA_REQ_SDHC1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 mxc_sdhc1_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .dev = { - .dma_mask = &mxc_sdhc1_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), - .resource = mxc_sdhc1_resources, -}; - -static struct resource mxc_sdhc2_resources[] = { - { - .start = SDHC2_BASE_ADDR, - .end = SDHC2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC2, - .end = MXC_INT_SDHC2, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC2, - .end = DMA_REQ_SDHC2, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ + static struct resource mxc_sdhc_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, { \ + .start = dmareq, \ + .end = dmareq, \ + .flags = IORESOURCE_DMA, \ + }, \ + }; \ + \ + static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \ + \ + struct platform_device mxc_sdhc_device ## n = { \ + .name = "mxc-mmc", \ + .id = n, \ + .dev = { \ + .dma_mask = &mxc_sdhc ## n ## _dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ + .resource = mxc_sdhc_resources ## n, \ + } -static u64 mxc_sdhc2_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .dev = { - .dma_mask = &mxc_sdhc2_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), - .resource = mxc_sdhc2_resources, -}; +DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); +DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); #ifdef CONFIG_MACH_MX27 static struct resource otg_resources[] = { -- GitLab From 69ddb488035068fce9a4ac4a63cffa91dfb3f37f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Feb 2010 12:03:37 +0100 Subject: [PATCH 182/370] arm/mx2: use cpp magic to create imx-ssi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the source shorter and easier to verify. While at it switch to use the SoC-prefixed constants. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 107 +++++++++++------------------------- 1 file changed, 32 insertions(+), 75 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 71fd2c5e8a0dc..bed0fdb43bb85 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -387,83 +387,40 @@ struct platform_device mxc_usbh2 = { }; #endif -static struct resource imx_ssi_resources0[] = { - { - .start = SSI1_BASE_ADDR, - .end = SSI1_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI1, - .end = MXC_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI1_TX0, - .end = DMA_REQ_SSI1_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI1_RX0, - .end = DMA_REQ_SSI1_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI1_TX1, - .end = DMA_REQ_SSI1_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI1_RX1, - .end = DMA_REQ_SSI1_RX1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = SSI2_BASE_ADDR, - .end = SSI2_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI2, - .end = MXC_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI2_TX0, - .end = DMA_REQ_SSI2_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI2_RX0, - .end = DMA_REQ_SSI2_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI2_TX1, - .end = DMA_REQ_SSI2_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI2_RX1, - .end = DMA_REQ_SSI2_RX1, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ + { \ + .name = _name, \ + .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .flags = IORESOURCE_DMA, \ + } -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; +#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ + static struct resource imx_ssi_resources ## n[] = { \ + { \ + .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ + .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = MX2x_INT_SSI1, \ + .end = MX2x_INT_SSI1, \ + .flags = IORESOURCE_IRQ, \ + }, \ + DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ + DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ + DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ + DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ + }; \ + \ + struct platform_device imx_ssi_device ## n = { \ + .name = "imx-ssi", \ + .id = n, \ + .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ + .resource = imx_ssi_resources ## n, \ + } -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; +DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); +DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { -- GitLab From 58152a16901dfce8662f5ec7e16d06dfce6fd31e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Feb 2010 11:42:54 +0100 Subject: [PATCH 183/370] arm/mx2/devices: use SoC-prefixed names where possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is only NFC_BASE_ADDR left which is defined differently for mx21 and mx27. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 110 ++++++++++++++++++------------------ 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index bed0fdb43bb85..9bf49da530728 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -116,9 +116,9 @@ DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); */ static struct resource mxc_wdt_resources[] = { { - .start = WDOG_BASE_ADDR, - .end = WDOG_BASE_ADDR + 0x30, - .flags = IORESOURCE_MEM, + .start = MX2x_WDOG_BASE_ADDR, + .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, }; @@ -131,8 +131,8 @@ struct platform_device mxc_wdt = { static struct resource mxc_w1_master_resources[] = { { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .start = MX2x_OWIRE_BASE_ADDR, + .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -146,13 +146,13 @@ struct platform_device mxc_w1_master_device = { static struct resource mxc_nand_resources[] = { { - .start = NFC_BASE_ADDR, - .end = NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, + .start = MX2x_INT_NANDFC, + .end = MX2x_INT_NANDFC, + .flags = IORESOURCE_IRQ, }, }; @@ -171,12 +171,12 @@ struct platform_device mxc_nand_device = { */ static struct resource mxc_fb[] = { { - .start = LCDC_BASE_ADDR, - .end = LCDC_BASE_ADDR + 0xFFF, + .start = MX2x_LCDC_BASE_ADDR, + .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_LCDC, - .end = MXC_INT_LCDC, + .start = MX2x_INT_LCDC, + .end = MX2x_INT_LCDC, .flags = IORESOURCE_IRQ, } }; @@ -195,13 +195,13 @@ struct platform_device mxc_fb_device = { #ifdef CONFIG_MACH_MX27 static struct resource mxc_fec_resources[] = { { - .start = FEC_BASE_ADDR, - .end = FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, + .start = MX27_FEC_BASE_ADDR, + .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_FEC, - .end = MXC_INT_FEC, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_FEC, + .end = MX27_INT_FEC, + .flags = IORESOURCE_IRQ, }, }; @@ -241,13 +241,13 @@ DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); static struct resource mxc_pwm_resources[] = { { - .start = PWM_BASE_ADDR, - .end = PWM_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, + .start = MX2x_PWM_BASE_ADDR, + .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_PWM, - .end = MXC_INT_PWM, - .flags = IORESOURCE_IRQ, + .start = MX2x_INT_PWM, + .end = MX2x_INT_PWM, + .flags = IORESOURCE_IRQ, } }; @@ -297,13 +297,13 @@ DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC #ifdef CONFIG_MACH_MX27 static struct resource otg_resources[] = { { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, + .start = MX27_USBOTG_BASE_ADDR, + .end = MX27_USBOTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_USB3, + .end = MX27_INT_USB3, + .flags = IORESOURCE_IRQ, }, }; @@ -311,14 +311,14 @@ static u64 otg_dmamask = 0xffffffffUL; /* OTG gadget device */ struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffffUL, + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &otg_dmamask, + .coherent_dma_mask = 0xffffffffUL, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), }; /* OTG host */ @@ -339,12 +339,12 @@ static u64 usbh1_dmamask = 0xffffffffUL; static struct resource mxc_usbh1_resources[] = { { - .start = OTG_BASE_ADDR + 0x200, - .end = OTG_BASE_ADDR + 0x3ff, + .start = MX27_USBOTG_BASE_ADDR + 0x200, + .end = MX27_USBOTG_BASE_ADDR + 0x3ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, + .start = MX27_INT_USB1, + .end = MX27_INT_USB1, .flags = IORESOURCE_IRQ, }, }; @@ -365,12 +365,12 @@ static u64 usbh2_dmamask = 0xffffffffUL; static struct resource mxc_usbh2_resources[] = { { - .start = OTG_BASE_ADDR + 0x400, - .end = OTG_BASE_ADDR + 0x5ff, + .start = MX27_USBOTG_BASE_ADDR + 0x400, + .end = MX27_USBOTG_BASE_ADDR + 0x5ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, + .start = MX27_INT_USB2, + .end = MX27_INT_USB2, .flags = IORESOURCE_IRQ, }, }; @@ -426,28 +426,28 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); static struct mxc_gpio_port imx_gpio_ports[] = { { .chip.label = "gpio-0", - .irq = MXC_INT_GPIO, - .base = IO_ADDRESS(GPIO_BASE_ADDR), + .irq = MX2x_INT_GPIO, + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR), .virtual_irq_start = MXC_GPIO_IRQ_START, }, { .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x100), .virtual_irq_start = MXC_GPIO_IRQ_START + 32, }, { .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x200), .virtual_irq_start = MXC_GPIO_IRQ_START + 64, }, { .chip.label = "gpio-3", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x300), .virtual_irq_start = MXC_GPIO_IRQ_START + 96, }, { .chip.label = "gpio-4", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x400), .virtual_irq_start = MXC_GPIO_IRQ_START + 128, }, { .chip.label = "gpio-5", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), + .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x500), .virtual_irq_start = MXC_GPIO_IRQ_START + 160, } }; -- GitLab From 62f60d6a37910501814c6281e6c21b485434a7f1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 10:53:13 +0000 Subject: [PATCH 184/370] ARM: mach-shmobile: optimize get_irqnr_preamble/and_base macros Optimize the SH-Mobile interrupt assembly macros to avoid reloading the INTFLGA register address in case of multiple pending interrupts. Kindly pointed out by Russell King. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/include/mach/entry-macro.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S index 796b304050cca..a285d13c74165 100644 --- a/arch/arm/mach-shmobile/include/mach/entry-macro.S +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -21,13 +21,13 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =INTFLGA .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =INTFLGA ldr \irqnr, [\base] cmp \irqnr, #0 beq 1000f -- GitLab From 4ae04acb81256719a71125c0f0280e2a3ad68e25 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 11:02:54 +0000 Subject: [PATCH 185/370] ARM: mach-shmobile: early console support using earlyprintk Add support for early console to the SH-Mobile boards. Simply perform an early platform probe for "earlyprintk" to trigger the early serial console code in sh-sci.c. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/configs/ap4evb_defconfig | 2 +- arch/arm/configs/g3evm_defconfig | 2 +- arch/arm/configs/g4evm_defconfig | 2 +- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/board-ap4evb.c | 3 +- arch/arm/mach-shmobile/board-g3evm.c | 3 +- arch/arm/mach-shmobile/board-g4evm.c | 3 +- arch/arm/mach-shmobile/console.c | 31 ++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 1 + 9 files changed, 42 insertions(+), 7 deletions(-) create mode 100644 arch/arm/mach-shmobile/console.c diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig index 261913d05b4a6..e14229be76769 100644 --- a/arch/arm/configs/ap4evb_defconfig +++ b/arch/arm/configs/ap4evb_defconfig @@ -322,7 +322,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC0,115200" +CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig index d323ff7efa25d..3c19031961dbc 100644 --- a/arch/arm/configs/g3evm_defconfig +++ b/arch/arm/configs/g3evm_defconfig @@ -317,7 +317,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC1,115200" +CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig index ce8e05fe1a103..8ee79a5371348 100644 --- a/arch/arm/configs/g4evm_defconfig +++ b/arch/arm/configs/g4evm_defconfig @@ -322,7 +322,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC4,115200" +CONFIG_CMDLINE="console=ttySC4,115200 earlyprintk=sh-sci.4,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 88893dbf71078..800e7dd9e9d15 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -3,7 +3,7 @@ # # Common objects -obj-y := timer.o +obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a8d815c962327..94b545b3fe820 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -105,9 +105,10 @@ static void __init ap4evb_map_io(void) { iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7372_add_early_devices(); sh7367_clock_init(); /* use g3 clocks for now */ + shmobile_setup_console(); } static void __init ap4evb_init(void) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index b4b202718e4d6..eba2311beba22 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -105,9 +105,10 @@ static void __init g3evm_map_io(void) { iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7367_add_early_devices(); sh7367_clock_init(); + shmobile_setup_console(); } static void __init g3evm_init(void) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 0d2948f17766d..0ddde038588e0 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -105,9 +105,10 @@ static void __init g4evm_map_io(void) { iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7377_add_early_devices(); sh7367_clock_init(); /* use g3 clocks for now */ + shmobile_setup_console(); } static void __init g4evm_init(void) diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c new file mode 100644 index 0000000000000..9411a5bf4fd6e --- /dev/null +++ b/arch/arm/mach-shmobile/console.c @@ -0,0 +1,31 @@ +/* + * SH-Mobile Console + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +void __init shmobile_setup_console(void) +{ + parse_early_param(); + + /* Let earlyprintk output early console messages */ + early_platform_driver_probe("earlyprintk", 1, 1); +} diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index a12eb4d75f638..f5986ea561f33 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -2,6 +2,7 @@ #define __ARCH_MACH_COMMON_H extern struct sys_timer shmobile_timer; +extern void shmobile_setup_console(void); extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); -- GitLab From f8eef1305b33438dd7a3a01e43b94e57ca87fc9b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:35:42 +0000 Subject: [PATCH 186/370] ARM: mach-shmobile: sh7367 INTCA support Add support for the sh7367 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7367.c | 270 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7367.c | 43 ---- 3 files changed, 271 insertions(+), 44 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7367.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 800e7dd9e9d15..1ae3633c8ab3d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -6,7 +6,7 @@ obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c new file mode 100644 index 0000000000000..6a547b47aabbb --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -0,0 +1,270 @@ +/* + * sh7367 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + DIRC, + CRYPT1_ERR, CRYPT2_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX, + ETM11_ACQCMP, ETM11_FULL, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, + MSU_MSU, MSU_MSU2, + IREM, + SIU, + SPU, + IRDA, + TPU0, TPU1, TPU2, TPU3, TPU4, + LCRC, + PINT1, PINT2, + TTI20, + MISTY, + DDM, + SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, + RWDT0, RWDT1, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, + ETM11, ARM11, USBHS, FLCTL, IIC1, SDHI0, SDHI1, SDHI2, +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(CRYPT1_ERR, 0x05e0), + INTC_VECT(CRYPT2_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840), + INTC_VECT(ARM11_COMMRX, 0x0860), + INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), + INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), + INTC_VECT(IREM, 0x0f60), + INTC_VECT(SIU, 0x0fa0), + INTC_VECT(SPU, 0x0fc0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), + INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), + INTC_VECT(TPU4, 0x0520), + INTC_VECT(LCRC, 0x0540), + INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(MISTY, 0x1120), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), + INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), + INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL), + INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2, SDHI1_SDHI1I3), + INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, + SDHI2_SDHI2I2, SDHI2_SDHI2I3), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { CRYPT1_ERR, CRYPT2_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { PINT1, PINT2, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, ETM11_FULL, ETM11_ACQCMP } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBDMAC_USHDMI, SPU, SIU } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, USBHS_USHI1, USBHS_USHI0, 0 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + LCRC, MSU_MSU2, IREM, MSU_MSU } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, TPU1, + TPU2, TPU3, TPU4, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, + MISTY, CMT3, RWDT1, RWDT0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, + CMT1_CMT11, ARM11 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2, + CMT1_CMT12, TPU4 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, USBHS } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + 0, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7367-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7367_init_irq(void) +{ + /* INTCA */ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index 840e5bcf2d68a..eca90716140e2 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -197,45 +196,3 @@ void __init sh7367_add_early_devices(void) early_platform_add_devices(sh7367_early_devices, ARRAY_SIZE(sh7367_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7367", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7367_init_irq(void) -{ - register_intc_controller(&intc_desc); -} -- GitLab From 6673be73809c8aa1ca5255c83f4fc85c43fdbfab Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:35:53 +0000 Subject: [PATCH 187/370] ARM: mach-shmobile: sh7377 INTCA support Add support for the sh7377 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7377.c | 350 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7377.c | 45 ---- 3 files changed, 351 insertions(+), 46 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7377.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 1ae3633c8ab3d..7864f6299af7e 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -7,7 +7,7 @@ obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o -obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o # Board objects diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c new file mode 100644 index 0000000000000..125021cfba5c6 --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -0,0 +1,350 @@ +/* + * sh7377 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, + IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, + DIRC, + _2DG, + CRYPT_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + _3DG_SGX540, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, + MSU_MSU, MSU_MSU2, + IRREM, + MSUG, + IRDA, + TPU0, TPU1, TPU2, TPU3, TPU4, + LCRC, + PINTCA_PINT1, PINTCA_PINT2, + TTI20, + MISTY, + DDM, + RWDT0, RWDT1, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + ICUSB_ICUSB0, ICUSB_ICUSB1, + ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, + SPU2_SPU0, SPU2_SPU1, + FSI, + FMSI, + SCUV, + IPMMU_IPMMUB, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + SCIFA6, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, + ICUSB, ICUDMC +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), + INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), + INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), + INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), + INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), + INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), + INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), + INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(_2DG, 0x05e0), + INTC_VECT(CRYPT_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(_3DG_SGX540, 0x0a60), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), + INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), + INTC_VECT(IRREM, 0x0f60), + INTC_VECT(MSUG, 0x0fa0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), + INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), + INTC_VECT(TPU4, 0x0520), + INTC_VECT(LCRC, 0x0540), + INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(MISTY, 0x1120), + INTC_VECT(DDM, 0x1140), + INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720), + INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0), + INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(SCUV, 0x1880), + INTC_VECT(IPMMU_IPMMUB, 0x1900), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), + INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), + INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), + INTC_VECT(MFIS2, 0x1a00), + INTC_VECT(CPORTR2S, 0x1a20), + INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), + INTC_VECT(SCIFA6, 0x1a80), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2, SDHI1_SDHI1I3), + INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), + INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1), + INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { _2DG, CRYPT_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { PINTCA_PINT1, PINTCA_PINT2, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBDMAC_USHDMI, 0, MSUG } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + LCRC, MSU_MSU2, IRREM, MSU_MSU } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, TPU1, + TPU2, TPU3, TPU4, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { 0, 0, 0, 0, + MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ + { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0, + ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } }, + { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ + { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, + SCUV, 0, 0, 0 } }, + { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ + { IPMMU_IPMMUB, 0, 0, 0, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { MFIS2, CPORTR2S, CMT14, CMT15, + SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690001c, 0, 32, 4, /* INTPRI30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, + CMT1_CMT11, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2, + CMT1_CMT12, TPU4 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, USBHS } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + _3DG_SGX540, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } }, + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } }, + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900008, 16, 2, /* ICR3A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690000c, 16, 2, /* ICR4A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900028, 0, 8, /* INTREQ20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690002c, 0, 8, /* INTREQ30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7377-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7377_init_irq(void) +{ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index e568124ce1972..60e37774c35c2 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -213,48 +213,3 @@ void __init sh7377_add_early_devices(void) early_platform_add_devices(sh7377_early_devices, ARRAY_SIZE(sh7377_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, SCIFA6, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), INTC_VECT(SCIFA6, 0x1a80), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, - { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ - { 0, 0, 0, 0, SCIFA6, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, - { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7377", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7377_init_irq(void) -{ - register_intc_controller(&intc_desc); -} -- GitLab From e4e430c611db75f58d3ca33869e182a530859426 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:36:03 +0000 Subject: [PATCH 188/370] ARM: mach-shmobile: sh7372 INTCA support Add support for the sh7372 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7372.c | 367 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7372.c | 42 --- 3 files changed, 368 insertions(+), 43 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7372.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 7864f6299af7e..89ea4b0ea52d1 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,7 +8,7 @@ obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o -obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c new file mode 100644 index 0000000000000..c6e747f92462b --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -0,0 +1,367 @@ +/* + * sh7372 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, + IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, + DIRC, + CRYPT_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBHSDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + _3DG_SGX540, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, + IRREM, + IRDA, + TPU0, + TTI20, + DDM, + SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, + RWDT0, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + HDMI, + SPU2_SPU0, SPU2_SPU1, + FSI, FMSI, + MIPI_HSI, + IPMMU_IPMMUD, + CEC_CEC_1, CEC_CEC_2, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + MMC_MMC_ERR, MMC_MMC_NOR, + IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, + IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, + USB0_USB0I1, USB0_USB0I0, + USB1_USB1I1, USB1_USB1I0, + USHSDMI, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), + INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), + INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), + INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), + INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), + INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), + INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), + INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(CRYPT_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBHSDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(_3DG_SGX540, 0x0a60), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), + INTC_VECT(IRREM, 0x0f60), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), + INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), + INTC_VECT(RWDT0, 0x1280), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(HDMI, 0x17e0), + INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(MIPI_HSI, 0x18e0), + INTC_VECT(IPMMU_IPMMUD, 0x1920), + INTC_VECT(CEC_CEC_1, 0x1940), INTC_VECT(CEC_CEC_2, 0x1960), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), + INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), + INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), + INTC_VECT(MFIS2, 0x1a00), + INTC_VECT(CPORTR2S, 0x1a20), + INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), + INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0), + INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20), + INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60), + INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0), + INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), + INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), + INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), + INTC_VECT(USHSDMI, 0x1d00), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2), + INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, + SDHI2_SDHI2I2, SDHI2_SDHI2I3), + INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { 0, CRYPT_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { 0, 0, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBHSDMAC_USHDMI, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, 0, 0, _3DG_SGX540 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + 0, 0, IRREM, 0 } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, 0, + 0, 0, 0, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, + 0, CMT3, 0, RWDT0 } }, + { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ + { 0, 0, 0, 0, + 0, 0, 0, HDMI } }, + { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ + { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, + 0, 0, 0, MIPI_HSI } }, + { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ + { 0, IPMMU_IPMMUD, CEC_CEC_1, CEC_CEC_2, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { MFIS2, CPORTR2S, CMT14, CMT15, + 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } }, + { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */ + { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, + IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, + { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */ + { 0, 0, 0, 0, + USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, + { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ + { USBHSDMAC_USHDMI, 0, 0, 0, + 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690001c, 0, 32, 4, /* INTPRI30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, + CMT1_CMT11, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, + CMT1_CMT12, 0 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, 0 } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + _3DG_SGX540, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, 0, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, + CEC_CEC_1, CEC_CEC_2 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, + MMC_MMC_ERR, MMC_MMC_NOR } }, + { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, + IIC4_WAITI4, IIC4_DTEI4 } }, + { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, + IIC3_WAITI3, IIC3_DTEI3 } }, + { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0, 0, 0, 0 } }, + { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, + USB1_USB1I1, USB1_USB1I0 } }, + { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC_USHDMI, 0, 0, 0 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900008, 16, 2, /* ICR3A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690000c, 16, 2, /* ICR4A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900028, 0, 8, /* INTREQ20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690002c, 0, 8, /* INTREQ30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7372_init_irq(void) +{ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index db972e61c0711..1d1153290f594 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -197,45 +197,3 @@ void __init sh7372_add_early_devices(void) early_platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7372", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7372_init_irq(void) -{ - register_intc_controller(&intc_desc); -} -- GitLab From a003708ad4ee9384226251431c7953a24079ff80 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 3 Dec 2009 22:36:41 +0200 Subject: [PATCH 189/370] mxc: TrustZone interrupt controller (TZIC) for Freescale i.MX5 family Freescale i.MX51 processor uses a new interrupt controller. Add driver for TrustZone Interrupt Controller Signed-off-by: Amit Kucheria --- arch/arm/plat-mxc/Kconfig | 8 + arch/arm/plat-mxc/Makefile | 3 + arch/arm/plat-mxc/include/mach/common.h | 1 + arch/arm/plat-mxc/include/mach/entry-macro.S | 34 +++- arch/arm/plat-mxc/include/mach/irqs.h | 6 +- arch/arm/plat-mxc/tzic.c | 172 +++++++++++++++++++ 6 files changed, 222 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-mxc/tzic.c diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 8b0a1ee039fa5..59558c4b9446e 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -62,6 +62,14 @@ config MXC_IRQ_PRIOR requirements for timing. Say N here, unless you have a specialized requirement. +config MXC_TZIC + bool "Enable TrustZone Interrupt Controller" + depends on ARCH_MX51 + help + This will be automatically selected for all processors + containing this interrupt controller. + Say N here only if you are really sure. + config MXC_PWM tristate "Enable PWM driver" depends on ARCH_MXC diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 7322bca8f5fba..a4bc6cb26aa42 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -5,6 +5,9 @@ # Common support obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +obj-$(CONFIG_MXC_TZIC) += tzic.o + obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4bf1068ffad9a..1394025068c36 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -22,6 +22,7 @@ extern void mx31_map_io(void); extern void mx35_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); +extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); extern void mx21_init_irq(void); extern void mx25_init_irq(void); diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 7cf290efe768a..aeb08697726b7 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Lennert Buytenhek - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -18,11 +18,16 @@ .endm .macro get_irqnr_preamble, base, tmp +#ifndef CONFIG_MXC_TZIC ldr \base, =avic_base ldr \base, [\base] #ifdef CONFIG_MXC_IRQ_PRIOR ldr r4, [\base, #AVIC_NIMASK] #endif +#elif defined CONFIG_MXC_TZIC + ldr \base, =tzic_base + ldr \base, [\base] +#endif /* CONFIG_MXC_TZIC */ .endm .macro arch_ret_to_user, tmp1, tmp2 @@ -32,6 +37,7 @@ @ and returns its number in irqnr @ and returns if an interrupt occured in irqstat .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#ifndef CONFIG_MXC_TZIC @ Load offset & priority of the highest priority @ interrupt pending from AVIC_NIVECSR ldr \irqstat, [\base, #0x40] @@ -44,6 +50,32 @@ bicne \tmp, \irqstat, #0xFFFFFFE0 strne \tmp, [\base, #AVIC_NIMASK] streq r4, [\base, #AVIC_NIMASK] +#endif +#elif defined CONFIG_MXC_TZIC + @ Load offset & priority of the highest priority + @ interrupt pending. + @ 0xD80 is HIPND0 register + mov \irqnr, #0 + mov \irqstat, #0x0D80 +1000: + ldr \tmp, [\irqstat, \base] + cmp \tmp, #0 + bne 1001f + addeq \irqnr, \irqnr, #32 + addeq \irqstat, \irqstat, #4 + cmp \irqnr, #128 + blo 1000b + b 2001f +1001: mov \irqstat, #1 +1002: tst \tmp, \irqstat + bne 2002f + movs \tmp, \tmp, lsr #1 + addne \irqnr, \irqnr, #1 + bne 1002b +2001: + mov \irqnr, #0 +2002: + movs \irqnr, \irqnr #endif .endm diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db49..38f150162e451 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -12,9 +12,13 @@ #define __ASM_ARCH_MXC_IRQS_H__ /* - * So far all i.MX SoCs have 64 internal interrupts + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#else #define MXC_INTERNAL_IRQS 64 +#endif #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c new file mode 100644 index 0000000000000..afa6709db0b34 --- /dev/null +++ b/arch/arm/plat-mxc/tzic.c @@ -0,0 +1,172 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + ***************************************** + * TZIC Registers * + ***************************************** + */ + +#define TZIC_INTCNTL 0x0000 /* Control register */ +#define TZIC_INTTYPE 0x0004 /* Controller Type register */ +#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ +#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ +#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ +#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ +#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ +#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ +#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ +#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ +#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ +#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ +#define TZIC_PND0 0x0D00 /* Pending Register 0 */ +#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ +#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ +#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ +#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ + +void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ + +/** + * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void tzic_mask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); +} + +/** + * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void tzic_unmask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); +} + +static unsigned int wakeup_intr[4]; + +/** + * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source. + * + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) +{ + unsigned int index, off; + + index = irq >> 5; + off = irq & 0x1F; + + if (index > 3) + return -EINVAL; + + if (enable) + wakeup_intr[index] |= (1 << off); + else + wakeup_intr[index] &= ~(1 << off); + + return 0; +} + +static struct irq_chip mxc_tzic_chip = { + .name = "MXC_TZIC", + .ack = tzic_mask_irq, + .mask = tzic_mask_irq, + .unmask = tzic_unmask_irq, + .set_wake = tzic_set_wake_irq, +}; + +/* + * This function initializes the TZIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init tzic_init_irq(void __iomem *irqbase) +{ + int i; + + tzic_base = irqbase; + /* put the TZIC into the reset value with + * all interrupts disabled + */ + i = __raw_readl(tzic_base + TZIC_INTCNTL); + + __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); + __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); + __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); + + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); + + /* disable all interrupts */ + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); + + /* all IRQ no FIQ Warning :: No selection */ + + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + set_irq_chip(i, &mxc_tzic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); +} + +/** + * tzic_enable_wake() - enable wakeup interrupt + * + * @param is_idle 1 if called in idle loop (ENSET0 register); + * 0 to be used when called from low power entry + * @return 0 if successful; non-zero otherwise + */ +int tzic_enable_wake(int is_idle) +{ + unsigned int i, v; + + __raw_writel(1, tzic_base + TZIC_DSMINT); + if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) + return -EAGAIN; + + for (i = 0; i < 4; i++) { + v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i]; + __raw_writel(v, TZIC_WAKEUP0(i)); + } + + return 0; +} -- GitLab From 0f3332c4fabb2227b1bc15dc7542017d08f10a09 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Dec 2009 09:34:51 +0100 Subject: [PATCH 190/370] mxc: refactor timer code to use timer versions Refactor the timer code into version 1 and version 2. Essentially there are 2 versions of the timer hardware on Freescale MXC hardware. Version 1 is found on MX1/MXL, MX21 and MX27. Version 2 is found on MX25, MX31, MX35, MX37, MX51, and future parts. Signed-off-by: Sascha Hauer Acked-by: Grant Likely Signed-off-by: Amit Kucheria --- arch/arm/plat-mxc/time.c | 41 +++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 844567ee35feb..c1ce51abdba61 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -30,9 +30,15 @@ #include #include +/* + * There are 2 versions of the timer hardware on Freescale MXC hardware. + * Version 1: MX1/MXL, MX21, MX27. + * Version 2: MX25, MX31, MX35, MX37, MX51 + */ + /* defines common for all i.MX */ #define MXC_TCTL 0x00 -#define MXC_TCTL_TEN (1 << 0) +#define MXC_TCTL_TEN (1 << 0) /* Enable module */ #define MXC_TPRER 0x04 /* MX1, MX21, MX27 */ @@ -47,8 +53,8 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25, MXC91231 */ -#define MX3_TCTL_WAITEN (1 << 3) +/* MX31, MX35, MX25, MXC91231, MX5 */ +#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_FRR (1 << 9) #define MX3_IR 0x0c @@ -57,6 +63,9 @@ #define MX3_TCN 0x24 #define MX3_TCMP 0x10 +#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) +#define timer_is_v2() (!timer_is_v1()) + static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; @@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void) { unsigned int tmp; - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(0, timer_base + MX3_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); @@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void) static inline void gpt_irq_enable(void) { - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(1<<0, timer_base + MX3_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, @@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void) static void gpt_irq_acknowledge(void) { - if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); - if (cpu_is_mx2()) - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v1()) { + if (cpu_is_mx1()) + __raw_writel(0, timer_base + MX1_2_TSTAT); + else + __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + timer_base + MX1_2_TSTAT); + } else if (timer_is_v2()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); } @@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, @@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else @@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) tstat = __raw_readl(timer_base + MX3_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); @@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, @@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; -- GitLab From 438caa3f6c91ba21c539a8547c4075b619dc6500 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 4 Feb 2010 12:09:40 -0800 Subject: [PATCH 191/370] mxc: changes to common plat-mxc code to add support for i.MX5 Prepare for i.MX5 SoC code by adding the relevant macros to common plat-mxc code. Signed-off-by: Amit Kucheria --- arch/arm/plat-mxc/include/mach/debug-macro.S | 9 +++++++++ arch/arm/plat-mxc/include/mach/hardware.h | 4 ++++ arch/arm/plat-mxc/include/mach/irqs.h | 3 +++ arch/arm/plat-mxc/include/mach/memory.h | 3 +++ arch/arm/plat-mxc/include/mach/mxc.h | 13 +++++++++++++ arch/arm/plat-mxc/include/mach/timex.h | 2 ++ 6 files changed, 34 insertions(+) diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 916d4fcb2ef2d..133d66bfb533c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -45,6 +45,15 @@ #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) #endif +#ifdef CONFIG_ARCH_MX5 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#include +#define UART_PADDR MX51_UART1_BASE_ADDR +#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) +#endif + #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index db14c56930a3a..ebadf4ac43fce 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -27,6 +27,10 @@ (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) +#ifdef CONFIG_ARCH_MX5 +#include +#endif + #ifdef CONFIG_ARCH_MX3 #include #include diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 38f150162e451..a3ad643de5a1c 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -30,6 +30,8 @@ #define MXC_GPIO_IRQS (32 * 3) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX5 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) #endif @@ -55,6 +57,7 @@ #else #define MX3_IPU_IRQS 0 #endif +/* REVISIT: Add IPU irqs on IMX51 */ #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 002eb91ab235c..7cae9cb6208dc 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -16,6 +16,7 @@ #define MX25_PHYS_OFFSET UL(0x80000000) #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX51_PHYS_OFFSET UL(0x90000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -31,6 +32,8 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX5 +# define PHYS_OFFSET MX51_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 800ae2a33b159..a790bf2129720 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -30,6 +30,7 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX51 51 #define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ @@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_MX5 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX51 +# endif +# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) +#else +# define cpu_is_mx51() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 527a6c24788ec..024416ed11cd9 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -28,6 +28,8 @@ #define CLOCK_TICK_RATE 16625000 #elif defined CONFIG_ARCH_MX25 #define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX5 +#define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MXC91231 #define CLOCK_TICK_RATE 13000000 #endif -- GitLab From a329b48c43e5e2e6b51ce159d99aefeb90c7c066 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 4 Feb 2010 12:21:53 -0800 Subject: [PATCH 192/370] mxc: Core support for Freescale i.MX5 series Add basic clock support, cpu identification, I/O mapping, interrupt controller, serial port and ethernet. Signed-off-by: Amit Kucheria --- arch/arm/mach-mx5/clock-mx51.c | 825 ++++++++++++++++++++ arch/arm/mach-mx5/cpu.c | 47 ++ arch/arm/mach-mx5/crm_regs.h | 583 ++++++++++++++ arch/arm/mach-mx5/devices.c | 96 +++ arch/arm/mach-mx5/devices.h | 4 + arch/arm/mach-mx5/mm.c | 89 +++ arch/arm/plat-mxc/include/mach/common.h | 4 + arch/arm/plat-mxc/include/mach/iomux-mx51.h | 326 ++++++++ arch/arm/plat-mxc/include/mach/iomux-v3.h | 8 +- arch/arm/plat-mxc/include/mach/mx51.h | 454 +++++++++++ 10 files changed, 2433 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-mx5/clock-mx51.c create mode 100644 arch/arm/mach-mx5/cpu.c create mode 100644 arch/arm/mach-mx5/crm_regs.h create mode 100644 arch/arm/mach-mx5/devices.c create mode 100644 arch/arm/mach-mx5/devices.h create mode 100644 arch/arm/mach-mx5/mm.c create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c new file mode 100644 index 0000000000000..be90c03101cd8 --- /dev/null +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -0,0 +1,825 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "crm_regs.h" + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; + +static struct clk osc_clk; +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk lp_apm_clk; +static struct clk periph_apm_clk; +static struct clk ahb_clk; +static struct clk ipg_clk; + +#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ + +static int _clk_ccgr_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_ccgr_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +} + +static void _clk_ccgr_disable_inwait(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return -EINVAL; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return MX51_DPLL1_BASE; + else if (pll == &pll2_sw_clk) + return MX51_DPLL2_BASE; + else if (pll == &pll3_sw_clk) + return MX51_DPLL3_BASE; + else + BUG(); + + return NULL; +} + +static unsigned long clk_pll_get_rate(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * parent_rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + void __iomem *pllbase; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4 * parent_rate; + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -EINVAL; + pdf--; + + temp64 = rate * (pdf+1) - quad_parent_rate * mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + int i = 0; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + do { + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_LRF) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: pll locking failed\n"); + return -EINVAL; + } + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, step; + + reg = __raw_readl(MXC_CCM_CCSR); + + /* When switching from pll_main_clk to a bypass clock, first select a + * multiplexed clock in 'step_sel', then shift the glitchless mux + * 'pll1_sw_clk_sel'. + * + * When switching back, do it in reverse order + */ + if (parent == &pll1_main_clk) { + /* Switch to pll1_main_clk */ + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* step_clk mux switched to lp_apm, to save power. */ + reg = __raw_readl(MXC_CCM_CCSR); + reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; + reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << + MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + if (parent == &lp_apm_clk) { + step = MXC_CCM_CCSR_STEP_SEL_LP_APM; + } else if (parent == &pll2_sw_clk) { + step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; + } else if (parent == &pll3_sw_clk) { + step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; + } else + return -EINVAL; + + reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; + reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CCSR); + /* Switch to step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static unsigned long clk_pll1_sw_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } else + div = 1; + return parent_rate / div; +} + +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll2_sw_clk) + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + else + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static unsigned long clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + + return parent_rate / div; +} + +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + int i = 0; + + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); + + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + /* Wait for lock */ + do { + reg = __raw_readl(MXC_CCM_CDHIPR); + if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: Set parent for periph_apm clock failed\n"); + return -EINVAL; + } + + return 0; +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + + if (parent == &pll2_sw_clk) + reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + else if (parent == &periph_apm_clk) + reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static struct clk main_bus_clk = { + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, +}; + +static unsigned long clk_ahb_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + return parent_rate / div; +} + + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + unsigned long parent_rate; + int i = 0; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + /* Wait for lock */ + do { + reg = __raw_readl(MXC_CCM_CDHIPR); + if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: clk_ahb_set_rate failed\n"); + return -EINVAL; + } + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return parent_rate / div; +} + + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static unsigned long clk_ipg_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + + return parent_rate / div; +} + +static unsigned long clk_ipg_per_get_rate(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + return parent_rate / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) + return parent_rate; + else + BUG(); +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCMR); + + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + + if (parent == &ipg_clk) + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + else if (parent == &lp_apm_clk) + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else if (parent != &main_bus_clk) + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static unsigned long clk_uart_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + return parent_rate / (prediv * podf); +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + .get_rate = get_low_reference_clock_rate, +}; + +static struct clk pll1_main_clk = { + .parent = &osc_clk, + .get_rate = clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* Clock tree block diagram (WIP): + * CCM: Clock Controller Module + * + * PLL output -> | + * | CCM Switcher -> CCM_CLK_ROOT_GEN -> + * PLL bypass -> | + * + */ + +/* PLL1 SW supplies to ARM core */ +static struct clk pll1_sw_clk = { + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = clk_pll1_sw_get_rate, +}; + +/* PLL2 SW supplies to AXI/AHB/IP buses */ +static struct clk pll2_sw_clk = { + .parent = &osc_clk, + .get_rate = clk_pll_get_rate, + .set_rate = _clk_pll_set_rate, + .set_parent = _clk_pll2_sw_set_parent, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ +static struct clk pll3_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .get_rate = clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* Low-power Audio Playback Mode clock */ +static struct clk lp_apm_clk = { + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, +}; + +static struct clk periph_apm_clk = { + .parent = &pll1_sw_clk, + .set_parent = _clk_periph_apm_set_parent, +}; + +static struct clk cpu_clk = { + .parent = &pll1_sw_clk, + .get_rate = clk_arm_get_rate, +}; + +static struct clk ahb_clk = { + .parent = &main_bus_clk, + .get_rate = clk_ahb_get_rate, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, +}; + +/* Main IP interface clock for access to registers */ +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = clk_ipg_get_rate, +}; + +static struct clk ipg_perclk = { + .parent = &lp_apm_clk, + .get_rate = clk_ipg_per_get_rate, + .set_parent = _clk_ipg_per_set_parent, +}; + +static struct clk uart_root_clk = { + .parent = &pll2_sw_clk, + .get_rate = clk_uart_get_rate, + .set_parent = _clk_uart_set_parent, +}; + +static struct clk ahb_max_clk = { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + +static struct clk aips_tz1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, +}; + +static struct clk gpt_32k_clk = { + .id = 0, + .parent = &ckil_clk, +}; + +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = gr, \ + .set_rate = sr, \ + .enable = _clk_ccgr_enable, \ + .disable = _clk_ccgr_disable, \ + .parent = p, \ + .secondary = s, \ + } + +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, + get_rate, set_rate, parent, secondary); */ + +/* Shared peripheral bus arbiter */ +DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +/* UART */ +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, + NULL, NULL, &ipg_clk, &aips_tz1_clk); +DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, &ipg_clk, &aips_tz1_clk); +DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, + NULL, NULL, &ipg_clk, &spba_clk); + +/* GPT */ +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_perclk, NULL); +DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +/* FEC */ +DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) +}; + +static void clk_tree_init(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + * + * FIXME: Verify if true for all boards + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); +} + +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), + MX51_MXC_INT_GPT); + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c new file mode 100644 index 0000000000000..41c769f08c4dd --- /dev/null +++ b/arch/arm/mach-mx5/cpu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * This file contains the CPU initialization code. + */ + +#include +#include +#include +#include +#include + +static int __init post_cpu_init(void) +{ + unsigned int reg; + void __iomem *base; + + if (!cpu_is_mx51()) + return 0; + + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + return 0; +} + +postcore_initcall(post_cpu_init); diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h new file mode 100644 index 0000000000000..c776b9af0624d --- /dev/null +++ b/arch/arm/mach-mx5/crm_regs.h @@ -0,0 +1,583 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) +#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) +#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) +#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) +#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) +#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 +#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ +#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 +#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, + 1: step_clk */ +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) + +/* Define the bits in register CHSCCDR */ +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) +#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGRx_CG_MASK 0x3 +#define MXC_CCM_CCGRx_MOD_OFF 0x0 +#define MXC_CCM_CCGRx_MOD_ON 0x3 +#define MXC_CCM_CCGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) + +#define MXC_CCM_CCGRx_CG15_OFFSET 30 +#define MXC_CCM_CCGRx_CG14_OFFSET 28 +#define MXC_CCM_CCGRx_CG13_OFFSET 26 +#define MXC_CCM_CCGRx_CG12_OFFSET 24 +#define MXC_CCM_CCGRx_CG11_OFFSET 22 +#define MXC_CCM_CCGRx_CG10_OFFSET 20 +#define MXC_CCM_CCGRx_CG9_OFFSET 18 +#define MXC_CCM_CCGRx_CG8_OFFSET 16 +#define MXC_CCM_CCGRx_CG7_OFFSET 14 +#define MXC_CCM_CCGRx_CG6_OFFSET 12 +#define MXC_CCM_CCGRx_CG5_OFFSET 10 +#define MXC_CCM_CCGRx_CG4_OFFSET 8 +#define MXC_CCM_CCGRx_CG3_OFFSET 6 +#define MXC_CCM_CCGRx_CG2_OFFSET 4 +#define MXC_CCM_CCGRx_CG1_OFFSET 2 +#define MXC_CCM_CCGRx_CG0_OFFSET 0 + +#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) +#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) +#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) + +/* CORTEXA8 platform */ +#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* GPC */ +#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) +#define MXC_GPC_PGR_ARMPG_OFFSET 8 +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c new file mode 100644 index 0000000000000..d6fd3961ade9a --- /dev/null +++ b/arch/arm/mach-mx5/devices.c @@ -0,0 +1,96 @@ +/* + * Copyright 2009 Amit Kucheria + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include + +static struct resource uart0[] = { + { + .start = MX51_UART1_BASE_ADDR, + .end = MX51_UART1_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART1, + .end = MX51_MXC_INT_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device0 = { + .name = "imx-uart", + .id = 0, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct resource uart1[] = { + { + .start = MX51_UART2_BASE_ADDR, + .end = MX51_UART2_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART2, + .end = MX51_MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device1 = { + .name = "imx-uart", + .id = 1, + .resource = uart1, + .num_resources = ARRAY_SIZE(uart1), +}; + +static struct resource uart2[] = { + { + .start = MX51_UART3_BASE_ADDR, + .end = MX51_UART3_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART3, + .end = MX51_MXC_INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device2 = { + .name = "imx-uart", + .id = 2, + .resource = uart2, + .num_resources = ARRAY_SIZE(uart2), +}; + +static struct resource mxc_fec_resources[] = { + { + .start = MX51_MXC_FEC_BASE_ADDR, + .end = MX51_MXC_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_FEC, + .end = MX51_MXC_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; + +/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ +int __init mxc_register_gpios(void) +{ + return 0; +} diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h new file mode 100644 index 0000000000000..f339ab8c19bec --- /dev/null +++ b/arch/arm/mach-mx5/devices.h @@ -0,0 +1,4 @@ +extern struct platform_device mxc_uart_device0; +extern struct platform_device mxc_uart_device1; +extern struct platform_device mxc_uart_device2; +extern struct platform_device mxc_fec_device; diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c new file mode 100644 index 0000000000000..c21e18be7af86 --- /dev/null +++ b/arch/arm/mach-mx5/mm.c @@ -0,0 +1,89 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Create static mapping between physical to virtual memory. + */ + +#include +#include + +#include + +#include +#include +#include + +/* + * Define the MX51 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = MX51_IRAM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), + .length = MX51_IRAM_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_DEBUG_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), + .length = MX51_DEBUG_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_TZIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR), + .length = MX51_TZIC_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), + .length = MX51_AIPS1_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), + .length = MX51_SPBA0_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), + .length = MX51_AIPS2_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR), + .length = MX51_NFC_AXI_SIZE, + .type = MT_DEVICE + }, +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx51_map_io(void) +{ + u32 tzic_addr; + + if (mx51_revision() < MX51_CHIP_REV_2_0) + tzic_addr = 0x8FFFC000; + else + tzic_addr = 0xE0003000; + mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr); + + mxc_set_cpu_type(MXC_CPU_MX51); + mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} + +void __init mx51_init_irq(void) +{ + tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 1394025068c36..2941472582d2a 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,6 +20,7 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void mx51_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -29,6 +30,7 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); +extern void mx51_init_irq(void); extern void mxc91231_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -37,6 +39,8 @@ extern int mx25_clocks_init(void); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h new file mode 100644 index 0000000000000..b4f975e6a6656 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX51_H__ +#define __MACH_IOMUX_MX51_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* Pad control groupings */ +#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + +/* + * The naming convention for the pad modes is MX51_PAD___ + * If or refers to a GPIO, it is named + * GPIO__ see also iomux-v3.h + */ + +/* + * FIXME: This was converted using scripts from existing Freescale code to + * this form used upstream. Need to verify the name format. + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ + +#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) + +/* Babbage UART3 */ +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) + +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +/* REVISIT: Not sure of these values + + #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +*/ +#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) + +/* Babbage UART1 */ +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) + +/* Babbage UART2 */ +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) + +#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ + (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) +#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) + +/* EIM */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 1deda0184892b..f2f73d31d5ba5 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -81,11 +81,13 @@ struct pad_desc { #define PAD_CTL_ODE (1 << 3) -#define PAD_CTL_DSE_STANDARD (0 << 1) -#define PAD_CTL_DSE_HIGH (1 << 1) -#define PAD_CTL_DSE_MAX (2 << 1) +#define PAD_CTL_DSE_LOW (0 << 1) +#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_HIGH (2 << 1) +#define PAD_CTL_DSE_MAX (3 << 1) #define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) /* * setups a single pad in the iomuxer diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h new file mode 100644 index 0000000000000..771532b6b4a60 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -0,0 +1,454 @@ +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +/* + * MX51 memory map: + * + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) + * 30000000 256M GPU + * 40000000 512M IPU + * FA200000 60000000 1M DEBUG + * FB100000 70000000 1M SPBA 0 + * FB000000 73F00000 1M AIPS 1 + * FB200000 83F00000 1M AIPS 2 + * FA100000 8FFFC000 16K TZIC (interrupt controller) + * 90000000 256M CSD0 SDRAM/DDR + * A0000000 256M CSD1 SDRAM/DDR + * B0000000 128M CS0 Flash + * B8000000 128M CS1 Flash + * C0000000 128M CS2 Flash + * C8000000 64M CS3 Flash + * CC000000 32M CS4 SRAM + * CE000000 32M CS5 SRAM + * F9000000 CFFF0000 64K NFC (NAND Flash AXI) + * + */ + +/* + * IRAM + */ +#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 +#define MX51_IRAM_PARTITIONS 16 +#define MX51_IRAM_PARTITIONS_TO1 12 +#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * NFC + */ +#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ +#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000 +#define MX51_NFC_AXI_SIZE SZ_64K + +/* + * Graphics Memory of GPU + */ +#define MX51_GPU_BASE_ADDR 0x20000000 +#define MX51_GPU2D_BASE_ADDR 0xD0000000 + +#define MX51_TZIC_BASE_ADDR 0x8FFFC000 +#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000 +#define MX51_TZIC_SIZE SZ_16K + +#define MX51_DEBUG_BASE_ADDR 0x60000000 +#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 +#define MX51_DEBUG_SIZE SZ_1M +#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) +#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) +#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) +#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) +#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) +#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) +#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) +#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX51_SPBA0_BASE_ADDR 0x70000000 +#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 +#define MX51_SPBA0_SIZE SZ_1M + +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * defines for SPBA modules + */ +#define MX51_SPBA_SDHC1 0x04 +#define MX51_SPBA_SDHC2 0x08 +#define MX51_SPBA_UART3 0x0C +#define MX51_SPBA_CSPI1 0x10 +#define MX51_SPBA_SSI2 0x14 +#define MX51_SPBA_SDHC3 0x20 +#define MX51_SPBA_SDHC4 0x24 +#define MX51_SPBA_SPDIF 0x28 +#define MX51_SPBA_ATA 0x30 +#define MX51_SPBA_SLIM 0x34 +#define MX51_SPBA_HSI2C 0x38 +#define MX51_SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define MX51_AIPS1_BASE_ADDR 0x73F00000 +#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000 +#define MX51_AIPS1_SIZE SZ_1M + +#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) +#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) +#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) +#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) +#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) +#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) +#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) +#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) +#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) +#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) +#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) +#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) +#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) +#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) +#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) +#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) +#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) +#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) +#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) +#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) + +/* + * Defines for modules using static and dynamic DMA channels + */ +#define MX51_MXC_DMA_CHANNEL_IRAM 30 +#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) +#else /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL + +/* + * AIPS 2 + */ +#define MX51_AIPS2_BASE_ADDR 0x83F00000 +#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000 +#define MX51_AIPS2_SIZE SZ_1M + +#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) +#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) +#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) +#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) +#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) +#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) +#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) +#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) +#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) +#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) +#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) +#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) +#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) +#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) +#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) +#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) +#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) +#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) +#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) +#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) +#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) +#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) +#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) +#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) +#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) +#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) +#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) +#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) +#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) +#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) +#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) + +/* + * Memory regions and CS + */ +#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 +#define MX51_CSD0_BASE_ADDR 0x90000000 +#define MX51_CSD1_BASE_ADDR 0xA0000000 +#define MX51_CS0_BASE_ADDR 0xB0000000 +#define MX51_CS1_BASE_ADDR 0xB8000000 +#define MX51_CS2_BASE_ADDR 0xC0000000 +#define MX51_CS3_BASE_ADDR 0xC8000000 +#define MX51_CS4_BASE_ADDR 0xCC000000 +#define MX51_CS5_BASE_ADDR 0xCE000000 + +/* Does given address belongs to the specified memory region? */ +#define ADDRESS_IN_REGION(addr, start, size) \ + (((addr) >= (start)) && ((addr) < (start)+(size))) + +/* Does given address belongs to the specified named `module'? */ +#define MX51_IS_MODULE(addr, module) \ + ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \ + MX51_ ## module ## _SIZE) +/* + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ + +#define MX51_IO_ADDRESS(x) \ + (void __iomem *) \ + (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ +#define MX51_IRAM_IO_ADDRESS(x) \ + (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) + +#define MX51_TZIC_IO_ADDRESS(x) \ + (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT) + +#define MX51_DEBUG_IO_ADDRESS(x) \ + (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) + +#define MX51_SPBA0_IO_ADDRESS(x) \ + (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT) + +#define MX51_AIPS1_IO_ADDRESS(x) \ + (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) + +#define MX51_AIPS2_IO_ADDRESS(x) \ + (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) + +#define MX51_NFC_AXI_IO_ADDRESS(x) \ + (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT) + +#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 + +/* + * DMA request assignments + */ +#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX1 46 +#define MX51_DMA_REQ_SPDIF 45 +#define MX51_DMA_REQ_UART3_TX 44 +#define MX51_DMA_REQ_UART3_RX 43 +#define MX51_DMA_REQ_SLIM_B_TX 42 +#define MX51_DMA_REQ_SDHC4 41 +#define MX51_DMA_REQ_SDHC3 40 +#define MX51_DMA_REQ_CSPI_TX 39 +#define MX51_DMA_REQ_CSPI_RX 38 +#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_IPU 36 +#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_EPIT2 34 +#define MX51_DMA_REQ_CTI2_1 33 +#define MX51_DMA_REQ_EMI_WR 32 +#define MX51_DMA_REQ_CTI2_0 31 +#define MX51_DMA_REQ_EMI_RD 30 +#define MX51_DMA_REQ_SSI1_TX1 29 +#define MX51_DMA_REQ_SSI1_RX1 28 +#define MX51_DMA_REQ_SSI1_TX2 27 +#define MX51_DMA_REQ_SSI1_RX2 26 +#define MX51_DMA_REQ_SSI2_TX1 25 +#define MX51_DMA_REQ_SSI2_RX1 24 +#define MX51_DMA_REQ_SSI2_TX2 23 +#define MX51_DMA_REQ_SSI2_RX2 22 +#define MX51_DMA_REQ_SDHC2 21 +#define MX51_DMA_REQ_SDHC1 20 +#define MX51_DMA_REQ_UART1_TX 19 +#define MX51_DMA_REQ_UART1_RX 18 +#define MX51_DMA_REQ_UART2_TX 17 +#define MX51_DMA_REQ_UART2_RX 16 +#define MX51_DMA_REQ_GPU 15 +#define MX51_DMA_REQ_EXTREQ1 14 +#define MX51_DMA_REQ_FIRI_TX 13 +#define MX51_DMA_REQ_FIRI_RX 12 +#define MX51_DMA_REQ_HS_I2C_RX 11 +#define MX51_DMA_REQ_HS_I2C_TX 10 +#define MX51_DMA_REQ_CSPI2_TX 9 +#define MX51_DMA_REQ_CSPI2_RX 8 +#define MX51_DMA_REQ_CSPI1_TX 7 +#define MX51_DMA_REQ_CSPI1_RX 6 +#define MX51_DMA_REQ_SLIM_B 5 +#define MX51_DMA_REQ_ATA_TX_END 4 +#define MX51_DMA_REQ_ATA_TX 3 +#define MX51_DMA_REQ_ATA_RX 2 +#define MX51_DMA_REQ_GPC 1 +#define MX51_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX51_MXC_INT_BASE 0 +#define MX51_MXC_INT_RESV0 0 +#define MX51_MXC_INT_MMC_SDHC1 1 +#define MX51_MXC_INT_MMC_SDHC2 2 +#define MX51_MXC_INT_MMC_SDHC3 3 +#define MX51_MXC_INT_MMC_SDHC4 4 +#define MX51_MXC_INT_RESV5 5 +#define MX51_MXC_INT_SDMA 6 +#define MX51_MXC_INT_IOMUX 7 +#define MX51_MXC_INT_NFC 8 +#define MX51_MXC_INT_VPU 9 +#define MX51_MXC_INT_IPU_ERR 10 +#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_MXC_INT_GPU 12 +#define MX51_MXC_INT_RESV13 13 +#define MX51_MXC_INT_USB_H1 14 +#define MX51_MXC_INT_EMI 15 +#define MX51_MXC_INT_USB_H2 16 +#define MX51_MXC_INT_USB_H3 17 +#define MX51_MXC_INT_USB_OTG 18 +#define MX51_MXC_INT_SAHARA_H0 19 +#define MX51_MXC_INT_SAHARA_H1 20 +#define MX51_MXC_INT_SCC_SMN 21 +#define MX51_MXC_INT_SCC_STZ 22 +#define MX51_MXC_INT_SCC_SCM 23 +#define MX51_MXC_INT_SRTC_NTZ 24 +#define MX51_MXC_INT_SRTC_TZ 25 +#define MX51_MXC_INT_RTIC 26 +#define MX51_MXC_INT_CSU 27 +#define MX51_MXC_INT_SLIM_B 28 +#define MX51_MXC_INT_SSI1 29 +#define MX51_MXC_INT_SSI2 30 +#define MX51_MXC_INT_UART1 31 +#define MX51_MXC_INT_UART2 32 +#define MX51_MXC_INT_UART3 33 +#define MX51_MXC_INT_RESV34 34 +#define MX51_MXC_INT_RESV35 35 +#define MX51_MXC_INT_CSPI1 36 +#define MX51_MXC_INT_CSPI2 37 +#define MX51_MXC_INT_CSPI 38 +#define MX51_MXC_INT_GPT 39 +#define MX51_MXC_INT_EPIT1 40 +#define MX51_MXC_INT_EPIT2 41 +#define MX51_MXC_INT_GPIO1_INT7 42 +#define MX51_MXC_INT_GPIO1_INT6 43 +#define MX51_MXC_INT_GPIO1_INT5 44 +#define MX51_MXC_INT_GPIO1_INT4 45 +#define MX51_MXC_INT_GPIO1_INT3 46 +#define MX51_MXC_INT_GPIO1_INT2 47 +#define MX51_MXC_INT_GPIO1_INT1 48 +#define MX51_MXC_INT_GPIO1_INT0 49 +#define MX51_MXC_INT_GPIO1_LOW 50 +#define MX51_MXC_INT_GPIO1_HIGH 51 +#define MX51_MXC_INT_GPIO2_LOW 52 +#define MX51_MXC_INT_GPIO2_HIGH 53 +#define MX51_MXC_INT_GPIO3_LOW 54 +#define MX51_MXC_INT_GPIO3_HIGH 55 +#define MX51_MXC_INT_GPIO4_LOW 56 +#define MX51_MXC_INT_GPIO4_HIGH 57 +#define MX51_MXC_INT_WDOG1 58 +#define MX51_MXC_INT_WDOG2 59 +#define MX51_MXC_INT_KPP 60 +#define MX51_MXC_INT_PWM1 61 +#define MX51_MXC_INT_I2C1 62 +#define MX51_MXC_INT_I2C2 63 +#define MX51_MXC_INT_HS_I2C 64 +#define MX51_MXC_INT_RESV65 65 +#define MX51_MXC_INT_RESV66 66 +#define MX51_MXC_INT_SIM_IPB 67 +#define MX51_MXC_INT_SIM_DAT 68 +#define MX51_MXC_INT_IIM 69 +#define MX51_MXC_INT_ATA 70 +#define MX51_MXC_INT_CCM1 71 +#define MX51_MXC_INT_CCM2 72 +#define MX51_MXC_INT_GPC1 73 +#define MX51_MXC_INT_GPC2 74 +#define MX51_MXC_INT_SRC 75 +#define MX51_MXC_INT_NM 76 +#define MX51_MXC_INT_PMU 77 +#define MX51_MXC_INT_CTI_IRQ 78 +#define MX51_MXC_INT_CTI1_TG0 79 +#define MX51_MXC_INT_CTI1_TG1 80 +#define MX51_MXC_INT_MCG_ERR 81 +#define MX51_MXC_INT_MCG_TMR 82 +#define MX51_MXC_INT_MCG_FUNC 83 +#define MX51_MXC_INT_GPU2_IRQ 84 +#define MX51_MXC_INT_GPU2_BUSY 85 +#define MX51_MXC_INT_RESV86 86 +#define MX51_MXC_INT_FEC 87 +#define MX51_MXC_INT_OWIRE 88 +#define MX51_MXC_INT_CTI1_TG2 89 +#define MX51_MXC_INT_SJC 90 +#define MX51_MXC_INT_SPDIF 91 +#define MX51_MXC_INT_TVE 92 +#define MX51_MXC_INT_FIRI 93 +#define MX51_MXC_INT_PWM2 94 +#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_MXC_INT_SSI3 96 +#define MX51_MXC_INT_EMI_BOOT 97 +#define MX51_MXC_INT_CTI1_TG3 98 +#define MX51_MXC_INT_SMC_RX 99 +#define MX51_MXC_INT_VPU_IDLE 100 +#define MX51_MXC_INT_EMI_NFC 101 +#define MX51_MXC_INT_GPU_IDLE 102 + +/* silicon revisions specific to i.MX51 */ +#define MX51_CHIP_REV_1_0 0x10 +#define MX51_CHIP_REV_1_1 0x11 +#define MX51_CHIP_REV_1_2 0x12 +#define MX51_CHIP_REV_1_3 0x13 +#define MX51_CHIP_REV_2_0 0x20 +#define MX51_CHIP_REV_2_1 0x21 +#define MX51_CHIP_REV_2_2 0x22 +#define MX51_CHIP_REV_2_3 0x23 +#define MX51_CHIP_REV_3_0 0x30 +#define MX51_CHIP_REV_3_1 0x31 +#define MX51_CHIP_REV_3_2 0x32 + +/* Mandatory defines used globally */ + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) + +extern unsigned int system_rev; + +static inline unsigned int mx51_revision(void) +{ + return system_rev; +} +#endif + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ -- GitLab From b996b5830364c1b1d2469be574f4ebe831987ba9 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Tue, 2 Feb 2010 11:57:53 -0800 Subject: [PATCH 193/370] mxc: Add support for the Babbage board (i.MX5) Babbage is a reference board from Freescale for their i.MX51 SoC. Add board definition, Kconfig and Makefiles to enable Freescale i.MX51 processor and Babbage board. Boot tested on a Babbage2.5 board Signed-off-by: Amit Kucheria --- arch/arm/Makefile | 1 + arch/arm/mach-mx5/Kconfig | 18 +++++ arch/arm/mach-mx5/Makefile | 9 +++ arch/arm/mach-mx5/Makefile.boot | 3 + arch/arm/mach-mx5/board-mx51_babbage.c | 98 ++++++++++++++++++++++++++ arch/arm/plat-mxc/Kconfig | 8 +++ 6 files changed, 137 insertions(+) create mode 100644 arch/arm/mach-mx5/Kconfig create mode 100644 arch/arm/mach-mx5/Makefile create mode 100644 arch/arm/mach-mx5/Makefile.boot create mode 100644 arch/arm/mach-mx5/board-mx51_babbage.c diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e9da08483b3cd..056daf8b68a5c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 +machine-$(CONFIG_ARCH_MX5) := mx5 machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig new file mode 100644 index 0000000000000..1576d51e676c9 --- /dev/null +++ b/arch/arm/mach-mx5/Kconfig @@ -0,0 +1,18 @@ +if ARCH_MX5 + +config ARCH_MX51 + bool + default y + select MXC_TZIC + select ARCH_MXC_IOMUX_V3 + +comment "MX5 platforms:" + +config MACH_MX51_BABBAGE + bool "Support MX51 BABBAGE platforms" + help + Include support for MX51 Babbage platform, also known as MX51EVK in + u-boot. This includes specific configurations for the board and its + peripherals. + +endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile new file mode 100644 index 0000000000000..bf23f869ef511 --- /dev/null +++ b/arch/arm/mach-mx5/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. +obj-y := cpu.o mm.o clock-mx51.o devices.o + +obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o + diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot new file mode 100644 index 0000000000000..9939a19d99a1f --- /dev/null +++ b/arch/arm/mach-mx5/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x90008000 +params_phys-y := 0x90000100 +initrd_phys-y := 0x90800000 diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c new file mode 100644 index 0000000000000..d5ccb5f4f39cb --- /dev/null +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -0,0 +1,98 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, +}; + +static struct pad_desc mx51babbage_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + + /* UART3 */ + MX51_PAD_EIM_D25__UART3_RXD, + MX51_PAD_EIM_D26__UART3_TXD, + MX51_PAD_EIM_D27__UART3_RTS, + MX51_PAD_EIM_D24__UART3_CTS, +}; + +/* Serial ports */ +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mxc_init_imx_uart(void) +{ + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); +} +#else /* !SERIAL_IMX */ +static inline void mxc_init_imx_uart(void) +{ +} +#endif /* SERIAL_IMX */ + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, + ARRAY_SIZE(mx51babbage_pads)); + mxc_init_imx_uart(); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init mx51_babbage_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 24576000); +} + +static struct sys_timer mxc_timer = { + .init = mx51_babbage_timer_init, +}; + +MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") + /* Maintainer: Amit Kucheria */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 59558c4b9446e..cea51a0ae9f75 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -41,6 +41,13 @@ config ARCH_MXC91231 help This enables support for systems based on the Freescale MXC91231 family +config ARCH_MX5 + bool "MX5-based" + select CPU_V7 + select COMMON_CLKDEV + help + This enables support for systems based on the Freescale i.MX51 family + endchoice source "arch/arm/mach-mx1/Kconfig" @@ -48,6 +55,7 @@ source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" +source "arch/arm/mach-mx5/Kconfig" endmenu -- GitLab From 51c23a04c39e6a95a37b8af8625a550e674ddef6 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 4 Dec 2009 00:57:20 +0200 Subject: [PATCH 194/370] mxc: Add mx51_defconfig This config is used to test the base support for i.MX51 processors on the Babbage board Signed-off-by: Amit Kucheria --- arch/arm/configs/mx51_defconfig | 1286 +++++++++++++++++++++++++++++++ 1 file changed, 1286 insertions(+) create mode 100644 arch/arm/configs/mx51_defconfig diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig new file mode 100644 index 0000000000000..c88e9527a8ecd --- /dev/null +++ b/arch/arm/configs/mx51_defconfig @@ -0,0 +1,1286 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc6 +# Tue Feb 2 15:20:48 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=18 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MXC91231 is not set +CONFIG_ARCH_MX5=y +CONFIG_ARCH_MX51=y + +# +# MX5 platforms: +# +CONFIG_MACH_MX51_BABBAGE=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +# CONFIG_MXC_PWM is not set +CONFIG_ARCH_MXC_IOMUX_V3=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_NATIONAL_PHY=y +CONFIG_STE10XP=y +CONFIG_LSI_ET1011C_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=m +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- GitLab From 3d48e1d0e8701d004ce7e1dd66088f42e429d079 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 4 Feb 2010 15:57:29 -0800 Subject: [PATCH 195/370] mxc: MAINTAINERS: Add maintainer for mach-mx5 Add self to MAINTAINERS for Freescale i.MX5 SoCs Signed-off-by: Amit Kucheria --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 66f5f7dab2856..6a1773d62e52b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -663,6 +663,12 @@ T: git://git.pengutronix.de/git/imx/linux-2.6.git F: arch/arm/mach-mx*/ F: arch/arm/plat-mxc/ +ARM/FREESCALE IMX51 +M: Amit Kucheria +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/mach-mx5/ + ARM/GLOMATION GESBC9312SX MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- GitLab From d74b96a73a99853708d6b278c2ce683657fa1ec5 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 9 Feb 2010 21:21:49 +0100 Subject: [PATCH 196/370] [ARM] Orion5x: set valid GPIO inhibit power-off for d2net This patch allow user-space to configure the switch power-off behaviour via the gpiolib sysfs interface. Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/d2net-setup.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 9d4bf763f25b0..0420e45f66b7d 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -301,6 +301,8 @@ static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ }; +#define D2NET_GPIO_INHIBIT_POWER_OFF 24 + static void __init d2net_init(void) { /* @@ -333,6 +335,8 @@ static void __init d2net_init(void) i2c_register_board_info(0, d2net_i2c_devices, ARRAY_SIZE(d2net_i2c_devices)); + + orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1); } /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ -- GitLab From 7a15726cb4aca67150b93a5ce5413efe6e87c95d Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 9 Feb 2010 21:21:50 +0100 Subject: [PATCH 197/370] [ARM] Orion5x: enable SATA LED blinking for d2net Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/d2net-setup.c | 41 ++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 0420e45f66b7d..7130904ad9998 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -149,10 +149,7 @@ static void __init d2net_sata_power_init(void) /* * The blue front LED is wired to the CPLD and can blink in relation with the - * SATA activity. This feature is disabled to make this LED compatible with - * the leds-gpio driver: MPP14 and MPP15 are configured to act like output - * GPIO's and have to stay in an active state. This is needed to set the blue - * LED in a "fix on" state regardless of the SATA activity. + * SATA activity. * * The following array detail the different LED registers and the combination * of their possible values: @@ -171,12 +168,11 @@ static void __init d2net_sata_power_init(void) #define D2NET_GPIO_RED_LED 6 #define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 #define D2NET_GPIO_BLUE_LED_OFF 23 -#define D2NET_GPIO_SATA0_ACT 14 -#define D2NET_GPIO_SATA1_ACT 15 static struct gpio_led d2net_leds[] = { { - .name = "d2net:blue:power", + .name = "d2net:blue:sata", + .default_trigger = "default-on", .gpio = D2NET_GPIO_BLUE_LED_OFF, .active_low = 1, }, @@ -201,25 +197,22 @@ static struct platform_device d2net_gpio_leds = { static void __init d2net_gpio_leds_init(void) { + int err; + /* Configure GPIO over MPP max number. */ orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1); - if (gpio_request(D2NET_GPIO_SATA0_ACT, "LED SATA0 activity") != 0) - return; - if (gpio_direction_output(D2NET_GPIO_SATA0_ACT, 1) != 0) - goto err_free_1; - if (gpio_request(D2NET_GPIO_SATA1_ACT, "LED SATA1 activity") != 0) - goto err_free_1; - if (gpio_direction_output(D2NET_GPIO_SATA1_ACT, 1) != 0) - goto err_free_2; - platform_device_register(&d2net_gpio_leds); - return; + /* Configure register blink_ctrl to allow SATA activity LED blinking. */ + err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); + if (err == 0) { + err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); + if (err) + gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); + } + if (err) + pr_err("d2net: failed to configure blue LED blink GPIO\n"); -err_free_2: - gpio_free(D2NET_GPIO_SATA1_ACT); -err_free_1: - gpio_free(D2NET_GPIO_SATA0_ACT); - return; + platform_device_register(&d2net_gpio_leds); } /**************************************************************************** @@ -289,8 +282,8 @@ static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { { 11, MPP_UNUSED }, { 12, MPP_GPIO }, /* SATA 1 power */ { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* SATA 0 active */ - { 15, MPP_GPIO }, /* SATA 1 active */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ { 16, MPP_GPIO }, /* Blue front LED blink control */ { 17, MPP_UNUSED }, { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ -- GitLab From ca9cea939932a0a64fee9d83b3c631431359446f Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 9 Feb 2010 21:20:55 +0100 Subject: [PATCH 198/370] [ARM] Kirkwood: add LaCie Internet Space v2 support The Internet and Network Space v2 boards are very close. The only difference is that there is no USB type B plug wired on the Internet Space v2. Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Kconfig | 6 ++++++ arch/arm/mach-kirkwood/Makefile | 1 + arch/arm/mach-kirkwood/netspace_v2-setup.c | 14 ++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 4ac6f463eb037..edc9aeb6e6b2f 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -69,6 +69,12 @@ config MACH_NETSPACE_V2 Say 'Y' here if you want your kernel to support the LaCie Network Space v2 NAS. +config MACH_INETSPACE_V2 + bool "LaCie Internet Space v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie Internet Space v2 NAS. + endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index df91d0789f182..55b4ccf3729ba 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 9a064065bebe9..4c1f4744fe62b 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -314,6 +314,7 @@ static void __init netspace_v2_init(void) pr_err("netspace_v2: failed to configure power-off GPIO\n"); } +#ifdef CONFIG_MACH_NETSPACE_V2 MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .phys_io = KIRKWOOD_REGS_PHYS_BASE, .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, @@ -323,3 +324,16 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .init_irq = kirkwood_init_irq, .timer = &netspace_v2_timer, MACHINE_END +#endif + +#ifdef CONFIG_MACH_INETSPACE_V2 +MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = netspace_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &netspace_v2_timer, +MACHINE_END +#endif -- GitLab From 1afeea84bd821e9a8c1c6606ba677bc229dd57de Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 9 Feb 2010 21:20:56 +0100 Subject: [PATCH 199/370] [ARM] Kirkwood: define SATA LED for netspace_v2 This patch add a GPIO LED named "ns_v2:blue:sata" which can be used to enable or disable SATA activity LED blinking. Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/netspace_v2-setup.c | 45 ++++++++++------------ 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 4c1f4744fe62b..3ae158d72681f 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -182,8 +182,14 @@ static struct platform_device netspace_v2_gpio_buttons = { static struct gpio_led netspace_v2_gpio_led_pins[] = { { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, + .name = "ns_v2:blue:sata", + .default_trigger = "default-on", + .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD, + .active_low = 1, + }, + { + .name = "ns_v2:red:fail", + .gpio = NETSPACE_V2_GPIO_RED_LED, }, }; @@ -202,30 +208,19 @@ static struct platform_device netspace_v2_gpio_leds = { static void __init netspace_v2_gpio_leds_init(void) { - platform_device_register(&netspace_v2_gpio_leds); + int err; - /* - * Configure the front blue LED to blink in relation with the SATA - * activity. - */ - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, - "SATA blue LED slow") != 0) - return; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0) != 0) - goto err_free_1; - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_CMD, - "SATA blue LED command") != 0) - goto err_free_1; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_CMD, 0) != 0) - goto err_free_2; - - return; - -err_free_2: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_CMD); -err_free_1: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); - pr_err("netspace_v2: failed to configure SATA blue LED\n"); + /* Configure register slow_led to allow SATA activity LED blinking */ + err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); + if (err == 0) { + err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0); + if (err) + gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); + } + if (err) + pr_err("netspace_v2: failed to configure blue LED slow GPIO\n"); + + platform_device_register(&netspace_v2_gpio_leds); } /***************************************************************************** -- GitLab From d9e557e5cb2052164f04af75c7d3d9bdd4111054 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 9 Feb 2010 10:48:16 +0100 Subject: [PATCH 200/370] add ssi header file Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/ssi.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/ssi.h diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h new file mode 100644 index 0000000000000..c34ded523f100 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ssi.h @@ -0,0 +1,18 @@ +#ifndef __MACH_SSI_H +#define __MACH_SSI_H + +struct snd_ac97; + +extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end; +extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer; + +struct imx_ssi_platform_data { + unsigned int flags; +#define IMX_SSI_DMA (1 << 0) +#define IMX_SSI_USE_AC97 (1 << 1) + void (*ac97_reset) (struct snd_ac97 *ac97); + void (*ac97_warm_reset)(struct snd_ac97 *ac97); +}; + +#endif /* __MACH_SSI_H */ + -- GitLab From c8a6885f2153087668b64d4ee25f78a7dda1dadb Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 8 Feb 2010 16:42:28 +0100 Subject: [PATCH 201/370] pca100: add sound support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/mach-pca100.c | 48 +++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index cda52a6a32909..d12bdb1fcabbd 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,8 @@ #include #endif #include +#include +#include #include #include #include @@ -193,6 +196,37 @@ static struct spi_imx_master pca100_spi_0_data = { }; #endif +static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) +{ + mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); + gpio_set_value(GPIO_PORTC + 20, 1); + udelay(2); + gpio_set_value(GPIO_PORTC + 20, 0); + mxc_gpio_mode(PC20_PF_SSI1_FS); + msleep(2); +} + +static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) +{ + mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */ + gpio_set_value(GPIO_PORTC + 20, 0); + mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */ + gpio_set_value(GPIO_PORTC + 22, 0); + mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */ + gpio_set_value(GPIO_PORTC + 28, 0); + udelay(10); + gpio_set_value(GPIO_PORTC + 28, 1); + mxc_gpio_mode(PC20_PF_SSI1_FS); + mxc_gpio_mode(PC22_PF_SSI1_TXD); + msleep(2); +} + +static struct imx_ssi_platform_data pca100_ssi_pdata = { + .ac97_reset = pca100_ac97_cold_reset, + .ac97_warm_reset = pca100_ac97_warm_reset, + .flags = IMX_SSI_USE_AC97, +}; + static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) { @@ -266,11 +300,25 @@ static void __init pca100_init(void) { int ret; + /* SSI unit */ + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V1_PCR_TFCSEL(3) | + MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */ + MXC_AUDMUX_V1_PCR_RXDSEL(3)); + mxc_audmux_v1_configure_port(3, + MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V1_PCR_TFCSEL(0) | + MXC_AUDMUX_V1_PCR_TFSDIR | + MXC_AUDMUX_V1_PCR_RXDSEL(0)); + ret = mxc_gpio_setup_multiple_pins(pca100_pins, ARRAY_SIZE(pca100_pins), "PCA100"); if (ret) printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); + mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); -- GitLab From d2831d1f543489ef97a20e6e65f625e195b521bf Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 9 Feb 2010 11:04:36 +0100 Subject: [PATCH 202/370] i.MX pcm043: Add AC97 sound support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mach-pcm043.c | 101 ++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index a9741c2b379fc..1bf1ec2eef5e6 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,8 @@ #include #include #include +#include +#include #include "devices.h" @@ -213,6 +216,91 @@ static struct pad_desc pcm043_pads[] = { /* USB host */ MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, + /* SSI */ + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, + MX35_PAD_STXD4__AUDMUX_AUD4_TXD, + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, + MX35_PAD_SCK4__AUDMUX_AUD4_TXC, +}; + +#define AC97_GPIO_TXFS (1 * 32 + 31) +#define AC97_GPIO_TXD (1 * 32 + 28) +#define AC97_GPIO_RESET (1 * 32 + 0) + +static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) +{ + struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + int ret; + + ret = gpio_request(AC97_GPIO_TXFS, "SSI"); + if (ret) { + printk("failed to get GPIO_TXFS: %d\n", ret); + return; + } + + mxc_iomux_v3_setup_pad(&txfs_gpio); + + /* warm reset */ + gpio_direction_output(AC97_GPIO_TXFS, 1); + udelay(2); + gpio_set_value(AC97_GPIO_TXFS, 0); + + gpio_free(AC97_GPIO_TXFS); + mxc_iomux_v3_setup_pad(&txfs); +} + +static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) +{ + struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; + struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; + struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; + int ret; + + ret = gpio_request(AC97_GPIO_TXFS, "SSI"); + if (ret) + goto err1; + + ret = gpio_request(AC97_GPIO_TXD, "SSI"); + if (ret) + goto err2; + + ret = gpio_request(AC97_GPIO_RESET, "SSI"); + if (ret) + goto err3; + + mxc_iomux_v3_setup_pad(&txfs_gpio); + mxc_iomux_v3_setup_pad(&txd_gpio); + mxc_iomux_v3_setup_pad(&reset_gpio); + + gpio_direction_output(AC97_GPIO_TXFS, 0); + gpio_direction_output(AC97_GPIO_TXD, 0); + + /* cold reset */ + gpio_direction_output(AC97_GPIO_RESET, 0); + udelay(10); + gpio_direction_output(AC97_GPIO_RESET, 1); + + mxc_iomux_v3_setup_pad(&txd); + mxc_iomux_v3_setup_pad(&txfs); + + gpio_free(AC97_GPIO_RESET); +err3: + gpio_free(AC97_GPIO_TXD); +err2: + gpio_free(AC97_GPIO_TXFS); +err1: + if (ret) + printk("%s failed with %d\n", __func__, ret); + mdelay(1); +} + +static struct imx_ssi_platform_data pcm043_ssi_pdata = { + .ac97_reset = pcm043_ac97_cold_reset, + .ac97_warm_reset = pcm043_ac97_warm_reset, + .flags = IMX_SSI_USE_AC97, }; static struct mxc_nand_platform_data pcm037_nand_board_info = { @@ -258,10 +346,23 @@ static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + mxc_audmux_v2_configure_port(3, + MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V2_PTCR_TFSEL(0) | + MXC_AUDMUX_V2_PTCR_TFSDIR, + MXC_AUDMUX_V2_PDCR_RXDSEL(0)); + + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V2_PTCR_TCSEL(3) | + MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ + MXC_AUDMUX_V2_PDCR_RXDSEL(3)); + platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); mxc_register_device(&mxc_uart_device1, &uart_pdata); -- GitLab From f8594c283e409024d817e75027074570ce27dcc5 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 9 Feb 2010 18:13:34 +0100 Subject: [PATCH 203/370] mx31moboard: change initial reset status for robot microcontollers We want the microcontrollers to be held in reset during kernel boot. We also set the turretcam as the default camera since it is present on all marxbots. Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard-marxbot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 1f44b9ccbb0f7..7f6f58cddcb19 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -127,12 +127,12 @@ static struct imxmmc_platform_data sdhc2_pdata = { static void dspics_resets_init(void) { if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 1); + gpio_direction_output(TRSLAT_RST_B, 0); gpio_export(TRSLAT_RST_B, false); } if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { - gpio_direction_output(DSPICS_RST_B, 1); + gpio_direction_output(DSPICS_RST_B, 0); gpio_export(DSPICS_RST_B, false); } } @@ -200,7 +200,7 @@ static int __init marxbot_cam_init(void) int ret = gpio_request(CAM_CHOICE, "cam-choice"); if (ret) return ret; - gpio_direction_output(CAM_CHOICE, 1); + gpio_direction_output(CAM_CHOICE, 0); ret = gpio_request(BASECAM_RST_B, "basecam-reset"); if (ret) -- GitLab From cda82f85c2bba92daa3d017f7c7bc5f8c61a2e11 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 9 Feb 2010 18:13:35 +0100 Subject: [PATCH 204/370] mx31moboard: make usbh2 enable gpio claim more atomic It is more cosmetic than fixing a real problem, but the code looks more logical like that Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mach-mx31moboard.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index fe18cd513cd7c..c357a72ee4064 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -352,9 +352,7 @@ static struct fsl_usb2_platform_data usb_pdata = { static int moboard_usbh2_hw_init(struct platform_device *pdev) { - int ret = gpio_request(USBH2_EN_B, "usbh2-en"); - if (ret) - return ret; + int ret; mxc_iomux_set_gpr(MUX_PGP_UH2, true); @@ -371,6 +369,9 @@ static int moboard_usbh2_hw_init(struct platform_device *pdev) mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); + ret = gpio_request(USBH2_EN_B, "usbh2-en"); + if (ret) + return ret; gpio_direction_output(USBH2_EN_B, 0); return 0; -- GitLab From e335c75cf32b7014f84c90bbe7ed9b7ecd8e7778 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 9 Feb 2010 18:13:36 +0100 Subject: [PATCH 205/370] mx31moboard: support for the smartbot baseboard This baseboard is used on the handbot and eybot robots. The sel gpios are used as enables and rst signals on smartbot, thus the sel init is moved from mx31moboard file to board files. Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Makefile | 2 +- arch/arm/mach-mx3/mach-mx31moboard.c | 36 +--- arch/arm/mach-mx3/mx31moboard-devboard.c | 32 ++++ arch/arm/mach-mx3/mx31moboard-marxbot.c | 33 ++++ arch/arm/mach-mx3/mx31moboard-smartbot.c | 162 ++++++++++++++++++ .../plat-mxc/include/mach/board-mx31moboard.h | 2 + 6 files changed, 233 insertions(+), 34 deletions(-) create mode 100644 arch/arm/mach-mx3/mx31moboard-smartbot.c diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 62b60931d87cd..5d650fda5d5d3 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o + mx31moboard-marxbot.o mx31moboard-smartbot.o obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index c357a72ee4064..a7dc5191bf5ea 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -96,9 +96,6 @@ static unsigned int moboard_pins[] = { /* LEDs */ MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, /* SPI1 */ MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, @@ -432,34 +429,6 @@ static struct platform_device mx31moboard_leds_device = { }, }; -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void mx31moboard_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} - static struct ipu_platform_data mx3_ipu_data = { .irq_base = MXC_IPU_IRQ_START, }; @@ -519,8 +488,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_uart_device4, &uart4_pdata); - mx31moboard_init_sel_gpios(); - mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); @@ -553,6 +520,9 @@ static void __init mxc_board_init(void) case MX31MARXBOT: mx31moboard_marxbot_init(); break; + case MX31SMARTBOT: + mx31moboard_smartbot_init(); + break; default: printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 438428eaf769c..9fbad2eb3a497 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -49,6 +49,9 @@ static unsigned int devboard_pins[] = { MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, + /* SEL */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; static struct imxuart_platform_data uart_pdata = { @@ -108,6 +111,33 @@ static struct imxmmc_platform_data sdhc2_pdata = { .exit = devboard_sdhc2_exit, }; +#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void devboard_init_sel_gpios(void) +{ + if (!gpio_request(SEL0, "sel0")) { + gpio_direction_input(SEL0); + gpio_export(SEL0, true); + } + + if (!gpio_request(SEL1, "sel1")) { + gpio_direction_input(SEL1); + gpio_export(SEL1, true); + } + + if (!gpio_request(SEL2, "sel2")) { + gpio_direction_input(SEL2); + gpio_export(SEL2, true); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -196,5 +226,7 @@ void __init mx31moboard_devboard_init(void) mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + devboard_init_sel_gpios(); + devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 7f6f58cddcb19..3958515d75bfd 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -66,6 +66,9 @@ static unsigned int marxbot_pins[] = { MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, + /* SEL */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) @@ -223,6 +226,34 @@ static int __init marxbot_cam_init(void) return 0; } +#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void marxbot_init_sel_gpios(void) +{ + if (!gpio_request(SEL0, "sel0")) { + gpio_direction_input(SEL0); + gpio_export(SEL0, true); + } + + if (!gpio_request(SEL1, "sel1")) { + gpio_direction_input(SEL1); + gpio_export(SEL1, true); + } + + if (!gpio_request(SEL2, "sel2")) { + gpio_direction_input(SEL2); + gpio_export(SEL2, true); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} + #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -307,6 +338,8 @@ void __init mx31moboard_marxbot_init(void) mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), "marxbot"); + marxbot_init_sel_gpios(); + dspics_resets_init(); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c new file mode 100644 index 0000000000000..52a69fc8b14fc --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "devices.h" + +static unsigned int smartbot_pins[] = { + /* UART1 */ + MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, + MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, + /* CSI */ + MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, + MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, + MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, + MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, + MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, + MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, + MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, + MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, + MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, + /* ENABLES */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) +#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) + +static int smartbot_cam_power(struct device *dev, int on) +{ + gpio_set_value(CAM_POWER, !on); + return 0; +} + +static int smartbot_cam_reset(struct device *dev) +{ + gpio_set_value(CAM_RST_B, 0); + udelay(100); + gpio_set_value(CAM_RST_B, 1); + return 0; +} + +static struct i2c_board_info smartbot_i2c_devices[] = { + { + I2C_BOARD_INFO("mt9t031", 0x5d), + }, +}; + +static struct soc_camera_link base_iclink = { + .bus_id = 0, /* Must match with the camera ID */ + .power = smartbot_cam_power, + .reset = smartbot_cam_reset, + .board_info = &smartbot_i2c_devices[0], + .i2c_adapter_id = 0, + .module_name = "mt9t031", +}; + +static struct platform_device smartbot_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &base_iclink, + }, + }, +}; + +static struct platform_device *smartbot_cameras[] __initdata = { + &smartbot_camera[0], +}; + +static int __init smartbot_cam_init(void) +{ + int ret = gpio_request(CAM_RST_B, "cam-reset"); + if (ret) + return ret; + gpio_direction_output(CAM_RST_B, 1); + ret = gpio_request(CAM_POWER, "cam-standby"); + if (ret) + return ret; + gpio_direction_output(CAM_POWER, 0); + + return 0; +} + +#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void smartbot_resets_init(void) +{ + if (!gpio_request(POWER_EN, "power-enable")) { + gpio_direction_output(POWER_EN, 0); + gpio_export(POWER_EN, false); + } + + if (!gpio_request(DSPIC_RST_B, "dspic-rst")) { + gpio_direction_output(DSPIC_RST_B, 0); + gpio_export(DSPIC_RST_B, false); + } + + if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { + gpio_direction_output(TRSLAT_RST_B, 0); + gpio_export(TRSLAT_RST_B, false); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} +/* + * system init for baseboard usage. Will be called by mx31moboard init. + */ +void __init mx31moboard_smartbot_init(void) +{ + printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); + + mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), + "smartbot"); + + mxc_register_device(&mxc_uart_device1, &uart_pdata); + + smartbot_resets_init(); + + smartbot_cam_init(); + platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras)); +} diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index d5be6b5a6acf9..fc5fec9b55f0d 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -25,6 +25,7 @@ enum mx31moboard_boards { MX31NOBOARD = 0, MX31DEVBOARD = 1, MX31MARXBOT = 2, + MX31SMARTBOT = 3, }; /* @@ -34,6 +35,7 @@ enum mx31moboard_boards { extern void mx31moboard_devboard_init(void); extern void mx31moboard_marxbot_init(void); +extern void mx31moboard_smartbot_init(void); #endif -- GitLab From b2a731aa5cbca7e0252da75e16de7ae5feb1313a Mon Sep 17 00:00:00 2001 From: Laurie Bradshaw Date: Wed, 10 Feb 2010 16:10:43 +0000 Subject: [PATCH 206/370] [ARM] orion5x: D-link DNS-323 revision A1 power LED This patch fixes the power LED on DNS-323 revision A1, and adds timer support for (hopefully) both A1 and B1 revisions. Power LED on revision A1 is active low and also requires GPIO 4 to be low to work. Tested on my DNS-323 revision A1. I have set the default trigger to timer as that replicates the behaviour of the original firmware, userspace can change the trigger at the end of the boot process providing a useful indication that booting has completed. Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/dns323-setup.c | 36 +++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 8f159db4d08a8..421b82f7c63d5 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -34,7 +34,8 @@ #define DNS323_GPIO_LED_RIGHT_AMBER 1 #define DNS323_GPIO_LED_LEFT_AMBER 2 #define DNS323_GPIO_SYSTEM_UP 3 -#define DNS323_GPIO_LED_POWER 5 +#define DNS323_GPIO_LED_POWER1 4 +#define DNS323_GPIO_LED_POWER2 5 #define DNS323_GPIO_OVERTEMP 6 #define DNS323_GPIO_RTC 7 #define DNS323_GPIO_POWER_OFF 8 @@ -237,11 +238,31 @@ static int __init dns323_read_mac_addr(void) * GPIO LEDs (simple - doesn't use hardware blinking support) */ +#define ORION_BLINK_HALF_PERIOD 100 /* ms */ + +static int dns323_gpio_blink_set(unsigned gpio, + unsigned long *delay_on, unsigned long *delay_off) +{ + static int value = 0; + + if (!*delay_on && !*delay_off) + *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; + + if (ORION_BLINK_HALF_PERIOD == *delay_on + && ORION_BLINK_HALF_PERIOD == *delay_off) { + value = !value; + orion_gpio_set_blink(gpio, value); + return 0; + } + + return -EINVAL; +} + static struct gpio_led dns323_leds[] = { { .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER, - .default_state = LEDS_GPIO_DEFSTATE_ON, + .gpio = DNS323_GPIO_LED_POWER2, + .default_trigger = "timer", }, { .name = "right:amber", .gpio = DNS323_GPIO_LED_RIGHT_AMBER, @@ -256,6 +277,7 @@ static struct gpio_led dns323_leds[] = { static struct gpio_led_platform_data dns323_led_data = { .num_leds = ARRAY_SIZE(dns323_leds), .leds = dns323_leds, + .gpio_blink_set = dns323_gpio_blink_set, }; static struct platform_device dns323_gpio_leds = { @@ -412,6 +434,14 @@ static void __init dns323_init(void) orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); + /* The 5181 power LED is active low and requires + * DNS323_GPIO_LED_POWER1 to also be low. + */ + if (dns323_dev_id() == MV88F5181_DEV_ID) { + dns323_leds[0].active_low = 1; + gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + } + platform_device_register(&dns323_gpio_leds); platform_device_register(&dns323_button_device); -- GitLab From 7fdda6780aaa21c7a94e09975649649bb0f4a932 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 10 Feb 2010 20:10:55 +0900 Subject: [PATCH 207/370] ARM: mach-shmobile: sh7367 and G3EVM pinmux support Add support for the sh7367 pinmux using drivers/sh/pfc.c and select serial console pins and some LEDs on G3EVM. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 4 + arch/arm/mach-shmobile/board-g3evm.c | 25 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/gpio.h | 49 +- arch/arm/mach-shmobile/include/mach/sh7367.h | 332 ++++ arch/arm/mach-shmobile/pfc-sh7367.c | 1801 ++++++++++++++++++ 7 files changed, 2212 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7367.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7367.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 06b3b6162ff7d..639df5ffbcef0 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -31,6 +31,7 @@ comment "SH-Mobile Board Type" config MACH_G3EVM bool "G3EVM board" depends on ARCH_SH7367 + select ARCH_REQUIRE_GPIOLIB config MACH_G4EVM bool "G4EVM board" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 89ea4b0ea52d1..9ef2630d14324 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -10,6 +10,10 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o +# Pinmux setup +pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o +obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) + # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index eba2311beba22..28ee589caba64 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -113,6 +115,29 @@ static void __init g3evm_map_io(void) static void __init g3evm_init(void) { + sh7367_pinmux_init(); + + /* Lit DS4 LED */ + gpio_request(GPIO_PORT22, NULL); + gpio_direction_output(GPIO_PORT22, 1); + gpio_export(GPIO_PORT22, 0); + + /* Lit DS8 LED */ + gpio_request(GPIO_PORT23, NULL); + gpio_direction_output(GPIO_PORT23, 1); + gpio_export(GPIO_PORT23, 0); + + /* Lit DS3 LED */ + gpio_request(GPIO_PORT24, NULL); + gpio_direction_output(GPIO_PORT24, 1); + gpio_export(GPIO_PORT24, 0); + + /* SCIFA1 */ + gpio_request(GPIO_FN_SCIFA1_TXD, NULL); + gpio_request(GPIO_FN_SCIFA1_RXD, NULL); + gpio_request(GPIO_FN_SCIFA1_CTS, NULL); + gpio_request(GPIO_FN_SCIFA1_RTS, NULL); + sh7367_add_standard_devices(); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index f5986ea561f33..a4846001e89a1 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,6 +8,7 @@ extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); extern void sh7367_add_standard_devices(void); extern void sh7367_clock_init(void); +extern void sh7367_pinmux_init(void); extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h index 40a8c178f10d9..5bc6bd444d723 100644 --- a/arch/arm/mach-shmobile/include/mach/gpio.h +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -1 +1,48 @@ -/* empty */ +/* + * Generic GPIO API and pinmux table support + * + * Copyright (c) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include +#include + +#define ARCH_NR_GPIOS 1024 +#include + +#ifdef CONFIG_GPIOLIB + +static inline int gpio_get_value(unsigned gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return -ENOSYS; +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return -EINVAL; +} + +#endif /* CONFIG_GPIOLIB */ + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h new file mode 100644 index 0000000000000..52d0de686f688 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7367.h @@ -0,0 +1,332 @@ +#ifndef __ASM_SH7367_H__ +#define __ASM_SH7367_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* 49-1 -> 49-6 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU, + GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU, + GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU, + GPIO_FN_PORT58_KEYIN6_PU, + + /* 49-1 (FN) */ + GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2, + GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6, + GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10, + GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2, + GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5, + GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2, + GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20, + GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22, + GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7, + GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2, + GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK, + GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, + GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK, + GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS, + + /* 49-2 (FN) */ + GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0, + GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1, + GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2, + GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3, + GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4, + GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5, + GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0, + GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1, + GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2, + GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC, + GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK, + GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD, + GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD, + GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3, + GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4, + GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5, + GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6, + GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1, + GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2, + GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A, + GPIO_FN_XTALB1L, + GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS, + GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK, + GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD, + GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD, + GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS, + GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS, + GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0, + GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1, + GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2, + GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3, + GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0, + GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1, + GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2, + GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3, + GPIO_FN_NMI, GPIO_FN_TPU4TO0, + GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3, + GPIO_FN_IRQ_TMPB, + GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1, + GPIO_FN_OVCN, GPIO_FN_MFG1_IN1, + GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2, + + /* 49-3 (FN) */ + GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2, + GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN, + GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1, + GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2, + GPIO_FN_SCIFA5_RXD, + GPIO_FN_SCIFA5_TXD, + GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1, + GPIO_FN_A0_EA0, GPIO_FN_BS, + GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0, + GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL, + GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2, + GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3, + GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4, + GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5, + GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0, + GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1, + GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2, + GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3, + GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4, + GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5, + GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL, + GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2, + GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5, + GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8, + GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11, + GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13, + GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15, + GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1, + GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A, + GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD, + GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE, + GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO, + GPIO_FN_NBRSTOUT, GPIO_FN_NBRST, + + /* 49-4 (FN) */ + GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD, + GPIO_FN_VIO_VD, GPIO_FN_VIO_HD, + GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, + GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, + GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, + GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, + GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, + GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, + GPIO_FN_VIO_CKO, + GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2, + GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0, + GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1, + GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2, + GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3, + GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0, + GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2, + GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1, + GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2, + GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3, + GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4, + GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2, + GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5, + GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2, + GPIO_FN_LCDD6, GPIO_FN_DV_D6, + GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2, + GPIO_FN_LCDD7, GPIO_FN_DV_D7, + GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3, + GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16, + GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17, + GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18, + GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19, + GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20, + GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21, + GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22, + GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23, + GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24, + GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK, + GPIO_FN_D26, GPIO_FN_ED26, + GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC, + GPIO_FN_D27, GPIO_FN_ED27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, + GPIO_FN_D28, GPIO_FN_ED28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, + GPIO_FN_D29, GPIO_FN_ED29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1, + GPIO_FN_D30, GPIO_FN_ED30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2, + GPIO_FN_D31, GPIO_FN_ED31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD, + GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC, + + + /* 49-5 (FN) */ + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK, + GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD, + GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3, + GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7, + GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR, + GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR, + GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0, + GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1, + GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3, + GPIO_FN_MSIOF1_SS2, + GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT, + GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, + GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3, + GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1, + GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK, + GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC, + GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD, + GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW, + GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, + GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, + GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2, + GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD, + GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_SDHICLK0, GPIO_FN_TCK2, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, GPIO_FN_TMS2, + GPIO_FN_SDHID0_1, GPIO_FN_TDO2, + GPIO_FN_SDHID0_2, GPIO_FN_TDI2, + GPIO_FN_SDHID0_3, GPIO_FN_RTCK2, + + /* 49-6 (FN) */ + GPIO_FN_SDHICMD0, GPIO_FN_TRST2, + GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2, + GPIO_FN_SDHICLK1, GPIO_FN_TCK3, + GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, + GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3, + GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2, + GPIO_FN_TS_SDAT2, GPIO_FN_TDO3, + GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, + GPIO_FN_TS_SDEN2, GPIO_FN_TDI3, + GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, + GPIO_FN_TS_SCK2, GPIO_FN_RTCK3, + GPIO_FN_SDHICMD1, GPIO_FN_TRST3, + GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK, + GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD, + GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS, + GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD, + GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS, + GPIO_FN_SDHICMD2, + GPIO_FN_RESETOUTS, + GPIO_FN_DIVLOCK, +}; + +#endif /* __ASM_SH7367_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c new file mode 100644 index 0000000000000..128555e76e430 --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7367.c @@ -0,0 +1,1801 @@ +/* + * sh7367 processor support - PFC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _90(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \ + _10(fn, pfx##9, sfx) + +#define _273(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _90(fn, pfx, sfx), \ + _10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \ + _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ + _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ + _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ + _10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \ + _1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_273(str) _273(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_273(IN), /* PORT0_IN -> PORT272_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */ + PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */ + PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */ + PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */ + PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */ + PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */ + PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */ + PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */ + PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */ + PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */ + + MSELBCR_MSEL2_1, MSELBCR_MSEL2_0, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Special Pull-up / Pull-down Functions */ + PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK, + PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK, + PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK, + PORT58_KEYIN6_PU_MARK, + + /* 49-1 */ + VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK, + CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK, + CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK, + CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK, + CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK, + CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK, + CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK, + RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK, + STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK, + MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK, + XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK, + IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK, + M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK, + XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK, + XCTS1_MARK, SCIFA4_CTS_MARK, + + /* 49-2 */ + HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK, + HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK, + HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK, + HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK, + HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK, + HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK, + HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK, + HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK, + HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK, + HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK, + HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK, + HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK, + HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK, + HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK, + HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK, + HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK, + B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK, + HSU_SDI_MARK, PORT55_KEYIN3_MARK, + HSU_SCO_MARK, PORT56_KEYIN4_MARK, + HSU_DREQ_MARK, PORT57_KEYIN5_MARK, + HSU_DACK_MARK, PORT58_KEYIN6_MARK, + HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK, + HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK, + PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK, + XTALB1L_MARK, + GPS_AGC1_MARK, SCIFA0_RTS_MARK, + GPS_AGC2_MARK, SCIFA0_SCK_MARK, + GPS_AGC3_MARK, SCIFA0_TXD_MARK, + GPS_AGC4_MARK, SCIFA0_RXD_MARK, + GPS_PWRD_MARK, SCIFA0_CTS_MARK, + GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK, + SIUBOMC_MARK, TPU2TO0_MARK, + SIUCKB_MARK, TPU2TO1_MARK, + SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK, + SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK, + SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK, + SIUBILR_MARK, TPU3TO1_MARK, + SIUBIBT_MARK, TPU3TO2_MARK, + SIUBISLD_MARK, TPU3TO3_MARK, + NMI_MARK, TPU4TO0_MARK, + DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK, + IRQ_TMPB_MARK, + PWEN_MARK, MFG1_OUT1_MARK, + OVCN_MARK, MFG1_IN1_MARK, + OVCN2_MARK, MFG1_IN2_MARK, + + /* 49-3 */ + RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK, + USBTERM_MARK, EXTLP_MARK, IDIN_MARK, + SCIFA5_CTS_MARK, MFG0_IN1_MARK, + SCIFA5_RTS_MARK, MFG0_IN2_MARK, + SCIFA5_RXD_MARK, + SCIFA5_TXD_MARK, + SCIFA5_SCK_MARK, MFG0_OUT1_MARK, + A0_EA0_MARK, BS_MARK, + A14_EA14_MARK, PORT102_KEYOUT0_MARK, + A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK, + A16_EA16_MARK, PORT104_KEYOUT2_MARK, + DV_VSYNCL_MARK, MSIOF0_SS1_MARK, + A17_EA17_MARK, PORT105_KEYOUT3_MARK, + DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK, + A18_EA18_MARK, PORT106_KEYOUT4_MARK, + DV_DL0_MARK, MSIOF0_TSCK_MARK, + A19_EA19_MARK, PORT107_KEYOUT5_MARK, + DV_DL1_MARK, MSIOF0_TXD_MARK, + A20_EA20_MARK, PORT108_KEYIN0_MARK, + DV_DL2_MARK, MSIOF0_RSCK_MARK, + A21_EA21_MARK, PORT109_KEYIN1_MARK, + DV_DL3_MARK, MSIOF0_RSYNC_MARK, + A22_EA22_MARK, PORT110_KEYIN2_MARK, + DV_DL4_MARK, MSIOF0_MCK0_MARK, + A23_EA23_MARK, PORT111_KEYIN3_MARK, + DV_DL5_MARK, MSIOF0_MCK1_MARK, + A24_EA24_MARK, PORT112_KEYIN4_MARK, + DV_DL6_MARK, MSIOF0_RXD_MARK, + A25_EA25_MARK, PORT113_KEYIN5_MARK, + DV_DL7_MARK, MSIOF0_SS2_MARK, + A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK, + D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK, + D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK, + D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK, + D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK, + D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK, + D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK, + CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK, + CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK, + DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK, + A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK, + WE1_XWR1_MARK, FRB_MARK, CKO_MARK, + NBRSTOUT_MARK, NBRST_MARK, + + /* 49-4 */ + RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK, + VIO_VD_MARK, VIO_HD_MARK, + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, + VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK, + VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK, + VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, + VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK, + VIO_CKO_MARK, + MFG3_IN1_MARK, MFG3_IN2_MARK, + M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK, + M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK, + M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK, + M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK, + LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK, + SIUCKA_MARK, MFG0_OUT2_MARK, + LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK, + SIUAOLR_MARK, BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK, + SIUAOBT_MARK, BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK, + SIUAOSLD_MARK, BBIF2_TXD1_MARK, + LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK, + SIUAISPD_MARK, MFG1_OUT2_MARK, + LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK, + SIUAILR_MARK, MFG2_OUT2_MARK, + LCDD6_MARK, DV_D6_MARK, + SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK, + LCDD7_MARK, DV_D7_MARK, + SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK, + LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK, + LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK, + LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK, + LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK, + LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK, + LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK, + LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK, + LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK, + LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK, + LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK, + LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK, + D26_MARK, ED26_MARK, + LCDD19_MARK, MSIOF0L_TSYNC_MARK, + D27_MARK, ED27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, + D28_MARK, ED28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, + D29_MARK, ED29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK, + D30_MARK, ED30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK, + D31_MARK, ED31_MARK, + LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK, + LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK, + + /* 49-5 */ + LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK, + LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK, + LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK, + LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK, + VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK, + VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK, + VIO_VDR_MARK, VIO_HDR_MARK, + VIO_CLKR_MARK, VIO_CKOR_MARK, + SCIFA1_TXD_MARK, GPS_PGFA0_MARK, + SCIFA1_SCK_MARK, GPS_PGFA1_MARK, + SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK, + SCIFA1_RXD_MARK, SCIFA1_CTS_MARK, + MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK, + MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK, + MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK, + MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK, + MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK, + MSIOF1_RSYNC_MARK, I2C_SCL2_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + MSIOF1_SS1_MARK, EDBGREQ3_MARK, + MSIOF1_SS2_MARK, + PORT236_IROUT_MARK, IRDA_OUT_MARK, + IRDA_IN_MARK, IRDA_FIRSEL_MARK, + TPU1TO0_MARK, TS_SPSYNC3_MARK, + TPU1TO1_MARK, TS_SDAT3_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK, + TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK, + M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK, + M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK, + PORT245_IROUT_MARK, M15_RSW_MARK, + SOUT3_MARK, SCIFA2_TXD1_MARK, + SIN3_MARK, SCIFA2_RXD1_MARK, + XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK, + XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK, + DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + SDHICLK0_MARK, TCK2_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, TMS2_MARK, + SDHID0_1_MARK, TDO2_MARK, + SDHID0_2_MARK, TDI2_MARK, + SDHID0_3_MARK, RTCK2_MARK, + + /* 49-6 */ + SDHICMD0_MARK, TRST2_MARK, + SDHIWP0_MARK, EDBGREQ2_MARK, + SDHICLK1_MARK, TCK3_MARK, + SDHID1_0_MARK, M11_SLCD_SO2_MARK, + TS_SPSYNC2_MARK, TMS3_MARK, + SDHID1_1_MARK, M9_SLCD_AO2_MARK, + TS_SDAT2_MARK, TDO3_MARK, + SDHID1_2_MARK, M10_SLCD_CK2_MARK, + TS_SDEN2_MARK, TDI3_MARK, + SDHID1_3_MARK, M12_SLCD_CE2_MARK, + TS_SCK2_MARK, RTCK3_MARK, + SDHICMD1_MARK, TRST3_MARK, + SDHICLK2_MARK, SCIFB_SCK_MARK, + SDHID2_0_MARK, SCIFB_TXD_MARK, + SDHID2_1_MARK, SCIFB_CTS_MARK, + SDHID2_2_MARK, SCIFB_RXD_MARK, + SDHID2_3_MARK, SCIFB_RTS_MARK, + SDHICMD2_MARK, + RESETOUTS_MARK, + DIVLOCK_MARK, + PINMUX_MARK_END, +}; + +#define PORT_DATA_I(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) + +#define PORT_DATA_I_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_I_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_I_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +#define PORT_DATA_O(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) + +#define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) + +#define PORT_DATA_IO_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_IO_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_IO_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + + +static pinmux_enum_t pinmux_data[] = { + + /* specify valid pin states for each pin in GPIO mode */ + + /* 49-1 (GPIO) */ + PORT_DATA_I_PD(0), + PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6), + PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9), + PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12), + PORT_DATA_I_PU(13), + PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), + PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19), + PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23), + PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26), + PORT_DATA_I_PD(27), PORT_DATA_I_PD(28), + PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32), + PORT_DATA_IO_PU(33), + PORT_DATA_O(34), + PORT_DATA_I_PU(35), + PORT_DATA_O(36), + PORT_DATA_I_PU_PD(37), + + /* 49-2 (GPIO) */ + PORT_DATA_IO_PU_PD(38), + PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41), + PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45), + PORT_DATA_O(46), PORT_DATA_O(47), + PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50), + PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52), + PORT_DATA_O(53), + PORT_DATA_IO_PD(54), + PORT_DATA_I_PU_PD(55), + PORT_DATA_IO_PU_PD(56), + PORT_DATA_I_PU_PD(57), + PORT_DATA_IO_PU_PD(58), + PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62), + PORT_DATA_O(63), + PORT_DATA_I_PU(64), + PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68), + PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70), + PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73), + PORT_DATA_I_PD(74), + PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76), + PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78), + PORT_DATA_O(79), + PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82), + PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84), + PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86), + PORT_DATA_I_PD(87), + PORT_DATA_IO_PU_PD(88), + PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90), + + /* 49-3 (GPIO) */ + PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98), + PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100), + PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103), + PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106), + PORT_DATA_IO_PD(107), + PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109), + PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PU_PD(114), + PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), + PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120), + PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123), + PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126), + PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129), + PORT_DATA_IO_PU(130), + PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133), + PORT_DATA_IO_PU(134), + PORT_DATA_O(135), PORT_DATA_O(136), + PORT_DATA_I_PU_PD(137), + PORT_DATA_IO(138), + PORT_DATA_IO_PU_PD(139), + PORT_DATA_IO(140), PORT_DATA_IO(141), + PORT_DATA_I_PU(142), + PORT_DATA_O(143), PORT_DATA_O(144), + PORT_DATA_I_PU(145), + + /* 49-4 (GPIO) */ + PORT_DATA_O(146), + PORT_DATA_I_PU_PD(147), + PORT_DATA_I_PD(148), PORT_DATA_I_PD(149), + PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152), + PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155), + PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158), + PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161), + PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164), + PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166), + PORT_DATA_IO_PU_PD(167), + PORT_DATA_O(168), + PORT_DATA_I_PD(169), PORT_DATA_I_PD(170), + PORT_DATA_O(171), + PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), + PORT_DATA_O(174), + PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177), + PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180), + PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183), + PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186), + PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), + PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192), + PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198), + PORT_DATA_O(199), + PORT_DATA_IO_PD(200), + + /* 49-5 (GPIO) */ + PORT_DATA_O(201), + PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203), + PORT_DATA_I(204), + PORT_DATA_O(205), + PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208), + PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214), + PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216), + PORT_DATA_O(217), + PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219), + PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222), + PORT_DATA_I_PD(223), + PORT_DATA_I_PU_PD(224), + PORT_DATA_O(225), + PORT_DATA_IO_PD(226), + PORT_DATA_IO_PU_PD(227), + PORT_DATA_I_PD(228), + PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230), + PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232), + PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234), + PORT_DATA_I_PU_PD(235), + PORT_DATA_O(236), + PORT_DATA_I_PD(237), + PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239), + PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241), + PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243), + PORT_DATA_O(244), + PORT_DATA_IO_PU_PD(245), + PORT_DATA_O(246), + PORT_DATA_I_PD(247), + PORT_DATA_IO_PU_PD(248), + PORT_DATA_I_PU_PD(249), + PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251), + PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253), + PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255), + PORT_DATA_IO_PU_PD(256), + + /* 49-6 (GPIO) */ + PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258), + PORT_DATA_IO_PD(259), + PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262), + PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264), + PORT_DATA_O(265), + PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268), + PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270), + PORT_DATA_O(271), + PORT_DATA_I_PD(272), + + /* Special Pull-up / Pull-down Functions */ + PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1, + PORT48_FN2, PORT48_IN_PU), + PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1, + PORT49_FN2, PORT49_IN_PU), + PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1, + PORT50_FN2, PORT50_IN_PU), + PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1, + PORT55_FN2, PORT55_IN_PU), + PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1, + PORT56_FN2, PORT56_IN_PU), + PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1, + PORT57_FN2, PORT57_IN_PU), + PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1, + PORT58_FN2, PORT58_IN_PU), + + /* 49-1 (FN) */ + PINMUX_DATA(VBUS0_MARK, PORT0_FN1), + PINMUX_DATA(CPORT0_MARK, PORT1_FN1), + PINMUX_DATA(CPORT1_MARK, PORT2_FN1), + PINMUX_DATA(CPORT2_MARK, PORT3_FN1), + PINMUX_DATA(CPORT3_MARK, PORT4_FN1), + PINMUX_DATA(CPORT4_MARK, PORT5_FN1), + PINMUX_DATA(CPORT5_MARK, PORT6_FN1), + PINMUX_DATA(CPORT6_MARK, PORT7_FN1), + PINMUX_DATA(CPORT7_MARK, PORT8_FN1), + PINMUX_DATA(CPORT8_MARK, PORT9_FN1), + PINMUX_DATA(CPORT9_MARK, PORT10_FN1), + PINMUX_DATA(CPORT10_MARK, PORT11_FN1), + PINMUX_DATA(CPORT11_MARK, PORT12_FN1), + PINMUX_DATA(SIN2_MARK, PORT12_FN2), + PINMUX_DATA(CPORT12_MARK, PORT13_FN1), + PINMUX_DATA(XCTS2_MARK, PORT13_FN2), + PINMUX_DATA(CPORT13_MARK, PORT14_FN1), + PINMUX_DATA(RFSPO4_MARK, PORT14_FN2), + PINMUX_DATA(CPORT14_MARK, PORT15_FN1), + PINMUX_DATA(RFSPO5_MARK, PORT15_FN2), + PINMUX_DATA(CPORT15_MARK, PORT16_FN1), + PINMUX_DATA(CPORT16_MARK, PORT17_FN1), + PINMUX_DATA(CPORT17_MARK, PORT18_FN1), + PINMUX_DATA(SOUT2_MARK, PORT18_FN2), + PINMUX_DATA(CPORT18_MARK, PORT19_FN1), + PINMUX_DATA(XRTS2_MARK, PORT19_FN1), + PINMUX_DATA(CPORT19_MARK, PORT20_FN1), + PINMUX_DATA(CPORT20_MARK, PORT21_FN1), + PINMUX_DATA(RFSPO6_MARK, PORT21_FN2), + PINMUX_DATA(CPORT21_MARK, PORT22_FN1), + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(CPORT22_MARK, PORT23_FN1), + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(CPORT23_MARK, PORT24_FN1), + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(RFSPO7_MARK, PORT24_FN3), + PINMUX_DATA(MPORT0_MARK, PORT25_FN1), + PINMUX_DATA(MPORT1_MARK, PORT26_FN1), + PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1), + PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1), + PINMUX_DATA(XMAINPS_MARK, PORT29_FN1), + PINMUX_DATA(XDIVPS_MARK, PORT30_FN1), + PINMUX_DATA(XIDRST_MARK, PORT31_FN1), + PINMUX_DATA(IDCLK_MARK, PORT32_FN1), + PINMUX_DATA(IDIO_MARK, PORT33_FN1), + PINMUX_DATA(SOUT1_MARK, PORT34_FN1), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2), + PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3), + PINMUX_DATA(SIN1_MARK, PORT35_FN1), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2), + PINMUX_DATA(XWUP_MARK, PORT35_FN3), + PINMUX_DATA(XRTS1_MARK, PORT36_FN1), + PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2), + PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3), + PINMUX_DATA(XCTS1_MARK, PORT37_FN1), + PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2), + + /* 49-2 (FN) */ + PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1), + PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3), + PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1), + PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3), + PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3), + PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1), + PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3), + PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1), + PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2), + PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1), + PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2), + PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1), + PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2), + PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1), + PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2), + PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1), + PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2), + PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1), + PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2), + PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1), + PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2), + PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1), + PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2), + PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1), + PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2), + PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1), + PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2), + PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1), + PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2), + PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1), + PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2), + PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1), + PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2), + PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1), + PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2), + PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1), + PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2), + PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1), + PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2), + PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1), + PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2), + PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1), + PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2), + PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1), + PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2), + PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1), + PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1), + PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1), + PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1), + PINMUX_DATA(XTALB1L_MARK, PORT65_FN1), + PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2), + PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2), + PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2), + PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2), + PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2), + PINMUX_DATA(GPS_IM_MARK, PORT71_FN1), + PINMUX_DATA(GPS_IS_MARK, PORT72_FN1), + PINMUX_DATA(GPS_QM_MARK, PORT73_FN1), + PINMUX_DATA(GPS_QS_MARK, PORT74_FN1), + PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1), + PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3), + PINMUX_DATA(SIUCKB_MARK, PORT76_FN1), + PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3), + PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1), + PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2), + PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3), + PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1), + PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2), + PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3), + PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1), + PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2), + PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3), + PINMUX_DATA(SIUBILR_MARK, PORT80_FN1), + PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3), + PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1), + PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3), + PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1), + PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3), + PINMUX_DATA(NMI_MARK, PORT83_FN1), + PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3), + PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1), + PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3), + PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3), + PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3), + PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1), + PINMUX_DATA(PWEN_MARK, PORT88_FN1), + PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2), + PINMUX_DATA(OVCN_MARK, PORT89_FN1), + PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2), + PINMUX_DATA(OVCN2_MARK, PORT90_FN1), + PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2), + + /* 49-3 (FN) */ + PINMUX_DATA(RFSPO1_MARK, PORT91_FN1), + PINMUX_DATA(RFSPO2_MARK, PORT92_FN1), + PINMUX_DATA(RFSPO3_MARK, PORT93_FN1), + PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2), + PINMUX_DATA(USBTERM_MARK, PORT94_FN1), + PINMUX_DATA(EXTLP_MARK, PORT94_FN2), + PINMUX_DATA(IDIN_MARK, PORT95_FN1), + PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1), + PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2), + PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1), + PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2), + PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1), + PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1), + PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1), + PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2), + PINMUX_DATA(A0_EA0_MARK, PORT101_FN1), + PINMUX_DATA(BS_MARK, PORT101_FN2), + PINMUX_DATA(A14_EA14_MARK, PORT102_FN1), + PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2), + PINMUX_DATA(A15_EA15_MARK, PORT103_FN1), + PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2), + PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3), + PINMUX_DATA(A16_EA16_MARK, PORT104_FN1), + PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2), + PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4), + PINMUX_DATA(A17_EA17_MARK, PORT105_FN1), + PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2), + PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4), + PINMUX_DATA(A18_EA18_MARK, PORT106_FN1), + PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2), + PINMUX_DATA(DV_DL0_MARK, PORT106_FN3), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4), + PINMUX_DATA(A19_EA19_MARK, PORT107_FN1), + PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2), + PINMUX_DATA(DV_DL1_MARK, PORT107_FN3), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4), + PINMUX_DATA(A20_EA20_MARK, PORT108_FN1), + PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2), + PINMUX_DATA(DV_DL2_MARK, PORT108_FN3), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4), + PINMUX_DATA(A21_EA21_MARK, PORT109_FN1), + PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2), + PINMUX_DATA(DV_DL3_MARK, PORT109_FN3), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4), + PINMUX_DATA(A22_EA22_MARK, PORT110_FN1), + PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2), + PINMUX_DATA(DV_DL4_MARK, PORT110_FN3), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4), + PINMUX_DATA(A23_EA23_MARK, PORT111_FN1), + PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2), + PINMUX_DATA(DV_DL5_MARK, PORT111_FN3), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4), + PINMUX_DATA(A24_EA24_MARK, PORT112_FN1), + PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2), + PINMUX_DATA(DV_DL6_MARK, PORT112_FN3), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4), + PINMUX_DATA(A25_EA25_MARK, PORT113_FN1), + PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2), + PINMUX_DATA(DV_DL7_MARK, PORT113_FN3), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4), + PINMUX_DATA(A26_MARK, PORT114_FN1), + PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2), + PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3), + PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1), + PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1), + PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1), + PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1), + PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1), + PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1), + PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1), + PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1), + PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1), + PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1), + PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1), + PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1), + PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1), + PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1), + PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1), + PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1), + PINMUX_DATA(CS4_MARK, PORT131_FN1), + PINMUX_DATA(CS5A_MARK, PORT132_FN1), + PINMUX_DATA(CS5B_MARK, PORT133_FN1), + PINMUX_DATA(FCE1_MARK, PORT133_FN2), + PINMUX_DATA(CS6B_MARK, PORT134_FN1), + PINMUX_DATA(XCS2_MARK, PORT134_FN2), + PINMUX_DATA(FCE0_MARK, PORT135_FN1), + PINMUX_DATA(CS6A_MARK, PORT136_FN1), + PINMUX_DATA(DACK0_MARK, PORT136_FN2), + PINMUX_DATA(WAIT_MARK, PORT137_FN1), + PINMUX_DATA(DREQ0_MARK, PORT137_FN2), + PINMUX_DATA(RD_XRD_MARK, PORT138_FN1), + PINMUX_DATA(A27_MARK, PORT139_FN1), + PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2), + PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1), + PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1), + PINMUX_DATA(FRB_MARK, PORT142_FN1), + PINMUX_DATA(CKO_MARK, PORT143_FN1), + PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1), + PINMUX_DATA(NBRST_MARK, PORT145_FN1), + + /* 49-4 (FN) */ + PINMUX_DATA(RFSPO0_MARK, PORT146_FN1), + PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2), + PINMUX_DATA(TSTMD_MARK, PORT147_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT148_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT149_FN1), + PINMUX_DATA(VIO_D0_MARK, PORT150_FN1), + PINMUX_DATA(VIO_D1_MARK, PORT151_FN1), + PINMUX_DATA(VIO_D2_MARK, PORT152_FN1), + PINMUX_DATA(VIO_D3_MARK, PORT153_FN1), + PINMUX_DATA(VIO_D4_MARK, PORT154_FN1), + PINMUX_DATA(VIO_D5_MARK, PORT155_FN1), + PINMUX_DATA(VIO_D6_MARK, PORT156_FN1), + PINMUX_DATA(VIO_D7_MARK, PORT157_FN1), + PINMUX_DATA(VIO_D8_MARK, PORT158_FN1), + PINMUX_DATA(VIO_D9_MARK, PORT159_FN1), + PINMUX_DATA(VIO_D10_MARK, PORT160_FN1), + PINMUX_DATA(VIO_D11_MARK, PORT161_FN1), + PINMUX_DATA(VIO_D12_MARK, PORT162_FN1), + PINMUX_DATA(VIO_D13_MARK, PORT163_FN1), + PINMUX_DATA(VIO_D14_MARK, PORT164_FN1), + PINMUX_DATA(VIO_D15_MARK, PORT165_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1), + PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1), + PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2), + PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2), + PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1), + PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2), + PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3), + PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1), + PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2), + PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3), + PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1), + PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2), + PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3), + PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1), + PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2), + PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3), + PINMUX_DATA(LCDD0_MARK, PORT175_FN1), + PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2), + PINMUX_DATA(DV_D0_MARK, PORT175_FN3), + PINMUX_DATA(SIUCKA_MARK, PORT175_FN4), + PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5), + PINMUX_DATA(LCDD1_MARK, PORT176_FN1), + PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2), + PINMUX_DATA(DV_D1_MARK, PORT176_FN3), + PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5), + PINMUX_DATA(LCDD2_MARK, PORT177_FN1), + PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2), + PINMUX_DATA(DV_D2_MARK, PORT177_FN3), + PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4), + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5), + PINMUX_DATA(LCDD3_MARK, PORT178_FN1), + PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2), + PINMUX_DATA(DV_D3_MARK, PORT178_FN3), + PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5), + PINMUX_DATA(LCDD4_MARK, PORT179_FN1), + PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2), + PINMUX_DATA(DV_D4_MARK, PORT179_FN3), + PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4), + PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5), + PINMUX_DATA(LCDD5_MARK, PORT180_FN1), + PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2), + PINMUX_DATA(DV_D5_MARK, PORT180_FN3), + PINMUX_DATA(SIUAILR_MARK, PORT180_FN4), + PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5), + PINMUX_DATA(LCDD6_MARK, PORT181_FN1), + PINMUX_DATA(DV_D6_MARK, PORT181_FN3), + PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4), + PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5), + PINMUX_DATA(XWR2_MARK, PORT181_FN7), + PINMUX_DATA(LCDD7_MARK, PORT182_FN1), + PINMUX_DATA(DV_D7_MARK, PORT182_FN3), + PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4), + PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5), + PINMUX_DATA(XWR3_MARK, PORT182_FN7), + PINMUX_DATA(LCDD8_MARK, PORT183_FN1), + PINMUX_DATA(DV_D8_MARK, PORT183_FN3), + PINMUX_DATA(D16_MARK, PORT183_FN6), + PINMUX_DATA(ED16_MARK, PORT183_FN7), + PINMUX_DATA(LCDD9_MARK, PORT184_FN1), + PINMUX_DATA(DV_D9_MARK, PORT184_FN3), + PINMUX_DATA(D17_MARK, PORT184_FN6), + PINMUX_DATA(ED17_MARK, PORT184_FN7), + PINMUX_DATA(LCDD10_MARK, PORT185_FN1), + PINMUX_DATA(DV_D10_MARK, PORT185_FN3), + PINMUX_DATA(D18_MARK, PORT185_FN6), + PINMUX_DATA(ED18_MARK, PORT185_FN7), + PINMUX_DATA(LCDD11_MARK, PORT186_FN1), + PINMUX_DATA(DV_D11_MARK, PORT186_FN3), + PINMUX_DATA(D19_MARK, PORT186_FN6), + PINMUX_DATA(ED19_MARK, PORT186_FN7), + PINMUX_DATA(LCDD12_MARK, PORT187_FN1), + PINMUX_DATA(DV_D12_MARK, PORT187_FN3), + PINMUX_DATA(D20_MARK, PORT187_FN6), + PINMUX_DATA(ED20_MARK, PORT187_FN7), + PINMUX_DATA(LCDD13_MARK, PORT188_FN1), + PINMUX_DATA(DV_D13_MARK, PORT188_FN3), + PINMUX_DATA(D21_MARK, PORT188_FN6), + PINMUX_DATA(ED21_MARK, PORT188_FN7), + PINMUX_DATA(LCDD14_MARK, PORT189_FN1), + PINMUX_DATA(DV_D14_MARK, PORT189_FN3), + PINMUX_DATA(D22_MARK, PORT189_FN6), + PINMUX_DATA(ED22_MARK, PORT189_FN7), + PINMUX_DATA(LCDD15_MARK, PORT190_FN1), + PINMUX_DATA(DV_D15_MARK, PORT190_FN3), + PINMUX_DATA(D23_MARK, PORT190_FN6), + PINMUX_DATA(ED23_MARK, PORT190_FN7), + PINMUX_DATA(LCDD16_MARK, PORT191_FN1), + PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3), + PINMUX_DATA(D24_MARK, PORT191_FN6), + PINMUX_DATA(ED24_MARK, PORT191_FN7), + PINMUX_DATA(LCDD17_MARK, PORT192_FN1), + PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3), + PINMUX_DATA(D25_MARK, PORT192_FN6), + PINMUX_DATA(ED25_MARK, PORT192_FN7), + PINMUX_DATA(LCDD18_MARK, PORT193_FN1), + PINMUX_DATA(DREQ2_MARK, PORT193_FN2), + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5), + PINMUX_DATA(D26_MARK, PORT193_FN6), + PINMUX_DATA(ED26_MARK, PORT193_FN7), + PINMUX_DATA(LCDD19_MARK, PORT194_FN1), + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5), + PINMUX_DATA(D27_MARK, PORT194_FN6), + PINMUX_DATA(ED27_MARK, PORT194_FN7), + PINMUX_DATA(LCDD20_MARK, PORT195_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2), + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5), + PINMUX_DATA(D28_MARK, PORT195_FN6), + PINMUX_DATA(ED28_MARK, PORT195_FN7), + PINMUX_DATA(LCDD21_MARK, PORT196_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2), + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5), + PINMUX_DATA(D29_MARK, PORT196_FN6), + PINMUX_DATA(ED29_MARK, PORT196_FN7), + PINMUX_DATA(LCDD22_MARK, PORT197_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2), + PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5), + PINMUX_DATA(D30_MARK, PORT197_FN6), + PINMUX_DATA(ED30_MARK, PORT197_FN7), + PINMUX_DATA(LCDD23_MARK, PORT198_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2), + PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5), + PINMUX_DATA(D31_MARK, PORT198_FN6), + PINMUX_DATA(ED31_MARK, PORT198_FN7), + PINMUX_DATA(LCDDCK_MARK, PORT199_FN1), + PINMUX_DATA(LCDWR_MARK, PORT199_FN2), + PINMUX_DATA(DV_CKO_MARK, PORT199_FN3), + PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4), + PINMUX_DATA(LCDRD_MARK, PORT200_FN1), + PINMUX_DATA(DACK2_MARK, PORT200_FN2), + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5), + + /* 49-5 (FN) */ + PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1), + PINMUX_DATA(LCDCS_MARK, PORT201_FN2), + PINMUX_DATA(LCDCS2_MARK, PORT201_FN3), + PINMUX_DATA(DACK3_MARK, PORT201_FN4), + PINMUX_DATA(LCDDISP_MARK, PORT202_FN1), + PINMUX_DATA(LCDRS_MARK, PORT202_FN2), + PINMUX_DATA(DREQ3_MARK, PORT202_FN4), + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5), + PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1), + PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2), + PINMUX_DATA(DV_CKI_MARK, PORT203_FN3), + PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1), + PINMUX_DATA(DREQ1_MARK, PORT204_FN3), + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5), + PINMUX_DATA(LCDDON_MARK, PORT205_FN1), + PINMUX_DATA(LCDDON2_MARK, PORT205_FN2), + PINMUX_DATA(DACK1_MARK, PORT205_FN3), + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5), + PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1), + PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1), + PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1), + PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1), + PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1), + PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1), + PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1), + PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1), + PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1), + PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1), + PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1), + PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2), + PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2), + PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2), + PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1), + PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2), + PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1), + PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2), + PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1), + PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1), + PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2), + PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1), + PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1), + PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1), + PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2), + PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1), + PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1), + PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2), + PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1), + PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4), + PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3), + PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4), + PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3), + PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4), + PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5), + PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3), + PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5), + PINMUX_DATA(M13_BSW_MARK, PORT243_FN2), + PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5), + PINMUX_DATA(M14_GSW_MARK, PORT244_FN2), + PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5), + PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1), + PINMUX_DATA(M15_RSW_MARK, PORT245_FN2), + PINMUX_DATA(SOUT3_MARK, PORT246_FN1), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2), + PINMUX_DATA(SIN3_MARK, PORT247_FN1), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2), + PINMUX_DATA(XRTS3_MARK, PORT248_FN1), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2), + PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5), + PINMUX_DATA(XCTS3_MARK, PORT249_FN1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2), + PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5), + PINMUX_DATA(DINT_MARK, PORT250_FN1), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2), + PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4), + PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1), + PINMUX_DATA(TCK2_MARK, PORT251_FN2), + PINMUX_DATA(SDHICD0_MARK, PORT252_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1), + PINMUX_DATA(TMS2_MARK, PORT253_FN2), + PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1), + PINMUX_DATA(TDO2_MARK, PORT254_FN2), + PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1), + PINMUX_DATA(TDI2_MARK, PORT255_FN2), + PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1), + PINMUX_DATA(RTCK2_MARK, PORT256_FN2), + + /* 49-6 (FN) */ + PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1), + PINMUX_DATA(TRST2_MARK, PORT257_FN2), + PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1), + PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2), + PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1), + PINMUX_DATA(TCK3_MARK, PORT259_FN4), + PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1), + PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3), + PINMUX_DATA(TMS3_MARK, PORT260_FN4), + PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1), + PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2), + PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3), + PINMUX_DATA(TDO3_MARK, PORT261_FN4), + PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1), + PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2), + PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3), + PINMUX_DATA(TDI3_MARK, PORT262_FN4), + PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1), + PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2), + PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3), + PINMUX_DATA(RTCK3_MARK, PORT263_FN4), + PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1), + PINMUX_DATA(TRST3_MARK, PORT264_FN4), + PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1), + PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2), + PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1), + PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2), + PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1), + PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2), + PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1), + PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2), + PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1), + PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2), + PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1), + PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1), + PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_273() _273(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + /* 49-1 -> 49-6 (GPIO) */ + GPIO_PORT_273(), + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU), + GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU), + GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU), + GPIO_FN(PORT58_KEYIN6_PU), + + /* 49-1 (FN) */ + GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2), + GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6), + GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10), + GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2), + GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5), + GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2), + GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20), + GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22), + GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7), + GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2), + GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK), + GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), + GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP), + GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK), + GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS), + + /* 49-2 (FN) */ + GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1), + GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK), + GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0), + GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1), + GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2), + GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3), + GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4), + GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5), + GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0), + GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1), + GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2), + GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC), + GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK), + GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD), + GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD), + GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3), + GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4), + GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5), + GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6), + GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1), + GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2), + GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A), + GPIO_FN(XTALB1L), + GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS), + GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK), + GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD), + GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD), + GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS), + GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS), + GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0), + GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1), + GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2), + GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3), + GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0), + GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1), + GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2), + GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3), + GPIO_FN(NMI), GPIO_FN(TPU4TO0), + GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3), + GPIO_FN(IRQ_TMPB), + GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1), + GPIO_FN(OVCN), GPIO_FN(MFG1_IN1), + GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2), + + /* 49-3 (FN) */ + GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3), + GPIO_FN(PORT93_VIO_CKO2), + GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN), + GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1), + GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2), + GPIO_FN(SCIFA5_RXD), + GPIO_FN(SCIFA5_TXD), + GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1), + GPIO_FN(A0_EA0), GPIO_FN(BS), + GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0), + GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL), + GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2), + GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3), + GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4), + GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5), + GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0), + GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1), + GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2), + GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3), + GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4), + GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5), + GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL), + GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2), + GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5), + GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8), + GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11), + GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13), + GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15), + GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1), + GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A), + GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD), + GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE), + GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO), + GPIO_FN(NBRSTOUT), GPIO_FN(NBRST), + + /* 49-4 (FN) */ + GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD), + GPIO_FN(VIO_VD), GPIO_FN(VIO_HD), + GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2), + GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5), + GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8), + GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11), + GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14), + GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), + GPIO_FN(VIO_CKO), + GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2), + GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0), + GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1), + GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2), + GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3), + GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0), + GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2), + GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1), + GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2), + GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3), + GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4), + GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2), + GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5), + GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2), + GPIO_FN(LCDD6), GPIO_FN(DV_D6), + GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2), + GPIO_FN(LCDD7), GPIO_FN(DV_D7), + GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3), + GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16), + GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17), + GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18), + GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19), + GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20), + GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21), + GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22), + GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23), + GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24), + GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25), + GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK), + GPIO_FN(D26), GPIO_FN(ED26), + GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC), + GPIO_FN(D27), GPIO_FN(ED27), + GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0), + GPIO_FN(D28), GPIO_FN(ED28), + GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1), + GPIO_FN(D29), GPIO_FN(ED29), + GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1), + GPIO_FN(D30), GPIO_FN(ED30), + GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2), + GPIO_FN(D31), GPIO_FN(ED31), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD), + GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC), + + /* 49-5 (FN) */ + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK), + GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI), + GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD), + GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD), + GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3), + GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7), + GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR), + GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR), + GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0), + GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1), + GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON), + GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS), + GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD), + GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2), + GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2), + GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2), + GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3), + GPIO_FN(MSIOF1_SS2), + GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT), + GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), + GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3), + GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3), + GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1), + GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK), + GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC), + GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD), + GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW), + GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), + GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), + GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2), + GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD), + GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3), + GPIO_FN(SDHICLK0), GPIO_FN(TCK2), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), GPIO_FN(TMS2), + GPIO_FN(SDHID0_1), GPIO_FN(TDO2), + GPIO_FN(SDHID0_2), GPIO_FN(TDI2), + GPIO_FN(SDHID0_3), GPIO_FN(RTCK2), + + /* 49-6 (FN) */ + GPIO_FN(SDHICMD0), GPIO_FN(TRST2), + GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2), + GPIO_FN(SDHICLK1), GPIO_FN(TCK3), + GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), + GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3), + GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2), + GPIO_FN(TS_SDAT2), GPIO_FN(TDO3), + GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), + GPIO_FN(TS_SDEN2), GPIO_FN(TDI3), + GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), + GPIO_FN(TS_SCK2), GPIO_FN(RTCK3), + GPIO_FN(SDHICMD1), GPIO_FN(TRST3), + GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK), + GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD), + GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS), + GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD), + GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS), + GPIO_FN(SDHICMD2), + GPIO_FN(RESETOUTS), + GPIO_FN(DIVLOCK), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ + PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + PORTCR(84, 0xe6050054), /* PORT84CR */ + PORTCR(85, 0xe6050055), /* PORT85CR */ + PORTCR(86, 0xe6050056), /* PORT86CR */ + PORTCR(87, 0xe6050057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6051060), /* PORT96CR */ + PORTCR(97, 0xe6051061), /* PORT97CR */ + PORTCR(98, 0xe6051062), /* PORT98CR */ + PORTCR(99, 0xe6051063), /* PORT99CR */ + + PORTCR(100, 0xe6051064), /* PORT100CR */ + PORTCR(101, 0xe6051065), /* PORT101CR */ + PORTCR(102, 0xe6051066), /* PORT102CR */ + PORTCR(103, 0xe6051067), /* PORT103CR */ + PORTCR(104, 0xe6051068), /* PORT104CR */ + PORTCR(105, 0xe6051069), /* PORT105CR */ + PORTCR(106, 0xe605106a), /* PORT106CR */ + PORTCR(107, 0xe605106b), /* PORT107CR */ + PORTCR(108, 0xe605106c), /* PORT108CR */ + PORTCR(109, 0xe605106d), /* PORT109CR */ + + PORTCR(110, 0xe605106e), /* PORT110CR */ + PORTCR(111, 0xe605106f), /* PORT111CR */ + PORTCR(112, 0xe6051070), /* PORT112CR */ + PORTCR(113, 0xe6051071), /* PORT113CR */ + PORTCR(114, 0xe6051072), /* PORT114CR */ + PORTCR(115, 0xe6051073), /* PORT115CR */ + PORTCR(116, 0xe6051074), /* PORT116CR */ + PORTCR(117, 0xe6051075), /* PORT117CR */ + PORTCR(118, 0xe6051076), /* PORT118CR */ + PORTCR(119, 0xe6051077), /* PORT119CR */ + + PORTCR(120, 0xe6051078), /* PORT120CR */ + PORTCR(121, 0xe6051079), /* PORT121CR */ + PORTCR(122, 0xe605107a), /* PORT122CR */ + PORTCR(123, 0xe605107b), /* PORT123CR */ + PORTCR(124, 0xe605107c), /* PORT124CR */ + PORTCR(125, 0xe605107d), /* PORT125CR */ + PORTCR(126, 0xe605107e), /* PORT126CR */ + PORTCR(127, 0xe605107f), /* PORT127CR */ + PORTCR(128, 0xe6051080), /* PORT128CR */ + PORTCR(129, 0xe6051081), /* PORT129CR */ + + PORTCR(130, 0xe6051082), /* PORT130CR */ + PORTCR(131, 0xe6051083), /* PORT131CR */ + PORTCR(132, 0xe6051084), /* PORT132CR */ + PORTCR(133, 0xe6051085), /* PORT133CR */ + PORTCR(134, 0xe6051086), /* PORT134CR */ + PORTCR(135, 0xe6051087), /* PORT135CR */ + PORTCR(136, 0xe6051088), /* PORT136CR */ + PORTCR(137, 0xe6051089), /* PORT137CR */ + PORTCR(138, 0xe605108a), /* PORT138CR */ + PORTCR(139, 0xe605108b), /* PORT139CR */ + + PORTCR(140, 0xe605108c), /* PORT140CR */ + PORTCR(141, 0xe605108d), /* PORT141CR */ + PORTCR(142, 0xe605108e), /* PORT142CR */ + PORTCR(143, 0xe605108f), /* PORT143CR */ + PORTCR(144, 0xe6051090), /* PORT144CR */ + PORTCR(145, 0xe6051091), /* PORT145CR */ + PORTCR(146, 0xe6051092), /* PORT146CR */ + PORTCR(147, 0xe6051093), /* PORT147CR */ + PORTCR(148, 0xe6051094), /* PORT148CR */ + PORTCR(149, 0xe6051095), /* PORT149CR */ + + PORTCR(150, 0xe6051096), /* PORT150CR */ + PORTCR(151, 0xe6051097), /* PORT151CR */ + PORTCR(152, 0xe6051098), /* PORT152CR */ + PORTCR(153, 0xe6051099), /* PORT153CR */ + PORTCR(154, 0xe605109a), /* PORT154CR */ + PORTCR(155, 0xe605109b), /* PORT155CR */ + PORTCR(156, 0xe605109c), /* PORT156CR */ + PORTCR(157, 0xe605109d), /* PORT157CR */ + PORTCR(158, 0xe605109e), /* PORT158CR */ + PORTCR(159, 0xe605109f), /* PORT159CR */ + + PORTCR(160, 0xe60510a0), /* PORT160CR */ + PORTCR(161, 0xe60510a1), /* PORT161CR */ + PORTCR(162, 0xe60510a2), /* PORT162CR */ + PORTCR(163, 0xe60510a3), /* PORT163CR */ + PORTCR(164, 0xe60510a4), /* PORT164CR */ + PORTCR(165, 0xe60510a5), /* PORT165CR */ + PORTCR(166, 0xe60510a6), /* PORT166CR */ + PORTCR(167, 0xe60510a7), /* PORT167CR */ + PORTCR(168, 0xe60510a8), /* PORT168CR */ + PORTCR(169, 0xe60510a9), /* PORT169CR */ + + PORTCR(170, 0xe60510aa), /* PORT170CR */ + PORTCR(171, 0xe60510ab), /* PORT171CR */ + PORTCR(172, 0xe60510ac), /* PORT172CR */ + PORTCR(173, 0xe60510ad), /* PORT173CR */ + PORTCR(174, 0xe60510ae), /* PORT174CR */ + PORTCR(175, 0xe60520af), /* PORT175CR */ + PORTCR(176, 0xe60520b0), /* PORT176CR */ + PORTCR(177, 0xe60520b1), /* PORT177CR */ + PORTCR(178, 0xe60520b2), /* PORT178CR */ + PORTCR(179, 0xe60520b3), /* PORT179CR */ + + PORTCR(180, 0xe60520b4), /* PORT180CR */ + PORTCR(181, 0xe60520b5), /* PORT181CR */ + PORTCR(182, 0xe60520b6), /* PORT182CR */ + PORTCR(183, 0xe60520b7), /* PORT183CR */ + PORTCR(184, 0xe60520b8), /* PORT184CR */ + PORTCR(185, 0xe60520b9), /* PORT185CR */ + PORTCR(186, 0xe60520ba), /* PORT186CR */ + PORTCR(187, 0xe60520bb), /* PORT187CR */ + PORTCR(188, 0xe60520bc), /* PORT188CR */ + PORTCR(189, 0xe60520bd), /* PORT189CR */ + + PORTCR(190, 0xe60520be), /* PORT190CR */ + PORTCR(191, 0xe60520bf), /* PORT191CR */ + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60520e0), /* PORT224CR */ + PORTCR(225, 0xe60520e1), /* PORT225CR */ + PORTCR(226, 0xe60520e2), /* PORT226CR */ + PORTCR(227, 0xe60520e3), /* PORT227CR */ + PORTCR(228, 0xe60520e4), /* PORT228CR */ + PORTCR(229, 0xe60520e5), /* PORT229CR */ + + PORTCR(230, 0xe60520e6), /* PORT230CR */ + PORTCR(231, 0xe60520e7), /* PORT231CR */ + PORTCR(232, 0xe60520e8), /* PORT232CR */ + PORTCR(233, 0xe60520e9), /* PORT233CR */ + PORTCR(234, 0xe60520ea), /* PORT234CR */ + PORTCR(235, 0xe60520eb), /* PORT235CR */ + PORTCR(236, 0xe60530ec), /* PORT236CR */ + PORTCR(237, 0xe60530ed), /* PORT237CR */ + PORTCR(238, 0xe60530ee), /* PORT238CR */ + PORTCR(239, 0xe60530ef), /* PORT239CR */ + + PORTCR(240, 0xe60530f0), /* PORT240CR */ + PORTCR(241, 0xe60530f1), /* PORT241CR */ + PORTCR(242, 0xe60530f2), /* PORT242CR */ + PORTCR(243, 0xe60530f3), /* PORT243CR */ + PORTCR(244, 0xe60530f4), /* PORT244CR */ + PORTCR(245, 0xe60530f5), /* PORT245CR */ + PORTCR(246, 0xe60530f6), /* PORT246CR */ + PORTCR(247, 0xe60530f7), /* PORT247CR */ + PORTCR(248, 0xe60530f8), /* PORT248CR */ + PORTCR(249, 0xe60530f9), /* PORT249CR */ + + PORTCR(250, 0xe60530fa), /* PORT250CR */ + PORTCR(251, 0xe60530fb), /* PORT251CR */ + PORTCR(252, 0xe60530fc), /* PORT252CR */ + PORTCR(253, 0xe60530fd), /* PORT253CR */ + PORTCR(254, 0xe60530fe), /* PORT254CR */ + PORTCR(255, 0xe60530ff), /* PORT255CR */ + PORTCR(256, 0xe6053100), /* PORT256CR */ + PORTCR(257, 0xe6053101), /* PORT257CR */ + PORTCR(258, 0xe6053102), /* PORT258CR */ + PORTCR(259, 0xe6053103), /* PORT259CR */ + + PORTCR(260, 0xe6053104), /* PORT260CR */ + PORTCR(261, 0xe6053105), /* PORT261CR */ + PORTCR(262, 0xe6053106), /* PORT262CR */ + PORTCR(263, 0xe6053107), /* PORT263CR */ + PORTCR(264, 0xe6053108), /* PORT264CR */ + PORTCR(265, 0xe6053109), /* PORT265CR */ + PORTCR(266, 0xe605310a), /* PORT266CR */ + PORTCR(267, 0xe605310b), /* PORT267CR */ + PORTCR(268, 0xe605310c), /* PORT268CR */ + PORTCR(269, 0xe605310d), /* PORT269CR */ + + PORTCR(270, 0xe605310e), /* PORT270CR */ + PORTCR(271, 0xe605310f), /* PORT271CR */ + PORTCR(272, 0xe6053110), /* PORT272CR */ + + { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSELBCR_MSEL2_0, MSELBCR_MSEL2_1, + 0, 0, + 0, 0 } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { + PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { }, +}; + +static struct pinmux_info sh7367_pinmux_info = { + .name = "sh7367_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_DIVLOCK, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7367_pinmux_init(void) +{ + register_pinmux(&sh7367_pinmux_info); +} -- GitLab From 3a7b802d1a8c279876ec74094d71f3c6c45d8030 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 10 Feb 2010 20:13:31 +0900 Subject: [PATCH 208/370] ARM: mach-shmobile: G3EVM USBHS support Add G3EVM platform data and a magic setup sequence to initialize the r8a66597 block aka USBHS in sh7367. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-g3evm.c | 58 +++++++++++++++++++++++++++ arch/arm/mach-shmobile/clock-sh7367.c | 7 ++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 28ee589caba64..f36c9a94d3264 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -86,9 +87,49 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* USBHS */ +void usb_host_port_power(int port, int power) +{ + if (!power) /* only power-on supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ + __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); +} + +static struct r8a66597_platdata usb_host_data = { + .on_chip = 1, + .port_power = usb_host_port_power, +}; + +static struct resource usb_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xe6890000, + .end = 0xe68900e5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .platform_data = &usb_host_data, + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; static struct platform_device *g3evm_devices[] __initdata = { &nor_flash_device, + &usb_host_device, }; static struct map_desc g3evm_io_desc[] __initdata = { @@ -138,6 +179,23 @@ static void __init g3evm_init(void) gpio_request(GPIO_FN_SCIFA1_CTS, NULL); gpio_request(GPIO_FN_SCIFA1_RTS, NULL); + /* USBHS */ + gpio_request(GPIO_FN_VBUS0, NULL); + gpio_request(GPIO_FN_PWEN, NULL); + gpio_request(GPIO_FN_OVCN, NULL); + gpio_request(GPIO_FN_OVCN2, NULL); + gpio_request(GPIO_FN_EXTLP, NULL); + gpio_request(GPIO_FN_IDIN, NULL); + + /* enable clock in SYMSTPCR2 */ + __raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048); + + /* setup USB phy */ + __raw_writew(0x0300, 0xe605810a); /* USBCR1 */ + __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ + __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ + __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + sh7367_add_standard_devices(); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 3b2e3f2fc7eaf..58bd54e1113a8 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -70,11 +70,18 @@ static struct clk r_clk = { .rate = 32768, }; +/* a static usb0 for now - enough to get r8a66597 working */ +static struct clk usb0_clk = { + .name = "usb0", +}; + static struct clk_lookup lookups[] = { { .clk = &peripheral_clk, }, { .clk = &r_clk, + }, { + .clk = &usb0_clk, } }; -- GitLab From 276b4f623cfd30320c004269725683ba8f262bb6 Mon Sep 17 00:00:00 2001 From: NISHIMOTO Hiroki Date: Fri, 12 Feb 2010 08:10:06 +0000 Subject: [PATCH 209/370] ARM: mach-shmobile: sh7377 and G4EVM pinmux support Add support for the sh 7377 pinmux using drivers/sh/pfc.c and some LEDs on G4EVM. Signed-off-by: NISHIMOTO Hiroki Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/board-g4evm.c | 24 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/sh7377.h | 360 ++++ arch/arm/mach-shmobile/pfc-sh7377.c | 1766 ++++++++++++++++++ 6 files changed, 2153 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7377.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7377.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 639df5ffbcef0..a96c25a262729 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -36,6 +36,7 @@ config MACH_G3EVM config MACH_G4EVM bool "G4EVM board" depends on ARCH_SH7377 + select ARCH_REQUIRE_GPIOLIB config MACH_AP4EVB bool "AP4EVB board" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 9ef2630d14324..ce01951edda33 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Pinmux setup pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o +pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) # Board objects diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 0ddde038588e0..ef4b0f59af492 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -113,6 +115,28 @@ static void __init g4evm_map_io(void) static void __init g4evm_init(void) { + sh7377_pinmux_init(); + + /* Lit DS14 LED */ + gpio_request(GPIO_PORT109, NULL); + gpio_direction_output(GPIO_PORT109, 1); + gpio_export(GPIO_PORT109, 1); + + /* Lit DS15 LED */ + gpio_request(GPIO_PORT110, NULL); + gpio_direction_output(GPIO_PORT110, 1); + gpio_export(GPIO_PORT110, 1); + + /* Lit DS16 LED */ + gpio_request(GPIO_PORT112, NULL); + gpio_direction_output(GPIO_PORT112, 1); + gpio_export(GPIO_PORT112, 1); + + /* Lit DS17 LED */ + gpio_request(GPIO_PORT113, NULL); + gpio_direction_output(GPIO_PORT113, 1); + gpio_export(GPIO_PORT113, 1); + sh7377_add_standard_devices(); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index a4846001e89a1..d6f927b4bef65 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -13,6 +13,7 @@ extern void sh7367_pinmux_init(void); extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); extern void sh7377_add_standard_devices(void); +extern void sh7377_pinmux_init(void); extern void sh7372_init_irq(void); extern void sh7372_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h new file mode 100644 index 0000000000000..f580e227dd1c9 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7377.h @@ -0,0 +1,360 @@ +#ifndef __ASM_SH7377_H__ +#define __ASM_SH7377_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* 55-1 -> 55-5 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU, + GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU, + GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU, + GPIO_FN_PORT72_KEYIN6_PU, + + /* 55-1 (FN) */ + GPIO_FN_VBUS_0, + GPIO_FN_CPORT0, + GPIO_FN_CPORT1, + GPIO_FN_CPORT2, + GPIO_FN_CPORT3, + GPIO_FN_CPORT4, + GPIO_FN_CPORT5, + GPIO_FN_CPORT6, + GPIO_FN_CPORT7, + GPIO_FN_CPORT8, + GPIO_FN_CPORT9, + GPIO_FN_CPORT10, + GPIO_FN_CPORT11, GPIO_FN_SIN2, + GPIO_FN_CPORT12, GPIO_FN_XCTS2, + GPIO_FN_CPORT13, GPIO_FN_RFSPO4, + GPIO_FN_CPORT14, GPIO_FN_RFSPO5, + GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2, + GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3, + GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2, + GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_CPORT19_MPORT1, + GPIO_FN_CPORT20, GPIO_FN_RFSPO6, + GPIO_FN_CPORT21, GPIO_FN_STATUS0, + GPIO_FN_CPORT22, GPIO_FN_STATUS1, + GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7, + GPIO_FN_B_SYNLD1, + GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK, + GPIO_FN_XMAINPS, + GPIO_FN_XDIVPS, + GPIO_FN_XIDRST, + GPIO_FN_IDCLK, GPIO_FN_IC_DP, + GPIO_FN_IDIO, GPIO_FN_IC_DM, + GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT, + GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK, + GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS, + GPIO_FN_PCMCLKO, + GPIO_FN_SYNC8KO, + + /* 55-2 (FN) */ + GPIO_FN_DNPCM_A, + GPIO_FN_UPPCM_A, + GPIO_FN_VACK, + GPIO_FN_XTALB1L, + GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS, + GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD, + GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS, + GPIO_FN_GPS_IM, + GPIO_FN_GPS_IS, + GPIO_FN_GPS_QM, + GPIO_FN_GPS_QS, + GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, + GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3, + GPIO_FN_FMSIOLR, + GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1, + GPIO_FN_FMSIOBT, + GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2, + GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, + GPIO_FN_OPORT3, GPIO_FN_FMSIILR, + GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, + GPIO_FN_FMSIIBT, + GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0, + GPIO_FN_A0_EA0, GPIO_FN_BS, + GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2, + GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2, + GPIO_FN_TPU0TO1, + GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5, + GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4, + GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6, + GPIO_FN_D0_ED0_NAF0, + GPIO_FN_D1_ED1_NAF1, + GPIO_FN_D2_ED2_NAF2, + GPIO_FN_D3_ED3_NAF3, + GPIO_FN_D4_ED4_NAF4, + GPIO_FN_D5_ED5_NAF5, + GPIO_FN_D6_ED6_NAF6, + GPIO_FN_D7_ED7_NAF7, + GPIO_FN_D8_ED8_NAF8, + GPIO_FN_D9_ED9_NAF9, + GPIO_FN_D10_ED10_NAF10, + GPIO_FN_D11_ED11_NAF11, + GPIO_FN_D12_ED12_NAF12, + GPIO_FN_D13_ED13_NAF13, + GPIO_FN_D14_ED14_NAF14, + GPIO_FN_D15_ED15_NAF15, + GPIO_FN_CS4, + GPIO_FN_CS5A, GPIO_FN_FMSICK, + GPIO_FN_CS5B, GPIO_FN_FCE1, + + /* 55-3 (FN) */ + GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0, + GPIO_FN_FCE0, + GPIO_FN_WAIT, GPIO_FN_DREQ0, + GPIO_FN_RD_XRD, + GPIO_FN_WE0_XWR0_FWE, + GPIO_FN_WE1_XWR1, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT, + GPIO_FN_NBRST, + GPIO_FN_GPS_EPPSIN, + GPIO_FN_LATCHPULSE, + GPIO_FN_LTESIGNAL, + GPIO_FN_LEGACYSTATE, + GPIO_FN_TCKON, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0, + GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2, + GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC, + GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD, + GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3, + GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC, + GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR, + GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2, + GPIO_FN_PORT140_FSIAOBT, + GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3, + GPIO_FN_PORT141_FSIAOSLD, + GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK, + GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR, + GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD, + GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2, + GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5, + GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6, + GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD, + + /* 55-4 (FN) */ + GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0, + GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0, + GPIO_FN_MFG3_IN2, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0, + GPIO_FN_MFG3_IN1, + GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0, + GPIO_FN_MFG3_OUT1, + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI, + GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS, + GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS, + GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD, + GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK, + GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, GPIO_FN_XWR2, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3, + GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16, + GPIO_FN_ED16, + GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17, + GPIO_FN_ED17, + GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18, + GPIO_FN_ED18, + GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19, + GPIO_FN_ED19, + GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20, + GPIO_FN_ED20, + GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21, + GPIO_FN_ED21, + GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22, + GPIO_FN_ED22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0, + GPIO_FN_VIO_DR7, + GPIO_FN_D23, GPIO_FN_ED23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1, + GPIO_FN_VIO_VDR, + GPIO_FN_D24, GPIO_FN_ED24, + GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25, + GPIO_FN_ED25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_ED26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_ED28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_ED29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_ED30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_ED31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3, + GPIO_FN_VIO_CLKR, + GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3, + GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, + GPIO_FN_MSIOF0L_TXD, + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM, + GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG, + GPIO_FN_PORT233_FSIACK, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2, + GPIO_FN_PORT235_FSIAILR, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD, + GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3, + + /* 55-5 (FN) */ + GPIO_FN_MSIOF1_SS2, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS, + GPIO_FN_PORT244_MSIOF2_RXD, + GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS, + GPIO_FN_PORT245_MSIOF2_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, + GPIO_FN_PORT248_MSIOF2_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC, + GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0, + GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0, + GPIO_FN_SDHID0_2, GPIO_FN_TDI2, + GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0, + GPIO_FN_SDHICMD0, GPIO_FN_TRST2, + GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2, + GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1, + GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2, + GPIO_FN_TMS3_SWDIO_MC1, + GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2, + GPIO_FN_TDO3_SWO0_MC1, + GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3, + GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2, + GPIO_FN_RTCK3_SWO1_MC1, + GPIO_FN_SDHICMD1, GPIO_FN_TRST3, + GPIO_FN_RESETOUTS, +}; + +#endif /* __ASM_SH7377_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c new file mode 100644 index 0000000000000..79b53d87d91ba --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7377.c @@ -0,0 +1,1766 @@ +/* + * sh7377 processor support - PFC hardware block + * + * Copyright (C) 2010 NISHIMOTO Hiroki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _90(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \ + _10(fn, pfx##9, sfx) + +#define _265(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _90(fn, pfx, sfx), \ + _10(fn, pfx##10, sfx), \ + _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ + _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ + _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ + _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ + _1(fn, pfx##118, sfx), \ + _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ + _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ + _10(fn, pfx##15, sfx), \ + _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ + _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ + _1(fn, pfx##164, sfx), \ + _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ + _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ + _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ + _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \ + _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ + _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ + _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ + _1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \ + _1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \ + _1(fn, pfx##264, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_265(str) _265(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_265(IN), /* PORT0_IN -> PORT264_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */ + PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */ + PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */ + PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */ + PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */ + PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */ + PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */ + PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */ + PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */ + PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */ + + MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Special Pull-up / Pull-down Functions */ + PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK, + PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK, + PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK, + PORT72_KEYIN6_PU_MARK, + + /* 55-1 */ + VBUS_0_MARK, + CPORT0_MARK, + CPORT1_MARK, + CPORT2_MARK, + CPORT3_MARK, + CPORT4_MARK, + CPORT5_MARK, + CPORT6_MARK, + CPORT7_MARK, + CPORT8_MARK, + CPORT9_MARK, + CPORT10_MARK, + CPORT11_MARK, SIN2_MARK, + CPORT12_MARK, XCTS2_MARK, + CPORT13_MARK, RFSPO4_MARK, + CPORT14_MARK, RFSPO5_MARK, + CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK, + CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK, + CPORT17_IC_OE_MARK, SOUT2_MARK, + CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK, + CPORT19_MPORT1_MARK, + CPORT20_MARK, RFSPO6_MARK, + CPORT21_MARK, STATUS0_MARK, + CPORT22_MARK, STATUS1_MARK, + CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK, + B_SYNLD1_MARK, + B_SYNLD2_MARK, SYSENMSK_MARK, + XMAINPS_MARK, + XDIVPS_MARK, + XIDRST_MARK, + IDCLK_MARK, IC_DP_MARK, + IDIO_MARK, IC_DM_MARK, + SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK, + SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK, + XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK, + XCTS1_MARK, SCIFA4_CTS_MARK, + PCMCLKO_MARK, + SYNC8KO_MARK, + + /* 55-2 */ + DNPCM_A_MARK, + UPPCM_A_MARK, + VACK_MARK, + XTALB1L_MARK, + GPS_AGC1_MARK, SCIFA0_RTS_MARK, + GPS_AGC4_MARK, SCIFA0_RXD_MARK, + GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK, + GPS_IM_MARK, + GPS_IS_MARK, + GPS_QM_MARK, + GPS_QS_MARK, + FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, + FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK, + FMSIOLR_MARK, + FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK, + FMSIOBT_MARK, + FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK, + FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK, + FMSIILR_MARK, + FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK, + FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK, + A0_EA0_MARK, BS_MARK, + A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK, + A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK, + A14_EA14_MARK, PORT60_KEYOUT5_MARK, + A15_EA15_MARK, PORT61_KEYOUT4_MARK, + A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK, + A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK, + A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK, + A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK, + A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK, + A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK, + A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK, + A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK, + A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK, + A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK, + A26_MARK, PORT72_KEYIN6_MARK, + D0_ED0_NAF0_MARK, + D1_ED1_NAF1_MARK, + D2_ED2_NAF2_MARK, + D3_ED3_NAF3_MARK, + D4_ED4_NAF4_MARK, + D5_ED5_NAF5_MARK, + D6_ED6_NAF6_MARK, + D7_ED7_NAF7_MARK, + D8_ED8_NAF8_MARK, + D9_ED9_NAF9_MARK, + D10_ED10_NAF10_MARK, + D11_ED11_NAF11_MARK, + D12_ED12_NAF12_MARK, + D13_ED13_NAF13_MARK, + D14_ED14_NAF14_MARK, + D15_ED15_NAF15_MARK, + CS4_MARK, + CS5A_MARK, FMSICK_MARK, + CS5B_MARK, FCE1_MARK, + + /* 55-3 */ + CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK, + FCE0_MARK, + WAIT_MARK, DREQ0_MARK, + RD_XRD_MARK, + WE0_XWR0_FWE_MARK, + WE1_XWR1_MARK, + FRB_MARK, + CKO_MARK, + NBRSTOUT_MARK, + NBRST_MARK, + GPS_EPPSIN_MARK, + LATCHPULSE_MARK, + LTESIGNAL_MARK, + LEGACYSTATE_MARK, + TCKON_MARK, + VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK, + VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK, + VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK, + VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK, + VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK, + VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK, + VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK, + VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK, + VIO_D6_MARK, PORT136_KEYIN2_MARK, + VIO_D7_MARK, PORT137_KEYIN3_MARK, + VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK, + VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK, + VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK, + VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK, + VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK, + VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK, + VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK, + VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK, + VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK, + VIO_FIELD_MARK, PORT147_KEYIN5_MARK, + VIO_CKO_MARK, PORT148_KEYIN6_MARK, + A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK, + MFG0_IN2_MARK, + TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, + TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, + SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, + SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, + XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK, + XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK, + + /* 55-4 */ + DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, + PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK, + PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK, + MFG3_IN2_MARK, + PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK, + MFG3_IN1_MARK, + PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK, + MFG3_OUT1_MARK, TPU3TO0_MARK, + LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK, + LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK, + BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK, + BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK, + BBIF2_TXD1_MARK, + LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK, + LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK, + MFG2_OUT2_MARK, + TPU2TO1_MARK, + LCDD6_MARK, XWR2_MARK, + LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK, + LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK, + LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK, + LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK, + LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK, + LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK, + LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK, + LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK, + LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK, + VIO_DR7_MARK, D23_MARK, ED23_MARK, + LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK, + VIO_VDR_MARK, D24_MARK, ED24_MARK, + LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK, + LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK, + LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK, + LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK, + LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK, + LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK, + PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK, + LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK, + LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK, + LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, + SCIFA1_TXD_MARK, OVCN2_MARK, + EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK, + SCIFA1_RTS_MARK, IDIN_MARK, + SCIFA1_RXD_MARK, + SCIFA1_CTS_MARK, MFG1_IN1_MARK, + MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK, + MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK, + MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK, + MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK, + PORT233_FSIACK_MARK, + MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK, + MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK, + MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK, + MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK, + MSIOF1_SS1_MARK, EDBGREQ3_MARK, + + /* 55-5 */ + MSIOF1_SS2_MARK, + SCIFA6_TXD_MARK, + PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, + TPU4TO0_MARK, + PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, + PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, + PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK, + PORT244_MSIOF2_RXD_MARK, + PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK, + PORT245_MSIOF2_TXD_MARK, + PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, + TPU1TO0_MARK, + PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, + TPU3TO1_MARK, + PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, + TPU2TO0_MARK, + PORT248_MSIOF2_TSCK_MARK, + PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK, + SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK, + SDHID0_1_MARK, TDO2_SWO0_MC0_MARK, + SDHID0_2_MARK, TDI2_MARK, + SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK, + SDHICMD0_MARK, TRST2_MARK, + SDHIWP0_MARK, EDBGREQ2_MARK, + SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK, + SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK, + TMS3_SWDIO_MC1_MARK, + SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK, + SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK, + SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK, + SDHICMD1_MARK, TRST3_MARK, + RESETOUTS_MARK, + PINMUX_MARK_END, +}; + +#define PORT_DATA_I(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) + +#define PORT_DATA_I_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_I_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_I_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_O(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT) + +#define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN) + +#define PORT_DATA_IO_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD) + +#define PORT_DATA_IO_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_IO_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +static pinmux_enum_t pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + /* 55-1 (GPIO) */ + PORT_DATA_I_PD(0), PORT_DATA_I_PU(1), + PORT_DATA_I_PU(2), PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), + PORT_DATA_I_PU(6), PORT_DATA_I_PU(7), + PORT_DATA_I_PU(8), PORT_DATA_I_PU(9), + PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), + PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13), + PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), + PORT_DATA_O(16), PORT_DATA_IO(17), + PORT_DATA_O(18), PORT_DATA_O(19), + PORT_DATA_O(20), PORT_DATA_O(21), + PORT_DATA_O(22), PORT_DATA_O(23), + PORT_DATA_O(24), PORT_DATA_I_PD(25), + PORT_DATA_I_PD(26), PORT_DATA_O(27), + PORT_DATA_O(28), PORT_DATA_O(29), + PORT_DATA_IO(30), PORT_DATA_IO_PU(31), + PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33), + PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35), + PORT_DATA_O(36), PORT_DATA_IO(37), + + /* 55-2 (GPIO) */ + PORT_DATA_O(38), PORT_DATA_I_PU(39), + PORT_DATA_I_PU_PD(40), PORT_DATA_O(41), + PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43), + PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45), + PORT_DATA_I_PD(46), PORT_DATA_I_PD(47), + PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49), + PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51), + PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53), + PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55), + PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57), + PORT_DATA_IO(58), PORT_DATA_IO(59), + PORT_DATA_IO(60), PORT_DATA_IO(61), + PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), + PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), + PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73), + PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75), + PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77), + PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79), + PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81), + PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83), + PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85), + PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87), + PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89), + PORT_DATA_O(90), PORT_DATA_IO_PU(91), + PORT_DATA_O(92), + + /* 55-3 (GPIO) */ + PORT_DATA_IO_PU(93), + PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO(96), PORT_DATA_IO(97), + PORT_DATA_IO(98), PORT_DATA_I_PU(99), + PORT_DATA_O(100), PORT_DATA_O(101), + PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103), + PORT_DATA_I_PD(104), PORT_DATA_I_PD(105), + PORT_DATA_I_PD(106), PORT_DATA_I_PD(107), + PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109), + PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111), + PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), + PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115), + PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117), + PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128), + PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130), + PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132), + PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134), + PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136), + PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138), + PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140), + PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142), + PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144), + PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146), + PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148), + PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150), + PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152), + PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), + PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156), + PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158), + + /* 55-4 (GPIO) */ + PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160), + PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162), + PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164), + PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193), + PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), + PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199), + PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207), + PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209), + PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), + PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215), + PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217), + PORT_DATA_O(218), PORT_DATA_IO_PD(219), + PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221), + PORT_DATA_IO_PU_PD(222), + PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224), + PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226), + PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228), + PORT_DATA_I_PD(229), PORT_DATA_IO(230), + PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232), + PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234), + PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236), + PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238), + + /* 55-5 (GPIO) */ + PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240), + PORT_DATA_O(241), PORT_DATA_I_PD(242), + PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244), + PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246), + PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248), + PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250), + PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252), + PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254), + PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256), + PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258), + PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260), + PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262), + PORT_DATA_IO_PU_PD(263), + + /* Special Pull-up / Pull-down Functions */ + PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, + PORT66_FN2, PORT66_IN_PU), + PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, + PORT67_FN2, PORT67_IN_PU), + PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, + PORT68_FN2, PORT68_IN_PU), + PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, + PORT69_FN2, PORT69_IN_PU), + PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, + PORT70_FN2, PORT70_IN_PU), + PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, + PORT71_FN2, PORT71_IN_PU), + PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, + PORT72_FN2, PORT72_IN_PU), + + + /* 55-1 (FN) */ + PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), + PINMUX_DATA(CPORT0_MARK, PORT1_FN1), + PINMUX_DATA(CPORT1_MARK, PORT2_FN1), + PINMUX_DATA(CPORT2_MARK, PORT3_FN1), + PINMUX_DATA(CPORT3_MARK, PORT4_FN1), + PINMUX_DATA(CPORT4_MARK, PORT5_FN1), + PINMUX_DATA(CPORT5_MARK, PORT6_FN1), + PINMUX_DATA(CPORT6_MARK, PORT7_FN1), + PINMUX_DATA(CPORT7_MARK, PORT8_FN1), + PINMUX_DATA(CPORT8_MARK, PORT9_FN1), + PINMUX_DATA(CPORT9_MARK, PORT10_FN1), + PINMUX_DATA(CPORT10_MARK, PORT11_FN1), + PINMUX_DATA(CPORT11_MARK, PORT12_FN1), + PINMUX_DATA(SIN2_MARK, PORT12_FN2), + PINMUX_DATA(CPORT12_MARK, PORT13_FN1), + PINMUX_DATA(XCTS2_MARK, PORT13_FN2), + PINMUX_DATA(CPORT13_MARK, PORT14_FN1), + PINMUX_DATA(RFSPO4_MARK, PORT14_FN2), + PINMUX_DATA(CPORT14_MARK, PORT15_FN1), + PINMUX_DATA(RFSPO5_MARK, PORT15_FN2), + PINMUX_DATA(CPORT15_MARK, PORT16_FN1), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), + PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3), + PINMUX_DATA(CPORT16_MARK, PORT17_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), + PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3), + PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1), + PINMUX_DATA(SOUT2_MARK, PORT18_FN2), + PINMUX_DATA(CPORT18_MARK, PORT19_FN1), + PINMUX_DATA(XRTS2_MARK, PORT19_FN2), + PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), + PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1), + PINMUX_DATA(CPORT20_MARK, PORT21_FN1), + PINMUX_DATA(RFSPO6_MARK, PORT21_FN2), + PINMUX_DATA(CPORT21_MARK, PORT22_FN1), + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(CPORT22_MARK, PORT23_FN1), + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(CPORT23_MARK, PORT24_FN1), + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(RFSPO7_MARK, PORT24_FN3), + PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1), + PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1), + PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2), + PINMUX_DATA(XMAINPS_MARK, PORT27_FN1), + PINMUX_DATA(XDIVPS_MARK, PORT28_FN1), + PINMUX_DATA(XIDRST_MARK, PORT29_FN1), + PINMUX_DATA(IDCLK_MARK, PORT30_FN1), + PINMUX_DATA(IC_DP_MARK, PORT30_FN2), + PINMUX_DATA(IDIO_MARK, PORT31_FN1), + PINMUX_DATA(IC_DM_MARK, PORT31_FN2), + PINMUX_DATA(SOUT1_MARK, PORT32_FN1), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), + PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3), + PINMUX_DATA(SIN1_MARK, PORT33_FN1), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), + PINMUX_DATA(XWUP_MARK, PORT33_FN3), + PINMUX_DATA(XRTS1_MARK, PORT34_FN1), + PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2), + PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3), + PINMUX_DATA(XCTS1_MARK, PORT35_FN1), + PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2), + PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1), + PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1), + + /* 55-2 (FN) */ + PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1), + PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1), + PINMUX_DATA(VACK_MARK, PORT40_FN1), + PINMUX_DATA(XTALB1L_MARK, PORT41_FN1), + PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2), + PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), + PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2), + PINMUX_DATA(GPS_IM_MARK, PORT45_FN1), + PINMUX_DATA(GPS_IS_MARK, PORT46_FN1), + PINMUX_DATA(GPS_QM_MARK, PORT47_FN1), + PINMUX_DATA(GPS_QS_MARK, PORT48_FN1), + PINMUX_DATA(FMSOCK_MARK, PORT49_FN1), + PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2), + PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3), + PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1), + PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), + PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), + PINMUX_DATA(IPORT3_MARK, PORT50_FN4), + PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5), + PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1), + PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), + PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), + PINMUX_DATA(OPORT1_MARK, PORT51_FN4), + PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5), + PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1), + PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), + PINMUX_DATA(OPORT2_MARK, PORT52_FN3), + PINMUX_DATA(FMSOILR_MARK, PORT53_FN1), + PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2), + PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), + PINMUX_DATA(OPORT3_MARK, PORT53_FN4), + PINMUX_DATA(FMSIILR_MARK, PORT53_FN5), + PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1), + PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2), + PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), + PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4), + PINMUX_DATA(FMSISLD_MARK, PORT55_FN1), + PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2), + PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), + PINMUX_DATA(A0_EA0_MARK, PORT57_FN1), + PINMUX_DATA(BS_MARK, PORT57_FN2), + PINMUX_DATA(A12_EA12_MARK, PORT58_FN1), + PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2), + PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3), + PINMUX_DATA(A13_EA13_MARK, PORT59_FN1), + PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2), + PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3), + PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), + PINMUX_DATA(A14_EA14_MARK, PORT60_FN1), + PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2), + PINMUX_DATA(A15_EA15_MARK, PORT61_FN1), + PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2), + PINMUX_DATA(A16_EA16_MARK, PORT62_FN1), + PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3), + PINMUX_DATA(A17_EA17_MARK, PORT63_FN1), + PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3), + PINMUX_DATA(A18_EA18_MARK, PORT64_FN1), + PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3), + PINMUX_DATA(A19_EA19_MARK, PORT65_FN1), + PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3), + PINMUX_DATA(A20_EA20_MARK, PORT66_FN1), + PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3), + PINMUX_DATA(A21_EA21_MARK, PORT67_FN1), + PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3), + PINMUX_DATA(A22_EA22_MARK, PORT68_FN1), + PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3), + PINMUX_DATA(A23_EA23_MARK, PORT69_FN1), + PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3), + PINMUX_DATA(A24_EA24_MARK, PORT70_FN1), + PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3), + PINMUX_DATA(A25_EA25_MARK, PORT71_FN1), + PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3), + PINMUX_DATA(A26_MARK, PORT72_FN1), + PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2), + PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1), + PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1), + PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1), + PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1), + PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1), + PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1), + PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1), + PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1), + PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1), + PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1), + PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1), + PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1), + PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1), + PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1), + PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1), + PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1), + PINMUX_DATA(CS4_MARK, PORT90_FN1), + PINMUX_DATA(CS5A_MARK, PORT91_FN1), + PINMUX_DATA(FMSICK_MARK, PORT91_FN2), + PINMUX_DATA(CS5B_MARK, PORT92_FN1), + PINMUX_DATA(FCE1_MARK, PORT92_FN2), + + /* 55-3 (FN) */ + PINMUX_DATA(CS6B_MARK, PORT93_FN1), + PINMUX_DATA(XCS2_MARK, PORT93_FN2), + PINMUX_DATA(CS6A_MARK, PORT93_FN3), + PINMUX_DATA(DACK0_MARK, PORT93_FN4), + PINMUX_DATA(FCE0_MARK, PORT94_FN1), + PINMUX_DATA(WAIT_MARK, PORT95_FN1), + PINMUX_DATA(DREQ0_MARK, PORT95_FN2), + PINMUX_DATA(RD_XRD_MARK, PORT96_FN1), + PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1), + PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1), + PINMUX_DATA(FRB_MARK, PORT99_FN1), + PINMUX_DATA(CKO_MARK, PORT100_FN1), + PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1), + PINMUX_DATA(NBRST_MARK, PORT102_FN1), + PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1), + PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1), + PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1), + PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1), + PINMUX_DATA(TCKON_MARK, PORT118_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), + PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2), + PINMUX_DATA(IPORT0_MARK, PORT128_FN3), + PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), + PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2), + PINMUX_DATA(IPORT1_MARK, PORT129_FN3), + PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), + PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2), + PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3), + PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), + PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2), + PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), + PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), + PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2), + PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), + PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), + PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2), + PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3), + PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), + PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2), + PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3), + PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), + PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2), + PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3), + PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), + PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2), + PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), + PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2), + PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), + PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2), + PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3), + PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), + PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2), + PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3), + PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), + PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2), + PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3), + PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4), + PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), + PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2), + PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3), + PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4), + PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), + PINMUX_DATA(M13_BSW_MARK, PORT142_FN2), + PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3), + PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), + PINMUX_DATA(M14_GSW_MARK, PORT143_FN2), + PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3), + PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), + PINMUX_DATA(M15_RSW_MARK, PORT144_FN2), + PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3), + PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), + PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2), + PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3), + PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), + PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2), + PINMUX_DATA(IPORT2_MARK, PORT146_FN3), + PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), + PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2), + PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), + PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2), + PINMUX_DATA(A27_MARK, PORT149_FN1), + PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2), + PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), + PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2), + PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2), + PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1), + PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2), + PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3), + PINMUX_DATA(SOUT3_MARK, PORT154_FN1), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3), + PINMUX_DATA(SIN3_MARK, PORT155_FN1), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3), + PINMUX_DATA(XRTS3_MARK, PORT156_FN1), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2), + PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3), + PINMUX_DATA(XCTS3_MARK, PORT157_FN1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2), + PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3), + + /* 55-4 (FN) */ + PINMUX_DATA(DINT_MARK, PORT158_FN1), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2), + PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3), + PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1), + PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2), + PINMUX_DATA(NMI_MARK, PORT159_FN3), + PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1), + PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2), + PINMUX_DATA(SOUT0_MARK, PORT160_FN3), + PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1), + PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2), + PINMUX_DATA(XCTS0_MARK, PORT161_FN3), + PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4), + PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1), + PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2), + PINMUX_DATA(SIN0_MARK, PORT162_FN3), + PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4), + PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1), + PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2), + PINMUX_DATA(XRTS0_MARK, PORT163_FN3), + PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4), + PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), + PINMUX_DATA(LCDD0_MARK, PORT192_FN1), + PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2), + PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3), + PINMUX_DATA(LCDD1_MARK, PORT193_FN1), + PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2), + PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4), + PINMUX_DATA(LCDD2_MARK, PORT194_FN1), + PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2), + PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3), + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4), + PINMUX_DATA(LCDD3_MARK, PORT195_FN1), + PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2), + PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4), + PINMUX_DATA(LCDD4_MARK, PORT196_FN1), + PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2), + PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3), + PINMUX_DATA(LCDD5_MARK, PORT197_FN1), + PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2), + PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3), + PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4), + PINMUX_DATA(LCDD6_MARK, PORT198_FN1), + PINMUX_DATA(LCDD7_MARK, PORT199_FN1), + PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), + PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3), + PINMUX_DATA(LCDD8_MARK, PORT200_FN1), + PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2), + PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3), + PINMUX_DATA(D16_MARK, PORT200_FN4), + PINMUX_DATA(LCDD9_MARK, PORT201_FN1), + PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2), + PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3), + PINMUX_DATA(D17_MARK, PORT201_FN4), + PINMUX_DATA(LCDD10_MARK, PORT202_FN1), + PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2), + PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3), + PINMUX_DATA(D18_MARK, PORT202_FN4), + PINMUX_DATA(LCDD11_MARK, PORT203_FN1), + PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2), + PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3), + PINMUX_DATA(D19_MARK, PORT203_FN4), + PINMUX_DATA(LCDD12_MARK, PORT204_FN1), + PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2), + PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3), + PINMUX_DATA(D20_MARK, PORT204_FN4), + PINMUX_DATA(LCDD13_MARK, PORT205_FN1), + PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2), + PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3), + PINMUX_DATA(D21_MARK, PORT205_FN4), + PINMUX_DATA(LCDD14_MARK, PORT206_FN1), + PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2), + PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3), + PINMUX_DATA(D22_MARK, PORT206_FN4), + PINMUX_DATA(LCDD15_MARK, PORT207_FN1), + PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2), + PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3), + PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4), + PINMUX_DATA(D23_MARK, PORT207_FN5), + PINMUX_DATA(LCDD16_MARK, PORT208_FN1), + PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2), + PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3), + PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4), + PINMUX_DATA(D24_MARK, PORT208_FN5), + PINMUX_DATA(LCDD17_MARK, PORT209_FN1), + PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2), + PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3), + PINMUX_DATA(D25_MARK, PORT209_FN4), + PINMUX_DATA(LCDD18_MARK, PORT210_FN1), + PINMUX_DATA(DREQ2_MARK, PORT210_FN2), + PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3), + PINMUX_DATA(D26_MARK, PORT210_FN4), + PINMUX_DATA(LCDD19_MARK, PORT211_FN1), + PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2), + PINMUX_DATA(D27_MARK, PORT211_FN3), + PINMUX_DATA(LCDD20_MARK, PORT212_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3), + PINMUX_DATA(D28_MARK, PORT212_FN4), + PINMUX_DATA(LCDD21_MARK, PORT213_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3), + PINMUX_DATA(D29_MARK, PORT213_FN4), + PINMUX_DATA(LCDD22_MARK, PORT214_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3), + PINMUX_DATA(D30_MARK, PORT214_FN4), + PINMUX_DATA(LCDD23_MARK, PORT215_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3), + PINMUX_DATA(D31_MARK, PORT215_FN4), + PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), + PINMUX_DATA(LCDWR_MARK, PORT216_FN2), + PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3), + PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4), + PINMUX_DATA(LCDRD_MARK, PORT217_FN1), + PINMUX_DATA(DACK2_MARK, PORT217_FN2), + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3), + PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), + PINMUX_DATA(LCDCS_MARK, PORT218_FN2), + PINMUX_DATA(LCDCS2_MARK, PORT218_FN3), + PINMUX_DATA(DACK3_MARK, PORT218_FN4), + PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), + PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6), + PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), + PINMUX_DATA(LCDRS_MARK, PORT219_FN2), + PINMUX_DATA(DREQ3_MARK, PORT219_FN3), + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4), + PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), + PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), + PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3), + PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), + PINMUX_DATA(DREQ1_MARK, PORT221_FN2), + PINMUX_DATA(PWEN_MARK, PORT221_FN3), + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4), + PINMUX_DATA(LCDDON_MARK, PORT222_FN1), + PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), + PINMUX_DATA(DACK1_MARK, PORT222_FN3), + PINMUX_DATA(OVCN_MARK, PORT222_FN4), + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1), + PINMUX_DATA(OVCN2_MARK, PORT225_FN2), + PINMUX_DATA(EXTLP_MARK, PORT226_FN1), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), + PINMUX_DATA(USBTERM_MARK, PORT226_FN3), + PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1), + PINMUX_DATA(IDIN_MARK, PORT227_FN2), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1), + PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), + PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2), + PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), + PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2), + PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), + PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2), + PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), + PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2), + PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3), + PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), + PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2), + PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), + PINMUX_DATA(OPORT0_MARK, PORT235_FN2), + PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), + PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), + PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2), + PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), + PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2), + PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), + PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2), + + /* 55-5 (FN) */ + PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), + PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1), + PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), + PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), + PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), + PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1), + PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2), + PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1), + PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), + PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1), + PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), + PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3), + PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1), + PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), + PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3), + PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1), + PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), + PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3), + PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), + PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1), + PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), + PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3), + PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), + PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1), + PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), + PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3), + PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), + PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), + PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), + PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), + PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2), + PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), + PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2), + PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), + PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2), + PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), + PINMUX_DATA(TDI2_MARK, PORT254_FN2), + PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), + PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2), + PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), + PINMUX_DATA(TRST2_MARK, PORT256_FN2), + PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), + PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2), + PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), + PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2), + PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), + PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), + PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4), + PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), + PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2), + PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), + PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4), + PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), + PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2), + PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), + PINMUX_DATA(TDI3_MARK, PORT261_FN4), + PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), + PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2), + PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), + PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4), + PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), + PINMUX_DATA(TRST3_MARK, PORT263_FN2), + PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_265() _265(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + /* 55-1 -> 55-5 (GPIO) */ + GPIO_PORT_265(), + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU), + GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU), + GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU), + GPIO_FN(PORT72_KEYIN6_PU), + + /* 55-1 (FN) */ + GPIO_FN(VBUS_0), + GPIO_FN(CPORT0), + GPIO_FN(CPORT1), + GPIO_FN(CPORT2), + GPIO_FN(CPORT3), + GPIO_FN(CPORT4), + GPIO_FN(CPORT5), + GPIO_FN(CPORT6), + GPIO_FN(CPORT7), + GPIO_FN(CPORT8), + GPIO_FN(CPORT9), + GPIO_FN(CPORT10), + GPIO_FN(CPORT11), GPIO_FN(SIN2), + GPIO_FN(CPORT12), GPIO_FN(XCTS2), + GPIO_FN(CPORT13), GPIO_FN(RFSPO4), + GPIO_FN(CPORT14), GPIO_FN(RFSPO5), + GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2), + GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3), + GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2), + GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2), + GPIO_FN(CPORT19_MPORT1), + GPIO_FN(CPORT20), GPIO_FN(RFSPO6), + GPIO_FN(CPORT21), GPIO_FN(STATUS0), + GPIO_FN(CPORT22), GPIO_FN(STATUS1), + GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7), + GPIO_FN(B_SYNLD1), + GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK), + GPIO_FN(XMAINPS), + GPIO_FN(XDIVPS), + GPIO_FN(XIDRST), + GPIO_FN(IDCLK), GPIO_FN(IC_DP), + GPIO_FN(IDIO), GPIO_FN(IC_DM), + GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT), + GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP), + GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK), + GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS), + GPIO_FN(PCMCLKO), + GPIO_FN(SYNC8KO), + + /* 55-2 (FN) */ + GPIO_FN(DNPCM_A), + GPIO_FN(UPPCM_A), + GPIO_FN(VACK), + GPIO_FN(XTALB1L), + GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS), + GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD), + GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS), + GPIO_FN(GPS_IM), + GPIO_FN(GPS_IS), + GPIO_FN(GPS_QM), + GPIO_FN(GPS_QS), + GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT), + GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2), + GPIO_FN(IPORT3), GPIO_FN(FMSIOLR), + GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3), + GPIO_FN(OPORT1), GPIO_FN(FMSIOBT), + GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2), + GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3), + GPIO_FN(OPORT3), GPIO_FN(FMSIILR), + GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2), + GPIO_FN(FMSIIBT), + GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0), + GPIO_FN(A0_EA0), GPIO_FN(BS), + GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2), + GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2), + GPIO_FN(TPU0TO1), + GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5), + GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4), + GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6), + GPIO_FN(D0_ED0_NAF0), + GPIO_FN(D1_ED1_NAF1), + GPIO_FN(D2_ED2_NAF2), + GPIO_FN(D3_ED3_NAF3), + GPIO_FN(D4_ED4_NAF4), + GPIO_FN(D5_ED5_NAF5), + GPIO_FN(D6_ED6_NAF6), + GPIO_FN(D7_ED7_NAF7), + GPIO_FN(D8_ED8_NAF8), + GPIO_FN(D9_ED9_NAF9), + GPIO_FN(D10_ED10_NAF10), + GPIO_FN(D11_ED11_NAF11), + GPIO_FN(D12_ED12_NAF12), + GPIO_FN(D13_ED13_NAF13), + GPIO_FN(D14_ED14_NAF14), + GPIO_FN(D15_ED15_NAF15), + GPIO_FN(CS4), + GPIO_FN(CS5A), GPIO_FN(FMSICK), + + /* 55-3 (FN) */ + GPIO_FN(CS5B), GPIO_FN(FCE1), + GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0), + GPIO_FN(FCE0), + GPIO_FN(WAIT), GPIO_FN(DREQ0), + GPIO_FN(RD_XRD), + GPIO_FN(WE0_XWR0_FWE), + GPIO_FN(WE1_XWR1), + GPIO_FN(FRB), + GPIO_FN(CKO), + GPIO_FN(NBRSTOUT), + GPIO_FN(NBRST), + GPIO_FN(GPS_EPPSIN), + GPIO_FN(LATCHPULSE), + GPIO_FN(LTESIGNAL), + GPIO_FN(LEGACYSTATE), + GPIO_FN(TCKON), + GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0), + GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1), + GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD), + GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1), + GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2), + GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5), + GPIO_FN(PORT133_MSIOF2_TSYNC), + GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD), + GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK), + GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2), + GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3), + GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC), + GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR), + GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2), + GPIO_FN(PORT140_FSIAOBT), + GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3), + GPIO_FN(PORT141_FSIAOSLD), + GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK), + GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR), + GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT), + GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD), + GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2), + GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5), + GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6), + GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1), + GPIO_FN(MFG0_IN2), + GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK), + GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1), + GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1), + GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2), + GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD), + + /* 55-4 (FN) */ + GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3), + GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI), + GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0), + GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0), + GPIO_FN(MFG3_IN2), + GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0), + GPIO_FN(MFG3_IN1), + GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0), + GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0), + GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI), + GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS), + GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS), + GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD), + GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD), + GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK), + GPIO_FN(MFG2_OUT2), + GPIO_FN(LCDD6), + GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2), + GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0), + GPIO_FN(D16), + GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1), + GPIO_FN(D17), + GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2), + GPIO_FN(D18), + GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3), + GPIO_FN(D19), + GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4), + GPIO_FN(D20), + GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5), + GPIO_FN(D21), + GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6), + GPIO_FN(D22), + GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0), + GPIO_FN(VIO_DR7), GPIO_FN(D23), + GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1), + GPIO_FN(VIO_VDR), GPIO_FN(D24), + GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR), + GPIO_FN(D25), + GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1), + GPIO_FN(D26), + GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27), + GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0), + GPIO_FN(D28), + GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1), + GPIO_FN(D29), + GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK), + GPIO_FN(D30), + GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC), + GPIO_FN(D31), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3), + GPIO_FN(VIO_CLKR), + GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC), + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3), + GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK), + GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5), + GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD), + GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN), + GPIO_FN(MSIOF0L_TXD), + GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2), + GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM), + GPIO_FN(PORT226_VIO_CKO2), + GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN), + GPIO_FN(SCIFA1_RXD), + GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1), + GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC), + GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR), + GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT), + GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG), + GPIO_FN(PORT233_FSIACK), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD), + GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2), + GPIO_FN(PORT235_FSIAILR), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT), + GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD), + GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3), + + /* 55-5 (FN) */ + GPIO_FN(MSIOF1_SS2), + GPIO_FN(SCIFA6_TXD), + GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1), + GPIO_FN(TPU4TO0), + GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2), + GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2), + GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1), + GPIO_FN(PORT244_SCIFB_CTS), + GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2), + GPIO_FN(PORT245_SCIFB_RTS), + GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1), + GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0), + GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2), + GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1), + GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1), + GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0), + GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1), + GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0), + GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0), + GPIO_FN(SDHID0_2), GPIO_FN(TDI2), + GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0), + GPIO_FN(SDHICMD0), GPIO_FN(TRST2), + GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2), + GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1), + GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2), + GPIO_FN(TMS3_SWDIO_MC1), + GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2), + GPIO_FN(TDO3_SWO0_MC1), + GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2), + GPIO_FN(TDI3), + GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2), + GPIO_FN(RTCK3_SWO1_MC1), + GPIO_FN(SDHICMD1), GPIO_FN(TRST3), + GPIO_FN(RESETOUTS), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + PORTCR(84, 0xe6050054), /* PORT84CR */ + PORTCR(85, 0xe6050055), /* PORT85CR */ + PORTCR(86, 0xe6050056), /* PORT86CR */ + PORTCR(87, 0xe6050057), /* PORT87CR */ + PORTCR(88, 0xe6050058), /* PORT88CR */ + PORTCR(89, 0xe6050059), /* PORT89CR */ + + PORTCR(90, 0xe605005a), /* PORT90CR */ + PORTCR(91, 0xe605005b), /* PORT91CR */ + PORTCR(92, 0xe605005c), /* PORT92CR */ + PORTCR(93, 0xe605005d), /* PORT93CR */ + PORTCR(94, 0xe605005e), /* PORT94CR */ + PORTCR(95, 0xe605005f), /* PORT95CR */ + PORTCR(96, 0xe6050060), /* PORT96CR */ + PORTCR(97, 0xe6050061), /* PORT97CR */ + PORTCR(98, 0xe6050062), /* PORT98CR */ + PORTCR(99, 0xe6050063), /* PORT99CR */ + + PORTCR(100, 0xe6050064), /* PORT100CR */ + PORTCR(101, 0xe6050065), /* PORT101CR */ + PORTCR(102, 0xe6050066), /* PORT102CR */ + PORTCR(103, 0xe6050067), /* PORT103CR */ + PORTCR(104, 0xe6050068), /* PORT104CR */ + PORTCR(105, 0xe6050069), /* PORT105CR */ + PORTCR(106, 0xe605006a), /* PORT106CR */ + PORTCR(107, 0xe605006b), /* PORT107CR */ + PORTCR(108, 0xe605006c), /* PORT108CR */ + PORTCR(109, 0xe605006d), /* PORT109CR */ + + PORTCR(110, 0xe605006e), /* PORT110CR */ + PORTCR(111, 0xe605006f), /* PORT111CR */ + PORTCR(112, 0xe6050070), /* PORT112CR */ + PORTCR(113, 0xe6050071), /* PORT113CR */ + PORTCR(114, 0xe6050072), /* PORT114CR */ + PORTCR(115, 0xe6050073), /* PORT115CR */ + PORTCR(116, 0xe6050074), /* PORT116CR */ + PORTCR(117, 0xe6050075), /* PORT117CR */ + PORTCR(118, 0xe6050076), /* PORT118CR */ + + PORTCR(128, 0xe6051080), /* PORT128CR */ + PORTCR(129, 0xe6051081), /* PORT129CR */ + + PORTCR(130, 0xe6051082), /* PORT130CR */ + PORTCR(131, 0xe6051083), /* PORT131CR */ + PORTCR(132, 0xe6051084), /* PORT132CR */ + PORTCR(133, 0xe6051085), /* PORT133CR */ + PORTCR(134, 0xe6051086), /* PORT134CR */ + PORTCR(135, 0xe6051087), /* PORT135CR */ + PORTCR(136, 0xe6051088), /* PORT136CR */ + PORTCR(137, 0xe6051089), /* PORT137CR */ + PORTCR(138, 0xe605108a), /* PORT138CR */ + PORTCR(139, 0xe605108b), /* PORT139CR */ + + PORTCR(140, 0xe605108c), /* PORT140CR */ + PORTCR(141, 0xe605108d), /* PORT141CR */ + PORTCR(142, 0xe605108e), /* PORT142CR */ + PORTCR(143, 0xe605108f), /* PORT143CR */ + PORTCR(144, 0xe6051090), /* PORT144CR */ + PORTCR(145, 0xe6051091), /* PORT145CR */ + PORTCR(146, 0xe6051092), /* PORT146CR */ + PORTCR(147, 0xe6051093), /* PORT147CR */ + PORTCR(148, 0xe6051094), /* PORT148CR */ + PORTCR(149, 0xe6051095), /* PORT149CR */ + + PORTCR(150, 0xe6051096), /* PORT150CR */ + PORTCR(151, 0xe6051097), /* PORT151CR */ + PORTCR(152, 0xe6051098), /* PORT152CR */ + PORTCR(153, 0xe6051099), /* PORT153CR */ + PORTCR(154, 0xe605109a), /* PORT154CR */ + PORTCR(155, 0xe605109b), /* PORT155CR */ + PORTCR(156, 0xe605109c), /* PORT156CR */ + PORTCR(157, 0xe605109d), /* PORT157CR */ + PORTCR(158, 0xe605109e), /* PORT158CR */ + PORTCR(159, 0xe605109f), /* PORT159CR */ + + PORTCR(160, 0xe60510a0), /* PORT160CR */ + PORTCR(161, 0xe60510a1), /* PORT161CR */ + PORTCR(162, 0xe60510a2), /* PORT162CR */ + PORTCR(163, 0xe60510a3), /* PORT163CR */ + PORTCR(164, 0xe60510a4), /* PORT164CR */ + + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60520e0), /* PORT224CR */ + PORTCR(225, 0xe60520e1), /* PORT225CR */ + PORTCR(226, 0xe60520e2), /* PORT226CR */ + PORTCR(227, 0xe60520e3), /* PORT227CR */ + PORTCR(228, 0xe60520e4), /* PORT228CR */ + PORTCR(229, 0xe60520e5), /* PORT229CR */ + + PORTCR(230, 0xe60520e6), /* PORT230CR */ + PORTCR(231, 0xe60520e7), /* PORT231CR */ + PORTCR(232, 0xe60520e8), /* PORT232CR */ + PORTCR(233, 0xe60520e9), /* PORT233CR */ + PORTCR(234, 0xe60520ea), /* PORT234CR */ + PORTCR(235, 0xe60520eb), /* PORT235CR */ + PORTCR(236, 0xe60520ec), /* PORT236CR */ + PORTCR(237, 0xe60520ed), /* PORT237CR */ + PORTCR(238, 0xe60520ee), /* PORT238CR */ + PORTCR(239, 0xe60520ef), /* PORT239CR */ + + PORTCR(240, 0xe60520f0), /* PORT240CR */ + PORTCR(241, 0xe60520f1), /* PORT241CR */ + PORTCR(242, 0xe60520f2), /* PORT242CR */ + PORTCR(243, 0xe60520f3), /* PORT243CR */ + PORTCR(244, 0xe60520f4), /* PORT244CR */ + PORTCR(245, 0xe60520f5), /* PORT245CR */ + PORTCR(246, 0xe60520f6), /* PORT246CR */ + PORTCR(247, 0xe60520f7), /* PORT247CR */ + PORTCR(248, 0xe60520f8), /* PORT248CR */ + PORTCR(249, 0xe60520f9), /* PORT249CR */ + + PORTCR(250, 0xe60520fa), /* PORT250CR */ + PORTCR(251, 0xe60520fb), /* PORT251CR */ + PORTCR(252, 0xe60520fc), /* PORT252CR */ + PORTCR(253, 0xe60520fd), /* PORT253CR */ + PORTCR(254, 0xe60520fe), /* PORT254CR */ + PORTCR(255, 0xe60520ff), /* PORT255CR */ + PORTCR(256, 0xe6052100), /* PORT256CR */ + PORTCR(257, 0xe6052101), /* PORT257CR */ + PORTCR(258, 0xe6052102), /* PORT258CR */ + PORTCR(259, 0xe6052103), /* PORT259CR */ + + PORTCR(260, 0xe6052104), /* PORT260CR */ + PORTCR(261, 0xe6052105), /* PORT261CR */ + PORTCR(262, 0xe6052106), /* PORT262CR */ + PORTCR(263, 0xe6052107), /* PORT263CR */ + PORTCR(264, 0xe6052108), /* PORT264CR */ + + { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MSELBCR_MSEL17_0, MSELBCR_MSEL17_1, + 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { }, +}; + +static struct pinmux_info sh7377_pinmux_info = { + .name = "sh7377_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_RESETOUTS, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7377_pinmux_init(void) +{ + register_pinmux(&sh7377_pinmux_info); +} -- GitLab From aa18ef609b65a76e4531b09dd0c196be3e04eb94 Mon Sep 17 00:00:00 2001 From: NISHIMOTO Hiroki Date: Fri, 12 Feb 2010 08:11:18 +0000 Subject: [PATCH 210/370] ARM: mach-shmobile: G4EVM USBHS support Add G4EVM platform data and a magic setup sequence to initialize the r8a66597 block aka USBHS in sh7377. Signed-off-by: NISHIMOTO Hiroki Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-g4evm.c | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index ef4b0f59af492..5acd623f93e79 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -86,9 +87,50 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* USBHS */ +void usb_host_port_power(int port, int power) +{ + if (!power) /* only power-on supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ + __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); +} + +static struct r8a66597_platdata usb_host_data = { + .on_chip = 1, + .port_power = usb_host_port_power, +}; + +static struct resource usb_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xe6890000, + .end = 0xe68900e5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .platform_data = &usb_host_data, + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; static struct platform_device *g4evm_devices[] __initdata = { &nor_flash_device, + &usb_host_device, }; static struct map_desc g4evm_io_desc[] __initdata = { @@ -137,6 +179,23 @@ static void __init g4evm_init(void) gpio_direction_output(GPIO_PORT113, 1); gpio_export(GPIO_PORT113, 1); + /* USBHS */ + gpio_request(GPIO_FN_VBUS_0, NULL); + gpio_request(GPIO_FN_PWEN, NULL); + gpio_request(GPIO_FN_OVCN, NULL); + gpio_request(GPIO_FN_OVCN2, NULL); + gpio_request(GPIO_FN_EXTLP, NULL); + gpio_request(GPIO_FN_IDIN, NULL); + + /* enable clock in SMSTPCR3 */ + __raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c); + + /* setup USB phy */ + __raw_writew(0x0200, 0xe605810a); /* USBCR1 */ + __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ + __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ + __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + sh7377_add_standard_devices(); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); -- GitLab From deded43508f065c95af506d18b8309ba842c397e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 12 Feb 2010 09:55:08 +0000 Subject: [PATCH 211/370] ARM: mach-shmobile: intc-sh7372 tidyup This patch is based on Rev 0.5 manual Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/intc-sh7372.c | 90 ++++++++++++++-------------- 1 file changed, 46 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index c6e747f92462b..c57a923f97a6d 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -39,8 +39,7 @@ enum { AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, MFI_MFIM, MFI_MFIS, BBIF1, BBIF2, - USBHSDMAC_USHDMI, - USBHS_USHI0, USBHS_USHI1, + USBHSDMAC0_USHDMI, _3DG_SGX540, CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, KEYSC_KEY, @@ -57,8 +56,8 @@ enum { DDM, SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, RWDT0, - DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, - DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, @@ -69,7 +68,7 @@ enum { FSI, FMSI, MIPI_HSI, IPMMU_IPMMUD, - CEC_CEC_1, CEC_CEC_2, + CEC_1, CEC_2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, MFIS2, CPORTR2S, @@ -79,14 +78,14 @@ enum { IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0, - USHSDMI, + USBHSDMAC1_USHDMI, /* interrupt groups INTCA */ - DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, - AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 + DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 }; -static struct intc_vect intca_vectors[] = { +static struct intc_vect intca_vectors[] __initdata = { INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), @@ -111,8 +110,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(AP_ARM_COMMRX, 0x0860), INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), - INTC_VECT(USBHSDMAC_USHDMI, 0x0a00), - INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00), INTC_VECT(_3DG_SGX540, 0x0a60), INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), @@ -137,10 +135,10 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), INTC_VECT(RWDT0, 0x1280), - INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), - INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), - INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), - INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), + INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), + INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0), + INTC_VECT(DMAC1_2_DADERR, 0x20c0), INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), @@ -149,7 +147,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), INTC_VECT(DMAC3_2_DADERR, 0x22c0), - INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320), INTC_VECT(SHWYSTAT_COM, 0x1340), INTC_VECT(HDMI, 0x17e0), INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), @@ -157,7 +155,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(FMSI, 0x1860), INTC_VECT(MIPI_HSI, 0x18e0), INTC_VECT(IPMMU_IPMMUD, 0x1920), - INTC_VECT(CEC_CEC_1, 0x1940), INTC_VECT(CEC_CEC_2, 0x1960), + INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960), INTC_VECT(AP_ARM_CTIIRQ, 0x1980), INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), @@ -172,14 +170,14 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), - INTC_VECT(USHSDMI, 0x1d00), + INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00), }; static struct intc_group intca_groups[] __initdata = { - INTC_GROUP(DMAC_1, DMAC_1_DEI0, - DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), - INTC_GROUP(DMAC_2, DMAC_2_DEI4, - DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC1_1, DMAC1_1_DEI0, + DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), + INTC_GROUP(DMAC1_2, DMAC1_2_DEI4, + DMAC1_2_DEI5, DMAC1_2_DADERR), INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, @@ -188,8 +186,9 @@ static struct intc_group intca_groups[] __initdata = { DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), - INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), - INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX), + INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ), INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), @@ -203,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = { INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), }; -static struct intc_mask_reg intca_mask_registers[] = { +static struct intc_mask_reg intca_mask_registers[] __initdata = { { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ @@ -218,7 +217,7 @@ static struct intc_mask_reg intca_mask_registers[] = { AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ { 0, CRYPT_STD, DIRC, 0, - DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ { 0, 0, 0, 0, BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, @@ -229,7 +228,7 @@ static struct intc_mask_reg intca_mask_registers[] = { { DDM, 0, 0, 0, 0, 0, 0, 0 } }, { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ { SCIFB, SCIFA5, SCIFA4, MSIOF1, @@ -239,7 +238,7 @@ static struct intc_mask_reg intca_mask_registers[] = { FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, - TTI20, USBHSDMAC_USHDMI, 0, 0 } }, + TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, CMT2, 0, 0, _3DG_SGX540 } }, @@ -265,7 +264,7 @@ static struct intc_mask_reg intca_mask_registers[] = { { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, 0, 0, 0, MIPI_HSI } }, { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ - { 0, IPMMU_IPMMUD, CEC_CEC_1, CEC_CEC_2, + { 0, IPMMU_IPMMUD, CEC_1, CEC_2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ @@ -278,16 +277,16 @@ static struct intc_mask_reg intca_mask_registers[] = { { 0, 0, 0, 0, USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ - { USBHSDMAC_USHDMI, 0, 0, 0, + { USBHSDMAC1_USHDMI, 0, 0, 0, 0, 0, 0, 0 } }, }; -static struct intc_prio_reg intca_prio_registers[] = { +static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6900010, 0, 32, 4, /* INTPRI00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900014, 0, 32, 4, /* INTPRI10A */ { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { 0xe6900018, 0, 32, 4, /* INTPRI20A */ { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, { 0xe690001c, 0, 32, 4, /* INTPRI30A */ { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, @@ -298,16 +297,18 @@ static struct intc_prio_reg intca_prio_registers[] = { CMT1_CMT11, AP_ARM1 } }, { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_CMT12, 0 } }, - { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS, MFI_MFIM, 0 } }, - { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2, _3DG_SGX540, CMT1_CMT10 } }, { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, SCIFA2, SCIFA3 } }, - { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC_USHDMI, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI, FLCTL, SDHI0 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, - { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, 0, TTI20 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, + 0/* MSU */, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, + 0/* MSUG */, TTI20 } }, { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, @@ -318,7 +319,7 @@ static struct intc_prio_reg intca_prio_registers[] = { { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, - CEC_CEC_1, CEC_CEC_2 } }, + CEC_1, CEC_2 } }, { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, CMT14, CMT15 } }, @@ -328,20 +329,21 @@ static struct intc_prio_reg intca_prio_registers[] = { IIC4_WAITI4, IIC4_DTEI4 } }, { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, - { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0, 0, 0, 0 } }, + { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, + 0/*TXI*/, 0/*TEI*/} }, { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, - { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC_USHDMI, 0, 0, 0 } }, + { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, }; static struct intc_sense_reg intca_sense_registers[] __initdata = { - { 0xe6900000, 16, 2, /* ICR1A */ + { 0xe6900000, 32, 4, /* ICR1A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900004, 16, 2, /* ICR2A */ + { 0xe6900004, 32, 4, /* ICR2A */ { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900008, 16, 2, /* ICR3A */ + { 0xe6900008, 32, 4, /* ICR3A */ { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690000c, 16, 2, /* ICR4A */ + { 0xe690000c, 32, 4, /* ICR4A */ { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, }; -- GitLab From f0d3ab49110327516b7f0b6d27fd33d6fa079d6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Feb 2010 16:57:59 +0100 Subject: [PATCH 212/370] arm/mx2: define seperate imx_nand devices for imx21 and imx27 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the NFC controller has different addresses on imx21 and imx27 there are two different devices needed if not relying on the overloaded cpp macro NFC_BASE_ADDR. So some cpp magic is added to minimize code duplication. As obviously these two defines need different names, the name of the old device is #defined to the new one when building for only one of imx21 or imx27. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx2/devices.c | 43 ++++++++++++++++++++++--------------- arch/arm/mach-mx2/devices.h | 11 +++++++++- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 9bf49da530728..cda4aced7a39c 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -144,24 +144,33 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = NFC_BASE_ADDR, - .end = NFC_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_NANDFC, - .end = MX2x_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; +#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ + static struct resource pfx ## _nand_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device pfx ## _nand_device = { \ + .name = "mxc_nand", \ + .id = 0, \ + .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ + .resource = pfx ## _nand_resources, \ + } -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); +#endif /* * lcdc: diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 0dee0f5e681c4..02e5dd203095b 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -13,7 +13,16 @@ extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_nand_device; +#ifdef CONFIG_MACH_MX21 +extern struct platform_device imx21_nand_device; +#define mxc_nand_device imx21_nand_device +#endif +#ifdef CONFIG_MACH_MX27 +extern struct platform_device imx27_nand_device; +#ifndef CONFIG_MACH_MX21 +#define mxc_nand_device imx27_nand_device +#endif +#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; -- GitLab From 94d32f99c6aba8b702a9cf78cb328aeb7882b1e5 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Mon, 1 Feb 2010 13:28:54 +0100 Subject: [PATCH 213/370] imx-serial-excessive-status-clearing-on-break.patch cc: Sasha Hauer We noticed that we were only able to communicate once with a GSM module per session, if we powered down the module then the serial driver was broken until reset, no traffic or /proc/interrupts activity could be seen any more. Volker noticed it was provoked by a long "break" seen on the wire when the RX was not driven during powerdown, we discovered we could kill the serial driver just by forcing RX low extenally for a little while. I saw that the processing for BREAK in the driver gets too excited and clears down all set bits in USR2, including that a character is pending. This stops all further characters getting processed. The attached one-liner makes the serial driver immortal against BREAK. Signed-off-by: Andy Green Signed-off-by: Volker Ernst Signed-off-by: Sascha Hauer --- drivers/serial/imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 18130f11238e6..c5b546a98520f 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c @@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) temp = readl(sport->port.membase + USR2); if (temp & USR2_BRCD) { - writel(temp | USR2_BRCD, sport->port.membase + USR2); + writel(USR2_BRCD, sport->port.membase + USR2); if (uart_handle_break(&sport->port)) continue; } -- GitLab From b789b3fdccc1690826331f4c878b644c3904ca6b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 17 Feb 2010 09:39:10 +0000 Subject: [PATCH 214/370] ARM: mach-shmobile: Add sh7372 pinmux support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/sh7372.h | 434 +++++ arch/arm/mach-shmobile/pfc-sh7372.c | 1637 ++++++++++++++++++ 5 files changed, 2074 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7372.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7372.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a96c25a262729..aeceb9b92aeb3 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -41,6 +41,7 @@ config MACH_G4EVM config MACH_AP4EVB bool "AP4EVB board" depends on ARCH_SH7372 + select ARCH_REQUIRE_GPIOLIB comment "SH-Mobile System Configuration" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index ce01951edda33..6d385d371c332 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Pinmux setup pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o +pfc-$(CONFIG_ARCH_SH7372) := pfc-sh7372.o obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) # Board objects diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d6f927b4bef65..57903605cc51a 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -18,5 +18,6 @@ extern void sh7377_pinmux_init(void); extern void sh7372_init_irq(void); extern void sh7372_add_early_devices(void); extern void sh7372_add_standard_devices(void); +extern void sh7372_pinmux_init(void); #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h new file mode 100644 index 0000000000000..dc34f00c56b80 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2010 Renesas Solutions Corp. + * + * Kuninori Morimoto + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_SH7372_H__ +#define __ASM_SH7372_H__ + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, + + /* IRQ */ + GPIO_FN_IRQ0_6, /* PORT 6 */ + GPIO_FN_IRQ0_162, /* PORT 162 */ + GPIO_FN_IRQ1, /* PORT 12 */ + GPIO_FN_IRQ2_4, /* PORT 4 */ + GPIO_FN_IRQ2_5, /* PORT 5 */ + GPIO_FN_IRQ3_8, /* PORT 8 */ + GPIO_FN_IRQ3_16, /* PORT 16 */ + GPIO_FN_IRQ4_17, /* PORT 17 */ + GPIO_FN_IRQ4_163, /* PORT 163 */ + GPIO_FN_IRQ5, /* PORT 18 */ + GPIO_FN_IRQ6_39, /* PORT 39 */ + GPIO_FN_IRQ6_164, /* PORT 164 */ + GPIO_FN_IRQ7_40, /* PORT 40 */ + GPIO_FN_IRQ7_167, /* PORT 167 */ + GPIO_FN_IRQ8_41, /* PORT 41 */ + GPIO_FN_IRQ8_168, /* PORT 168 */ + GPIO_FN_IRQ9_42, /* PORT 42 */ + GPIO_FN_IRQ9_169, /* PORT 169 */ + GPIO_FN_IRQ10, /* PORT 65 */ + GPIO_FN_IRQ11, /* PORT 67 */ + GPIO_FN_IRQ12_80, /* PORT 80 */ + GPIO_FN_IRQ12_137, /* PORT 137 */ + GPIO_FN_IRQ13_81, /* PORT 81 */ + GPIO_FN_IRQ13_145, /* PORT 145 */ + GPIO_FN_IRQ14_82, /* PORT 82 */ + GPIO_FN_IRQ14_146, /* PORT 146 */ + GPIO_FN_IRQ15_83, /* PORT 83 */ + GPIO_FN_IRQ15_147, /* PORT 147 */ + GPIO_FN_IRQ16_84, /* PORT 84 */ + GPIO_FN_IRQ16_170, /* PORT 170 */ + GPIO_FN_IRQ17, /* PORT 85 */ + GPIO_FN_IRQ18, /* PORT 86 */ + GPIO_FN_IRQ19, /* PORT 87 */ + GPIO_FN_IRQ20, /* PORT 92 */ + GPIO_FN_IRQ21, /* PORT 93 */ + GPIO_FN_IRQ22, /* PORT 94 */ + GPIO_FN_IRQ23, /* PORT 95 */ + GPIO_FN_IRQ24, /* PORT 112 */ + GPIO_FN_IRQ25, /* PORT 119 */ + GPIO_FN_IRQ26_121, /* PORT 121 */ + GPIO_FN_IRQ26_172, /* PORT 172 */ + GPIO_FN_IRQ27_122, /* PORT 122 */ + GPIO_FN_IRQ27_180, /* PORT 180 */ + GPIO_FN_IRQ28_123, /* PORT 123 */ + GPIO_FN_IRQ28_181, /* PORT 181 */ + GPIO_FN_IRQ29_129, /* PORT 129 */ + GPIO_FN_IRQ29_182, /* PORT 182 */ + GPIO_FN_IRQ30_130, /* PORT 130 */ + GPIO_FN_IRQ30_183, /* PORT 183 */ + GPIO_FN_IRQ31_138, /* PORT 138 */ + GPIO_FN_IRQ31_184, /* PORT 184 */ + + /* + * MSIOF0 (PORT 36, 37, 38, 39 + * 40, 41, 42, 43, 44, 45) + */ + GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD, + + /* + * MSIOF1 (PORT 39, 40, 41, 42, 43, 44 + * 84, 85, 86, 87, 88, 89, 90, 91, 92, 93) + */ + GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40, + GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89, + GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42, + GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91, + GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44, + GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + /* + * MSIOF2 (PORT 134, 135, 136, 137, 138, 139 + * 148, 149, 150, 151) + */ + GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2, + GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD, + + /* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD, + GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N, + + /* MSIOF4 (PORT 0, 1, 2, 3) */ + GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD, + + /* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */ + GPIO_FN_FSIACK, GPIO_FN_FSIBCK, + GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11, + GPIO_FN_FSIASPDIF_15, + + /* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */ + GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR, + GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT, + GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOILR, GPIO_FN_FMSIILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT, + GPIO_FN_FMSISLD, GPIO_FN_FMSICK, + + /* SCIFA0 (PORT 152, 153, 156, 157, 158) */ + GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS, + GPIO_FN_SCIFA0_CTS, + + /* SCIFA1 (PORT 154, 155, 159, 160, 161) */ + GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS, + GPIO_FN_SCIFA1_CTS, + + /* SCIFA2 (PORT 94, 95, 96, 97, 98) */ + GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1, + GPIO_FN_SCIFA2_SCK1, + + /* SCIFA3 (PORT 43, 44, + 140, 141, 142, 143, 144) */ + GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140, + GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141, + GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD, + GPIO_FN_SCIFA3_RXD, + + /* SCIFA4 (PORT 5, 6) */ + GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD, + + /* SCIFA5 (PORT 8, 12) */ + GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD, + + /* SCIFB (PORT 162, 163, 164, 165, 166) */ + GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS, + GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD, + GPIO_FN_SCIFB_RXD, + + /* + * CEU (PORT 16, 17, + * 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, + * 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, + * 120) + */ + GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, + GPIO_FN_VIO_CKO, + GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, + GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, + GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, + GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, + GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, + GPIO_FN_VIO_D15, + + /* USB0 (PORT 113, 114, 115, 116, 117, 167) */ + GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0, + GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0, + GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0, + + /* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */ + GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113, + GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138, + GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162, + GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1, + GPIO_FN_VBUS0_1, + + /* GPIO (PORT 41, 42, 43, 44) */ + GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1, + + /* + * BSC (PORT 19, + * 20, 21, 22, 25, 26, 27, 28, 29, + * 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, + * 40, 41, 42, 43, 44, 45, + * 62, 63, 64, 65, 66, 67, + * 71, 72, 74, 75) + */ + GPIO_FN_BS, GPIO_FN_WE1, + GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR, + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A, + + /* + * BSC/FLCTL (PORT 23, 24, + * 46, 47, 48, 49, + * 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, + * 60, 61, 69, 70) + */ + GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE, + GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE, + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + + /* + * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89, + * 90, 91, 92, 99) + */ + GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5, + GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7, + GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0, + + /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */ + GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2, + GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5, + GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7, + GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1, + + /* SPU2 (PORT 65) */ + GPIO_FN_VINT_I, + + /* FLCTL (PORT 66, 68, 73) */ + GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB, + + /* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ + GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY, + GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA, + GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE, + + /* + * MFI (PORT 76, 77, 78, 79, + * 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, + * 90, 91, 92, 93, 94, 95, 96, 97, 98, 99) + */ + GPIO_FN_MFIv6, /* see MSEL4CR 6 */ + GPIO_FN_MFIv4, /* see MSEL4CR 6 */ + + GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0, + GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0, + GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT, + + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, + + /* SIM (PORT 94, 95, 98) */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D, + + /* TPU (PORT 93, 99, 112, 160, 161) */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99, + GPIO_FN_TPU0TO3, + + /* I2C2 (PORT 110, 111) */ + GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2, + + /* I2C3(1) (PORT 114, 115) */ + GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3, + + /* I2C3(2) (PORT 137, 145) */ + GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S, + + /* I2C4(2) (PORT 116, 117) */ + GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4, + + /* I2C4(2) (PORT 146, 147) */ + GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S, + + /* + * KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, + * 130, 131, 132, 133, 134, 135, 136) + */ + GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136, + GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135, + GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134, + GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133, + GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4, + GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6, + GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7, + + /* + * LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, + * 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, + * 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, + * 150, 151) + */ + GPIO_FN_LCDC0_SELECT, /* LCDC 0 */ + GPIO_FN_LCDC1_SELECT, /* LCDC 1 */ + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK, + GPIO_FN_LCDDON, + + GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3, + GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7, + GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11, + GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15, + GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19, + GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23, + + /* IRDA (PORT 139, 140, 141, 142) */ + GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, + GPIO_FN_IROUT_139, GPIO_FN_IROUT_140, + + /* TSIF1 (PORT 156, 157, 158, 159) */ + GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */ + GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */ + GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */ + GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */ + + GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1, + GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1, + + /* TSIF2 (PORT 137, 145, 146, 147) */ + GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2, + GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2, + + /* HDMI (PORT 169, 170) */ + GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, + + /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */ + GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, + GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0, + GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3, + + /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */ + GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0, + GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3, + + /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */ + GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0, + GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3, + + /* SDENC see MSEL4CR 19 */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, +}; + +#endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c new file mode 100644 index 0000000000000..9557d0964d73e --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7372.c @@ -0,0 +1,1637 @@ +/* + * sh7372 processor support - PFC hardware block + * + * Copyright (C) 2010 Kuninori Morimoto + * + * Based on + * sh7367 processor support - PFC hardware block + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _80(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx) + +#define _190(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \ + _10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_ALL(str) _190(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT190_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT190_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_IN_PU -> PORT190_IN_PU */ + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), + PINMUX_INPUT_PULLUP_END, + + /* PORT0_IN_PD -> PORT190_IN_PD */ + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), + PINMUX_INPUT_PULLDOWN_END, + + /* PORT0_OUT -> PORT190_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_8_0, MSEL1CR_8_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + MSEL1CR_0_0, MSEL1CR_0_1, + + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_15_0, MSEL3CR_15_1, + MSEL3CR_9_0, MSEL3CR_9_1, + MSEL3CR_6_0, MSEL3CR_6_1, + + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_6_0, MSEL4CR_6_1, + MSEL4CR_4_0, MSEL4CR_4_1, + MSEL4CR_1_0, MSEL4CR_1_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* IRQ */ + IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK, + IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK, + IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK, + IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK, + IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK, + IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK, + IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK, + IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK, + IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK, + IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK, + IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK, + IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK, + IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK, + + /* MSIOF0 */ + MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK, + MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK, + MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, + MSIOF0_TXD_MARK, + + /* MSIOF1 */ + MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK, + MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK, + MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK, + MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK, + MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK, + MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK, + MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + + /* MSIOF2 */ + MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK, + MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK, + MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, + MSIOF2_TXD_MARK, + + /* MSIOF3 */ + BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, + BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, + BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, + + /* MSIOF4 */ + BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, + BBIF2_TXD1_MARK, BBIF2_RXD_MARK, + + /* FSI */ + FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK, + FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK, + FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK, + + /* FMSI */ + FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK, + FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK, + FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK, + + /* SCIFA0 */ + SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK, + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, + + /* SCIFA1 */ + SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK, + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, + + /* SCIFA2 */ + SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK, + SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK, + + /* SCIFA3 */ + SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK, + SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK, + SCIFA3_RXD_MARK, + + /* SCIFA4 */ + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, + + /* SCIFA5 */ + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, + + /* SCIFB */ + SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK, + SCIFB_TXD_MARK, SCIFB_RXD_MARK, + + /* CEU */ + VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK, + VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK, + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, + VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, + VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, + + /* USB0 */ + IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK, + OVCN_0_MARK, VBUS0_0_MARK, + + /* USB1 */ + IDIN_1_18_MARK, IDIN_1_113_MARK, + PWEN_1_115_MARK, PWEN_1_138_MARK, + OVCN_1_114_MARK, OVCN_1_162_MARK, + EXTLP_1_MARK, OVCN2_1_MARK, + VBUS0_1_MARK, + + /* GPIO */ + GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK, + + /* BSC */ + BS_MARK, WE1_MARK, + CKO_MARK, WAIT_MARK, RDWR_MARK, + + A0_MARK, A1_MARK, A2_MARK, A3_MARK, + A6_MARK, A7_MARK, A8_MARK, A9_MARK, + A10_MARK, A11_MARK, A12_MARK, A13_MARK, + A14_MARK, A15_MARK, A16_MARK, A17_MARK, + A18_MARK, A19_MARK, A20_MARK, A21_MARK, + A22_MARK, A23_MARK, A24_MARK, A25_MARK, + A26_MARK, + + CS0_MARK, CS2_MARK, CS4_MARK, + CS5A_MARK, CS5B_MARK, CS6A_MARK, + + /* BSC/FLCTL */ + RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK, + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, + + /* MMCIF(1) */ + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, + MMCCMD0_MARK, MMCCLK0_MARK, + + /* MMCIF(2) */ + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, + MMCCLK1_MARK, MMCCMD1_MARK, + + /* SPU2 */ + VINT_I_MARK, + + /* FLCTL */ + FCE1_MARK, FCE0_MARK, FRB_MARK, + + /* HSI */ + GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK, + GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK, + MP_RX_READY_MARK, MP_TX_WAKE_MARK, + + /* MFI */ + MFIv6_MARK, + MFIv4_MARK, + + MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK, + MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK, + MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK, + MEMC_NWE_MARK, MEMC_INT_MARK, + + MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, + MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK, + MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK, + MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, + MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, + MEMC_AD15_MARK, + + /* SIM */ + SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK, + + /* TPU */ + TPU0TO0_MARK, TPU0TO1_MARK, + TPU0TO2_93_MARK, TPU0TO2_99_MARK, + TPU0TO3_MARK, + + /* I2C2 */ + I2C_SCL2_MARK, I2C_SDA2_MARK, + + /* I2C3(1) */ + I2C_SCL3_MARK, I2C_SDA3_MARK, + + /* I2C3(2) */ + I2C_SCL3S_MARK, I2C_SDA3S_MARK, + + /* I2C4(2) */ + I2C_SCL4_MARK, I2C_SDA4_MARK, + + /* I2C4(2) */ + I2C_SCL4S_MARK, I2C_SDA4S_MARK, + + /* KEYSC */ + KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK, + KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK, + KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK, + KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK, + KEYOUT4_MARK, KEYIN4_MARK, + KEYOUT5_MARK, KEYIN5_MARK, + KEYOUT6_MARK, KEYIN6_MARK, + KEYOUT7_MARK, KEYIN7_MARK, + + /* LCDC */ + LCDC0_SELECT_MARK, + LCDC1_SELECT_MARK, + LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK, + LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK, + LCDLCLK_MARK, LCDDON_MARK, + + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, + + /* IRDA */ + IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK, + IROUT_139_MARK, IROUT_140_MARK, + + /* TSIF1 */ + TS0_1SELECT_MARK, + TS0_2SELECT_MARK, + TS1_1SELECT_MARK, + TS1_2SELECT_MARK, + + TS_SPSYNC1_MARK, TS_SDAT1_MARK, + TS_SDEN1_MARK, TS_SCK1_MARK, + + /* TSIF2 */ + TS_SPSYNC2_MARK, TS_SDAT2_MARK, + TS_SDEN2_MARK, TS_SCK2_MARK, + + /* HDMI */ + HDMI_HPD_MARK, HDMI_CEC_MARK, + + /* SDHI0 */ + SDHICLK0_MARK, SDHICD0_MARK, + SDHICMD0_MARK, SDHIWP0_MARK, + SDHID0_0_MARK, SDHID0_1_MARK, + SDHID0_2_MARK, SDHID0_3_MARK, + + /* SDHI1 */ + SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK, + SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, + + /* SDHI2 */ + SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK, + SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, + + /* SDENC */ + SDENC_CPG_MARK, + SDENC_DV_CLKI_MARK, + + PINMUX_MARK_END, +}; + +/* PORT_DATA_I_PD(nr) */ +#define _I___D(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +/* PORT_DATA_I_PU(nr) */ +#define _I__U_(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +/* PORT_DATA_I_PU_PD(nr) */ +#define _I__UD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +/* PORT_DATA_O(nr) */ +#define __O___(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) + +/* PORT_DATA_IO(nr) */ +#define _IO___(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) + +/* PORT_DATA_IO_PD(nr) */ +#define _IO__D(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +/* PORT_DATA_IO_PU(nr) */ +#define _IO_U_(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +/* PORT_DATA_IO_PU_PD(nr) */ +#define _IO_UD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + + +static pinmux_enum_t pinmux_data[] = { + + /* specify valid pin states for each pin in GPIO mode */ + + _IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4), + _I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9), + + __O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14), + __O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19), + + _IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24), + _IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29), + + _IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34), + _IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39), + + _IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44), + _IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49), + + _IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54), + _IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59), + + _IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64), + _IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/ + + _IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74), + _IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79), + + _IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84), + _IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89), + + _IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94), + _IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/ + + _IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104), + _IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109), + + _IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114), + _IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119), + + _IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124), + _IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129), + + _IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134), + _IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139), + + _IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144), + _IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149), + + _IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154), + _I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159), + + __O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164), + _IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169), + + _I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174), + _IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179), + + _IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184), + __O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189), + + _IO_UD(190), + + /* IRQ */ + PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), + PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1), + PINMUX_DATA(IRQ1_MARK, PORT12_FN0), + PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0), + PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1), + PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0), + PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1), + PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0), + PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1), + PINMUX_DATA(IRQ5_MARK, PORT18_FN0), + PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0), + PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1), + PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1), + PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0), + PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1), + PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0), + PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0), + PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1), + PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1), + PINMUX_DATA(IRQ11_MARK, PORT67_FN0), + PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0), + PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1), + PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0), + PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1), + PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0), + PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1), + PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0), + PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1), + PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0), + PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1), + PINMUX_DATA(IRQ17_MARK, PORT85_FN0), + PINMUX_DATA(IRQ18_MARK, PORT86_FN0), + PINMUX_DATA(IRQ19_MARK, PORT87_FN0), + PINMUX_DATA(IRQ20_MARK, PORT92_FN0), + PINMUX_DATA(IRQ21_MARK, PORT93_FN0), + PINMUX_DATA(IRQ22_MARK, PORT94_FN0), + PINMUX_DATA(IRQ23_MARK, PORT95_FN0), + PINMUX_DATA(IRQ24_MARK, PORT112_FN0), + PINMUX_DATA(IRQ25_MARK, PORT119_FN0), + PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1), + PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0), + PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1), + PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0), + PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1), + PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0), + PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1), + PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0), + PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1), + PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0), + PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1), + PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0), + + /* Function 1 */ + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1), + PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1), + PINMUX_DATA(FSIACK_MARK, PORT4_FN1), + PINMUX_DATA(FSIAILR_MARK, PORT5_FN1), + PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1), + PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1), + PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1), + PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1), + PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1), + PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1), + PINMUX_DATA(FMSOCK_MARK, PORT12_FN1), + PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1), + PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1), + PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1), + PINMUX_DATA(FMSOILR_MARK, PORT16_FN1), + PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1), + PINMUX_DATA(FMSISLD_MARK, PORT18_FN1), + PINMUX_DATA(A0_MARK, PORT19_FN1), + PINMUX_DATA(A1_MARK, PORT20_FN1), + PINMUX_DATA(A2_MARK, PORT21_FN1), + PINMUX_DATA(A3_MARK, PORT22_FN1), + PINMUX_DATA(A4_FOE_MARK, PORT23_FN1), + PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1), + PINMUX_DATA(A6_MARK, PORT25_FN1), + PINMUX_DATA(A7_MARK, PORT26_FN1), + PINMUX_DATA(A8_MARK, PORT27_FN1), + PINMUX_DATA(A9_MARK, PORT28_FN1), + PINMUX_DATA(A10_MARK, PORT29_FN1), + PINMUX_DATA(A11_MARK, PORT30_FN1), + PINMUX_DATA(A12_MARK, PORT31_FN1), + PINMUX_DATA(A13_MARK, PORT32_FN1), + PINMUX_DATA(A14_MARK, PORT33_FN1), + PINMUX_DATA(A15_MARK, PORT34_FN1), + PINMUX_DATA(A16_MARK, PORT35_FN1), + PINMUX_DATA(A17_MARK, PORT36_FN1), + PINMUX_DATA(A18_MARK, PORT37_FN1), + PINMUX_DATA(A19_MARK, PORT38_FN1), + PINMUX_DATA(A20_MARK, PORT39_FN1), + PINMUX_DATA(A21_MARK, PORT40_FN1), + PINMUX_DATA(A22_MARK, PORT41_FN1), + PINMUX_DATA(A23_MARK, PORT42_FN1), + PINMUX_DATA(A24_MARK, PORT43_FN1), + PINMUX_DATA(A25_MARK, PORT44_FN1), + PINMUX_DATA(A26_MARK, PORT45_FN1), + PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1), + PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1), + PINMUX_DATA(CS0_MARK, PORT62_FN1), + PINMUX_DATA(CS2_MARK, PORT63_FN1), + PINMUX_DATA(CS4_MARK, PORT64_FN1), + PINMUX_DATA(CS5A_MARK, PORT65_FN1), + PINMUX_DATA(CS5B_MARK, PORT66_FN1), + PINMUX_DATA(CS6A_MARK, PORT67_FN1), + PINMUX_DATA(FCE0_MARK, PORT68_FN1), + PINMUX_DATA(RD_FSC_MARK, PORT69_FN1), + PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1), + PINMUX_DATA(WE1_MARK, PORT71_FN1), + PINMUX_DATA(CKO_MARK, PORT72_FN1), + PINMUX_DATA(FRB_MARK, PORT73_FN1), + PINMUX_DATA(WAIT_MARK, PORT74_FN1), + PINMUX_DATA(RDWR_MARK, PORT75_FN1), + PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1), + PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1), + PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1), + PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1), + PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1), + PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1), + PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1), + PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1), + PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1), + PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1), + PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1), + PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1), + PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1), + PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1), + PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1), + PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1), + PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1), + PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1), + PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1), + PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1), + PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1), + PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1), + PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1), + PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT100_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT101_FN1), + PINMUX_DATA(VIO_D0_MARK, PORT102_FN1), + PINMUX_DATA(VIO_D1_MARK, PORT103_FN1), + PINMUX_DATA(VIO_D2_MARK, PORT104_FN1), + PINMUX_DATA(VIO_D3_MARK, PORT105_FN1), + PINMUX_DATA(VIO_D4_MARK, PORT106_FN1), + PINMUX_DATA(VIO_D5_MARK, PORT107_FN1), + PINMUX_DATA(VIO_D6_MARK, PORT108_FN1), + PINMUX_DATA(VIO_D7_MARK, PORT109_FN1), + PINMUX_DATA(VIO_D8_MARK, PORT110_FN1), + PINMUX_DATA(VIO_D9_MARK, PORT111_FN1), + PINMUX_DATA(VIO_D10_MARK, PORT112_FN1), + PINMUX_DATA(VIO_D11_MARK, PORT113_FN1), + PINMUX_DATA(VIO_D12_MARK, PORT114_FN1), + PINMUX_DATA(VIO_D13_MARK, PORT115_FN1), + PINMUX_DATA(VIO_D14_MARK, PORT116_FN1), + PINMUX_DATA(VIO_D15_MARK, PORT117_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1), + PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1), + PINMUX_DATA(LCDD0_MARK, PORT121_FN1), + PINMUX_DATA(LCDD1_MARK, PORT122_FN1), + PINMUX_DATA(LCDD2_MARK, PORT123_FN1), + PINMUX_DATA(LCDD3_MARK, PORT124_FN1), + PINMUX_DATA(LCDD4_MARK, PORT125_FN1), + PINMUX_DATA(LCDD5_MARK, PORT126_FN1), + PINMUX_DATA(LCDD6_MARK, PORT127_FN1), + PINMUX_DATA(LCDD7_MARK, PORT128_FN1), + PINMUX_DATA(LCDD8_MARK, PORT129_FN1), + PINMUX_DATA(LCDD9_MARK, PORT130_FN1), + PINMUX_DATA(LCDD10_MARK, PORT131_FN1), + PINMUX_DATA(LCDD11_MARK, PORT132_FN1), + PINMUX_DATA(LCDD12_MARK, PORT133_FN1), + PINMUX_DATA(LCDD13_MARK, PORT134_FN1), + PINMUX_DATA(LCDD14_MARK, PORT135_FN1), + PINMUX_DATA(LCDD15_MARK, PORT136_FN1), + PINMUX_DATA(LCDD16_MARK, PORT137_FN1), + PINMUX_DATA(LCDD17_MARK, PORT138_FN1), + PINMUX_DATA(LCDD18_MARK, PORT139_FN1), + PINMUX_DATA(LCDD19_MARK, PORT140_FN1), + PINMUX_DATA(LCDD20_MARK, PORT141_FN1), + PINMUX_DATA(LCDD21_MARK, PORT142_FN1), + PINMUX_DATA(LCDD22_MARK, PORT143_FN1), + PINMUX_DATA(LCDD23_MARK, PORT144_FN1), + PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1), + PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1), + PINMUX_DATA(LCDDCK_MARK, PORT147_FN1), + PINMUX_DATA(LCDRD_MARK, PORT148_FN1), + PINMUX_DATA(LCDDISP_MARK, PORT149_FN1), + PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1), + PINMUX_DATA(LCDDON_MARK, PORT151_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1), + PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1), + PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1), + PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1), + PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1), + PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1), + PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1), + PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1), + PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1), + PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1), + PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1), + PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1), + PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1), + PINMUX_DATA(SDHICD0_MARK, PORT172_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1), + PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1), + PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1), + PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1), + PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1), + PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1), + PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1), + PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1), + PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1), + PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1), + PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1), + PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1), + + /* Function 2 */ + PINMUX_DATA(FSIBCK_MARK, PORT4_FN2), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2), + PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2), + PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2), + PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2), + PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2), + PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2), + PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2), + PINMUX_DATA(FMSIILR_MARK, PORT16_FN2), + PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2), + PINMUX_DATA(BS_MARK, PORT19_FN2), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2), + PINMUX_DATA(FMSICK_MARK, PORT65_FN2), + PINMUX_DATA(FCE1_MARK, PORT66_FN2), + PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2), + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2), + PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2), + PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2), + PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2), + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2), + PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2), + PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2), + PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2), + PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2), + PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2), + PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1), + PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1), + PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1), + PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2), + PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2), + PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1), + PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2), + PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2), + PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2), + PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2), + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2), + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2), + + /* Function 3 */ + PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3), + PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3), + PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1), + PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0), + PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1), + PINMUX_DATA(VINT_I_MARK, PORT65_FN3), + PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1), + PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3), + PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3), + PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3), + PINMUX_DATA(IDIN_0_MARK, PORT113_FN3), + PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3), + PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3), + PINMUX_DATA(PWEN_0_MARK, PORT116_FN3), + PINMUX_DATA(OVCN_0_MARK, PORT117_FN3), + PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3), + PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3), + PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3), + PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3), + PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3), + PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3), + PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3), + PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3), + PINMUX_DATA(KEYIN7_MARK, PORT129_FN3), + PINMUX_DATA(KEYIN6_MARK, PORT130_FN3), + PINMUX_DATA(KEYIN5_MARK, PORT131_FN3), + PINMUX_DATA(KEYIN4_MARK, PORT132_FN3), + PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3), + PINMUX_DATA(IROUT_139_MARK, PORT139_FN3), + PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3), + PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3), + PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3), + PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3), + PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3), + + /* Function 4 */ + PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0), + PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4), + PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4), + PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4), + PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4), + PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4), + PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4), + PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4), + PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4), + PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4), + PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0), + PINMUX_DATA(SIM_RST_MARK, PORT94_FN4), + PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4), + PINMUX_DATA(SIM_D_MARK, PORT98_FN4), + PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0), + PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0), + PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0), + PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4), + PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4), + PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4), + PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1), + PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4), + PINMUX_DATA(IROUT_140_MARK, PORT140_FN4), + PINMUX_DATA(LCDCS_MARK, PORT145_FN4), + PINMUX_DATA(LCDWR_MARK, PORT147_FN4), + PINMUX_DATA(LCDRS_MARK, PORT149_FN4), + PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1), + + /* Function 5 */ + PINMUX_DATA(GPI0_MARK, PORT41_FN5), + PINMUX_DATA(GPI1_MARK, PORT42_FN5), + PINMUX_DATA(GPO0_MARK, PORT43_FN5), + PINMUX_DATA(GPO1_MARK, PORT44_FN5), + PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0), + PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0), + PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0), + PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0), + + /* Function select */ + PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), + PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), + + PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0), + PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1), + PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0), + PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1), + + PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), + PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), + + PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0), + PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + + /* PORT */ + GPIO_PORT_ALL(), + + /* IRQ */ + GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), + GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), + GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), + GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), + GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), + GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), + GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), + GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), + GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), + GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), + GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), + GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), + GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), + GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), + GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), + GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), + GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), + + /* MSIOF0 */ + GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), + GPIO_FN(MSIOF0_TXD), + + /* MSIOF1 */ + GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), + GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), + GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), + GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), + GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), + GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + + /* MSIOF2 */ + GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), + GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), + GPIO_FN(MSIOF2_TXD), + + /* MSIOF3 */ + GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), + GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), + GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), + + /* MSIOF4 */ + GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), + + /* FSI */ + GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), + GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), + GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), + GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), + + /* FMSI */ + GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), + GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), + GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), + GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), + + /* SCIFA0 */ + GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), + GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), + + /* SCIFA1 */ + GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), + GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), + + /* SCIFA2 */ + GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), + GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), + + /* SCIFA3 */ + GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), + GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), + GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), + GPIO_FN(SCIFA3_RXD), + + /* SCIFA4 */ + GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), + + /* SCIFA5 */ + GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), + + /* SCIFB */ + GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), + GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), + + /* CEU */ + GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), + GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), + GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), + GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), + GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), + GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), + GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), + GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), + + /* USB0 */ + GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), + GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), + + /* USB1 */ + GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), + GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), + GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), + GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), + GPIO_FN(VBUS0_1), + + /* GPIO */ + GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), + + /* BSC */ + GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), + GPIO_FN(WAIT), GPIO_FN(RDWR), + + GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), + GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), + GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), + GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), + GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), + GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), + GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), + GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), + GPIO_FN(A26), + + GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), + GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), + + /* BSC/FLCTL */ + GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), + GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), + GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), + GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), + GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), + GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), + GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), + + /* MMCIF(1) */ + GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5), + GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0), + GPIO_FN(MMCCLK0), + + /* MMCIF(2) */ + GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2), + GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5), + GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1), + GPIO_FN(MMCCMD1), + + /* SPU2 */ + GPIO_FN(VINT_I), + + /* FLCTL */ + GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), + + /* HSI */ + GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), + GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), + GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), + + /* MFI */ + GPIO_FN(MFIv6), + GPIO_FN(MFIv4), + + GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), + GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), + GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), + GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), + + GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), + GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), + GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), + GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), + GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), + GPIO_FN(MEMC_AD15), + + /* SIM */ + GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), + + /* TPU */ + GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), + GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), + + /* I2C2 */ + GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), + + /* I2C3(1) */ + GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), + + /* I2C3(2) */ + GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), + + /* I2C4(2) */ + GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), + + /* I2C4(2) */ + GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), + + /* KEYSC */ + GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), + GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), + GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), + GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), + GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), + GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), + GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), + + /* LCDC */ + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), + GPIO_FN(LCDDON), + + GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), + GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), + GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), + GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), + GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), + GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), + GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), + GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), + + /* IRDA */ + GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), + GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), + + /* TSIF1 */ + GPIO_FN(TS0_1SELECT), + GPIO_FN(TS0_2SELECT), + GPIO_FN(TS1_1SELECT), + GPIO_FN(TS1_2SELECT), + + GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), + GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), + + /* TSIF2 */ + GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), + GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), + + /* HDMI */ + GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), + + /* SDHI0 */ + GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0), + GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3), + + /* SDHI1 */ + GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0), + GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3), + + /* SDHI2 */ + GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0), + GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3), + + /* SDENC */ + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ + PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xE6051000), /* PORT0CR */ + PORTCR(1, 0xE6051001), /* PORT1CR */ + PORTCR(2, 0xE6051002), /* PORT2CR */ + PORTCR(3, 0xE6051003), /* PORT3CR */ + PORTCR(4, 0xE6051004), /* PORT4CR */ + PORTCR(5, 0xE6051005), /* PORT5CR */ + PORTCR(6, 0xE6051006), /* PORT6CR */ + PORTCR(7, 0xE6051007), /* PORT7CR */ + PORTCR(8, 0xE6051008), /* PORT8CR */ + PORTCR(9, 0xE6051009), /* PORT9CR */ + PORTCR(10, 0xE605100A), /* PORT10CR */ + PORTCR(11, 0xE605100B), /* PORT11CR */ + PORTCR(12, 0xE605100C), /* PORT12CR */ + PORTCR(13, 0xE605100D), /* PORT13CR */ + PORTCR(14, 0xE605100E), /* PORT14CR */ + PORTCR(15, 0xE605100F), /* PORT15CR */ + PORTCR(16, 0xE6051010), /* PORT16CR */ + PORTCR(17, 0xE6051011), /* PORT17CR */ + PORTCR(18, 0xE6051012), /* PORT18CR */ + PORTCR(19, 0xE6051013), /* PORT19CR */ + PORTCR(20, 0xE6051014), /* PORT20CR */ + PORTCR(21, 0xE6051015), /* PORT21CR */ + PORTCR(22, 0xE6051016), /* PORT22CR */ + PORTCR(23, 0xE6051017), /* PORT23CR */ + PORTCR(24, 0xE6051018), /* PORT24CR */ + PORTCR(25, 0xE6051019), /* PORT25CR */ + PORTCR(26, 0xE605101A), /* PORT26CR */ + PORTCR(27, 0xE605101B), /* PORT27CR */ + PORTCR(28, 0xE605101C), /* PORT28CR */ + PORTCR(29, 0xE605101D), /* PORT29CR */ + PORTCR(30, 0xE605101E), /* PORT30CR */ + PORTCR(31, 0xE605101F), /* PORT31CR */ + PORTCR(32, 0xE6051020), /* PORT32CR */ + PORTCR(33, 0xE6051021), /* PORT33CR */ + PORTCR(34, 0xE6051022), /* PORT34CR */ + PORTCR(35, 0xE6051023), /* PORT35CR */ + PORTCR(36, 0xE6051024), /* PORT36CR */ + PORTCR(37, 0xE6051025), /* PORT37CR */ + PORTCR(38, 0xE6051026), /* PORT38CR */ + PORTCR(39, 0xE6051027), /* PORT39CR */ + PORTCR(40, 0xE6051028), /* PORT40CR */ + PORTCR(41, 0xE6051029), /* PORT41CR */ + PORTCR(42, 0xE605102A), /* PORT42CR */ + PORTCR(43, 0xE605102B), /* PORT43CR */ + PORTCR(44, 0xE605102C), /* PORT44CR */ + PORTCR(45, 0xE605102D), /* PORT45CR */ + PORTCR(46, 0xE605202E), /* PORT46CR */ + PORTCR(47, 0xE605202F), /* PORT47CR */ + PORTCR(48, 0xE6052030), /* PORT48CR */ + PORTCR(49, 0xE6052031), /* PORT49CR */ + PORTCR(50, 0xE6052032), /* PORT50CR */ + PORTCR(51, 0xE6052033), /* PORT51CR */ + PORTCR(52, 0xE6052034), /* PORT52CR */ + PORTCR(53, 0xE6052035), /* PORT53CR */ + PORTCR(54, 0xE6052036), /* PORT54CR */ + PORTCR(55, 0xE6052037), /* PORT55CR */ + PORTCR(56, 0xE6052038), /* PORT56CR */ + PORTCR(57, 0xE6052039), /* PORT57CR */ + PORTCR(58, 0xE605203A), /* PORT58CR */ + PORTCR(59, 0xE605203B), /* PORT59CR */ + PORTCR(60, 0xE605203C), /* PORT60CR */ + PORTCR(61, 0xE605203D), /* PORT61CR */ + PORTCR(62, 0xE605203E), /* PORT62CR */ + PORTCR(63, 0xE605203F), /* PORT63CR */ + PORTCR(64, 0xE6052040), /* PORT64CR */ + PORTCR(65, 0xE6052041), /* PORT65CR */ + PORTCR(66, 0xE6052042), /* PORT66CR */ + PORTCR(67, 0xE6052043), /* PORT67CR */ + PORTCR(68, 0xE6052044), /* PORT68CR */ + PORTCR(69, 0xE6052045), /* PORT69CR */ + PORTCR(70, 0xE6052046), /* PORT70CR */ + PORTCR(71, 0xE6052047), /* PORT71CR */ + PORTCR(72, 0xE6052048), /* PORT72CR */ + PORTCR(73, 0xE6052049), /* PORT73CR */ + PORTCR(74, 0xE605204A), /* PORT74CR */ + PORTCR(75, 0xE605204B), /* PORT75CR */ + PORTCR(76, 0xE605004C), /* PORT76CR */ + PORTCR(77, 0xE605004D), /* PORT77CR */ + PORTCR(78, 0xE605004E), /* PORT78CR */ + PORTCR(79, 0xE605004F), /* PORT79CR */ + PORTCR(80, 0xE6050050), /* PORT80CR */ + PORTCR(81, 0xE6050051), /* PORT81CR */ + PORTCR(82, 0xE6050052), /* PORT82CR */ + PORTCR(83, 0xE6050053), /* PORT83CR */ + PORTCR(84, 0xE6050054), /* PORT84CR */ + PORTCR(85, 0xE6050055), /* PORT85CR */ + PORTCR(86, 0xE6050056), /* PORT86CR */ + PORTCR(87, 0xE6050057), /* PORT87CR */ + PORTCR(88, 0xE6050058), /* PORT88CR */ + PORTCR(89, 0xE6050059), /* PORT89CR */ + PORTCR(90, 0xE605005A), /* PORT90CR */ + PORTCR(91, 0xE605005B), /* PORT91CR */ + PORTCR(92, 0xE605005C), /* PORT92CR */ + PORTCR(93, 0xE605005D), /* PORT93CR */ + PORTCR(94, 0xE605005E), /* PORT94CR */ + PORTCR(95, 0xE605005F), /* PORT95CR */ + PORTCR(96, 0xE6050060), /* PORT96CR */ + PORTCR(97, 0xE6050061), /* PORT97CR */ + PORTCR(98, 0xE6050062), /* PORT98CR */ + PORTCR(99, 0xE6050063), /* PORT99CR */ + PORTCR(100, 0xE6053064), /* PORT100CR */ + PORTCR(101, 0xE6053065), /* PORT101CR */ + PORTCR(102, 0xE6053066), /* PORT102CR */ + PORTCR(103, 0xE6053067), /* PORT103CR */ + PORTCR(104, 0xE6053068), /* PORT104CR */ + PORTCR(105, 0xE6053069), /* PORT105CR */ + PORTCR(106, 0xE605306A), /* PORT106CR */ + PORTCR(107, 0xE605306B), /* PORT107CR */ + PORTCR(108, 0xE605306C), /* PORT108CR */ + PORTCR(109, 0xE605306D), /* PORT109CR */ + PORTCR(110, 0xE605306E), /* PORT110CR */ + PORTCR(111, 0xE605306F), /* PORT111CR */ + PORTCR(112, 0xE6053070), /* PORT112CR */ + PORTCR(113, 0xE6053071), /* PORT113CR */ + PORTCR(114, 0xE6053072), /* PORT114CR */ + PORTCR(115, 0xE6053073), /* PORT115CR */ + PORTCR(116, 0xE6053074), /* PORT116CR */ + PORTCR(117, 0xE6053075), /* PORT117CR */ + PORTCR(118, 0xE6053076), /* PORT118CR */ + PORTCR(119, 0xE6053077), /* PORT119CR */ + PORTCR(120, 0xE6053078), /* PORT120CR */ + PORTCR(121, 0xE6050079), /* PORT121CR */ + PORTCR(122, 0xE605007A), /* PORT122CR */ + PORTCR(123, 0xE605007B), /* PORT123CR */ + PORTCR(124, 0xE605007C), /* PORT124CR */ + PORTCR(125, 0xE605007D), /* PORT125CR */ + PORTCR(126, 0xE605007E), /* PORT126CR */ + PORTCR(127, 0xE605007F), /* PORT127CR */ + PORTCR(128, 0xE6050080), /* PORT128CR */ + PORTCR(129, 0xE6050081), /* PORT129CR */ + PORTCR(130, 0xE6050082), /* PORT130CR */ + PORTCR(131, 0xE6050083), /* PORT131CR */ + PORTCR(132, 0xE6050084), /* PORT132CR */ + PORTCR(133, 0xE6050085), /* PORT133CR */ + PORTCR(134, 0xE6050086), /* PORT134CR */ + PORTCR(135, 0xE6050087), /* PORT135CR */ + PORTCR(136, 0xE6050088), /* PORT136CR */ + PORTCR(137, 0xE6050089), /* PORT137CR */ + PORTCR(138, 0xE605008A), /* PORT138CR */ + PORTCR(139, 0xE605008B), /* PORT139CR */ + PORTCR(140, 0xE605008C), /* PORT140CR */ + PORTCR(141, 0xE605008D), /* PORT141CR */ + PORTCR(142, 0xE605008E), /* PORT142CR */ + PORTCR(143, 0xE605008F), /* PORT143CR */ + PORTCR(144, 0xE6050090), /* PORT144CR */ + PORTCR(145, 0xE6050091), /* PORT145CR */ + PORTCR(146, 0xE6050092), /* PORT146CR */ + PORTCR(147, 0xE6050093), /* PORT147CR */ + PORTCR(148, 0xE6050094), /* PORT148CR */ + PORTCR(149, 0xE6050095), /* PORT149CR */ + PORTCR(150, 0xE6050096), /* PORT150CR */ + PORTCR(151, 0xE6050097), /* PORT151CR */ + PORTCR(152, 0xE6053098), /* PORT152CR */ + PORTCR(153, 0xE6053099), /* PORT153CR */ + PORTCR(154, 0xE605309A), /* PORT154CR */ + PORTCR(155, 0xE605309B), /* PORT155CR */ + PORTCR(156, 0xE605009C), /* PORT156CR */ + PORTCR(157, 0xE605009D), /* PORT157CR */ + PORTCR(158, 0xE605009E), /* PORT158CR */ + PORTCR(159, 0xE605009F), /* PORT159CR */ + PORTCR(160, 0xE60500A0), /* PORT160CR */ + PORTCR(161, 0xE60500A1), /* PORT161CR */ + PORTCR(162, 0xE60500A2), /* PORT162CR */ + PORTCR(163, 0xE60500A3), /* PORT163CR */ + PORTCR(164, 0xE60500A4), /* PORT164CR */ + PORTCR(165, 0xE60500A5), /* PORT165CR */ + PORTCR(166, 0xE60500A6), /* PORT166CR */ + PORTCR(167, 0xE60520A7), /* PORT167CR */ + PORTCR(168, 0xE60520A8), /* PORT168CR */ + PORTCR(169, 0xE60520A9), /* PORT169CR */ + PORTCR(170, 0xE60520AA), /* PORT170CR */ + PORTCR(171, 0xE60520AB), /* PORT171CR */ + PORTCR(172, 0xE60520AC), /* PORT172CR */ + PORTCR(173, 0xE60520AD), /* PORT173CR */ + PORTCR(174, 0xE60520AE), /* PORT174CR */ + PORTCR(175, 0xE60520AF), /* PORT175CR */ + PORTCR(176, 0xE60520B0), /* PORT176CR */ + PORTCR(177, 0xE60520B1), /* PORT177CR */ + PORTCR(178, 0xE60520B2), /* PORT178CR */ + PORTCR(179, 0xE60520B3), /* PORT179CR */ + PORTCR(180, 0xE60520B4), /* PORT180CR */ + PORTCR(181, 0xE60520B5), /* PORT181CR */ + PORTCR(182, 0xE60520B6), /* PORT182CR */ + PORTCR(183, 0xE60520B7), /* PORT183CR */ + PORTCR(184, 0xE60520B8), /* PORT184CR */ + PORTCR(185, 0xE60520B9), /* PORT185CR */ + PORTCR(186, 0xE60520BA), /* PORT186CR */ + PORTCR(187, 0xE60520BB), /* PORT187CR */ + PORTCR(188, 0xE60520BC), /* PORT188CR */ + PORTCR(189, 0xE60520BD), /* PORT189CR */ + PORTCR(190, 0xE60520BE), /* PORT190CR */ + + { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + 0, 0, 0, 0, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_8_0, MSEL1CR_8_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + 0, 0, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + 0, 0, + MSEL1CR_0_0, MSEL1CR_0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, + MSEL3CR_9_0, MSEL3CR_9_1, + 0, 0, 0, 0, + MSEL3CR_6_0, MSEL3CR_6_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + 0, 0, 0, 0, + 0, 0, + MSEL4CR_10_0, MSEL4CR_10_1, + 0, 0, 0, 0, + 0, 0, + MSEL4CR_6_0, MSEL4CR_6_1, + 0, 0, + MSEL4CR_4_0, MSEL4CR_4_1, + 0, 0, 0, 0, + MSEL4CR_1_0, MSEL4CR_1_1, + 0, 0, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, + } + }, + { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + 0, 0, 0, 0, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, + } + }, + { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, + } + }, + { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, + } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, + } + }, + { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, + } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) { + 0, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) { + 0, 0, 0, 0, + 0, 0, 0, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) { + 0, 0, 0, 0, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { }, +}; + +static struct pinmux_info sh7372_pinmux_info = { + .name = "sh7372_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_SDENC_DV_CLKI, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7372_pinmux_init(void) +{ + register_pinmux(&sh7372_pinmux_info); +} -- GitLab From 1b7e0677fb1513605df327ae2987d17e0b2ae3ea Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 17 Feb 2010 09:30:14 +0000 Subject: [PATCH 215/370] ARM: mach-shmobile: SMSC 9220 support for AP4EVB. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 94b545b3fe820..70277e0738083 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -27,11 +27,15 @@ #include #include #include +#include +#include #include +#include #include #include #include +/* MTD */ static struct mtd_partition nor_flash_partitions[] = { { .name = "loader", @@ -84,9 +88,37 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* SMSC 9220 */ +static struct resource smc911x_resources[] = { + { + .start = 0x14000000, + .end = 0x16000000 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 6, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct smsc911x_platform_config smsc911x_info = { + .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device smc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, + .dev = { + .platform_data = &smsc911x_info, + }, +}; static struct platform_device *ap4evb_devices[] __initdata = { &nor_flash_device, + &smc911x_device, }; static struct map_desc ap4evb_io_desc[] __initdata = { @@ -113,6 +145,12 @@ static void __init ap4evb_map_io(void) static void __init ap4evb_init(void) { + sh7372_pinmux_init(); + + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); -- GitLab From f601441916d1e19291d0b4f044b4a7551e2924d0 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 17 Feb 2010 12:33:23 +0200 Subject: [PATCH 216/370] imxfb: add support for i.MX25 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The commit also introduces the HAVE_FB_IMX config that is to be selected from the MX25 platform config. Once this commit gets merged, the two other i.MX archs, ARCH_MX1 and ARCH_MX2, should follow this one. Signed-off-by: Baruch Siach Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 1 + drivers/video/Kconfig | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index cea51a0ae9f75..cdee9176a7753 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -24,6 +24,7 @@ config ARCH_MX25 bool "MX25-based" select CPU_ARM926T select COMMON_CLKDEV + select HAVE_FB_IMX help This enables support for systems based on the Freescale i.MX25 family diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a5c303a63735..83d40ed2f2d65 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -400,9 +400,12 @@ config FB_SA1100 If you plan to use the LCD display with your SA-1100 system, say Y here. +config HAVE_FB_IMX + bool + config FB_IMX tristate "Motorola i.MX LCD support" - depends on FB && (ARCH_MX1 || ARCH_MX2) + depends on FB && (HAVE_FB_IMX || ARCH_MX1 || ARCH_MX2) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- GitLab From 04a03e5fe3d337242e5c0a9c93d2fd24cff545ef Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 17 Feb 2010 12:33:24 +0200 Subject: [PATCH 217/370] mx25: add platform support for imxfb Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 12 ++++++++++++ arch/arm/mach-mx25/devices.c | 23 +++++++++++++++++++++++ arch/arm/mach-mx25/devices.h | 1 + arch/arm/plat-mxc/include/mach/mx25.h | 2 ++ 4 files changed, 38 insertions(+) diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 744b52a613fc7..56bf958d8c34e 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk) return get_rate_per(5); } +static unsigned long get_rate_lcdc(struct clk *clk) +{ + return get_rate_per(7); +} + static unsigned long get_rate_otg(struct clk *clk) { return 48000000; /* FIXME */ @@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); +DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); +DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); @@ -183,6 +190,7 @@ DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -216,6 +224,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) + _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) }; int __init mx25_clocks_init(void) @@ -233,6 +242,9 @@ int __init mx25_clocks_init(void) __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); + /* Clock source for lcdc is upll */ + __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); + mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index b0b75fc99058f..3f4b8a0b5facf 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -477,3 +477,26 @@ struct platform_device mx25_rtc_device = { .num_resources = ARRAY_SIZE(mx25_rtc_resources), .resource = mx25_rtc_resources, }; + +static struct resource mx25_fb_resources[] = { + { + .start = MX25_LCDC_BASE_ADDR, + .end = MX25_LCDC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_LCDC, + .end = MX25_INT_LCDC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx25_fb_device = { + .name = "imx-fb", + .id = 0, + .resource = mx25_fb_resources, + .num_resources = ARRAY_SIZE(mx25_fb_resources), + .dev = { + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index 37e6a08214470..39560e13bc0d5 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -20,3 +20,4 @@ extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; extern struct platform_device mxc_nand_device; extern struct platform_device mx25_rtc_device; +extern struct platform_device mx25_fb_device; diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4ef9d5332b4a8..4eb6e334bda58 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -33,10 +33,12 @@ #define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 +#define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_INT_DRYICE 25 #define MX25_INT_FEC 57 #define MX25_INT_NANDFC 33 +#define MX25_INT_LCDC 39 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) #define UART1_BASE_ADDR MX25_UART1_BASE_ADDR -- GitLab From 0f547dc1f6e4faf05fd9946c6b7e9a828e7f901e Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 17 Feb 2010 12:33:25 +0200 Subject: [PATCH 218/370] mx25pdk: add LCD support Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/mach-mx25pdk.c | 55 +++++++++++++++++++++ arch/arm/plat-mxc/include/mach/iomux-mx25.h | 2 + 2 files changed, 57 insertions(+) diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c index 10be38eb82a88..99b9463ca1547 100644 --- a/arch/arm/mach-mx25/mach-mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25pdk.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "devices.h" #include @@ -54,6 +55,31 @@ static struct pad_desc mx25pdk_pads[] = { MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */ MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */ + + /* LCD */ + MX25_PAD_LD0__LD0, + MX25_PAD_LD1__LD1, + MX25_PAD_LD2__LD2, + MX25_PAD_LD3__LD3, + MX25_PAD_LD4__LD4, + MX25_PAD_LD5__LD5, + MX25_PAD_LD6__LD6, + MX25_PAD_LD7__LD7, + MX25_PAD_LD8__LD8, + MX25_PAD_LD9__LD9, + MX25_PAD_LD10__LD10, + MX25_PAD_LD11__LD11, + MX25_PAD_LD12__LD12, + MX25_PAD_LD13__LD13, + MX25_PAD_LD14__LD14, + MX25_PAD_LD15__LD15, + MX25_PAD_GPIO_E__LD16, + MX25_PAD_GPIO_F__LD17, + MX25_PAD_HSYNC__HSYNC, + MX25_PAD_VSYNC__VSYNC, + MX25_PAD_LSCLK__LSCLK, + MX25_PAD_OE_ACD__OE_ACD, + MX25_PAD_CONTRAST__CONTRAST, }; static struct fec_platform_data mx25_fec_pdata = { @@ -83,6 +109,34 @@ static struct mxc_nand_platform_data mx25pdk_nand_board_info = { .flash_bbt = 1, }; +static struct imx_fb_videomode mx25pdk_modes[] = { + { + .mode = { + .name = "CRT-VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39683, + .left_margin = 45, + .right_margin = 114, + .upper_margin = 33, + .lower_margin = 11, + .hsync_len = 1, + .vsync_len = 1, + }, + .bpp = 16, + .pcr = 0xFA208B80, + }, +}; + +static struct imx_fb_platform_data mx25pdk_fb_pdata = { + .mode = mx25pdk_modes, + .num_modes = ARRAY_SIZE(mx25pdk_modes), + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -92,6 +146,7 @@ static void __init mx25pdk_init(void) mxc_register_device(&mxc_usbh2, NULL); mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); mxc_register_device(&mx25_rtc_device, NULL); + mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index 9af494f0ab3da..5418d52c4a9d5 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -462,9 +462,11 @@ #define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) -- GitLab From b228b48e454007436a8e6ff1c6b6f4f6602fc45e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 18 Feb 2010 16:44:41 +0900 Subject: [PATCH 219/370] ARM: mach-shmobile: ap4evb: Add SCIFA0 support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 70277e0738083..4fd9ec8735d69 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -147,6 +147,10 @@ static void __init ap4evb_init(void) { sh7372_pinmux_init(); + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIFA0_TXD, NULL); + gpio_request(GPIO_FN_SCIFA0_RXD, NULL); + /* enable SMSC911X */ gpio_request(GPIO_FN_CS5A, NULL); gpio_request(GPIO_FN_IRQ6_39, NULL); -- GitLab From 02624a17896036c663fd5992c22919af8dad93ed Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 18 Feb 2010 17:58:19 +0900 Subject: [PATCH 220/370] ARM: mach-shmobile: ap4evb: Add tiny document Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 4fd9ec8735d69..41bc2487de4d9 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -35,6 +35,48 @@ #include #include +/* + * Address Interface BusWidth note + * ------------------------------------------------------------------ + * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON + * 0x0800_0000 user area - + * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF + * 0x1400_0000 Ether (LAN9220) 16bit + * 0x1600_0000 user area - cannot use with NAND + * 0x1800_0000 user area - + * 0x1A00_0000 - + * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit + */ + +/* + * NOR Flash ROM + * + * SW1 | SW2 | SW7 | NOR Flash ROM + * bit1 | bit1 bit2 | bit1 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | Area 0 + * OFF | ON OFF | OFF | Area 4 + */ + +/* + * NAND Flash ROM + * + * SW1 | SW2 | SW7 | NAND Flash ROM + * bit1 | bit1 bit2 | bit2 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | FCE 0 + * OFF | ON OFF | OFF | FCE 1 + */ + +/* + * SMSC 9220 + * + * SW1 SMSC 9220 + * ----------------------- + * ON access disable + * OFF access enable + */ + /* MTD */ static struct mtd_partition nor_flash_partitions[] = { { -- GitLab From 3501c9ae9fc5414d09c9a8d3a5452d2b167db916 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 10:45:40 +0900 Subject: [PATCH 221/370] ARM: S3C64XX: Move headers into machine include directory Move the register and GPIO definition files from plat-s3c64xx into the machine include direcotry as they are unlikely to be reused outside mach-s3c64xx. This move includes removing the empty and replacing it with the implementation. Signed-off-by: Ben Dooks --- .../include/mach}/gpio-bank-a.h | 2 +- .../include/mach}/gpio-bank-b.h | 2 +- .../include/mach}/gpio-bank-c.h | 2 +- .../include/mach}/gpio-bank-d.h | 2 +- .../include/mach}/gpio-bank-e.h | 2 +- .../include/mach}/gpio-bank-f.h | 2 +- .../include/mach}/gpio-bank-g.h | 2 +- .../include/mach}/gpio-bank-h.h | 2 +- .../include/mach}/gpio-bank-i.h | 2 +- .../include/mach}/gpio-bank-j.h | 2 +- .../include/mach}/gpio-bank-n.h | 2 +- .../include/mach}/gpio-bank-o.h | 2 +- .../include/mach}/gpio-bank-p.h | 2 +- .../include/mach}/gpio-bank-q.h | 2 +- .../mach-s3c64xx/include/mach/regs-clock.h | 148 ++++++++++++++++- .../include/mach}/regs-gpio-memport.h | 0 .../include/mach}/regs-gpio.h | 0 .../include/mach}/regs-modem.h | 0 .../include/mach}/regs-srom.h | 0 .../include/mach}/regs-sys.h | 0 .../include/mach}/regs-syscon-power.h | 0 arch/arm/mach-s3c64xx/mach-anw6410.c | 4 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 8 +- arch/arm/mach-s3c64xx/s3c6400.c | 2 +- arch/arm/mach-s3c64xx/s3c6410.c | 2 +- arch/arm/plat-s3c64xx/clock.c | 4 +- arch/arm/plat-s3c64xx/dev-audio.c | 9 +- arch/arm/plat-s3c64xx/dev-spi.c | 3 +- arch/arm/plat-s3c64xx/dma.c | 2 +- arch/arm/plat-s3c64xx/gpiolib.c | 2 +- arch/arm/plat-s3c64xx/include/plat/pm-core.h | 2 +- .../plat-s3c64xx/include/plat/regs-clock.h | 156 ------------------ arch/arm/plat-s3c64xx/irq-eint.c | 2 +- arch/arm/plat-s3c64xx/irq-pm.c | 2 +- arch/arm/plat-s3c64xx/pm.c | 12 +- arch/arm/plat-s3c64xx/s3c6400-clock.c | 2 +- arch/arm/plat-s3c64xx/setup-i2c0.c | 2 +- arch/arm/plat-s3c64xx/setup-i2c1.c | 2 +- arch/arm/plat-s3c64xx/sleep.S | 6 +- 39 files changed, 191 insertions(+), 207 deletions(-) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-a.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-b.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-c.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-d.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-e.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-f.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-g.h (95%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-h.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-i.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-j.h (95%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-n.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-o.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-p.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/gpio-bank-q.h (96%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-gpio-memport.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-gpio.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-modem.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-srom.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-sys.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/regs-syscon-power.h (100%) delete mode 100644 arch/arm/plat-s3c64xx/include/plat/regs-clock.h diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h index 9aa0e427d1134..34212e1a7e81d 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h similarity index 97% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h index 3933adb4d50a5..7232c037e6420 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h index e22b49f4f982b..db189ab1639a7 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h index 6fe4a49c26f0e..1a01cee7aca30 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h index 7fcf3d8e0a486..f057adb627ddf 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h similarity index 97% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h index f3faff974a189..62ab8f5e7835e 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h similarity index 95% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h index 35bbd2378e55a..b94954af1598b 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h similarity index 97% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h index 2ba1767512d7e..5d75aaad865e5 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h index ce9ebe3355669..4ceaa6098bc7a 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h similarity index 95% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h index 21a906299d30e..6f25cd079a406 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h index 569e761208819..d0aeda1cd9def 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h similarity index 97% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h index b09e12954b576..21868fa102d0f 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h similarity index 97% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h index 92f00517926b0..46bcfb63b8dea 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h similarity index 96% rename from arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h rename to arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h index 565e60aaee478..1712223487b0b 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index a6c7f4eb3a1b5..3ef62741e5d10 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -1,16 +1,156 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h +/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ * Ben Dooks + * http://armlinux.simtec.co.uk/ * - * S3C64XX - clock register compatibility with s3c24xx + * S3C64XX clock register definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include +#ifndef __PLAT_REGS_CLOCK_H +#define __PLAT_REGS_CLOCK_H __FILE__ + +#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S3C_APLL_LOCK S3C_CLKREG(0x00) +#define S3C_MPLL_LOCK S3C_CLKREG(0x04) +#define S3C_EPLL_LOCK S3C_CLKREG(0x08) +#define S3C_APLL_CON S3C_CLKREG(0x0C) +#define S3C_MPLL_CON S3C_CLKREG(0x10) +#define S3C_EPLL_CON0 S3C_CLKREG(0x14) +#define S3C_EPLL_CON1 S3C_CLKREG(0x18) +#define S3C_CLK_SRC S3C_CLKREG(0x1C) +#define S3C_CLK_DIV0 S3C_CLKREG(0x20) +#define S3C_CLK_DIV1 S3C_CLKREG(0x24) +#define S3C_CLK_DIV2 S3C_CLKREG(0x28) +#define S3C_CLK_OUT S3C_CLKREG(0x2C) +#define S3C_HCLK_GATE S3C_CLKREG(0x30) +#define S3C_PCLK_GATE S3C_CLKREG(0x34) +#define S3C_SCLK_GATE S3C_CLKREG(0x38) +#define S3C_MEM0_GATE S3C_CLKREG(0x3C) + +/* CLKDIV0 */ +#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) +#define S3C6400_CLKDIV0_PCLK_SHIFT (12) +#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) +#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) +#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) +#define S3C6400_CLKDIV0_HCLK_SHIFT (8) +#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S3C6400_CLKDIV0_MPLL_SHIFT (4) + +#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) +#define S3C6400_CLKDIV0_ARM_SHIFT (0) + +/* HCLK GATE Registers */ +#define S3C_CLKCON_HCLK_3DSE (1<<31) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) +#define S3C_CLKCON_HCLK_IROM (1<<25) +#define S3C_CLKCON_HCLK_DDR1 (1<<24) +#define S3C_CLKCON_HCLK_DDR0 (1<<23) +#define S3C_CLKCON_HCLK_MEM1 (1<<22) +#define S3C_CLKCON_HCLK_MEM0 (1<<21) +#define S3C_CLKCON_HCLK_USB (1<<20) +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) +#define S3C_CLKCON_HCLK_MDP (1<<16) +#define S3C_CLKCON_HCLK_DHOST (1<<15) +#define S3C_CLKCON_HCLK_IHOST (1<<14) +#define S3C_CLKCON_HCLK_DMA1 (1<<13) +#define S3C_CLKCON_HCLK_DMA0 (1<<12) +#define S3C_CLKCON_HCLK_JPEG (1<<11) +#define S3C_CLKCON_HCLK_CAMIF (1<<10) +#define S3C_CLKCON_HCLK_SCALER (1<<9) +#define S3C_CLKCON_HCLK_2D (1<<8) +#define S3C_CLKCON_HCLK_TV (1<<7) +#define S3C_CLKCON_HCLK_POST0 (1<<5) +#define S3C_CLKCON_HCLK_ROT (1<<4) +#define S3C_CLKCON_HCLK_LCD (1<<3) +#define S3C_CLKCON_HCLK_TZIC (1<<2) +#define S3C_CLKCON_HCLK_INTC (1<<1) +#define S3C_CLKCON_HCLK_MFC (1<<0) + +/* PCLK GATE Registers */ +#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) +#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) +#define S3C_CLKCON_PCLK_SKEY (1<<24) +#define S3C_CLKCON_PCLK_CHIPID (1<<23) +#define S3C_CLKCON_PCLK_SPI1 (1<<22) +#define S3C_CLKCON_PCLK_SPI0 (1<<21) +#define S3C_CLKCON_PCLK_HSIRX (1<<20) +#define S3C_CLKCON_PCLK_HSITX (1<<19) +#define S3C_CLKCON_PCLK_GPIO (1<<18) +#define S3C_CLKCON_PCLK_IIC (1<<17) +#define S3C_CLKCON_PCLK_IIS1 (1<<16) +#define S3C_CLKCON_PCLK_IIS0 (1<<15) +#define S3C_CLKCON_PCLK_AC97 (1<<14) +#define S3C_CLKCON_PCLK_TZPC (1<<13) +#define S3C_CLKCON_PCLK_TSADC (1<<12) +#define S3C_CLKCON_PCLK_KEYPAD (1<<11) +#define S3C_CLKCON_PCLK_IRDA (1<<10) +#define S3C_CLKCON_PCLK_PCM1 (1<<9) +#define S3C_CLKCON_PCLK_PCM0 (1<<8) +#define S3C_CLKCON_PCLK_PWM (1<<7) +#define S3C_CLKCON_PCLK_RTC (1<<6) +#define S3C_CLKCON_PCLK_WDT (1<<5) +#define S3C_CLKCON_PCLK_UART3 (1<<4) +#define S3C_CLKCON_PCLK_UART2 (1<<3) +#define S3C_CLKCON_PCLK_UART1 (1<<2) +#define S3C_CLKCON_PCLK_UART0 (1<<1) +#define S3C_CLKCON_PCLK_MFC (1<<0) + +/* SCLK GATE Registers */ +#define S3C_CLKCON_SCLK_UHOST (1<<30) +#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) +#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) +#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) +#define S3C_CLKCON_SCLK_MMC2 (1<<26) +#define S3C_CLKCON_SCLK_MMC1 (1<<25) +#define S3C_CLKCON_SCLK_MMC0 (1<<24) +#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) +#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) +#define S3C_CLKCON_SCLK_SPI1 (1<<21) +#define S3C_CLKCON_SCLK_SPI0 (1<<20) +#define S3C_CLKCON_SCLK_DAC27 (1<<19) +#define S3C_CLKCON_SCLK_TV27 (1<<18) +#define S3C_CLKCON_SCLK_SCALER27 (1<<17) +#define S3C_CLKCON_SCLK_SCALER (1<<16) +#define S3C_CLKCON_SCLK_LCD27 (1<<15) +#define S3C_CLKCON_SCLK_LCD (1<<14) +#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) +#define S3C6410_CLKCON_FIMC (1<<13) +#define S3C_CLKCON_SCLK_POST0_27 (1<<12) +#define S3C6400_CLKCON_SCLK_POST1 (1<<11) +#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) +#define S3C_CLKCON_SCLK_POST0 (1<<10) +#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) +#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) +#define S3C_CLKCON_SCLK_SECUR (1<<7) +#define S3C_CLKCON_SCLK_IRDA (1<<6) +#define S3C_CLKCON_SCLK_UART (1<<5) +#define S3C_CLKCON_SCLK_ONENAND (1<<4) +#define S3C_CLKCON_SCLK_MFC (1<<3) +#define S3C_CLKCON_SCLK_CAM (1<<2) +#define S3C_CLKCON_SCLK_JPEG (1<<1) + +/* CLKSRC */ + +#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) +#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) +#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) +#define S3C6400_CLKSRC_MFC (1 << 4) +#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h rename to arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-gpio.h rename to arch/arm/mach-s3c64xx/include/mach/regs-gpio.h diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-modem.h b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-modem.h rename to arch/arm/mach-s3c64xx/include/mach/regs-modem.h diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-srom.h rename to arch/arm/mach-s3c64xx/include/mach/regs-srom.h diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-sys.h rename to arch/arm/mach-s3c64xx/include/mach/regs-sys.h diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h rename to arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 49032a85f6f85..06d8fe579e102 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -49,8 +49,8 @@ #include #include #include -#include -#include +#include +#include /* DM9000 */ #define ANW6410_PA_DM9000 (0x18000000) diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 6e6ff354da429..021670e39d3ea 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -46,10 +46,10 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 884858a78d496..2fba1b263fed5 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -30,7 +30,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 185f15cbb701f..b881d6a50b118 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 2989c3a2e94d3..64439de206cb7 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -21,8 +21,8 @@ #include #include -#include -#include +#include +#include #include #include #include diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index f6b7bfb519d7b..aaffb80667070 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c @@ -19,12 +19,13 @@ #include #include -#include -#include -#include -#include #include +#include +#include +#include +#include + static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) { switch (pdev->id) { diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c index ca10388d7ed15..0c20d27d9b65a 100644 --- a/arch/arm/plat-s3c64xx/dev-spi.c +++ b/arch/arm/plat-s3c64xx/dev-spi.c @@ -16,11 +16,10 @@ #include #include #include +#include #include - #include -#include #include #include diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c index d554b936fcfb3..0e0edf75e8edd 100644 --- a/arch/arm/plat-s3c64xx/dma.c +++ b/arch/arm/plat-s3c64xx/dma.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index b6e3f55321fa6..66e6794481d2f 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include /* GPIO bank summary: * diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h index d347de3ba0dc6..61b8aae76d3da 100644 --- a/arch/arm/plat-s3c64xx/include/plat/pm-core.h +++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h @@ -12,7 +12,7 @@ * published by the Free Software Foundation. */ -#include +#include static inline void s3c_pm_debug_init_uart(void) { diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h deleted file mode 100644 index 3ef62741e5d10..0000000000000 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ /dev/null @@ -1,156 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_CLOCK_H -#define __PLAT_REGS_CLOCK_H __FILE__ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_APLL_LOCK S3C_CLKREG(0x00) -#define S3C_MPLL_LOCK S3C_CLKREG(0x04) -#define S3C_EPLL_LOCK S3C_CLKREG(0x08) -#define S3C_APLL_CON S3C_CLKREG(0x0C) -#define S3C_MPLL_CON S3C_CLKREG(0x10) -#define S3C_EPLL_CON0 S3C_CLKREG(0x14) -#define S3C_EPLL_CON1 S3C_CLKREG(0x18) -#define S3C_CLK_SRC S3C_CLKREG(0x1C) -#define S3C_CLK_DIV0 S3C_CLKREG(0x20) -#define S3C_CLK_DIV1 S3C_CLKREG(0x24) -#define S3C_CLK_DIV2 S3C_CLKREG(0x28) -#define S3C_CLK_OUT S3C_CLKREG(0x2C) -#define S3C_HCLK_GATE S3C_CLKREG(0x30) -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C_SCLK_GATE S3C_CLKREG(0x38) -#define S3C_MEM0_GATE S3C_CLKREG(0x3C) - -/* CLKDIV0 */ -#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) -#define S3C6400_CLKDIV0_PCLK_SHIFT (12) -#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) -#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) -#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) -#define S3C6400_CLKDIV0_HCLK_SHIFT (8) -#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) -#define S3C6400_CLKDIV0_MPLL_SHIFT (4) - -#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) -#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) -#define S3C6400_CLKDIV0_ARM_SHIFT (0) - -/* HCLK GATE Registers */ -#define S3C_CLKCON_HCLK_3DSE (1<<31) -#define S3C_CLKCON_HCLK_UHOST (1<<29) -#define S3C_CLKCON_HCLK_SECUR (1<<28) -#define S3C_CLKCON_HCLK_SDMA1 (1<<27) -#define S3C_CLKCON_HCLK_SDMA0 (1<<26) -#define S3C_CLKCON_HCLK_IROM (1<<25) -#define S3C_CLKCON_HCLK_DDR1 (1<<24) -#define S3C_CLKCON_HCLK_DDR0 (1<<23) -#define S3C_CLKCON_HCLK_MEM1 (1<<22) -#define S3C_CLKCON_HCLK_MEM0 (1<<21) -#define S3C_CLKCON_HCLK_USB (1<<20) -#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) -#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) -#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) -#define S3C_CLKCON_HCLK_MDP (1<<16) -#define S3C_CLKCON_HCLK_DHOST (1<<15) -#define S3C_CLKCON_HCLK_IHOST (1<<14) -#define S3C_CLKCON_HCLK_DMA1 (1<<13) -#define S3C_CLKCON_HCLK_DMA0 (1<<12) -#define S3C_CLKCON_HCLK_JPEG (1<<11) -#define S3C_CLKCON_HCLK_CAMIF (1<<10) -#define S3C_CLKCON_HCLK_SCALER (1<<9) -#define S3C_CLKCON_HCLK_2D (1<<8) -#define S3C_CLKCON_HCLK_TV (1<<7) -#define S3C_CLKCON_HCLK_POST0 (1<<5) -#define S3C_CLKCON_HCLK_ROT (1<<4) -#define S3C_CLKCON_HCLK_LCD (1<<3) -#define S3C_CLKCON_HCLK_TZIC (1<<2) -#define S3C_CLKCON_HCLK_INTC (1<<1) -#define S3C_CLKCON_HCLK_MFC (1<<0) - -/* PCLK GATE Registers */ -#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) -#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) -#define S3C_CLKCON_PCLK_SKEY (1<<24) -#define S3C_CLKCON_PCLK_CHIPID (1<<23) -#define S3C_CLKCON_PCLK_SPI1 (1<<22) -#define S3C_CLKCON_PCLK_SPI0 (1<<21) -#define S3C_CLKCON_PCLK_HSIRX (1<<20) -#define S3C_CLKCON_PCLK_HSITX (1<<19) -#define S3C_CLKCON_PCLK_GPIO (1<<18) -#define S3C_CLKCON_PCLK_IIC (1<<17) -#define S3C_CLKCON_PCLK_IIS1 (1<<16) -#define S3C_CLKCON_PCLK_IIS0 (1<<15) -#define S3C_CLKCON_PCLK_AC97 (1<<14) -#define S3C_CLKCON_PCLK_TZPC (1<<13) -#define S3C_CLKCON_PCLK_TSADC (1<<12) -#define S3C_CLKCON_PCLK_KEYPAD (1<<11) -#define S3C_CLKCON_PCLK_IRDA (1<<10) -#define S3C_CLKCON_PCLK_PCM1 (1<<9) -#define S3C_CLKCON_PCLK_PCM0 (1<<8) -#define S3C_CLKCON_PCLK_PWM (1<<7) -#define S3C_CLKCON_PCLK_RTC (1<<6) -#define S3C_CLKCON_PCLK_WDT (1<<5) -#define S3C_CLKCON_PCLK_UART3 (1<<4) -#define S3C_CLKCON_PCLK_UART2 (1<<3) -#define S3C_CLKCON_PCLK_UART1 (1<<2) -#define S3C_CLKCON_PCLK_UART0 (1<<1) -#define S3C_CLKCON_PCLK_MFC (1<<0) - -/* SCLK GATE Registers */ -#define S3C_CLKCON_SCLK_UHOST (1<<30) -#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) -#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) -#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) -#define S3C_CLKCON_SCLK_MMC2 (1<<26) -#define S3C_CLKCON_SCLK_MMC1 (1<<25) -#define S3C_CLKCON_SCLK_MMC0 (1<<24) -#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) -#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) -#define S3C_CLKCON_SCLK_SPI1 (1<<21) -#define S3C_CLKCON_SCLK_SPI0 (1<<20) -#define S3C_CLKCON_SCLK_DAC27 (1<<19) -#define S3C_CLKCON_SCLK_TV27 (1<<18) -#define S3C_CLKCON_SCLK_SCALER27 (1<<17) -#define S3C_CLKCON_SCLK_SCALER (1<<16) -#define S3C_CLKCON_SCLK_LCD27 (1<<15) -#define S3C_CLKCON_SCLK_LCD (1<<14) -#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) -#define S3C6410_CLKCON_FIMC (1<<13) -#define S3C_CLKCON_SCLK_POST0_27 (1<<12) -#define S3C6400_CLKCON_SCLK_POST1 (1<<11) -#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) -#define S3C_CLKCON_SCLK_POST0 (1<<10) -#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) -#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) -#define S3C_CLKCON_SCLK_SECUR (1<<7) -#define S3C_CLKCON_SCLK_IRDA (1<<6) -#define S3C_CLKCON_SCLK_UART (1<<5) -#define S3C_CLKCON_SCLK_ONENAND (1<<4) -#define S3C_CLKCON_SCLK_MFC (1<<3) -#define S3C_CLKCON_SCLK_CAM (1<<2) -#define S3C_CLKCON_SCLK_JPEG (1<<1) - -/* CLKSRC */ - -#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) -#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) -#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) -#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) -#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) -#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) -#define S3C6400_CLKSRC_MFC (1 << 4) - -#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index ebdf183a09116..5682d6a7f4af9 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c index ca523b5d4c171..da1bec64b9dad 100644 --- a/arch/arm/plat-s3c64xx/irq-pm.c +++ b/arch/arm/plat-s3c64xx/irq-pm.c @@ -23,7 +23,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c index 47632fc7eb661..b8ac4597fad70 100644 --- a/arch/arm/plat-s3c64xx/pm.c +++ b/arch/arm/plat-s3c64xx/pm.c @@ -20,14 +20,14 @@ #include #include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK -#include +#include void s3c_pm_debug_smdkled(u32 set, u32 clear) { diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index cb2bf4bff0514..85f7bb053f727 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -27,7 +27,7 @@ #include -#include +#include #include #include #include diff --git a/arch/arm/plat-s3c64xx/setup-i2c0.c b/arch/arm/plat-s3c64xx/setup-i2c0.c index 3644807637288..d1b11e6e77e83 100644 --- a/arch/arm/plat-s3c64xx/setup-i2c0.c +++ b/arch/arm/plat-s3c64xx/setup-i2c0.c @@ -18,8 +18,8 @@ struct platform_device; /* don't need the contents */ #include +#include #include -#include #include void s3c_i2c0_cfg_gpio(struct platform_device *dev) diff --git a/arch/arm/plat-s3c64xx/setup-i2c1.c b/arch/arm/plat-s3c64xx/setup-i2c1.c index bbe229bd90ca9..2dce57d8c6f8c 100644 --- a/arch/arm/plat-s3c64xx/setup-i2c1.c +++ b/arch/arm/plat-s3c64xx/setup-i2c1.c @@ -18,8 +18,8 @@ struct platform_device; /* don't need the contents */ #include +#include #include -#include #include void s3c_i2c1_cfg_gpio(struct platform_device *dev) diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S index 8e71fe90a3733..b2ef44317368a 100644 --- a/arch/arm/plat-s3c64xx/sleep.S +++ b/arch/arm/plat-s3c64xx/sleep.S @@ -1,4 +1,4 @@ -/* linux/0arch/arm/plat-s3c64xx/sleep.S +/* linux/arch/arm/plat-s3c64xx/sleep.S * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics @@ -19,8 +19,8 @@ #undef S3C64XX_VA_GPIO #define S3C64XX_VA_GPIO (0x0) -#include -#include +#include +#include #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) -- GitLab From ed618aff8a952f712caf1d475e0947a32a8b6606 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 11:07:23 +0900 Subject: [PATCH 222/370] ARM: S3C64XX: Move IRQ support into mach-s3c64xx Move IRQ support to mach-s3c64xx as it is unlikely to be re-used outside this machine. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Makefile | 7 + .../mach-s3c64xx/include/mach/entry-macro.S | 2 +- arch/arm/mach-s3c64xx/include/mach/irqs.h | 210 ++++++++++++++++- .../{plat-s3c64xx => mach-s3c64xx}/irq-eint.c | 0 .../{plat-s3c64xx => mach-s3c64xx}/irq-pm.c | 0 arch/arm/{plat-s3c64xx => mach-s3c64xx}/irq.c | 0 arch/arm/plat-s3c64xx/Makefile | 3 - arch/arm/plat-s3c64xx/include/plat/irqs.h | 214 ------------------ 8 files changed, 212 insertions(+), 224 deletions(-) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/irq-eint.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/irq-pm.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/irq.c (100%) delete mode 100644 arch/arm/plat-s3c64xx/include/plat/irqs.h diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 21ddf6b29280d..103bed48b46ec 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -15,10 +15,17 @@ obj- := obj-$(CONFIG_CPU_S3C6400) += s3c6400.o obj-$(CONFIG_CPU_S3C6410) += s3c6410.o +obj-y += irq.o +obj-y += irq-eint.o + # setup support obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o +# PM + +obj-$(CONFIG_PM) += irq-pm.o + # Machine support obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S index 33a8fe2408825..dd362604dccec 100644 --- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S +++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S @@ -13,6 +13,6 @@ */ #include -#include +#include #include diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 4c97f9a4370b5..44bb3e491b5c9 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -1,16 +1,214 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h +/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks * http://armlinux.simtec.co.uk/ * - * S3C6400 - IRQ definitions + * S3C64XX - IRQ support */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ +#ifndef __ASM_MACH_S3C64XX_IRQS_H +#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ -#include +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S3C_IRQ_OFFSET (32) + +#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) + +#define IRQ_VIC0_BASE S3C_IRQ(0) +#define IRQ_VIC1_BASE S3C_IRQ(32) + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S3CUART_BASE0 (16) +#define IRQ_S3CUART_BASE1 (20) +#define IRQ_S3CUART_BASE2 (24) +#define IRQ_S3CUART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) +#define UART_IRQ_MODEM (3) + +#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) + +/* VIC based IRQs */ + +#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) + +/* VIC0 */ + +#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) +#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) +#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) +#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) +#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) +#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) +#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) +#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) +#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) +#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) +#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) +#define IRQ_2D S3C64XX_IRQ_VIC0(11) +#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) +#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) +#define IRQ_BATF S3C64XX_IRQ_VIC0(14) +#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) +#define IRQ_MFC S3C64XX_IRQ_VIC0(16) +#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) +#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) +#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) +#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) +#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) +#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) +#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) +#define IRQ_WDT S3C64XX_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) +#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) +#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) +#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) +#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) +#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) +#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) +#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) +#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) +#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) +#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) +#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) +#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) +#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) +#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) +#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) +#define IRQ_NFC S3C64XX_IRQ_VIC1(13) +#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) +#define IRQ_USBH S3C64XX_IRQ_VIC1(15) +#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) +#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) +#define IRQ_IIC S3C64XX_IRQ_VIC1(18) +#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) +#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) +#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) +#define IRQ_MSM S3C64XX_IRQ_VIC1(22) +#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) +#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) +#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S3C64XX_IRQ_VIC1(26) +#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) +#define IRQ_SEC S3C64XX_IRQ_VIC1(29) +#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S3C64XX_IRQ_VIC1(31) + +#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) + +#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) +#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) +#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) +#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) +#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) + +/* compatibility for device defines */ + +#define IRQ_IIC1 IRQ_S3C6410_IIC1 + +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE + * which we place after the pair of VICs. */ + +#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) + +#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) +#define IRQ_EINT(x) S3C_EINT(x) +#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) + +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Define a group of interrupts for board-specific use (eg, for MFD + * interrupt controllers). */ +#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) + +#ifdef CONFIG_SMDK6410_WM1190_EV1 +#define IRQ_BOARD_NR 64 +#else +#define IRQ_BOARD_NR 16 +#endif + +#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_BOARD_END + 1) + +#endif /* __ASM_MACH_S3C64XX_IRQS_H */ -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c similarity index 100% rename from arch/arm/plat-s3c64xx/irq-eint.c rename to arch/arm/mach-s3c64xx/irq-eint.c diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c similarity index 100% rename from arch/arm/plat-s3c64xx/irq-pm.c rename to arch/arm/mach-s3c64xx/irq-pm.c diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c similarity index 100% rename from arch/arm/plat-s3c64xx/irq.c rename to arch/arm/mach-s3c64xx/irq.c diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 80255a5e17891..3e52dcdb36488 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -15,8 +15,6 @@ obj- := obj-y += dev-uart.o obj-y += dev-rtc.o obj-y += cpu.o -obj-y += irq.o -obj-y += irq-eint.o obj-y += clock.o obj-y += gpiolib.o @@ -30,7 +28,6 @@ obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += sleep.o -obj-$(CONFIG_PM) += irq-pm.o # DMA support diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h deleted file mode 100644 index a22758194e6d2..0000000000000 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ /dev/null @@ -1,214 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Common IRQ support - */ - -#ifndef __ASM_PLAT_S3C64XX_IRQS_H -#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - * note, since we're using the VICs, our start must be a - * mulitple of 32 to allow the common code to work - */ - -#define S3C_IRQ_OFFSET (32) - -#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) - -#define IRQ_VIC0_BASE S3C_IRQ(0) -#define IRQ_VIC1_BASE S3C_IRQ(32) - -/* UART interrupts, each UART has 4 intterupts per channel so - * use the space between the ISA and S3C main interrupts. Note, these - * are not in the same order as the S3C24XX series! */ - -#define IRQ_S3CUART_BASE0 (16) -#define IRQ_S3CUART_BASE1 (20) -#define IRQ_S3CUART_BASE2 (24) -#define IRQ_S3CUART_BASE3 (28) - -#define UART_IRQ_RXD (0) -#define UART_IRQ_ERR (1) -#define UART_IRQ_TXD (2) -#define UART_IRQ_MODEM (3) - -#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) - -/* VIC based IRQs */ - -#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) - -/* VIC0 */ - -#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) -#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) -#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) -#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) -#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) -#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) -#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) -#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) -#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) -#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) -#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) -#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) -#define IRQ_2D S3C64XX_IRQ_VIC0(11) -#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) -#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) -#define IRQ_BATF S3C64XX_IRQ_VIC0(14) -#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) -#define IRQ_MFC S3C64XX_IRQ_VIC0(16) -#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) -#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) -#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) -#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) -#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) -#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) -#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) -#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) -#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) -#define IRQ_WDT S3C64XX_IRQ_VIC0(26) -#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) -#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) -#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) -#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) -#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) - -/* VIC1 */ - -#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) -#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) -#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) -#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) -#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) -#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) -#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) -#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) -#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) -#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) -#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) -#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) -#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) -#define IRQ_NFC S3C64XX_IRQ_VIC1(13) -#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) -#define IRQ_USBH S3C64XX_IRQ_VIC1(15) -#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) -#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) -#define IRQ_IIC S3C64XX_IRQ_VIC1(18) -#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) -#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) -#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) -#define IRQ_MSM S3C64XX_IRQ_VIC1(22) -#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) -#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) -#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) -#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ -#define IRQ_OTG S3C64XX_IRQ_VIC1(26) -#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) -#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) -#define IRQ_SEC S3C64XX_IRQ_VIC1(29) -#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) -#define IRQ_TC IRQ_PENDN -#define IRQ_ADC S3C64XX_IRQ_VIC1(31) - -#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) - -#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) -#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) -#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) -#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) -#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) - -/* compatibility for device defines */ - -#define IRQ_IIC1 IRQ_S3C6410_IIC1 - -/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series - * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE - * which we place after the pair of VICs. */ - -#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) - -#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) -#define IRQ_EINT(x) S3C_EINT(x) -#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) - -/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) - * that they are sourced from the GPIO pins but with a different scheme for - * priority and source indication. - * - * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO - * interrupts, but for historical reasons they are kept apart from these - * next interrupts. - * - * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the - * machine specific support files. - */ - -#define IRQ_EINT_GROUP1_NR (15) -#define IRQ_EINT_GROUP2_NR (8) -#define IRQ_EINT_GROUP3_NR (5) -#define IRQ_EINT_GROUP4_NR (14) -#define IRQ_EINT_GROUP5_NR (7) -#define IRQ_EINT_GROUP6_NR (10) -#define IRQ_EINT_GROUP7_NR (16) -#define IRQ_EINT_GROUP8_NR (15) -#define IRQ_EINT_GROUP9_NR (9) - -#define IRQ_EINT_GROUP_BASE S3C_EINT(28) -#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) -#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) -#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) -#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) -#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) -#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) -#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) -#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) -#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) - -#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) - -/* Define a group of interrupts for board-specific use (eg, for MFD - * interrupt controllers). */ -#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) - -#ifdef CONFIG_SMDK6410_WM1190_EV1 -#define IRQ_BOARD_NR 64 -#else -#define IRQ_BOARD_NR 16 -#endif - -#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) - -/* Set the default NR_IRQS */ - -#define NR_IRQS (IRQ_BOARD_END + 1) - -#endif /* __ASM_PLAT_S3C64XX_IRQS_H */ - -- GitLab From 88fc68a280709f3fb9488986ab39eac330d17b6d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 11:19:18 +0900 Subject: [PATCH 223/370] ARM: S3C64XX: Move device and device setup into mach-s3c64xx Move the S3C64XX specific device and setup files into mach-s3c64xx as they are unlikely to be used outside of this code. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 26 +++++++++++++++++++ arch/arm/mach-s3c64xx/Makefile | 13 +++++++++- .../{plat-s3c64xx => mach-s3c64xx}/dev-adc.c | 0 .../dev-audio.c | 0 .../{plat-s3c64xx => mach-s3c64xx}/dev-rtc.c | 0 .../{plat-s3c64xx => mach-s3c64xx}/dev-spi.c | 2 +- .../{plat-s3c64xx => mach-s3c64xx}/dev-uart.c | 0 .../include/mach}/spi-clocks.h | 2 +- .../setup-fb-24bpp.c | 0 .../setup-i2c0.c | 0 .../setup-i2c1.c | 0 .../setup-sdhci-gpio.c | 0 arch/arm/plat-s3c64xx/Kconfig | 26 ------------------- arch/arm/plat-s3c64xx/Makefile | 15 ----------- 14 files changed, 40 insertions(+), 44 deletions(-) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dev-adc.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dev-audio.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dev-rtc.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dev-spi.c (99%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dev-uart.c (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/spi-clocks.h (89%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/setup-fb-24bpp.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/setup-i2c0.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/setup-i2c1.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/setup-sdhci-gpio.c (100%) diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index ce32e4997d763..15e065ef19a50 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -26,6 +26,32 @@ config S3C64XX_SETUP_SDHCI Internal configuration for default SDHCI setup for S3C6400 and S3C6410 SoCs. +# platform specific device setup + +config S3C64XX_SETUP_I2C0 + bool + default y + help + Common setup code for i2c bus 0. + + Note, currently since i2c0 is always compiled, this setup helper + is always compiled with it. + +config S3C64XX_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + +config S3C64XX_SETUP_FB_24BPP + bool + help + Common setup code for S3C64XX with an 24bpp RGB display helper. + +config S3C64XX_SETUP_SDHCI_GPIO + bool + help + Common setup code for S3C64XX SDHCI GPIO configurations + # S36400 Macchine support config MACH_SMDK6400 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 103bed48b46ec..49b71d5f2e598 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -18,9 +18,13 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o obj-y += irq.o obj-y += irq-eint.o -# setup support +# Device setup +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o +obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # PM @@ -33,3 +37,10 @@ obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o obj-$(CONFIG_MACH_NCP) += mach-ncp.o obj-$(CONFIG_MACH_HMT) += mach-hmt.o + +# device support + +obj-y += dev-uart.o +obj-y += dev-rtc.o +obj-$(CONFIG_S3C_ADC) += dev-adc.o +obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o diff --git a/arch/arm/plat-s3c64xx/dev-adc.c b/arch/arm/mach-s3c64xx/dev-adc.c similarity index 100% rename from arch/arm/plat-s3c64xx/dev-adc.c rename to arch/arm/mach-s3c64xx/dev-adc.c diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c similarity index 100% rename from arch/arm/plat-s3c64xx/dev-audio.c rename to arch/arm/mach-s3c64xx/dev-audio.c diff --git a/arch/arm/plat-s3c64xx/dev-rtc.c b/arch/arm/mach-s3c64xx/dev-rtc.c similarity index 100% rename from arch/arm/plat-s3c64xx/dev-rtc.c rename to arch/arm/mach-s3c64xx/dev-rtc.c diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c similarity index 99% rename from arch/arm/plat-s3c64xx/dev-spi.c rename to arch/arm/mach-s3c64xx/dev-spi.c index 0c20d27d9b65a..29c32d0885151 100644 --- a/arch/arm/plat-s3c64xx/dev-spi.c +++ b/arch/arm/mach-s3c64xx/dev-spi.c @@ -17,8 +17,8 @@ #include #include #include +#include -#include #include #include #include diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c similarity index 100% rename from arch/arm/plat-s3c64xx/dev-uart.c rename to arch/arm/mach-s3c64xx/dev-uart.c diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h similarity index 89% rename from arch/arm/plat-s3c64xx/include/plat/spi-clocks.h rename to arch/arm/mach-s3c64xx/include/mach/spi-clocks.h index 524bdae3f6255..9d0c43b4b6871 100644 --- a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h +++ b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h +/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h * * Copyright (C) 2009 Samsung Electronics Ltd. * Jaswinder Singh diff --git a/arch/arm/plat-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c similarity index 100% rename from arch/arm/plat-s3c64xx/setup-fb-24bpp.c rename to arch/arm/mach-s3c64xx/setup-fb-24bpp.c diff --git a/arch/arm/plat-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c similarity index 100% rename from arch/arm/plat-s3c64xx/setup-i2c0.c rename to arch/arm/mach-s3c64xx/setup-i2c0.c diff --git a/arch/arm/plat-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c similarity index 100% rename from arch/arm/plat-s3c64xx/setup-i2c1.c rename to arch/arm/mach-s3c64xx/setup-i2c1.c diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c similarity index 100% rename from arch/arm/plat-s3c64xx/setup-sdhci-gpio.c rename to arch/arm/mach-s3c64xx/setup-sdhci-gpio.c diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 37b4519fb832a..4edb580a02b7e 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -46,30 +46,4 @@ config S3C64XX_DMA bool "S3C64XX DMA" select S3C_DMA -# platform specific device setup - -config S3C64XX_SETUP_I2C0 - bool - default y - help - Common setup code for i2c bus 0. - - Note, currently since i2c0 is always compiled, this setup helper - is always compiled with it. - -config S3C64XX_SETUP_I2C1 - bool - help - Common setup code for i2c bus 1. - -config S3C64XX_SETUP_FB_24BPP - bool - help - Common setup code for S3C64XX with an 24bpp RGB display helper. - -config S3C64XX_SETUP_SDHCI_GPIO - bool - help - Common setup code for S3C64XX SDHCI GPIO configurations - endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 3e52dcdb36488..187b779a2bdc9 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -11,9 +11,6 @@ obj-n := dummy.o obj- := # Core files - -obj-y += dev-uart.o -obj-y += dev-rtc.o obj-y += cpu.o obj-y += clock.o obj-y += gpiolib.o @@ -33,15 +30,3 @@ obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_S3C64XX_DMA) += dma.o -# ADC support - -obj-$(CONFIG_S3C_ADC) += dev-adc.o - -# Device setup - -obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o -obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o -obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o -- GitLab From f7be9abaa5f4a64fdcca6808bb7eacb3547e574e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 13:41:30 +0900 Subject: [PATCH 224/370] ARM: S3C64XX: Move core support to mach-s3c64xx Move the core S3C64XX support to mach-s3c64xx as it is unlikely to be used outside of this directory. Also move the SoC header files in with it. This includes the clock, cpu, cpufreq, dma, gpiolib and pll support. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 4 ++++ arch/arm/mach-s3c64xx/Makefile | 15 +++++++++++++++ arch/arm/{plat-s3c64xx => mach-s3c64xx}/clock.c | 2 ++ arch/arm/{plat-s3c64xx => mach-s3c64xx}/cpu.c | 4 ++-- .../arm/{plat-s3c64xx => mach-s3c64xx}/cpufreq.c | 0 arch/arm/{plat-s3c64xx => mach-s3c64xx}/dma.c | 0 .../arm/{plat-s3c64xx => mach-s3c64xx}/gpiolib.c | 0 .../plat => mach-s3c64xx/include/mach}/pll.h | 0 .../plat => mach-s3c64xx/include/mach}/s3c6400.h | 3 +-- .../plat => mach-s3c64xx/include/mach}/s3c6410.h | 2 +- arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +- arch/arm/mach-s3c64xx/mach-hmt.c | 2 +- arch/arm/mach-s3c64xx/mach-ncp.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +- arch/arm/{plat-s3c64xx => mach-s3c64xx}/pm.c | 0 arch/arm/mach-s3c64xx/s3c6400.c | 2 +- arch/arm/mach-s3c64xx/s3c6410.c | 4 ++-- arch/arm/{plat-s3c64xx => mach-s3c64xx}/sleep.S | 0 arch/arm/plat-s3c64xx/Kconfig | 4 ---- arch/arm/plat-s3c64xx/Makefile | 16 ---------------- arch/arm/plat-s3c64xx/s3c6400-init.c | 4 ++-- 22 files changed, 35 insertions(+), 35 deletions(-) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/clock.c (99%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/cpu.c (98%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/cpufreq.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/dma.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/gpiolib.c (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/pll.h (100%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/s3c6400.h (95%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/s3c6410.h (93%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/pm.c (100%) rename arch/arm/{plat-s3c64xx => mach-s3c64xx}/sleep.S (100%) diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 15e065ef19a50..7c9cd9a9901a9 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -19,6 +19,10 @@ config CPU_S3C6410 help Enable S3C6410 CPU support +config S3C64XX_DMA + bool "S3C64XX DMA" + select S3C_DMA + config S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_SDHCI_GPIO bool diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 49b71d5f2e598..4417f1ad99b6d 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -10,6 +10,11 @@ obj-m := obj-n := obj- := +# Core files +obj-y += cpu.o +obj-y += clock.o +obj-y += gpiolib.o + # Core support for S3C6400 system obj-$(CONFIG_CPU_S3C6400) += s3c6400.o @@ -18,6 +23,14 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o obj-y += irq.o obj-y += irq-eint.o +# CPU frequency scaling + +obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o + +# DMA support + +obj-$(CONFIG_S3C64XX_DMA) += dma.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o @@ -28,6 +41,8 @@ obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # PM +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_PM) += irq-pm.o # Machine support diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c similarity index 99% rename from arch/arm/plat-s3c64xx/clock.c rename to arch/arm/mach-s3c64xx/clock.c index 64439de206cb7..229bb3bcc54fd 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -23,6 +23,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c similarity index 98% rename from arch/arm/plat-s3c64xx/cpu.c rename to arch/arm/mach-s3c64xx/cpu.c index bc7ca1812e32d..410d688a69107 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/mach-s3c64xx/cpu.c @@ -33,8 +33,8 @@ #include #include -#include -#include +#include +#include /* table of supported CPUs */ diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c similarity index 100% rename from arch/arm/plat-s3c64xx/cpufreq.c rename to arch/arm/mach-s3c64xx/cpufreq.c diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c similarity index 100% rename from arch/arm/plat-s3c64xx/dma.c rename to arch/arm/mach-s3c64xx/dma.c diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c similarity index 100% rename from arch/arm/plat-s3c64xx/gpiolib.c rename to arch/arm/mach-s3c64xx/gpiolib.c diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h similarity index 100% rename from arch/arm/plat-s3c64xx/include/plat/pll.h rename to arch/arm/mach-s3c64xx/include/mach/pll.h diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h similarity index 95% rename from arch/arm/plat-s3c64xx/include/plat/s3c6400.h rename to arch/arm/mach-s3c64xx/include/mach/s3c6400.h index 11f2e1e119b09..2bc7c07a928f9 100644 --- a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h +++ b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h +/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics @@ -33,4 +33,3 @@ extern void s3c6400_init_clocks(int xtal); #define s3c6400_map_io NULL #define s3c6400_init NULL #endif - diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h similarity index 93% rename from arch/arm/plat-s3c64xx/include/plat/s3c6410.h rename to arch/arm/mach-s3c64xx/include/mach/s3c6410.h index 50dcdd6f68006..24f1141ffcb7c 100644 --- a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h +++ b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h +/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 06d8fe579e102..4a0bb243d14ab 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 284886c26a285..a6d91c39f22e2 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index 9be92ddd21767..bf65747ea68ec 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index ba8a052a61421..f7b18983950c5 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -31,7 +31,7 @@ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 021670e39d3ea..fdf8f7539a120 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -54,7 +54,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c similarity index 100% rename from arch/arm/plat-s3c64xx/pm.c rename to arch/arm/mach-s3c64xx/pm.c diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 2fba1b263fed5..720d0d1f3bfca 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include void __init s3c6400_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index b881d6a50b118..fd457cc3ab87c 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -38,8 +38,8 @@ #include #include #include -#include -#include +#include +#include void __init s3c6410_map_io(void) { diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S similarity index 100% rename from arch/arm/plat-s3c64xx/sleep.S rename to arch/arm/mach-s3c64xx/sleep.S diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 4edb580a02b7e..fb7e25f710e06 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -42,8 +42,4 @@ config CPU_S3C6400_CLOCK Common clock support code for the S3C6400 that is shared by other CPUs in the series, such as the S3C6410. -config S3C64XX_DMA - bool "S3C64XX DMA" - select S3C_DMA - endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 187b779a2bdc9..bd4fe3b48eaa9 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -10,23 +10,7 @@ obj-m := obj-n := dummy.o obj- := -# Core files -obj-y += cpu.o -obj-y += clock.o -obj-y += gpiolib.o - # CPU support obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o -obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o - -# PM support - -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += sleep.o - -# DMA support - -obj-$(CONFIG_S3C64XX_DMA) += dma.o - diff --git a/arch/arm/plat-s3c64xx/s3c6400-init.c b/arch/arm/plat-s3c64xx/s3c6400-init.c index 6c28f39df0975..e64caa4d02d9b 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-init.c +++ b/arch/arm/plat-s3c64xx/s3c6400-init.c @@ -18,8 +18,8 @@ #include #include -#include -#include +#include +#include /* uart registration process */ -- GitLab From 6ce8fde296e56cda9d7416e015ed2fe495c9c48c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 14:32:09 +0900 Subject: [PATCH 225/370] ARM: S3C64XX: Merge s3c6400-init.c into cpu.c Since this file is small, and is compiled for both systems in this architecture merge it into the cpu support file and remove the original instead of moving it. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 2 -- arch/arm/mach-s3c64xx/cpu.c | 6 ++++++ arch/arm/plat-s3c64xx/Kconfig | 6 ------ arch/arm/plat-s3c64xx/Makefile | 1 - arch/arm/plat-s3c64xx/s3c6400-init.c | 29 ---------------------------- 5 files changed, 6 insertions(+), 38 deletions(-) delete mode 100644 arch/arm/plat-s3c64xx/s3c6400-init.c diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 7c9cd9a9901a9..33d82b1c9eff8 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -7,14 +7,12 @@ config CPU_S3C6400 bool - select CPU_S3C6400_INIT select CPU_S3C6400_CLOCK help Enable S3C6400 CPU support config CPU_S3C6410 bool - select CPU_S3C6400_INIT select CPU_S3C6400_CLOCK help Enable S3C6410 CPU support diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c index 410d688a69107..374e45e566b8c 100644 --- a/arch/arm/mach-s3c64xx/cpu.c +++ b/arch/arm/mach-s3c64xx/cpu.c @@ -129,6 +129,12 @@ static struct sys_device s3c64xx_sysdev = { .cls = &s3c64xx_sysclass, }; +/* uart registration process */ + +void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); +} /* read cpu identification code */ diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index fb7e25f710e06..cc300894f364c 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -30,12 +30,6 @@ if PLAT_S3C64XX # Configuration options shared by all S3C64XX implementations -config CPU_S3C6400_INIT - bool - help - Common initialisation code for the S3C6400 that is shared - by other CPUs in the series, such as the S3C6410. - config CPU_S3C6400_CLOCK bool help diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index bd4fe3b48eaa9..62fc25305ec4c 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -12,5 +12,4 @@ obj- := # CPU support -obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o diff --git a/arch/arm/plat-s3c64xx/s3c6400-init.c b/arch/arm/plat-s3c64xx/s3c6400-init.c deleted file mode 100644 index e64caa4d02d9b..0000000000000 --- a/arch/arm/plat-s3c64xx/s3c6400-init.c +++ /dev/null @@ -1,29 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6400 - CPU initialisation (common with other S3C64XX chips) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include - -/* uart registration process */ - -void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); -} -- GitLab From 62acb2f82dc27cd40729e7d4c2879e57fe41b927 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 14:53:19 +0900 Subject: [PATCH 226/370] ARM: S3C64XX: Merge s3c6400-clock.c and clock.c into mach-s3c64xx Merge plat-s3c64xx/s3c6400-clock.c mach-s3c64xx/clock.c placing all the clock code into one place. Note, no effort is made in this patch to squash the init functions together. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 2 - arch/arm/mach-s3c64xx/clock.c | 507 ++++++++++++++++++++++++ arch/arm/plat-s3c64xx/Kconfig | 12 - arch/arm/plat-s3c64xx/Makefile | 3 - arch/arm/plat-s3c64xx/s3c6400-clock.c | 536 -------------------------- 5 files changed, 507 insertions(+), 553 deletions(-) delete mode 100644 arch/arm/plat-s3c64xx/s3c6400-clock.c diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 33d82b1c9eff8..8c2c89c24fce2 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -7,13 +7,11 @@ config CPU_S3C6400 bool - select CPU_S3C6400_CLOCK help Enable S3C6400 CPU support config CPU_S3C6410 bool - select CPU_S3C6400_CLOCK help Enable S3C6410 CPU support diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 229bb3bcc54fd..9b587e267422b 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include @@ -27,7 +29,25 @@ #include #include +#include #include +#include + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * ext_xtal_mux for want of an actual name from the manual. +*/ + +static struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", + .id = -1, +}; + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux + +#define clk_fout_mpll clk_mpll +#define clk_fout_epll clk_epll struct clk clk_h2 = { .name = "hclk2", @@ -273,6 +293,493 @@ static struct clk init_clocks[] = { } }; + +static struct clk clk_fout_apll = { + .name = "fout_apll", + .id = -1, +}; + +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +static struct clksrc_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, + .sources = &clk_src_apll, +}; + +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +static struct clksrc_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, + .sources = &clk_src_epll, +}; + +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +static struct clksrc_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, + .sources = &clk_src_mpll, +}; + +static unsigned int armclk_mask; + +static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv; + + /* divisor mask starts at bit0, so no need to shift */ + clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; + + return rate / (clkdiv + 1); +} + +static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + + if (parent < rate) + return parent; + + div = (parent / rate) - 1; + if (div > armclk_mask) + div = armclk_mask; + + return parent / (div + 1); +} + +static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + u32 val; + + if (rate < parent / (armclk_mask + 1)) + return -EINVAL; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + + val = __raw_readl(S3C_CLK_DIV0); + val &= ~armclk_mask; + val |= (div - 1); + __raw_writel(val, S3C_CLK_DIV0); + + return 0; + +} + +static struct clk clk_arm = { + .name = "armclk", + .id = -1, + .parent = &clk_mout_apll.clk, + .ops = &(struct clk_ops) { + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, + .round_rate = s3c64xx_clk_arm_round_rate, + }, +}; + +static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) + rate /= 2; + + return rate; +} + +static struct clk_ops clk_dout_ops = { + .get_rate = s3c64xx_clk_doutmpll_get_rate, +}; + +static struct clk clk_dout_mpll = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, + .ops = &clk_dout_ops, +}; + +static struct clk *clkset_spi_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_27m, +}; + +static struct clksrc_sources clkset_spi_mmc = { + .sources = clkset_spi_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +}; + +static struct clk *clkset_irda_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + &clk_27m, +}; + +static struct clksrc_sources clkset_irda = { + .sources = clkset_irda_list, + .nr_sources = ARRAY_SIZE(clkset_irda_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + NULL +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_uhost_list[] = { + &clk_48m, + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, +}; + +static struct clksrc_sources clkset_uhost = { + .sources = clkset_uhost_list, + .nr_sources = ARRAY_SIZE(clkset_uhost_list), +}; + +/* The peripheral clocks are all controlled via clocksource followed + * by an optional divider and gate stage. We currently roll this into + * one clock which hides the intermediate clock from the mux. + * + * Note, the JPEG clock can only be an even divider... + * + * The scaler and LCD clocks depend on the S3C64XX version, and also + * have a common parent divisor so are not included here. + */ + +/* clocks that feed other parts of the clock source tree */ + +static struct clk clk_iis_cd0 = { + .name = "iis_cdclk0", + .id = -1, +}; + +static struct clk clk_iis_cd1 = { + .name = "iis_cdclk1", + .id = -1, +}; + +static struct clk clk_pcm_cd = { + .name = "pcm_cdclk", + .id = -1, +}; + +static struct clk *clkset_audio0_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd0, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio0 = { + .sources = clkset_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_audio0_list), +}; + +static struct clk *clkset_audio1_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd1, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio1 = { + .sources = clkset_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_audio1_list), +}; + +static struct clk *clkset_camif_list[] = { + &clk_h2, +}; + +static struct clksrc_sources clkset_camif = { + .sources = clkset_camif_list, + .nr_sources = ARRAY_SIZE(clkset_camif_list), +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "usb-bus-host", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, + .sources = &clkset_uhost, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, + .sources = &clkset_uart, + }, { +/* Where does UCLK0 come from? */ + .clk = { + .name = "spi-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "spi-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, + .sources = &clkset_audio0, + }, { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, + .sources = &clkset_audio1, + }, { + .clk = { + .name = "irda-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_IRDA, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, + .sources = &clkset_irda, + }, { + .clk = { + .name = "camera", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_CAM, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, + .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, + .sources = &clkset_camif, + }, +}; + +/* Clock initialisation code */ + +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, +}; + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +void __init_or_cpufreq s3c6400_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long hclk2; + unsigned long pclk; + unsigned long epll; + unsigned long apll; + unsigned long mpll; + unsigned int ptr; + u32 clkdiv0; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + clkdiv0 = __raw_readl(S3C_CLK_DIV0); + printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + /* For now assume the mux always selects the crystal */ + clk_ext_xtal_mux.parent = xtal_clk; + + epll = s3c6400_get_epll(xtal); + mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); + apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); + + fclk = mpll; + + printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", + apll, mpll, epll); + + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); + pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); + + printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", + hclk2, hclk, pclk); + + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + + clk_h2.rate = hclk2; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_f.rate = fclk; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); +} + +static struct clk *clks1[] __initdata = { + &clk_ext_xtal_mux, + &clk_iis_cd0, + &clk_iis_cd1, + &clk_pcm_cd, + &clk_mout_epll.clk, + &clk_mout_mpll.clk, + &clk_dout_mpll, + &clk_arm, +}; + +/** + * s3c6400_register_clocks - register clocks for s3c6400 and above + * @armclk_divlimit: Divisor mask for ARMCLK + * + * Register the clocks for the S3C6400 and above SoC range, such + * as ARMCLK and the clocks which have divider chains attached. + * + * This call does not setup the clocks, which is left to the + * s3c6400_setup_clocks() call which may be needed by the cpufreq + * or resume code to re-set the clocks if the bootloader has changed + * them. + */ +void __init s3c6400_register_clocks(unsigned armclk_divlimit) +{ + struct clk *clkp; + int ret; + int ptr; + + armclk_mask = armclk_divlimit; + + for (ptr = 0; ptr < ARRAY_SIZE(clks1); ptr++) { + clkp = clks1[ptr]; + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); +} + static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index cc300894f364c..94ac74eeca5f5 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -25,15 +25,3 @@ config PLAT_S3C64XX select SAMSUNG_GPIOLIB_4BIT help Base platform code for any Samsung S3C64XX device - -if PLAT_S3C64XX - -# Configuration options shared by all S3C64XX implementations - -config CPU_S3C6400_CLOCK - bool - help - Common clock support code for the S3C6400 that is shared - by other CPUs in the series, such as the S3C6410. - -endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 62fc25305ec4c..7ca1c09995955 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -10,6 +10,3 @@ obj-m := obj-n := dummy.o obj- := -# CPU support - -obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c deleted file mode 100644 index 85f7bb053f727..0000000000000 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ /dev/null @@ -1,536 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6400 based common clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include - -/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call - * ext_xtal_mux for want of an actual name from the manual. -*/ - -static struct clk clk_ext_xtal_mux = { - .name = "ext_xtal", - .id = -1, -}; - -#define clk_fin_apll clk_ext_xtal_mux -#define clk_fin_mpll clk_ext_xtal_mux -#define clk_fin_epll clk_ext_xtal_mux - -#define clk_fout_mpll clk_mpll -#define clk_fout_epll clk_epll - -static struct clk clk_fout_apll = { - .name = "fout_apll", - .id = -1, -}; - -static struct clk *clk_src_apll_list[] = { - [0] = &clk_fin_apll, - [1] = &clk_fout_apll, -}; - -static struct clksrc_sources clk_src_apll = { - .sources = clk_src_apll_list, - .nr_sources = ARRAY_SIZE(clk_src_apll_list), -}; - -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", - .id = -1, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, - .sources = &clk_src_apll, -}; - -static struct clk *clk_src_epll_list[] = { - [0] = &clk_fin_epll, - [1] = &clk_fout_epll, -}; - -static struct clksrc_sources clk_src_epll = { - .sources = clk_src_epll_list, - .nr_sources = ARRAY_SIZE(clk_src_epll_list), -}; - -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", - .id = -1, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, - .sources = &clk_src_epll, -}; - -static struct clk *clk_src_mpll_list[] = { - [0] = &clk_fin_mpll, - [1] = &clk_fout_mpll, -}; - -static struct clksrc_sources clk_src_mpll = { - .sources = clk_src_mpll_list, - .nr_sources = ARRAY_SIZE(clk_src_mpll_list), -}; - -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", - .id = -1, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, - .sources = &clk_src_mpll, -}; - -static unsigned int armclk_mask; - -static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv; - - /* divisor mask starts at bit0, so no need to shift */ - clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; - - return rate / (clkdiv + 1); -} - -static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - - if (parent < rate) - return parent; - - div = (parent / rate) - 1; - if (div > armclk_mask) - div = armclk_mask; - - return parent / (div + 1); -} - -static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - u32 val; - - if (rate < parent / (armclk_mask + 1)) - return -EINVAL; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - - val = __raw_readl(S3C_CLK_DIV0); - val &= ~armclk_mask; - val |= (div - 1); - __raw_writel(val, S3C_CLK_DIV0); - - return 0; - -} - -static struct clk clk_arm = { - .name = "armclk", - .id = -1, - .parent = &clk_mout_apll.clk, - .ops = &(struct clk_ops) { - .get_rate = s3c64xx_clk_arm_get_rate, - .set_rate = s3c64xx_clk_arm_set_rate, - .round_rate = s3c64xx_clk_arm_round_rate, - }, -}; - -static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) - rate /= 2; - - return rate; -} - -static struct clk_ops clk_dout_ops = { - .get_rate = s3c64xx_clk_doutmpll_get_rate, -}; - -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .id = -1, - .parent = &clk_mout_mpll.clk, - .ops = &clk_dout_ops, -}; - -static struct clk *clkset_spi_mmc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_27m, -}; - -static struct clksrc_sources clkset_spi_mmc = { - .sources = clkset_spi_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), -}; - -static struct clk *clkset_irda_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - NULL, - &clk_27m, -}; - -static struct clksrc_sources clkset_irda = { - .sources = clkset_irda_list, - .nr_sources = ARRAY_SIZE(clkset_irda_list), -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - NULL, - NULL -}; - -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; - -static struct clk *clkset_uhost_list[] = { - &clk_48m, - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, -}; - -static struct clksrc_sources clkset_uhost = { - .sources = clkset_uhost_list, - .nr_sources = ARRAY_SIZE(clkset_uhost_list), -}; - -/* The peripheral clocks are all controlled via clocksource followed - * by an optional divider and gate stage. We currently roll this into - * one clock which hides the intermediate clock from the mux. - * - * Note, the JPEG clock can only be an even divider... - * - * The scaler and LCD clocks depend on the S3C64XX version, and also - * have a common parent divisor so are not included here. - */ - -/* clocks that feed other parts of the clock source tree */ - -static struct clk clk_iis_cd0 = { - .name = "iis_cdclk0", - .id = -1, -}; - -static struct clk clk_iis_cd1 = { - .name = "iis_cdclk1", - .id = -1, -}; - -static struct clk clk_pcm_cd = { - .name = "pcm_cdclk", - .id = -1, -}; - -static struct clk *clkset_audio0_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_dout_mpll, - [2] = &clk_fin_epll, - [3] = &clk_iis_cd0, - [4] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio0 = { - .sources = clkset_audio0_list, - .nr_sources = ARRAY_SIZE(clkset_audio0_list), -}; - -static struct clk *clkset_audio1_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_dout_mpll, - [2] = &clk_fin_epll, - [3] = &clk_iis_cd1, - [4] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio1 = { - .sources = clkset_audio1_list, - .nr_sources = ARRAY_SIZE(clkset_audio1_list), -}; - -static struct clk *clkset_camif_list[] = { - &clk_h2, -}; - -static struct clksrc_sources clkset_camif = { - .sources = clkset_camif_list, - .nr_sources = ARRAY_SIZE(clkset_camif_list), -}; - -static struct clksrc_clk clksrcs[] = { - { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "usb-bus-host", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, - .sources = &clkset_uhost, - }, { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, - .sources = &clkset_uart, - }, { -/* Where does UCLK0 come from? */ - .clk = { - .name = "spi-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_SPI0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "spi-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_SPI1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, - .sources = &clkset_audio0, - }, { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, - .sources = &clkset_audio1, - }, { - .clk = { - .name = "irda-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_IRDA, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, - .sources = &clkset_irda, - }, { - .clk = { - .name = "camera", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_CAM, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, - .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, - .sources = &clkset_camif, - }, -}; - -/* Clock initialisation code */ - -static struct clksrc_clk *init_parents[] = { - &clk_mout_apll, - &clk_mout_epll, - &clk_mout_mpll, -}; - -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - -void __init_or_cpufreq s3c6400_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long hclk2; - unsigned long pclk; - unsigned long epll; - unsigned long apll; - unsigned long mpll; - unsigned int ptr; - u32 clkdiv0; - - printk(KERN_DEBUG "%s: registering clocks\n", __func__); - - clkdiv0 = __raw_readl(S3C_CLK_DIV0); - printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); - - xtal_clk = clk_get(NULL, "xtal"); - BUG_ON(IS_ERR(xtal_clk)); - - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - - /* For now assume the mux always selects the crystal */ - clk_ext_xtal_mux.parent = xtal_clk; - - epll = s3c6400_get_epll(xtal); - mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); - apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); - - fclk = mpll; - - printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", - apll, mpll, epll); - - hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); - hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); - pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); - - printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", - hclk2, hclk, pclk); - - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; - - clk_h2.rate = hclk2; - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = fclk; - - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr], true); -} - -static struct clk *clks[] __initdata = { - &clk_ext_xtal_mux, - &clk_iis_cd0, - &clk_iis_cd1, - &clk_pcm_cd, - &clk_mout_epll.clk, - &clk_mout_mpll.clk, - &clk_dout_mpll, - &clk_arm, -}; - -/** - * s3c6400_register_clocks - register clocks for s3c6400 and above - * @armclk_divlimit: Divisor mask for ARMCLK - * - * Register the clocks for the S3C6400 and above SoC range, such - * as ARMCLK and the clocks which have divider chains attached. - * - * This call does not setup the clocks, which is left to the - * s3c6400_setup_clocks() call which may be needed by the cpufreq - * or resume code to re-set the clocks if the bootloader has changed - * them. - */ -void __init s3c6400_register_clocks(unsigned armclk_divlimit) -{ - struct clk *clkp; - int ret; - int ptr; - - armclk_mask = armclk_divlimit; - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); -} -- GitLab From 55bf9267dd628c9369674ca75f5b00e275529289 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 15:10:38 +0900 Subject: [PATCH 227/370] ARM: S3C64XX: Combine the clock init code Turn the init sequence of s3c24xx_register_baseclocks(xtal); s3c64xx_register_clocks(); s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); into a single call as this is now contained within one file. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/clock.c | 50 ++++++++------------ arch/arm/mach-s3c64xx/include/mach/s3c6400.h | 3 +- arch/arm/mach-s3c64xx/s3c6400.c | 5 +- arch/arm/mach-s3c64xx/s3c6410.c | 4 +- arch/arm/plat-samsung/include/plat/clock.h | 1 - 5 files changed, 23 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 9b587e267422b..7f5e1aa99ce12 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -748,19 +748,29 @@ static struct clk *clks1[] __initdata = { &clk_arm, }; +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_27m, + &clk_48m, + &clk_h2, +}; + /** - * s3c6400_register_clocks - register clocks for s3c6400 and above - * @armclk_divlimit: Divisor mask for ARMCLK + * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410 + * @xtal: The rate for the clock crystal feeding the PLLs. + * @armclk_divlimit: Divisor mask for ARMCLK. * - * Register the clocks for the S3C6400 and above SoC range, such - * as ARMCLK and the clocks which have divider chains attached. + * Register the clocks for the S3C6400 and S3C6410 SoC range, such + * as ARMCLK as well as the necessary parent clocks. * * This call does not setup the clocks, which is left to the * s3c6400_setup_clocks() call which may be needed by the cpufreq * or resume code to re-set the clocks if the bootloader has changed * them. */ -void __init s3c6400_register_clocks(unsigned armclk_divlimit) +void __init s3c64xx_register_clocks(unsigned long xtal, + unsigned armclk_divlimit) { struct clk *clkp; int ret; @@ -768,33 +778,9 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) armclk_mask = armclk_divlimit; - for (ptr = 0; ptr < ARRAY_SIZE(clks1); ptr++) { - clkp = clks1[ptr]; - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); -} - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_epll, - &clk_27m, - &clk_48m, - &clk_h2, -}; - -void __init s3c64xx_register_clocks(void) -{ - struct clk *clkp; - int ret; - int ptr; - + s3c24xx_register_baseclocks(xtal); s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); clkp = init_clocks_disable; @@ -809,5 +795,7 @@ void __init s3c64xx_register_clocks(void) (clkp->enable)(clkp, 0); } + s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h index 2bc7c07a928f9..f86958d05352a 100644 --- a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h +++ b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h @@ -15,9 +15,10 @@ /* Common init code for S3C6400 related SoCs */ extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c6400_register_clocks(unsigned armclk_divlimit); extern void s3c6400_setup_clocks(void); +extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit); + #ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init(void); diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 720d0d1f3bfca..707e34e3afd1a 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -55,10 +55,7 @@ void __init s3c6400_map_io(void) void __init s3c6400_init_clocks(int xtal) { - printk(KERN_DEBUG "%s: initialising clocks\n", __func__); - s3c24xx_register_baseclocks(xtal); - s3c64xx_register_clocks(); - s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK); + s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK); s3c6400_setup_clocks(); } diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index fd457cc3ab87c..59635d19466a5 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -58,9 +58,7 @@ void __init s3c6410_map_io(void) void __init s3c6410_init_clocks(int xtal) { printk(KERN_DEBUG "%s: initialising clocks\n", __func__); - s3c24xx_register_baseclocks(xtal); - s3c64xx_register_clocks(); - s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); + s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK); s3c6400_setup_clocks(); } diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index ba9a1cdd3a28a..60b62692ac7ad 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -94,7 +94,6 @@ extern void s3c_register_clocks(struct clk *clk, int nr_clks); extern int s3c24xx_register_baseclocks(unsigned long xtal); -extern void s3c64xx_register_clocks(void); extern void s5p_register_clocks(unsigned long xtal_freq); extern void s3c24xx_setup_clocks(unsigned long fclk, -- GitLab From 89f0ce721c0bc95c109300edcd8525d8ea5df8f2 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 26 Jan 2010 15:49:15 +0900 Subject: [PATCH 228/370] ARM: S3C64XX: Remove plat-s3c64xx Kconfig and PLAT_S3C64XX Remove the Kconfig and PLAT_S3C64XX defines for the previous S3C64XX directory structure now that the code is moved into mach-s3c64xx. Note, we cannot currently remove plat-s3c64xx directory as we have a pair of include files used within plat-s3c and plat-samsung that need to find a new home. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 16 +++++++++++++++- arch/arm/Makefile | 2 +- arch/arm/plat-s3c64xx/Kconfig | 15 --------------- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 685ff7effff9e..89fbed5e11ecb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -627,9 +627,24 @@ config ARCH_S3C2410 config ARCH_S3C64XX bool "Samsung S3C64XX" + select PLAT_S3C + select CPU_V6 select GENERIC_GPIO + select ARM_VIC select HAVE_CLK + select NO_IOPORT select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_IRQ_UART + select S3C_GPIO_TRACK + select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX + select S3C_GPIO_CFG_S3C64XX + select S3C_DEV_NAND + select USB_ARCH_HAS_OHCI + select SAMSUNG_GPIOLIB_4BIT help Samsung S3C64XX series based systems @@ -784,7 +799,6 @@ source "arch/arm/mach-dove/Kconfig" source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" -source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ecf963d61aed5..c1300d88a0146 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,7 +183,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung -plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung +plat-$(CONFIG_ARCH_S3C64XX) := s3c64xx s3c samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 94ac74eeca5f5..ae034c2267f37 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -8,20 +8,5 @@ config PLAT_S3C64XX bool depends on ARCH_S3C64XX default y - select CPU_V6 - select PLAT_S3C - select ARM_VIC - select NO_IOPORT - select ARCH_REQUIRE_GPIOLIB - select SAMSUNG_CLKSRC - select SAMSUNG_IRQ_VIC_TIMER - select SAMSUNG_IRQ_UART - select S3C_GPIO_TRACK - select S3C_GPIO_PULL_UPDOWN - select S3C_GPIO_CFG_S3C24XX - select S3C_GPIO_CFG_S3C64XX - select S3C_DEV_NAND - select USB_ARCH_HAS_OHCI - select SAMSUNG_GPIOLIB_4BIT help Base platform code for any Samsung S3C64XX device -- GitLab From 431fb7df24ebf360ba35895a60d084de364e39f8 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 5 Feb 2010 13:52:53 +0100 Subject: [PATCH 229/370] ARM: SAMSUNG: Move pm-core.h to machine directory Move the pm-core.h to the machine include directory in the process of eliminating the plat-s3c64xx. Signed-off-by: Ben Dooks --- .../include/plat => mach-s3c2410/include/mach}/pm-core.h | 2 +- .../include/plat => mach-s3c64xx/include/mach}/pm-core.h | 2 +- arch/arm/plat-s3c/pm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm/{plat-s3c24xx/include/plat => mach-s3c2410/include/mach}/pm-core.h (97%) rename arch/arm/{plat-s3c64xx/include/plat => mach-s3c64xx/include/mach}/pm-core.h (98%) diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h similarity index 97% rename from arch/arm/plat-s3c24xx/include/plat/pm-core.h rename to arch/arm/mach-s3c2410/include/mach/pm-core.h index fb45dd9adca56..70a83b209e254 100644 --- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h +++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h +/* linux/arch/arm/mach-s3c2410/include/pm-core.h * * Copyright 2008 Simtec Electronics * Ben Dooks diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h similarity index 98% rename from arch/arm/plat-s3c64xx/include/plat/pm-core.h rename to arch/arm/mach-s3c64xx/include/mach/pm-core.h index 61b8aae76d3da..1e9f20f0bb7b0 100644 --- a/arch/arm/plat-s3c64xx/include/plat/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h +/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index e5eef126791b3..27cfca5976993 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c @@ -29,7 +29,7 @@ #include #include -#include +#include /* for external use */ -- GitLab From 992426bfe98e71db1ce767fd66f6c68ed18fcc14 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 20 Feb 2010 23:01:33 +0000 Subject: [PATCH 230/370] ARM: SAMSUNG: Remove dma-plat.h to allow plat-s3c64xx to be removed dma-plat.h is the last file left in plat-s3c64xx, but to remove it we must also change the use of dma-plat.h by the core code and the s3c24xx implementation. Rename the s3c24xx dma-plat.h in the common plat-samsung directory as it may be used for other ports. Move the specific dma bits into the mach-s3c64xx directory and update the build as needed. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/dma.c | 2 +- arch/arm/mach-s3c2412/dma.c | 2 +- arch/arm/mach-s3c2440/dma.c | 2 +- arch/arm/mach-s3c2443/dma.c | 2 +- arch/arm/mach-s3c64xx/dma.c | 1 - arch/arm/mach-s3c64xx/include/mach/dma.h | 57 +++++++++++++++ arch/arm/plat-s3c/dma.c | 2 - arch/arm/plat-s3c24xx/dma.c | 2 +- arch/arm/plat-s3c64xx/include/plat/dma-plat.h | 70 ------------------- .../include/plat/dma-s3c24xx.h} | 4 +- 10 files changed, 64 insertions(+), 80 deletions(-) delete mode 100644 arch/arm/plat-s3c64xx/include/plat/dma-plat.h rename arch/arm/{plat-s3c24xx/include/plat/dma-plat.h => plat-samsung/include/plat/dma-s3c24xx.h} (95%) diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 63b753f56c643..0d8e043804c21 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index f8d16fc10bc6a..e880524904eb5 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -20,7 +20,7 @@ #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index e08e081430f04..3b0529f54e9cf 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index 397f3b5c0b474..3f658685ec168 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -20,7 +20,7 @@ #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 0e0edf75e8edd..b62bdf18dca4e 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -27,7 +27,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index 6723860748be2..0a5d9268a23ee 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h @@ -67,4 +67,61 @@ static __inline__ bool s3c_dma_has_circular(void) #include +#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ + +struct s3c64xx_dma_buff; + +/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor + * @next: Pointer to next buffer in queue or ring. + * @pw: Client provided identifier + * @lli: Pointer to hardware descriptor this buffer is associated with. + * @lli_dma: Hardare address of the descriptor. + */ +struct s3c64xx_dma_buff { + struct s3c64xx_dma_buff *next; + + void *pw; + struct pl080s_lli *lli; + dma_addr_t lli_dma; +}; + +struct s3c64xx_dmac; + +struct s3c2410_dma_chan { + unsigned char number; /* number of this dma channel */ + unsigned char in_use; /* channel allocated */ + unsigned char bit; /* bit for enable/disable/etc */ + unsigned char hw_width; + unsigned char peripheral; + + unsigned int flags; + enum s3c2410_dmasrc source; + + + dma_addr_t dev_addr; + + struct s3c2410_dma_client *client; + struct s3c64xx_dmac *dmac; /* pointer to controller */ + + void __iomem *regs; + + /* cdriver callbacks */ + s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ + s3c2410_dma_opfn_t op_fn; /* channel op callback */ + + /* buffer list and information */ + struct s3c64xx_dma_buff *curr; /* current dma buffer */ + struct s3c64xx_dma_buff *next; /* next buffer to load */ + struct s3c64xx_dma_buff *end; /* end of queue */ + + /* note, when channel is running in circular mode, curr is the + * first buffer enqueued, end is the last and curr is where the + * last buffer-done event is set-at. The buffers are not freed + * and the last buffer hardware descriptor points back to the + * first. + */ +}; + +#include + #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c index a995850cd9d51..606db1af5fe75 100644 --- a/arch/arm/plat-s3c/dma.c +++ b/arch/arm/plat-s3c/dma.c @@ -20,8 +20,6 @@ struct s3c2410_dma_buf; #include #include -#include - /* dma channel state information */ struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX]; diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index f0ea7943ac5a0..93827b3d4e846 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include /* io map for dma */ diff --git a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h deleted file mode 100644 index 8f76a1e474d6c..0000000000000 --- a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h +++ /dev/null @@ -1,70 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h - * - * Copyright 2009 Openmoko, Inc. - * Copyright 2009 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX DMA core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ - -struct s3c64xx_dma_buff; - -/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor - * @next: Pointer to next buffer in queue or ring. - * @pw: Client provided identifier - * @lli: Pointer to hardware descriptor this buffer is associated with. - * @lli_dma: Hardare address of the descriptor. - */ -struct s3c64xx_dma_buff { - struct s3c64xx_dma_buff *next; - - void *pw; - struct pl080s_lli *lli; - dma_addr_t lli_dma; -}; - -struct s3c64xx_dmac; - -struct s3c2410_dma_chan { - unsigned char number; /* number of this dma channel */ - unsigned char in_use; /* channel allocated */ - unsigned char bit; /* bit for enable/disable/etc */ - unsigned char hw_width; - unsigned char peripheral; - - unsigned int flags; - enum s3c2410_dmasrc source; - - - dma_addr_t dev_addr; - - struct s3c2410_dma_client *client; - struct s3c64xx_dmac *dmac; /* pointer to controller */ - - void __iomem *regs; - - /* cdriver callbacks */ - s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ - s3c2410_dma_opfn_t op_fn; /* channel op callback */ - - /* buffer list and information */ - struct s3c64xx_dma_buff *curr; /* current dma buffer */ - struct s3c64xx_dma_buff *next; /* next buffer to load */ - struct s3c64xx_dma_buff *end; /* end of queue */ - - /* note, when channel is running in circular mode, curr is the - * first buffer enqueued, end is the last and curr is where the - * last buffer-done event is set-at. The buffers are not freed - * and the last buffer hardware descriptor points back to the - * first. - */ -}; - -#include diff --git a/arch/arm/plat-s3c24xx/include/plat/dma-plat.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h similarity index 95% rename from arch/arm/plat-s3c24xx/include/plat/dma-plat.h rename to arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index 9565ead1bc9b0..336d5ac02035b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/dma-plat.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -1,9 +1,9 @@ -/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h +/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h * * Copyright (C) 2006 Simtec Electronics * Ben Dooks * - * Samsung S3C24XX DMA support + * Samsung S3C24XX DMA support - per SoC functions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as -- GitLab From 5098280e015e36daebfd16f976ec3db6f4975fac Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 22 Feb 2010 09:20:39 +0000 Subject: [PATCH 231/370] ARM: mach-shmobile: ap4evb: Add LED support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 41bc2487de4d9..4714cad373b85 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -197,6 +197,20 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_CS5A, NULL); gpio_request(GPIO_FN_IRQ6_39, NULL); + /* enable LED 1 - 4 */ + gpio_request(GPIO_PORT185, NULL); + gpio_request(GPIO_PORT186, NULL); + gpio_request(GPIO_PORT187, NULL); + gpio_request(GPIO_PORT188, NULL); + gpio_direction_output(GPIO_PORT185, 1); + gpio_direction_output(GPIO_PORT186, 1); + gpio_direction_output(GPIO_PORT187, 1); + gpio_direction_output(GPIO_PORT188, 1); + gpio_export(GPIO_PORT185, 0); + gpio_export(GPIO_PORT186, 0); + gpio_export(GPIO_PORT187, 0); + gpio_export(GPIO_PORT188, 0); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); -- GitLab From 8cb3a2ebc19eef58bcbd5460c4fb463f30bc6459 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 22 Feb 2010 09:30:12 +0000 Subject: [PATCH 232/370] ARM: mach-shmobile: ap4evb: Add S6 debug switch support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 4714cad373b85..d9a46d0ce01c4 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -211,6 +211,20 @@ static void __init ap4evb_init(void) gpio_export(GPIO_PORT187, 0); gpio_export(GPIO_PORT188, 0); + /* enable Debug switch (S6) */ + gpio_request(GPIO_PORT32, NULL); + gpio_request(GPIO_PORT33, NULL); + gpio_request(GPIO_PORT34, NULL); + gpio_request(GPIO_PORT35, NULL); + gpio_direction_input(GPIO_PORT32); + gpio_direction_input(GPIO_PORT33); + gpio_direction_input(GPIO_PORT34); + gpio_direction_input(GPIO_PORT35); + gpio_export(GPIO_PORT32, 0); + gpio_export(GPIO_PORT33, 0); + gpio_export(GPIO_PORT34, 0); + gpio_export(GPIO_PORT35, 0); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); -- GitLab From 110d85acd479b80dc11b7fa3abef63285da8ea0c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 22 Feb 2010 23:26:47 +0000 Subject: [PATCH 233/370] ARM: S3C64XX: Eliminate plat-s3c64xx Now we've move the support out of plat-s3c64xx for everything, eliminate the platform directory arch/arm/plat-s3c64xx and remove it from the ARM build configuration. Note, PLAT_S3C64XX is kept around for the moment until the drivers that depend on it can be updated, so it is moved to the mach-s3c64xx Kconfig. Signed-off-by: Ben Dooks --- arch/arm/Makefile | 2 +- arch/arm/mach-s3c64xx/Kconfig | 9 +++++++++ arch/arm/plat-s3c64xx/Kconfig | 12 ------------ arch/arm/plat-s3c64xx/Makefile | 12 ------------ 4 files changed, 10 insertions(+), 25 deletions(-) delete mode 100644 arch/arm/plat-s3c64xx/Kconfig delete mode 100644 arch/arm/plat-s3c64xx/Makefile diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c1300d88a0146..5cda6e7cf86f1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,7 +183,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung -plat-$(CONFIG_ARCH_S3C64XX) := s3c64xx s3c samsung +plat-$(CONFIG_ARCH_S3C64XX) := s3c samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 8c2c89c24fce2..44cdd80ea107b 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -3,6 +3,15 @@ # # Licensed under GPLv2 +# temporary until we can eliminate all drivers using it. +config PLAT_S3C64XX + bool + depends on ARCH_S3C64XX + default y + help + Base platform code for any Samsung S3C64XX device + + # Configuration options for the S3C6410 CPU config CPU_S3C6400 diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig deleted file mode 100644 index ae034c2267f37..0000000000000 --- a/arch/arm/plat-s3c64xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics -# Ben Dooks -# -# Licensed under GPLv2 - -config PLAT_S3C64XX - bool - depends on ARCH_S3C64XX - default y - help - Base platform code for any Samsung S3C64XX device diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile deleted file mode 100644 index 7ca1c09995955..0000000000000 --- a/arch/arm/plat-s3c64xx/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# arch/arm/plat-s3c64xx/Makefile -# -# Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := dummy.o -obj- := - -- GitLab From c116c1d7254348c7247ec4d7ab005dcc3f42565b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:12 +0000 Subject: [PATCH 234/370] ARM: SAMSUNG: Move common headers from plat-s3c to plat-samsung Move common headers from plat-s3c's include/plat directory into plat-samsung. No need to fix any files, these are still included via Signed-off-by: Ben Dooks --- arch/arm/{plat-s3c => plat-samsung}/include/plat/audio.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/cpu-freq.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/cpu.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/debug-macro.S | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/devs.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/fb.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/pm.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-fb-v4.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-fb.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-serial.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/uncompress.h | 2 +- arch/arm/{plat-s3c => plat-samsung}/include/plat/usb-control.h | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/audio.h (91%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/cpu-freq.h (98%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/cpu.h (97%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/debug-macro.S (96%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/devs.h (98%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/fb.h (98%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/pm.h (99%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-fb-v4.h (99%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-fb.h (99%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/regs-serial.h (99%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/uncompress.h (98%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/usb-control.h (95%) diff --git a/arch/arm/plat-s3c/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h similarity index 91% rename from arch/arm/plat-s3c/include/plat/audio.h rename to arch/arm/plat-samsung/include/plat/audio.h index f22d23bb6271d..da561da2154f9 100644 --- a/arch/arm/plat-s3c/include/plat/audio.h +++ b/arch/arm/plat-samsung/include/plat/audio.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/audio.h +/* arch/arm/plat-samsung/include/plat/audio.h * * Copyright (c) 2009 Samsung Electronics Co. Ltd * Author: Jaswinder Singh diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h similarity index 98% rename from arch/arm/plat-s3c/include/plat/cpu-freq.h rename to arch/arm/plat-samsung/include/plat/cpu-freq.h index 94eb06a2ea5cf..80c4a809c721a 100644 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/cpu-freq.h +/* arch/arm/plat-samsung/include/plat/cpu-freq.h * * Copyright (c) 2006-2007 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h similarity index 97% rename from arch/arm/plat-s3c/include/plat/cpu.h rename to arch/arm/plat-samsung/include/plat/cpu.h index 676db94656749..d316b4a579f48 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c/include/plat/cpu.h +/* linux/arch/arm/plat-samsung/include/plat/cpu.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S similarity index 96% rename from arch/arm/plat-s3c/include/plat/debug-macro.S rename to arch/arm/plat-samsung/include/plat/debug-macro.S index 3634d4e3708b0..43ed0ec25f85a 100644 --- a/arch/arm/plat-s3c/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c/debug-macro.S +/* arch/arm/plat-samsung/include/plat/debug-macro.S * * Copyright 2005, 2007 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h similarity index 98% rename from arch/arm/plat-s3c/include/plat/devs.h rename to arch/arm/plat-samsung/include/plat/devs.h index c6f9b7310490e..0597ffae0cfce 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/devs.h +/* arch/arm/plat-samsung/include/plat/devs.h * * Copyright (c) 2004 Simtec Electronics * Ben Dooks diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h similarity index 98% rename from arch/arm/plat-s3c/include/plat/fb.h rename to arch/arm/plat-samsung/include/plat/fb.h index f8db87930f8b5..ffc01a76b7cee 100644 --- a/arch/arm/plat-s3c/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c/include/plat/fb.h +/* arch/arm/plat-samsung/include/plat/fb.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h similarity index 99% rename from arch/arm/plat-s3c/include/plat/pm.h rename to arch/arm/plat-samsung/include/plat/pm.h index 2543bd227f2d6..245836d919312 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/pm.h +/* arch/arm/plat-samsung/include/plat/pm.h * * Copyright (c) 2004 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h similarity index 99% rename from arch/arm/plat-s3c/include/plat/regs-fb-v4.h rename to arch/arm/plat-samsung/include/plat/regs-fb-v4.h index a60ed0d06c947..0f43599248ada 100644 --- a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h +/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h similarity index 99% rename from arch/arm/plat-s3c/include/plat/regs-fb.h rename to arch/arm/plat-samsung/include/plat/regs-fb.h index e9ee599d430eb..0ef806e50344e 100644 --- a/arch/arm/plat-s3c/include/plat/regs-fb.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/regs-fb.h +/* arch/arm/plat-samsung/include/plat/regs-fb.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h similarity index 99% rename from arch/arm/plat-s3c/include/plat/regs-serial.h rename to arch/arm/plat-samsung/include/plat/regs-serial.h index 60d6604185ea3..a6eba8496b24f 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-serial.h +/* arch/arm/plat-samsung/include/plat/regs-serial.h * * From linux/include/asm-arm/hardware/serial_s3c2410.h * diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h similarity index 98% rename from arch/arm/plat-s3c/include/plat/uncompress.h rename to arch/arm/plat-samsung/include/plat/uncompress.h index dc66a477f62e3..e87ce8ffbbcda 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c/uncompress.h +/* arch/arm/plat-samsung/include/plat/uncompress.h * * Copyright 2003, 2007 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s3c/include/plat/usb-control.h b/arch/arm/plat-samsung/include/plat/usb-control.h similarity index 95% rename from arch/arm/plat-s3c/include/plat/usb-control.h rename to arch/arm/plat-samsung/include/plat/usb-control.h index a6a57bf796bd3..7fa1fbefc3f22 100644 --- a/arch/arm/plat-s3c/include/plat/usb-control.h +++ b/arch/arm/plat-samsung/include/plat/usb-control.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/usb-control.h +/* arch/arm/plat-samsung/include/plat/usb-control.h * * Copyright (c) 2004 Simtec Electronics * Ben Dooks -- GitLab From 7086a9df056602c8e0d9ae8fe17b028832d05f3d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:13 +0000 Subject: [PATCH 235/370] ARM: SAMSUNG: Move map-base to plat-samsung Move the map-base file to plat-samsung. To make the move easier, we do not change the S3C_ prefix on many of the items as this would involve going through altering all the dependencies. Signed-off-by: Ben Dooks --- arch/arm/{plat-s3c => plat-samsung}/include/plat/map-base.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/map-base.h (100%) diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h similarity index 100% rename from arch/arm/plat-s3c/include/plat/map-base.h rename to arch/arm/plat-samsung/include/plat/map-base.h -- GitLab From 806c17b5497f62faa65a1fdd235b7fa2df17d704 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:14 +0000 Subject: [PATCH 236/370] ARM: SAMSUNG: Move pm.c to plat-samsung Move pm.c to plat-samsung, it should be usable by all Samsung systems Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 4 ---- arch/arm/plat-samsung/Makefile | 1 + arch/arm/{plat-s3c => plat-samsung}/pm.c | 0 3 files changed, 1 insertion(+), 4 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/pm.c (100%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 89dbdb0adebf1..197b9bd139acc 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -17,7 +17,3 @@ obj-y += time.o # DMA support obj-$(CONFIG_S3C_DMA) += dma.o - -# PM support - -obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index c8c8caec8cde0..629fd9f92a246 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o # PM support +obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm-gpio.o obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-samsung/pm.c similarity index 100% rename from arch/arm/plat-s3c/pm.c rename to arch/arm/plat-samsung/pm.c -- GitLab From 2c420fe22f3d526691773288807d010068ce3033 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:15 +0000 Subject: [PATCH 237/370] ARM: SAMSUNG: Move DMA support to plat-samsung Move the core of the DMA support to plat-samsung for everyone to use. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 4 ---- arch/arm/plat-samsung/Makefile | 4 ++++ arch/arm/{plat-s3c => plat-samsung}/dma.c | 0 arch/arm/{plat-s3c => plat-samsung}/include/plat/dma.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/dma.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/include/plat/dma.h (98%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 197b9bd139acc..2a3c4a49117a5 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -13,7 +13,3 @@ obj- := obj-y += init.o obj-y += time.o - -# DMA support - -obj-$(CONFIG_S3C_DMA) += dma.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 629fd9f92a246..facc7e387fc5d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -39,6 +39,10 @@ obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o +# DMA support + +obj-$(CONFIG_S3C_DMA) += dma.o + # PM support obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-samsung/dma.c similarity index 100% rename from arch/arm/plat-s3c/dma.c rename to arch/arm/plat-samsung/dma.c diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h similarity index 98% rename from arch/arm/plat-s3c/include/plat/dma.h rename to arch/arm/plat-samsung/include/plat/dma.h index e429d10be3ada..7584d751ed513 100644 --- a/arch/arm/plat-s3c/include/plat/dma.h +++ b/arch/arm/plat-samsung/include/plat/dma.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/dma.h +/* arch/arm/plat-samsung/include/plat/dma.h * * Copyright (C) 2003-2006 Simtec Electronics * Ben Dooks -- GitLab From 6c6971dc4e8c23bb61bf309898e1693f9c5c8c24 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:16 +0000 Subject: [PATCH 238/370] ARM: SAMSUNG: Move the last build from plat-s3c to plat-samsung Move the init.c and time.c files to plat-samsung from plat-s3c, thus clearing the last files that are being built in here. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 4 +--- arch/arm/plat-samsung/Makefile | 2 ++ arch/arm/plat-samsung/dma.c | 2 +- arch/arm/{plat-s3c => plat-samsung}/init.c | 0 arch/arm/{plat-s3c => plat-samsung}/time.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/{plat-s3c => plat-samsung}/init.c (100%) rename arch/arm/{plat-s3c => plat-samsung}/time.c (99%) diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 2a3c4a49117a5..867c9cf755a70 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -6,10 +6,8 @@ obj-y := obj-m := -obj-n := +obj-n := dummy.o obj- := # Core support for all Samsung SoCs -obj-y += init.o -obj-y += time.o diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index facc7e387fc5d..22c89d08f6e52 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -11,6 +11,8 @@ obj- := # Objects we always build independent of SoC choice +obj-y += init.o +obj-y += time.o obj-y += clock.o obj-y += pwm-clock.o obj-y += gpio.o diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c index 606db1af5fe75..cb459dd954595 100644 --- a/arch/arm/plat-samsung/dma.c +++ b/arch/arm/plat-samsung/dma.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c/dma.c +/* linux/arch/arm/plat-samsung/dma.c * * Copyright (c) 2003-2009 Simtec Electronics * Ben Dooks diff --git a/arch/arm/plat-s3c/init.c b/arch/arm/plat-samsung/init.c similarity index 100% rename from arch/arm/plat-s3c/init.c rename to arch/arm/plat-samsung/init.c diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-samsung/time.c similarity index 99% rename from arch/arm/plat-s3c/time.c rename to arch/arm/plat-samsung/time.c index 3b27b29da4787..2231d80ad8173 100644 --- a/arch/arm/plat-s3c/time.c +++ b/arch/arm/plat-samsung/time.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/time.c +/* linux/arch/arm/plat-samsung/time.c * * Copyright (C) 2003-2005 Simtec Electronics * Ben Dooks, -- GitLab From 41dcc17c735d4e99a91002b09850d0f09ee4ab4b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 19 Feb 2010 07:52:12 +0000 Subject: [PATCH 239/370] ARM: mach-shmobile: pfc-sh7377: modify KEYIN settings Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/pfc-sh7377.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c index 79b53d87d91ba..613e6842ad052 100644 --- a/arch/arm/mach-shmobile/pfc-sh7377.c +++ b/arch/arm/mach-shmobile/pfc-sh7377.c @@ -102,6 +102,7 @@ enum { PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */ MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, + MSELBCR_MSEL16_1, MSELBCR_MSEL16_0, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, @@ -528,19 +529,19 @@ static pinmux_enum_t pinmux_data[] = { PORT_DATA_IO_PU_PD(263), /* Special Pull-up / Pull-down Functions */ - PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT66_FN2, PORT66_IN_PU), - PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT67_FN2, PORT67_IN_PU), - PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT68_FN2, PORT68_IN_PU), - PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT69_FN2, PORT69_IN_PU), - PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT70_FN2, PORT70_IN_PU), - PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT71_FN2, PORT71_IN_PU), - PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT72_FN2, PORT72_IN_PU), @@ -1637,7 +1638,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MSELBCR_MSEL17_0, MSELBCR_MSEL17_1, - 0, 0, + MSELBCR_MSEL16_0, MSELBCR_MSEL16_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, -- GitLab From d8ecb3490050b33bf46ce77c7f239e0fc51a6835 Mon Sep 17 00:00:00 2001 From: John Holland Date: Fri, 19 Feb 2010 23:10:58 +0100 Subject: [PATCH 240/370] [ARM] eSATA SheevaPlug basic board support Allow basic eSATA SheevaPlug board configuration and build. Signed-off-by: John Holland Signed-off-by: Nicolas Pitre -- --- arch/arm/mach-kirkwood/Kconfig | 6 ++++++ arch/arm/mach-kirkwood/Makefile | 1 + arch/arm/mach-kirkwood/sheevaplug-setup.c | 14 ++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f6c6196a51fa4..1b8addaeb497d 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -32,6 +32,12 @@ config MACH_SHEEVAPLUG Say 'Y' here if you want your kernel to support the Marvell SheevaPlug Reference Board. +config MACH_ESATA_SHEEVAPLUG + bool "Marvell eSATA SheevaPlug Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell eSATA SheevaPlug Reference Board. + config MACH_TS219 bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index d4d7f53b0fb9d..704b8927dbb7f 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o +obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index c7319eeac8bbc..629ce84ae4339 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -96,6 +96,7 @@ static void __init sheevaplug_init(void) platform_device_register(&sheevaplug_leds); } +#ifdef CONFIG_MACH_SHEEVAPLUG MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") /* Maintainer: shadi Ammouri */ .phys_io = KIRKWOOD_REGS_PHYS_BASE, @@ -106,3 +107,16 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") .init_irq = kirkwood_init_irq, .timer = &kirkwood_timer, MACHINE_END +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = sheevaplug_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif -- GitLab From d7b222d708e6eff0cf47928f439c8bcf49f10bb6 Mon Sep 17 00:00:00 2001 From: John Holland Date: Fri, 19 Feb 2010 23:11:01 +0100 Subject: [PATCH 241/370] [ARM] eSATA SheevaPlug: configure SoC SATA interface Enable the kirkwood SATA SoC interface on the eSATA SheevaPlug. Signed-off-by: John Holland Signed-off-by: Nicolas Pitre -- --- arch/arm/mach-kirkwood/sheevaplug-setup.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 629ce84ae4339..bb9bc70381ef1 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,10 @@ static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; +static struct mv_sata_platform_data sheeva_esata_sata_data = { + .n_ports = 2, +}; + static struct mvsdio_platform_data sheevaplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ }; @@ -91,6 +96,11 @@ static void __init sheevaplug_init(void) kirkwood_ehci_init(); kirkwood_ge00_init(&sheevaplug_ge00_data); + + /* honor lower power consumption for plugs with out eSATA */ + if (machine_is_sheeva_esata()) + kirkwood_sata_init(&sheeva_esata_sata_data); + kirkwood_sdio_init(&sheevaplug_mvsdio_data); platform_device_register(&sheevaplug_leds); -- GitLab From d5b5746bed1023e4a55f96405422d3e51968fa43 Mon Sep 17 00:00:00 2001 From: John Holland Date: Fri, 19 Feb 2010 23:11:04 +0100 Subject: [PATCH 242/370] [ARM] eSATA SheevaPlug: correlate MPP to SD CD and SD WP Accept SD CD and SD WP in accordance to http://plugcomputer.org/data/docs/Sheeva-PowerPlug-V1.3-GTI-090906.pdf on MPP 47 and 44 respectively on the eSATA SheevaPlug Signed-off-by: John Holland Signed-off-by: Nicolas Pitre -- --- arch/arm/mach-kirkwood/sheevaplug-setup.c | 26 +++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index bb9bc70381ef1..a00879d34d541 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -51,6 +51,11 @@ static struct mvsdio_platform_data sheevaplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ }; +static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { + .gpio_write_protect = 44, /* MPP44 used as SD write protect */ + .gpio_card_detect = 47, /* MPP47 used as SD card detect */ +}; + static struct gpio_led sheevaplug_led_pins[] = { { .name = "plug:green:health", @@ -79,13 +84,26 @@ static unsigned int sheevaplug_mpp_config[] __initdata = { 0 }; +static unsigned int sheeva_esata_mpp_config[] __initdata = { + MPP29_GPIO, /* USB Power Enable */ + MPP44_GPIO, /* SD Write Protect */ + MPP47_GPIO, /* SD Card Detect */ + MPP49_GPIO, /* LED Green */ + 0 +}; + static void __init sheevaplug_init(void) { /* * Basic setup. Needs to be called early. */ kirkwood_init(); - kirkwood_mpp_conf(sheevaplug_mpp_config); + + /* setup gpio pin select */ + if (machine_is_sheeva_esata()) + kirkwood_mpp_conf(sheeva_esata_mpp_config); + else + kirkwood_mpp_conf(sheevaplug_mpp_config); kirkwood_uart0_init(); kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25); @@ -101,7 +119,11 @@ static void __init sheevaplug_init(void) if (machine_is_sheeva_esata()) kirkwood_sata_init(&sheeva_esata_sata_data); - kirkwood_sdio_init(&sheevaplug_mvsdio_data); + /* enable sd wp and sd cd on plugs with esata */ + if (machine_is_sheeva_esata()) + kirkwood_sdio_init(&sheeva_esata_mvsdio_data); + else + kirkwood_sdio_init(&sheevaplug_mvsdio_data); platform_device_register(&sheevaplug_leds); } -- GitLab From ee40ceab234d34abdfeb9922d0f1a18bfa7efdaf Mon Sep 17 00:00:00 2001 From: Sebastien Requiem Date: Tue, 23 Feb 2010 14:38:14 +0100 Subject: [PATCH 243/370] =?UTF-8?q?[ARM]=C2=A0MV78XX0:=20MPP=20routines=20?= =?UTF-8?q?and=20definitions?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch is composed of two new files : - mpp.c which is mainly inspired by the same file as in mach-kirkwood - mpp.h that is written from the documentation provided by Marvell http://www.marvell.com/products/processors/embedded/discovery_innovation/HW_MV78100_OpenSource.pdf Moreover, due to some implementation problem, I have defined some MPPX_UNUSED that offer developers the possibility to SET MPP to some unused value (such as for Buffalo WXL). Note: This patch doesn't support MV78200 yet (only 78100 MPP lines have been written) Signed-off-by: Sebastien Requiem Signed-off-by: Nicolas Pitre --- arch/arm/mach-mv78xx0/Makefile | 2 +- arch/arm/mach-mv78xx0/mpp.c | 96 +++++++++ arch/arm/mach-mv78xx0/mpp.h | 347 +++++++++++++++++++++++++++++++++ 3 files changed, 444 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-mv78xx0/mpp.c create mode 100644 arch/arm/mach-mv78xx0/mpp.h diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index da628b7f3bb65..4948eeeda5aab 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,3 +1,3 @@ -obj-y += common.o addr-map.o irq.o pcie.o +obj-y += common.o addr-map.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c new file mode 100644 index 0000000000000..354ac514eb899 --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-mv78x00/mpp.c + * + * MPP functions for Marvell MV78x00 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + +static unsigned int __init mv78xx0_variant(void) +{ + u32 dev, rev; + + mv78xx0_pcie_id(&dev, &rev); + + if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0) + return MPP_78100_A0_MASK; + + printk(KERN_ERR "MPP setup: unknown mv78x00 variant " + "(dev %#x rev %#x)\n", dev, rev); + return 0; +} + +#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) +#define MPP_NR_REGS (1 + MPP_MAX/8) + +void __init mv78xx0_mpp_conf(unsigned int *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + unsigned int variant_mask; + int i; + + variant_mask = mv78xx0_variant(); + if (!variant_mask) + return; + + /* Initialize gpiolib. */ + orion_gpio_init(); + + printk(KERN_DEBUG "initial MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + mpp_ctrl[i] = readl(MPP_CTRL(i)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); + + while (*mpp_list) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift, gpio_mode; + + if (num > MPP_MAX) { + printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + printk(KERN_WARNING + "mv78xx0_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + gpio_mode = 0; + if (*mpp_list & MPP_INPUT_MASK) + gpio_mode |= GPIO_INPUT_OK; + if (*mpp_list & MPP_OUTPUT_MASK) + gpio_mode |= GPIO_OUTPUT_OK; + if (sel != 0) + gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); + + mpp_list++; + } + + printk(KERN_DEBUG " final MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + writel(mpp_ctrl[i], MPP_CTRL(i)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); +} diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h new file mode 100644 index 0000000000000..80840b781eaa2 --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -0,0 +1,347 @@ +/* + * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins + * + * + * sebastien requiem + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MV78X00_MPP_H +#define __MV78X00_MPP_H + +#define MPP(_num, _sel, _in, _out, _78100_A0) (\ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on A0 */ ((!!(_78100_A0)) << 14)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 78100_A0 */ + +#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0) +#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0) + +#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) + +#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) +#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) +#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) + +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) +#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) +#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) + +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) +#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) +#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) +#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) + +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) +#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) +#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) + +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) +#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) + +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) +#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) + +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) +#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) + +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) +#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) + +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) +#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) +#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) +#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) + +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) +#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) +#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) +#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) + +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) +#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) +#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) +#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) + +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) +#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) +#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) +#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) + +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) +#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) +#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) +#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) + +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) +#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) + +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) +#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) +#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) + +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) +#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) +#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) + +#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) +#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) +#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) + + +#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) +#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) +#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) + + +#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) +#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) +#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) + + + +#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) +#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) + + +#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) +#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) +#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) +#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) + + + +#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) +#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) +#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) + + + +#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) +#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) +#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) + + + +#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) +#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) +#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) + + +#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) +#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) +#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) + + +#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) +#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) +#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) + + +#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) +#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) +#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) +#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) + + +#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) +#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) +#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) + + +#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) +#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) +#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) + +#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) +#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) +#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) + +#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) +#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) +#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) + +#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) +#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) + + +#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) +#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) + + +#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) +#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) +#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) + + + +#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) +#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) + + + +#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) +#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) +#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) + +#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) +#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) +#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) + + +#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) +#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) +#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) + + + + +#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) +#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) +#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) + + + + +#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) +#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) +#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) +#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) + + + +#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) +#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) +#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) + + + +#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) +#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) + + + +#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) +#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) +#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) + + + +#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) +#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) +#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) + + + +#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) +#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) +#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) + + + +#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) +#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) + + +#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) +#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) + + +#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1) +#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1) + + + +#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) +#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) + + + +#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) +#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) +#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) + + +#define MPP_MAX 49 + +void mv78xx0_mpp_conf(unsigned int *mpp_list); + +#endif -- GitLab From c499546f43f2c31b681271ef7db922839fcde5fe Mon Sep 17 00:00:00 2001 From: Sebastien Requiem Date: Tue, 23 Feb 2010 14:51:24 +0100 Subject: [PATCH 244/370] [ARM] MV78xx0: Support for Buffalo WXL (Terastation Duo) * Modification of Kconfig to add the Option * 1 new file : buffalo-wxl-setup.c This file is inspired from the db-78xx0-setup.c already present. The following is done: - Configure MPP Lines for the plateform (see my patch for MPP) This is taken from the stock kernel provided by buffalotech (the vendor) - GigaBit Ethernet - Sata - Uart are initiallized in a different way than on the dev board as we have one core only. - USB The kernel has been running for some days now on my plateform. Signed-off-by: Sebastien Requiem Signed-off-by: Nicolas Pitre --- arch/arm/configs/mv78xx0_defconfig | 1 + arch/arm/mach-mv78xx0/Kconfig | 6 + arch/arm/mach-mv78xx0/Makefile | 1 + arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 155 ++++++++++++++++++++++ 4 files changed, 163 insertions(+) create mode 100644 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 6afa2c108eaaf..da4710dd1da15 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -176,6 +176,7 @@ CONFIG_ARCH_MV78XX0=y # CONFIG_MACH_DB78X00_BP=y CONFIG_MACH_RD78X00_MASA=y +CONFIG_MACH_TERASTATION_WXL=y CONFIG_PLAT_ORION=y # diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index 6fbe68fe4412a..f2d309d0619ea 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -14,6 +14,12 @@ config MACH_RD78X00_MASA Say 'Y' here if you want your kernel to support the Marvell RD-78x00-mASA Reference Design. +config MACH_TERASTATION_WXL + bool "Buffalo WLX (Terastation Duo) NAS" + help + Say 'Y' here if you want your kernel to support the + Buffalo WXL Nas. + endmenu endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 4948eeeda5aab..67a13f9bfe643 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,3 +1,4 @@ obj-y += common.o addr-map.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o +obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c new file mode 100644 index 0000000000000..61e5e583603b1 --- /dev/null +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -0,0 +1,155 @@ +/* + * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c + * + * Buffalo WXL (Terastation Duo) Setup routines + * + * sebastien requiem + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + + +/* This arch has 2 Giga Ethernet */ + +static struct mv643xx_eth_platform_data db78x00_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct mv643xx_eth_platform_data db78x00_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + + +/* 2 SATA controller supporting HotPlug */ + +static struct mv_sata_platform_data db78x00_sata_data = { + .n_ports = 2, +}; + +static struct i2c_board_info __initdata db78x00_i2c_rtc = { + I2C_BOARD_INFO("ds1338", 0x68), +}; + + +static unsigned int wxl_mpp_config[] __initdata = { + MPP0_GE1_TXCLK, + MPP1_GE1_TXCTL, + MPP2_GE1_RXCTL, + MPP3_GE1_RXCLK, + MPP4_GE1_TXD0, + MPP5_GE1_TXD1, + MPP6_GE1_TXD2, + MPP7_GE1_TXD3, + MPP8_GE1_RXD0, + MPP9_GE1_RXD1, + MPP10_GE1_RXD2, + MPP11_GE1_RXD3, + MPP12_GPIO, + MPP13_SYSRST_OUTn, + MPP14_SATA1_ACTn, + MPP15_SATA0_ACTn, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPIO, + MPP19_GPIO, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_UA2_TXD, + MPP25_UA2_RXD, + MPP26_UA2_CTSn, + MPP27_UA2_RTSn, + MPP28_GPIO, + MPP29_SYSRST_OUTn, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_UNUSED, + MPP41_UNUSED, + MPP42_UNUSED, + MPP43_UNUSED, + MPP44_UNUSED, + MPP45_UNUSED, + MPP46_UNUSED, + MPP47_UNUSED, + MPP48_SATA1_ACTn, + MPP49_SATA0_ACTn, + 0 +}; + + +static void __init wxl_init(void) +{ + /* + * Basic MV78xx0 setup. Needs to be called early. + */ + mv78xx0_init(); + mv78xx0_mpp_conf(wxl_mpp_config); + + /* + * Partition on-chip peripherals between the two CPU cores. + */ + mv78xx0_ehci0_init(); + mv78xx0_ehci1_init(); + mv78xx0_ehci2_init(); + mv78xx0_ge00_init(&db78x00_ge00_data); + mv78xx0_ge01_init(&db78x00_ge01_data); + mv78xx0_sata_init(&db78x00_sata_data); + mv78xx0_uart0_init(); + mv78xx0_uart1_init(); + mv78xx0_uart2_init(); + mv78xx0_uart3_init(); + mv78xx0_i2c_init(); + i2c_register_board_info(0, &db78x00_i2c_rtc, 1); +} + +static int __init wxl_pci_init(void) +{ + if (machine_is_terastation_wxl()) { + /* + * Assign the x16 PCIe slot on the board to CPU core + * #0, and let CPU core #1 have the four x1 slots. + */ + if (mv78xx0_core_index() == 0) + mv78xx0_pcie_init(0, 1); + else + mv78xx0_pcie_init(1, 0); + } + + return 0; +} +subsys_initcall(wxl_pci_init); + +MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") + /* Maintainer: Sebastien Requiem */ + .phys_io = MV78XX0_REGS_PHYS_BASE, + .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = wxl_init, + .map_io = mv78xx0_map_io, + .init_irq = mv78xx0_init_irq, + .timer = &mv78xx0_timer, +MACHINE_END -- GitLab From 89f1fa080b5dca259c9779bcf81b95a409fdbf5b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:17 +0000 Subject: [PATCH 245/370] ARM: SAMSUNG: Move plat-s3c Kconfig entries to plat-samsung and plat-s3c24xx Move the Kconfig entries from plat-s3c to plat-samsung and plat-s3c24xx as necessary. The S3C_BOOT entries and the DMA configuration can go to plat-samsung. The low-level UART configurations are currently S3C2XX specific and can go to plat-s3c24xx. Eliminating plat-s3c from the build process will be submitted seperately. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 2 +- arch/arm/Kconfig.debug | 2 +- arch/arm/mach-s5pc100/include/mach/io.h | 18 +++++ arch/arm/mach-s5pc100/include/mach/timex.h | 24 ++++++ arch/arm/mach-s5pc100/include/mach/vmalloc.h | 17 ++++ arch/arm/plat-s3c/Kconfig | 85 -------------------- arch/arm/plat-s3c24xx/Kconfig | 22 +++++ arch/arm/plat-s5p/Kconfig | 1 - arch/arm/plat-samsung/Kconfig | 59 ++++++++++++++ 9 files changed, 142 insertions(+), 88 deletions(-) create mode 100644 arch/arm/mach-s5pc100/include/mach/io.h create mode 100644 arch/arm/mach-s5pc100/include/mach/timex.h create mode 100644 arch/arm/mach-s5pc100/include/mach/vmalloc.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9618dcfa66f35..5c691c658074e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -627,7 +627,7 @@ config ARCH_S3C2410 config ARCH_S3C64XX bool "Samsung S3C64XX" - select PLAT_S3C + select PLAT_SAMSUNG select CPU_V6 select GENERIC_GPIO select ARM_VIC diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5cb9326df7a7a..91344af75f396 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -117,7 +117,7 @@ config DEBUG_CLPS711X_UART2 cause the debug messages to appear on the first serial port. config DEBUG_S3C_UART - depends on PLAT_S3C + depends on PLAT_SAMSUNG int "S3C UART to use for low-level debug" default "0" help diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h new file mode 100644 index 0000000000000..819acf5eaf892 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/io.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s5pc100/include/mach/io.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * + * Default IO routines for S5PC100 systems + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s5pc100/include/mach/timex.h b/arch/arm/mach-s5pc100/include/mach/timex.h new file mode 100644 index 0000000000000..47ffb17aff962 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s5pc100/include/mach/timex.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + * + * S3C6400 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h new file mode 100644 index 0000000000000..61b95158a437b --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/vmalloc.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5pc100/include/mach/vmalloc.h + * + * Copyright 2010 Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C6400 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 2367908c4f626..6108ba9c2beeb 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -9,88 +9,3 @@ config PLAT_S3C select NO_IOPORT help Base platform code for any Samsung S3C device - -# low-level serial option nodes - -if PLAT_S3C - -config CPU_LLSERIAL_S3C2410_ONLY - bool - default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 - -config CPU_LLSERIAL_S3C2440_ONLY - bool - default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 - -config CPU_LLSERIAL_S3C2410 - bool - help - Selected if there is an S3C2410 (or register compatible) serial - low-level implementation needed - -config CPU_LLSERIAL_S3C2440 - bool - help - Selected if there is an S3C2440 (or register compatible) serial - low-level implementation needed - -# boot configurations - -comment "Boot options" - -config S3C_BOOT_WATCHDOG - bool "S3C Initialisation watchdog" - depends on S3C2410_WATCHDOG - help - Say y to enable the watchdog during the kernel decompression - stage. If the kernel fails to uncompress, then the watchdog - will trigger a reset and the system should restart. - -config S3C_BOOT_ERROR_RESET - bool "S3C Reboot on decompression error" - help - Say y here to use the watchdog to reset the system if the - kernel decompressor detects an error during decompression. - -config S3C_BOOT_UART_FORCE_FIFO - bool "Force UART FIFO on during boot process" - default y - help - Say Y here to force the UART FIFOs on during the kernel - uncompressor - - -config S3C_LOWLEVEL_UART_PORT - int "S3C UART to use for low-level messages" - default 0 - help - Choice of which UART port to use for the low-level messages, - such as the `Uncompressing...` at start time. The value of - this configuration should be between zero and two. The port - must have been initialised by the boot-loader before use. - -# options for gpiolib support - -config S3C_GPIO_SPACE - int "Space between gpio banks" - default 0 - help - Add a number of spare GPIO entries between each bank for debugging - purposes. This allows any problems where an counter overflows from - one bank to another to be caught, at the expense of using a little - more memory. - -config S3C_GPIO_TRACK - bool - help - Internal configuration option to enable the s3c specific gpio - chip tracking if the platform requires it. - -# DMA - -config S3C_DMA - bool - help - Internal configuration for S3C DMA core - -endif diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 0cc5760b668a1..6e93ef8f3d43f 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -14,6 +14,28 @@ config PLAT_S3C24XX if PLAT_S3C24XX +# low-level serial option nodes + +config CPU_LLSERIAL_S3C2410_ONLY + bool + default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 + +config CPU_LLSERIAL_S3C2440_ONLY + bool + default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 + +config CPU_LLSERIAL_S3C2410 + bool + help + Selected if there is an S3C2410 (or register compatible) serial + low-level implementation needed + +config CPU_LLSERIAL_S3C2440 + bool + help + Selected if there is an S3C2440 (or register compatible) serial + low-level implementation needed + # code that is shared between a number of the s3c24xx implementations config S3C2410_CLOCK diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index fca6dade9fd9c..e5d1305764a38 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -9,7 +9,6 @@ config PLAT_S5P bool depends on ARCH_S5P6440 default y - select PLAT_S3C select ARM_VIC select NO_IOPORT select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 72da6461db128..93bd89385f599 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -13,6 +13,43 @@ config PLAT_SAMSUNG if PLAT_SAMSUNG +# boot configurations + +comment "Boot options" + +config S3C_BOOT_WATCHDOG + bool "S3C Initialisation watchdog" + depends on S3C2410_WATCHDOG + help + Say y to enable the watchdog during the kernel decompression + stage. If the kernel fails to uncompress, then the watchdog + will trigger a reset and the system should restart. + +config S3C_BOOT_ERROR_RESET + bool "S3C Reboot on decompression error" + help + Say y here to use the watchdog to reset the system if the + kernel decompressor detects an error during decompression. + +config S3C_BOOT_UART_FORCE_FIFO + bool "Force UART FIFO on during boot process" + default y + help + Say Y here to force the UART FIFOs on during the kernel + uncompressor + + +config S3C_LOWLEVEL_UART_PORT + int "S3C UART to use for low-level messages" + default 0 + help + Choice of which UART port to use for the low-level messages, + such as the `Uncompressing...` at start time. The value of + this configuration should be between zero and two. The port + must have been initialised by the boot-loader before use. + +# clock options + config SAMSUNG_CLKSRC bool help @@ -81,6 +118,21 @@ config SAMSUNG_GPIO_EXTRA provides. This allows expanding the GPIO space for use with GPIO expanders. +config S3C_GPIO_SPACE + int "Space between gpio banks" + default 0 + help + Add a number of spare GPIO entries between each bank for debugging + purposes. This allows any problems where an counter overflows from + one bank to another to be caught, at the expense of using a little + more memory. + +config S3C_GPIO_TRACK + bool + help + Internal configuration option to enable the s3c specific gpio + chip tracking if the platform requires it. + # ADC driver config S3C_ADC @@ -138,6 +190,13 @@ config S3C64XX_DEV_SPI Compile in platform device definitions for S3C64XX's type SPI controllers. +# DMA + +config S3C_DMA + bool + help + Internal configuration for S3C DMA core + comment "Power management" config SAMSUNG_PM_DEBUG -- GitLab From 46ba2a7284fbd61fcba1e16bdd723c79ec5c268f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:18 +0000 Subject: [PATCH 246/370] ARM: S3C24XX: Move audio-simtec.h to plat-s3c24xx Continue the clearout of plat-s3c by moving audio-simtec.h to plat-s3c24xx as there are no current implementations outside of this platform. Signed-off-by: Ben Dooks --- arch/arm/{plat-s3c => plat-s3c24xx}/include/plat/audio-simtec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename arch/arm/{plat-s3c => plat-s3c24xx}/include/plat/audio-simtec.h (95%) diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h similarity index 95% rename from arch/arm/plat-s3c/include/plat/audio-simtec.h rename to arch/arm/plat-s3c24xx/include/plat/audio-simtec.h index 53a93656d5db9..de5e88fdcb31c 100644 --- a/arch/arm/plat-s3c/include/plat/audio-simtec.h +++ b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/audio-simtec.h +/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h * * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ -- GitLab From ae5fa355ec571525fab60f66dd9d6a2b12c7575e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:19 +0000 Subject: [PATCH 247/370] ARM: SAMSUNG: Select NO_IOPORT for plat-samsung All these platforms select NO_IOPORT, so move it to plat-samsung Kconfig Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 93bd89385f599..d552c65fa1b05 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -7,6 +7,7 @@ config PLAT_SAMSUNG bool depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX + select NO_IOPORT default y help Base platform code for all Samsung SoC based systems -- GitLab From f94327f2cebf3711defd25375df0c380562127ba Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 09:02:20 +0000 Subject: [PATCH 248/370] ARM: SAMSUNG: Move include/mach files out of plat-s3c Move the include/mach files out of plat-s3c and into the relevant machine files. This does mean copying the files, but there is nowhere else to put them. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/timex.h | 24 ++++++++++++++++++++ arch/arm/mach-s3c2410/include/mach/vmalloc.h | 20 ++++++++++++++++ arch/arm/mach-s3c24a0/include/mach/io.h | 18 +++++++++++++++ arch/arm/mach-s3c64xx/include/mach/io.h | 18 +++++++++++++++ arch/arm/mach-s3c64xx/include/mach/timex.h | 24 ++++++++++++++++++++ arch/arm/mach-s3c64xx/include/mach/vmalloc.h | 20 ++++++++++++++++ arch/arm/mach-s5p6440/include/mach/io.h | 18 +++++++++++++++ arch/arm/mach-s5p6440/include/mach/timex.h | 24 ++++++++++++++++++++ arch/arm/mach-s5p6440/include/mach/vmalloc.h | 17 ++++++++++++++ 9 files changed, 183 insertions(+) create mode 100644 arch/arm/mach-s3c2410/include/mach/timex.h create mode 100644 arch/arm/mach-s3c2410/include/mach/vmalloc.h create mode 100644 arch/arm/mach-s3c24a0/include/mach/io.h create mode 100644 arch/arm/mach-s3c64xx/include/mach/io.h create mode 100644 arch/arm/mach-s3c64xx/include/mach/timex.h create mode 100644 arch/arm/mach-s3c64xx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-s5p6440/include/mach/io.h create mode 100644 arch/arm/mach-s5p6440/include/mach/timex.h create mode 100644 arch/arm/mach-s5p6440/include/mach/vmalloc.h diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h new file mode 100644 index 0000000000000..fe9ca1ffd51b1 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s3c2410/include/mach/timex.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + * + * S3C2410 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h new file mode 100644 index 0000000000000..315b0078a34d6 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-s3c2410/include/mach/vmalloc.h + * + * from arch/arm/mach-iop3xx/include/mach/vmalloc.h + * + * Copyright (c) 2003 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h new file mode 100644 index 0000000000000..4326c30fabcb2 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/io.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s3c24a0/include/mach/io.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * + * Default IO routines for S3C24A0 + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h new file mode 100644 index 0000000000000..de5716dbbd652 --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/io.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s3c64xxinclude/mach/io.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * + * Default IO routines for S3C64XX based + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s3c64xx/include/mach/timex.h b/arch/arm/mach-s3c64xx/include/mach/timex.h new file mode 100644 index 0000000000000..fb2e8cd408293 --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s3c64xx/include/mach/timex.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + * + * S3C6400 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h new file mode 100644 index 0000000000000..7411ef3711a6e --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h + * + * from arch/arm/mach-iop3xx/include/mach/vmalloc.h + * + * Copyright (c) 2003 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C6400 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h new file mode 100644 index 0000000000000..fa2d69cb1ad7d --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/io.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s5p6440/include/mach/io.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * + * Default IO routines for S3C64XX based + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p6440/include/mach/timex.h new file mode 100644 index 0000000000000..fb2e8cd408293 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s3c64xx/include/mach/timex.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + * + * S3C6400 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p6440/include/mach/vmalloc.h new file mode 100644 index 0000000000000..16df257b1dce7 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/vmalloc.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5p6440/include/mach/vmalloc.h + * + * Copyright 2010 Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C6400 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ -- GitLab From 7965b214bfbe0e6b3dc843cd1d639dc2711ff86e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Feb 2010 00:18:36 +0000 Subject: [PATCH 249/370] ARM: SAMSUNG: Eliminate plat-s3c The plat-s3c directory is now clear, so remove the files in it and expunge it from the build process. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 1 - arch/arm/Makefile | 8 ++++---- arch/arm/plat-s3c/Kconfig | 11 ---------- arch/arm/plat-s3c/Makefile | 13 ------------ arch/arm/plat-s3c/include/mach/io.h | 18 ---------------- arch/arm/plat-s3c/include/mach/timex.h | 26 ------------------------ arch/arm/plat-s3c/include/mach/vmalloc.h | 20 ------------------ 7 files changed, 4 insertions(+), 93 deletions(-) delete mode 100644 arch/arm/plat-s3c/Kconfig delete mode 100644 arch/arm/plat-s3c/Makefile delete mode 100644 arch/arm/plat-s3c/include/mach/io.h delete mode 100644 arch/arm/plat-s3c/include/mach/timex.h delete mode 100644 arch/arm/plat-s3c/include/mach/vmalloc.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5c691c658074e..fd4882e61dd51 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,7 +799,6 @@ source "arch/arm/mach-dove/Kconfig" source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" -source "arch/arm/plat-s3c/Kconfig" source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a2a941d98c25c..13c5c2be31ade 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -182,10 +182,10 @@ plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa -plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung -plat-$(CONFIG_ARCH_S3C64XX) := s3c samsung -plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung -plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c +plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung +plat-$(CONFIG_ARCH_S3C64XX) := samsung +plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung +plat-$(CONFIG_PLAT_S5P) := s5p samsung plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig deleted file mode 100644 index 6108ba9c2beeb..0000000000000 --- a/arch/arm/plat-s3c/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -config PLAT_S3C - bool - depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX - default y - select NO_IOPORT - help - Base platform code for any Samsung S3C device diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile deleted file mode 100644 index 867c9cf755a70..0000000000000 --- a/arch/arm/plat-s3c/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# arch/arm/plat-s3c/Makefile -# -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := dummy.o -obj- := - -# Core support for all Samsung SoCs - diff --git a/arch/arm/plat-s3c/include/mach/io.h b/arch/arm/plat-s3c/include/mach/io.h deleted file mode 100644 index f6a53631b6658..0000000000000 --- a/arch/arm/plat-s3c/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/plat-s3c/include/mach/io.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks - * - * Default IO routines for plat-s3c based systems, such as S3C24A0 - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* No current ISA/PCI bus support. */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#define IO_SPACE_LIMIT (0xFFFFFFFF) - -#endif diff --git a/arch/arm/plat-s3c/include/mach/timex.h b/arch/arm/plat-s3c/include/mach/timex.h deleted file mode 100644 index 2a425ed0a7e0a..0000000000000 --- a/arch/arm/plat-s3c/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks - * - * S3C2410 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - - -#define CLOCK_TICK_RATE 12000000 - - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/plat-s3c/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h deleted file mode 100644 index bfd2ca6e3074a..0000000000000 --- a/arch/arm/plat-s3c/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* arch/arm/plat-s3c/include/mach/vmalloc.h - * - * from arch/arm/mach-iop3xx/include/mach/vmalloc.h - * - * Copyright (c) 2003 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 vmalloc definition -*/ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (0xE0000000) - -#endif /* __ASM_ARCH_VMALLOC_H */ -- GitLab From 0fe1309b4db2a994d0b8347cea034cf58cb4b312 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 18 Feb 2010 18:32:27 +0200 Subject: [PATCH 250/370] ARM: SAMSUNG: Add resources description for s3c24xx ts driver Without resources description driver fails during initialization. Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/devs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 986d4e5408f57..8c6de1c9968f4 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -158,9 +158,27 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) } /* Touchscreen */ + +static struct resource s3c_ts_resource[] = { + [0] = { + .start = S3C24XX_PA_ADC, + .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, + +}; + struct platform_device s3c_device_ts = { .name = "s3c2410-ts", .id = -1, + .dev.parent = &s3c_device_adc.dev, + .num_resources = ARRAY_SIZE(s3c_ts_resource), + .resource = s3c_ts_resource, }; EXPORT_SYMBOL(s3c_device_ts); -- GitLab From a0af8b3c701d254b55fc291150d5320317c0a338 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 18 Feb 2010 18:32:29 +0200 Subject: [PATCH 251/370] ARM: SAMSUNG: adc: disable/enable IRQ on suspend/resume IRQ should be disabled on suspend and re-enabled on resume. Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/plat-samsung/adc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 81caf21357219..0b5833b9ac5bc 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -412,6 +412,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) con |= S3C2410_ADCCON_STDBM; writel(con, adc->regs + S3C2410_ADCCON); + disable_irq(adc->irq); clk_disable(adc->clk); return 0; @@ -422,6 +423,7 @@ static int s3c_adc_resume(struct platform_device *pdev) struct adc_device *adc = platform_get_drvdata(pdev); clk_enable(adc->clk); + enable_irq(adc->irq); writel(adc->prescale | S3C2410_ADCCON_PRSCEN, adc->regs + S3C2410_ADCCON); -- GitLab From 5f7f6a4a0df9b43051d57fdb8ea96c083247a08f Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:12:14 +0900 Subject: [PATCH 252/370] ARM: S5P6442: Add Samsung S5P6442 CPU support This patch adds support for Samsung S5P6442 CPU. This patch also adds an entry for S5P6442 cpu in plat-s5p cpu table. Signed-off-by: Adityapratap Sharma Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/Kconfig | 24 ++++ arch/arm/mach-s5p6442/Makefile | 18 +++ arch/arm/mach-s5p6442/Makefile.boot | 2 + arch/arm/mach-s5p6442/cpu.c | 121 +++++++++++++++++ .../mach-s5p6442/include/mach/debug-macro.S | 36 +++++ .../mach-s5p6442/include/mach/entry-macro.S | 48 +++++++ arch/arm/mach-s5p6442/include/mach/gpio.h | 123 ++++++++++++++++++ arch/arm/mach-s5p6442/include/mach/hardware.h | 18 +++ arch/arm/mach-s5p6442/include/mach/map.h | 58 +++++++++ arch/arm/mach-s5p6442/include/mach/memory.h | 19 +++ arch/arm/mach-s5p6442/include/mach/system.h | 26 ++++ .../mach-s5p6442/include/mach/uncompress.h | 24 ++++ arch/arm/mach-s5p6442/init.c | 44 +++++++ arch/arm/plat-s5p/cpu.c | 10 ++ arch/arm/plat-s5p/include/plat/map-s5p.h | 1 + arch/arm/plat-s5p/include/plat/s5p6442.h | 33 +++++ .../plat-samsung/include/plat/debug-macro.S | 12 ++ 17 files changed, 617 insertions(+) create mode 100644 arch/arm/mach-s5p6442/Kconfig create mode 100644 arch/arm/mach-s5p6442/Makefile create mode 100644 arch/arm/mach-s5p6442/Makefile.boot create mode 100644 arch/arm/mach-s5p6442/cpu.c create mode 100644 arch/arm/mach-s5p6442/include/mach/debug-macro.S create mode 100644 arch/arm/mach-s5p6442/include/mach/entry-macro.S create mode 100644 arch/arm/mach-s5p6442/include/mach/gpio.h create mode 100644 arch/arm/mach-s5p6442/include/mach/hardware.h create mode 100644 arch/arm/mach-s5p6442/include/mach/map.h create mode 100644 arch/arm/mach-s5p6442/include/mach/memory.h create mode 100644 arch/arm/mach-s5p6442/include/mach/system.h create mode 100644 arch/arm/mach-s5p6442/include/mach/uncompress.h create mode 100644 arch/arm/mach-s5p6442/init.c create mode 100644 arch/arm/plat-s5p/include/plat/s5p6442.h diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig new file mode 100644 index 0000000000000..4f3f6de6a013f --- /dev/null +++ b/arch/arm/mach-s5p6442/Kconfig @@ -0,0 +1,24 @@ +# arch/arm/mach-s5p6442/Kconfig +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +# Configuration options for the S5P6442 + +if ARCH_S5P6442 + +config CPU_S5P6442 + bool + select PLAT_S5P + help + Enable S5P6442 CPU support + +config MACH_SMDK6442 + bool "SMDK6442" + select CPU_S5P6442 + help + Machine support for Samsung SMDK6442 + +endif diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile new file mode 100644 index 0000000000000..8a0f8ac656020 --- /dev/null +++ b/arch/arm/mach-s5p6442/Makefile @@ -0,0 +1,18 @@ +# arch/arm/mach-s5p6442/Makefile +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S5P6442 system + +obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o + +# machine support + diff --git a/arch/arm/mach-s5p6442/Makefile.boot b/arch/arm/mach-s5p6442/Makefile.boot new file mode 100644 index 0000000000000..ff90aa13bd674 --- /dev/null +++ b/arch/arm/mach-s5p6442/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c new file mode 100644 index 0000000000000..bc2524df89b36 --- /dev/null +++ b/arch/arm/mach-s5p6442/cpu.c @@ -0,0 +1,121 @@ +/* linux/arch/arm/mach-s5p6442/cpu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +/* Initial IO mappings */ + +static struct map_desc s5p6442_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC2, + .pfn = __phys_to_pfn(S5P6442_PA_VIC2), + .length = SZ_16K, + .type = MT_DEVICE, + } +}; + +static void s5p6442_idle(void) +{ + if (!need_resched()) + cpu_do_idle(); + + local_irq_enable(); +} + +/* s5p6442_map_io + * + * register the standard cpu IO areas +*/ + +void __init s5p6442_map_io(void) +{ + iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc)); +} + +void __init s5p6442_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5p6442_register_clocks(); + s5p6442_setup_clocks(); +} + +void __init s5p6442_init_irq(void) +{ + /* S5P6442 supports 3 VIC */ + u32 vic[3]; + + /* VIC0, VIC1, and VIC2: some interrupt reserved */ + vic[0] = 0x7fefffff; + vic[1] = 0X7f389c81; + vic[2] = 0X1bbbcfff; + + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +static struct sysdev_class s5p6442_sysclass = { + .name = "s5p6442-core", +}; + +static struct sys_device s5p6442_sysdev = { + .cls = &s5p6442_sysclass, +}; + +static int __init s5p6442_core_init(void) +{ + return sysdev_class_register(&s5p6442_sysclass); +} + +core_initcall(s5p6442_core_init); + +int __init s5p6442_init(void) +{ + printk(KERN_INFO "S5P6442: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5p6442_idle; + + return sysdev_register(&s5p6442_sysdev); +} diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S new file mode 100644 index 0000000000000..1aae691e58ef3 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include +#include + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C_PA_UART + ldrne \rx, = S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +#define fifo_full fifo_full_s5pv210 +#define fifo_level fifo_level_s5pv210 + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include diff --git a/arch/arm/mach-s5p6442/include/mach/entry-macro.S b/arch/arm/mach-s5p6442/include/mach/entry-macro.S new file mode 100644 index 0000000000000..6d574edbf1ae0 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/entry-macro.S @@ -0,0 +1,48 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Low-level IRQ helper macros for the Samsung S5P6442 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, # S5P_IRQ_OFFSET + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + @ otherwise try vic2 + addeq \tmp, \base, #(VA_VIC2 - VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-s5p6442/include/mach/gpio.h b/arch/arm/mach-s5p6442/include/mach/gpio.h new file mode 100644 index 0000000000000..b8715df2fdab8 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/gpio.h @@ -0,0 +1,123 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S5P6442_GPIO_A0_NR (8) +#define S5P6442_GPIO_A1_NR (2) +#define S5P6442_GPIO_B_NR (4) +#define S5P6442_GPIO_C0_NR (5) +#define S5P6442_GPIO_C1_NR (5) +#define S5P6442_GPIO_D0_NR (2) +#define S5P6442_GPIO_D1_NR (6) +#define S5P6442_GPIO_E0_NR (8) +#define S5P6442_GPIO_E1_NR (5) +#define S5P6442_GPIO_F0_NR (8) +#define S5P6442_GPIO_F1_NR (8) +#define S5P6442_GPIO_F2_NR (8) +#define S5P6442_GPIO_F3_NR (6) +#define S5P6442_GPIO_G0_NR (7) +#define S5P6442_GPIO_G1_NR (7) +#define S5P6442_GPIO_G2_NR (7) +#define S5P6442_GPIO_H0_NR (8) +#define S5P6442_GPIO_H1_NR (8) +#define S5P6442_GPIO_H2_NR (8) +#define S5P6442_GPIO_H3_NR (8) +#define S5P6442_GPIO_J0_NR (8) +#define S5P6442_GPIO_J1_NR (6) +#define S5P6442_GPIO_J2_NR (8) +#define S5P6442_GPIO_J3_NR (8) +#define S5P6442_GPIO_J4_NR (5) + +/* GPIO bank numbers */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ + +#define S5P6442_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + S5P6442_GPIO_A0_START = 0, + S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0), + S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1), + S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B), + S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0), + S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1), + S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0), + S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1), + S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0), + S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1), + S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0), + S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1), + S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2), + S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3), + S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0), + S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1), + S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2), + S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0), + S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1), + S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2), + S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3), + S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0), + S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1), + S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2), + S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3), +}; + +/* S5P6442 GPIO number definitions. */ +#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr)) +#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr)) +#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr)) +#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr)) +#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr)) +#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr)) +#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr)) +#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr)) +#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr)) +#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr)) +#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr)) +#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr)) +#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr)) +#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr)) +#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr)) +#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr)) +#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr)) +#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr)) +#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr)) +#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr)) +#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr)) +#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr)) +#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr)) +#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr)) +#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr)) + +/* the end of the S5P6442 specific gpios */ +#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1) +#define S3C_GPIO_END S5P6442_GPIO_END + +/* define the number of gpios we need to the one after the GPJ4() range */ +#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/hardware.h b/arch/arm/mach-s5p6442/include/mach/hardware.h new file mode 100644 index 0000000000000..8cd7b67b49d41 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h new file mode 100644 index 0000000000000..685277d792fb5 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -0,0 +1,58 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/map.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include +#include + +#define S5P6442_PA_CHIPID (0xE0000000) +#define S5P_PA_CHIPID S5P6442_PA_CHIPID + +#define S5P6442_PA_SYSCON (0xE0100000) +#define S5P_PA_SYSCON S5P6442_PA_SYSCON + +#define S5P6442_PA_GPIO (0xE0200000) +#define S5P_PA_GPIO S5P6442_PA_GPIO + +#define S5P6442_PA_VIC0 (0xE4000000) +#define S5P_PA_VIC0 S5P6442_PA_VIC0 + +#define S5P6442_PA_VIC1 (0xE4100000) +#define S5P_PA_VIC1 S5P6442_PA_VIC1 + +#define S5P6442_PA_VIC2 (0xE4200000) +#define S5P_PA_VIC2 S5P6442_PA_VIC2 + +#define S5P6442_PA_TIMER (0xEA000000) +#define S5P_PA_TIMER S5P6442_PA_TIMER + +#define S5P6442_PA_SYSTIMER (0xEA100000) + +#define S5P6442_PA_UART (0xEC000000) + +#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) +#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400) +#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800) +#define S5P_SZ_UART SZ_256 + +#define S5P6442_PA_IIC0 (0xEC100000) + +#define S5P6442_PA_SDRAM (0x20000000) +#define S5P_PA_SDRAM S5P6442_PA_SDRAM + +/* compatibiltiy defines. */ +#define S3C_PA_UART S5P6442_PA_UART +#define S3C_PA_IIC S5P6442_PA_IIC0 + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h new file mode 100644 index 0000000000000..9ddd877ba2eab --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/memory.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/memory.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x20000000) +#define CONSISTENT_DMA_SIZE SZ_8M + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h new file mode 100644 index 0000000000000..8bcd8ed0c3c37 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/system.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/system.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode, const char *cmd) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/uncompress.h b/arch/arm/mach-s5p6442/include/mach/uncompress.h new file mode 100644 index 0000000000000..5ac7cbeeb9870 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/uncompress.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5p6442/init.c b/arch/arm/mach-s5p6442/init.c new file mode 100644 index 0000000000000..1874bdb71e1d8 --- /dev/null +++ b/arch/arm/mach-s5p6442/init.c @@ -0,0 +1,44 @@ +/* linux/arch/arm/mach-s5p6442/s5p6442-init.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = { + [0] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, +}; + +/* uart registration process */ +void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + struct s3c2410_uartcfg *tcfg = cfg; + u32 ucnt; + + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + if (!tcfg->clocks) { + tcfg->clocks = s5p6442_serial_clocks; + tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks); + } + } + + s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index ee9c6b302dedf..e69992488e2e2 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -18,10 +18,12 @@ #include #include #include +#include /* table of supported CPUs */ static const char name_s5p6440[] = "S5P6440"; +static const char name_s5p6442[] = "S5P6442"; static struct cpu_table cpu_ids[] __initdata = { { @@ -32,6 +34,14 @@ static struct cpu_table cpu_ids[] __initdata = { .init_uarts = s5p6440_init_uarts, .init = s5p6440_init, .name = name_s5p6440, + }, { + .idcode = 0x36442000, + .idmask = 0xffffff00, + .map_io = s5p6442_map_io, + .init_clocks = s5p6442_init_clocks, + .init_uarts = s5p6442_init_uarts, + .init = s5p6442_init, + .name = name_s5p6442, }, }; diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index 51d9cb5a3e2bf..cc60604591dcc 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -28,5 +28,6 @@ #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) #define VA_VIC1 VA_VIC(1) +#define VA_VIC2 VA_VIC(2) #endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p6442.h b/arch/arm/plat-s5p/include/plat/s5p6442.h new file mode 100644 index 0000000000000..7b8801349c942 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6442.h @@ -0,0 +1,33 @@ +/* arch/arm/plat-s5p/include/plat/s5p6442.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p6442 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5P6442 related SoCs */ + +extern void s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5p6442_register_clocks(void); +extern void s5p6442_setup_clocks(void); + +#ifdef CONFIG_CPU_S5P6442 + +extern int s5p6442_init(void); +extern void s5p6442_init_irq(void); +extern void s5p6442_map_io(void); +extern void s5p6442_init_clocks(int xtal); + +#define s5p6442_init_uarts s5p6442_common_init_uarts + +#else +#define s5p6442_init_clocks NULL +#define s5p6442_init_uarts NULL +#define s5p6442_map_io NULL +#define s5p6442_init NULL +#endif diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S index 43ed0ec25f85a..dc6efd90e8ffa 100644 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -11,6 +11,18 @@ #include +/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */ + + .macro fifo_level_s5pv210 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + and \rd, \rd, #S5PV210_UFSTAT_TXMASK + .endm + + .macro fifo_full_s5pv210 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + tst \rd, #S5PV210_UFSTAT_TXFULL + .endm + /* The S3C2440 implementations are used by default as they are the * most widely re-used */ -- GitLab From b6f837575edc5213e00903afea240f0119ee5ec9 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 4 Feb 2010 09:42:13 +0900 Subject: [PATCH 253/370] ARM: S5P6442: Add clock support for S5P6442 This patch adds clock support for S5P6442. This patch adds the clock register definitions and the various system clocks in S5P6442. Signed-off-by: Adityapratap Sharma Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/Makefile | 2 +- arch/arm/mach-s5p6442/clock.c | 396 ++++++++++++++++++ .../arm/mach-s5p6442/include/mach/pwm-clock.h | 69 +++ .../mach-s5p6442/include/mach/regs-clock.h | 103 +++++ arch/arm/mach-s5p6442/include/mach/tick.h | 26 ++ 5 files changed, 595 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-s5p6442/clock.c create mode 100644 arch/arm/mach-s5p6442/include/mach/pwm-clock.h create mode 100644 arch/arm/mach-s5p6442/include/mach/regs-clock.h create mode 100644 arch/arm/mach-s5p6442/include/mach/tick.h diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index 8a0f8ac656020..501d2510a9a2d 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile @@ -12,7 +12,7 @@ obj- := # Core support for S5P6442 system -obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o +obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o # machine support diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c new file mode 100644 index 0000000000000..3aadbf42c1122 --- /dev/null +++ b/arch/arm/mach-s5p6442/clock.c @@ -0,0 +1,396 @@ +/* linux/arch/arm/mach-s5p6442/clock.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, +}; + +/* Possible clock sources for ARM Mux */ +static struct clk *clk_src_arm_list[] = { + [1] = &clk_mout_apll.clk, + [2] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clk_src_arm = { + .sources = clk_src_arm_list, + .nr_sources = ARRAY_SIZE(clk_src_arm_list), +}; + +static struct clksrc_clk clk_mout_arm = { + .clk = { + .name = "mout_arm", + .id = -1, + }, + .sources = &clk_src_arm, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, +}; + +static struct clk clk_dout_a2m = { + .name = "dout_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, +}; + +/* Possible clock sources for D0 Mux */ +static struct clk *clk_src_d0_list[] = { + [1] = &clk_mout_mpll.clk, + [2] = &clk_dout_a2m, +}; + +static struct clksrc_sources clk_src_d0 = { + .sources = clk_src_d0_list, + .nr_sources = ARRAY_SIZE(clk_src_d0_list), +}; + +static struct clksrc_clk clk_mout_d0 = { + .clk = { + .name = "mout_d0", + .id = -1, + }, + .sources = &clk_src_d0, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 }, +}; + +static struct clk clk_dout_apll = { + .name = "dout_apll", + .id = -1, + .parent = &clk_mout_arm.clk, +}; + +/* Possible clock sources for D0SYNC Mux */ +static struct clk *clk_src_d0sync_list[] = { + [1] = &clk_mout_d0.clk, + [2] = &clk_dout_apll, +}; + +static struct clksrc_sources clk_src_d0sync = { + .sources = clk_src_d0sync_list, + .nr_sources = ARRAY_SIZE(clk_src_d0sync_list), +}; + +static struct clksrc_clk clk_mout_d0sync = { + .clk = { + .name = "mout_d0sync", + .id = -1, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, +}; + +/* Possible clock sources for D1 Mux */ +static struct clk *clk_src_d1_list[] = { + [1] = &clk_mout_mpll.clk, + [2] = &clk_dout_a2m, +}; + +static struct clksrc_sources clk_src_d1 = { + .sources = clk_src_d1_list, + .nr_sources = ARRAY_SIZE(clk_src_d1_list), +}; + +static struct clksrc_clk clk_mout_d1 = { + .clk = { + .name = "mout_d1", + .id = -1, + }, + .sources = &clk_src_d1, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 }, +}; + +/* Possible clock sources for D1SYNC Mux */ +static struct clk *clk_src_d1sync_list[] = { + [1] = &clk_mout_d1.clk, + [2] = &clk_dout_apll, +}; + +static struct clksrc_sources clk_src_d1sync = { + .sources = clk_src_d1sync_list, + .nr_sources = ARRAY_SIZE(clk_src_d1sync_list), +}; + +static struct clksrc_clk clk_mout_d1sync = { + .clk = { + .name = "mout_d1sync", + .id = -1, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, +}; + +static struct clk clk_hclkd0 = { + .name = "hclkd0", + .id = -1, + .parent = &clk_mout_d0sync.clk, +}; + +static struct clk clk_hclkd1 = { + .name = "hclkd1", + .id = -1, + .parent = &clk_mout_d1sync.clk, +}; + +static struct clk clk_pclkd0 = { + .name = "pclkd0", + .id = -1, + .parent = &clk_hclkd0, +}; + +static struct clk clk_pclkd1 = { + .name = "pclkd1", + .id = -1, + .parent = &clk_hclkd1, +}; + +int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); +} + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "dout_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, + }, { + .clk = { + .name = "dout_apll", + .id = -1, + .parent = &clk_mout_arm.clk, + }, + .sources = &clk_src_arm, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, + }, { + .clk = { + .name = "hclkd1", + .id = -1, + .parent = &clk_mout_d1sync.clk, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "hclkd0", + .id = -1, + .parent = &clk_mout_d0sync.clk, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "pclkd0", + .id = -1, + .parent = &clk_hclkd0, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, + }, { + .clk = { + .name = "pclkd1", + .id = -1, + .parent = &clk_hclkd1, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, + } +}; + +/* Clock initialisation code */ +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_mpll, + &clk_mout_epll, + &clk_mout_arm, + &clk_mout_d0, + &clk_mout_d0sync, + &clk_mout_d1, + &clk_mout_d1sync, +}; + +void __init_or_cpufreq s5p6442_setup_clocks(void) +{ + struct clk *pclkd0_clk; + struct clk *pclkd1_clk; + + unsigned long xtal; + unsigned long arm; + unsigned long hclkd0 = 0; + unsigned long hclkd1 = 0; + unsigned long pclkd0 = 0; + unsigned long pclkd1 = 0; + + unsigned long apll; + unsigned long mpll; + unsigned long epll; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal = clk_get_rate(&clk_xtal); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); + epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); + + printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", + apll, mpll, epll); + + clk_fout_apll.rate = apll; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); + + arm = clk_get_rate(&clk_dout_apll); + hclkd0 = clk_get_rate(&clk_hclkd0); + hclkd1 = clk_get_rate(&clk_hclkd1); + + pclkd0_clk = clk_get(NULL, "pclkd0"); + BUG_ON(IS_ERR(pclkd0_clk)); + + pclkd0 = clk_get_rate(pclkd0_clk); + clk_put(pclkd0_clk); + + pclkd1_clk = clk_get(NULL, "pclkd1"); + BUG_ON(IS_ERR(pclkd1_clk)); + + pclkd1 = clk_get_rate(pclkd1_clk); + clk_put(pclkd1_clk); + + printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n", + hclkd0, hclkd1, pclkd0, pclkd1); + + /* For backward compatibility */ + clk_f.rate = arm; + clk_h.rate = hclkd1; + clk_p.rate = pclkd1; + + clk_pclkd0.rate = pclkd0; + clk_pclkd1.rate = pclkd1; +} + +static struct clk init_clocks[] = { + { + .name = "systimer", + .id = -1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<16), + }, { + .name = "uart", + .id = 0, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<17), + }, { + .name = "uart", + .id = 1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<18), + }, { + .name = "uart", + .id = 2, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<19), + }, { + .name = "timers", + .id = -1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<23), + }, +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_mout_apll.clk, + &clk_mout_mpll.clk, + &clk_mout_epll.clk, + &clk_mout_d0.clk, + &clk_mout_d0sync.clk, + &clk_mout_d1.clk, + &clk_mout_d1sync.clk, + &clk_hclkd0, + &clk_pclkd0, + &clk_hclkd1, + &clk_pclkd1, +}; + +void __init s5p6442_register_clocks(void) +{ + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + s3c_pwmclk_init(); +} diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h new file mode 100644 index 0000000000000..15e8525da0f13 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * + * S5P6442 - pwm clock and timer support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_PWMCLK_H +#define __ASM_ARCH_PWMCLK_H __FILE__ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @cfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C2410_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << (1 + tcfg1); +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 0; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div) - 1; +} + +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK + +#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h new file mode 100644 index 0000000000000..d8360b5d4ecea --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h @@ -0,0 +1,103 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include + +#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x08) +#define S5P_EPLL_LOCK S5P_CLKREG(0x10) +#define S5P_VPLL_LOCK S5P_CLKREG(0x20) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x108) +#define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_VPLL_CON S5P_CLKREG(0x120) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) +#define S5P_CLK_SRC4 S5P_CLKREG(0x210) +#define S5P_CLK_SRC5 S5P_CLKREG(0x214) +#define S5P_CLK_SRC6 S5P_CLKREG(0x218) + +#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) +#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) +#define S5P_CLK_DIV5 S5P_CLKREG(0x314) +#define S5P_CLK_DIV6 S5P_CLKREG(0x318) + +#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) + +/* CLK_OUT */ +#define S5P_CLK_OUT_SHIFT (12) +#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT) +#define S5P_CLK_OUT S5P_CLKREG(0x500) + +#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) +#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) + +#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) +#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) + +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) + +/* Register Bit definition */ +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_APLL_SHIFT (0) +#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) +#define S5P_CLKDIV0_A2M_SHIFT (4) +#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) +#define S5P_CLKDIV0_D0CLK_SHIFT (16) +#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT) +#define S5P_CLKDIV0_P0CLK_SHIFT (20) +#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT) +#define S5P_CLKDIV0_D1CLK_SHIFT (24) +#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT) +#define S5P_CLKDIV0_P1CLK_SHIFT (28) +#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT) + +/* Clock MUX status Registers */ +#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0) +#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT) +#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4) +#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8) +#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12) +#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16) +#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20) +#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24) +#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT) +#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24) +#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT) +#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28) +#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h new file mode 100644 index 0000000000000..e1d4cabf82970 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/tick.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/tick.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/mach-s3c6400/include/mach/tick.h + * + * S5P6442 - Timer tick support definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_TICK_H */ -- GitLab From d9f18a981bd0a724c87d04db1d61d91261a2feb4 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:17:20 +0900 Subject: [PATCH 254/370] ARM: S5P6442: Add IRQ support This patch adds IRQ support for S5P6442. This patch adds interrupt register definitions, IRQ definitions for various interrupt sources and new VIC base for VIC2 in plat-s5p common irq code. Signed-off-by: Adityapratap Sharma Signed-off-by: Atul Dahiya Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/include/mach/irqs.h | 86 +++++++++++++++++++ arch/arm/mach-s5p6442/include/mach/regs-irq.h | 19 ++++ arch/arm/plat-s5p/include/plat/irqs.h | 3 + arch/arm/plat-s5p/irq.c | 2 + 4 files changed, 110 insertions(+) create mode 100644 arch/arm/mach-s5p6442/include/mach/irqs.h create mode 100644 arch/arm/mach-s5p6442/include/mach/regs-irq.h diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h new file mode 100644 index 0000000000000..da665809f6e44 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/irqs.h @@ -0,0 +1,86 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - IRQ definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#include + +/* VIC0 */ +#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) +#define IRQ_BATF S5P_IRQ_VIC0(17) +#define IRQ_MDMA S5P_IRQ_VIC0(18) +#define IRQ_PDMA S5P_IRQ_VIC0(19) +#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) +#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) +#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) +#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) +#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) +#define IRQ_SYSTIMER S5P_IRQ_VIC0(26) +#define IRQ_WDT S5P_IRQ_VIC0(27) +#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) +#define IRQ_RTC_TIC S5P_IRQ_VIC0(29) +#define IRQ_GPIOINT S5P_IRQ_VIC0(30) + +/* VIC1 */ +#define IRQ_nPMUIRQ S5P_IRQ_VIC1(0) +#define IRQ_ONENAND S5P_IRQ_VIC1(7) +#define IRQ_UART0 S5P_IRQ_VIC1(10) +#define IRQ_UART1 S5P_IRQ_VIC1(11) +#define IRQ_UART2 S5P_IRQ_VIC1(12) +#define IRQ_SPI0 S5P_IRQ_VIC1(15) +#define IRQ_IIC S5P_IRQ_VIC1(19) +#define IRQ_IIC1 S5P_IRQ_VIC1(20) +#define IRQ_IIC2 S5P_IRQ_VIC1(21) +#define IRQ_OTG S5P_IRQ_VIC1(24) +#define IRQ_MSM S5P_IRQ_VIC1(25) +#define IRQ_HSMMC0 S5P_IRQ_VIC1(26) +#define IRQ_HSMMC1 S5P_IRQ_VIC1(27) +#define IRQ_HSMMC2 S5P_IRQ_VIC1(28) +#define IRQ_COMMRX S5P_IRQ_VIC1(29) +#define IRQ_COMMTX S5P_IRQ_VIC1(30) + +/* VIC2 */ +#define IRQ_LCD0 S5P_IRQ_VIC2(0) +#define IRQ_LCD1 S5P_IRQ_VIC2(1) +#define IRQ_LCD2 S5P_IRQ_VIC2(2) +#define IRQ_LCD3 S5P_IRQ_VIC2(3) +#define IRQ_ROTATOR S5P_IRQ_VIC2(4) +#define IRQ_FIMC0 S5P_IRQ_VIC2(5) +#define IRQ_FIMC1 S5P_IRQ_VIC2(6) +#define IRQ_FIMC2 S5P_IRQ_VIC2(7) +#define IRQ_JPEG S5P_IRQ_VIC2(8) +#define IRQ_3D S5P_IRQ_VIC2(10) +#define IRQ_Mixer S5P_IRQ_VIC2(11) +#define IRQ_MFC S5P_IRQ_VIC2(14) +#define IRQ_TVENC S5P_IRQ_VIC2(15) +#define IRQ_I2S0 S5P_IRQ_VIC2(16) +#define IRQ_I2S1 S5P_IRQ_VIC2(17) +#define IRQ_RP S5P_IRQ_VIC2(19) +#define IRQ_PCM0 S5P_IRQ_VIC2(20) +#define IRQ_PCM1 S5P_IRQ_VIC2(21) +#define IRQ_ADC S5P_IRQ_VIC2(23) +#define IRQ_PENDN S5P_IRQ_VIC2(24) +#define IRQ_KEYPAD S5P_IRQ_VIC2(25) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_VIC_END S5P_IRQ_VIC2(31) + +#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) + +#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \ + (S5P_IRQ_EINT_BASE + (x)-16)) +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT(31) + 1) + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/regs-irq.h b/arch/arm/mach-s5p6442/include/mach/regs-irq.h new file mode 100644 index 0000000000000..73782b52a83ba --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/regs-irq.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include +#include + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 101038d499440..9daad19ccd0da 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -28,11 +28,13 @@ #define S5P_VIC0_BASE S5P_IRQ(0) #define S5P_VIC1_BASE S5P_IRQ(32) +#define S5P_VIC2_BASE S5P_IRQ(64) #define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) #define IRQ_VIC0_BASE S5P_VIC0_BASE #define IRQ_VIC1_BASE S5P_VIC1_BASE +#define IRQ_VIC2_BASE S5P_VIC2_BASE /* UART interrupts, each UART has 4 intterupts per channel so * use the space between the ISA and S3C main interrupts. Note, these @@ -73,6 +75,7 @@ #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) +#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index 11535a5f534e6..25e1eb6de59e6 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -45,11 +45,13 @@ static struct s3c_uart_irq uart_irqs[] = { .base_irq = IRQ_S5P_UART_BASE2, .parent_irq = IRQ_UART2, }, +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 [3] = { .regs = S5P_VA_UART3, .base_irq = IRQ_S5P_UART_BASE3, .parent_irq = IRQ_UART3, }, +#endif }; void __init s5p_init_irq(u32 *vic, u32 num_vic) -- GitLab From d13de2ab8a7afe2d915be4c4758fe25825204226 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 24 Feb 2010 01:43:27 +0000 Subject: [PATCH 255/370] ARM: S5P6442: Add files missing from original commit The removal of plat-s3c has left these missing from the initial commit, so add copies from elsewhere. Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/include/mach/io.h | 17 ++++++++++++++ arch/arm/mach-s5p6442/include/mach/timex.h | 24 ++++++++++++++++++++ arch/arm/mach-s5p6442/include/mach/vmalloc.h | 17 ++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-s5p6442/include/mach/io.h create mode 100644 arch/arm/mach-s5p6442/include/mach/timex.h create mode 100644 arch/arm/mach-s5p6442/include/mach/vmalloc.h diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h new file mode 100644 index 0000000000000..5d2195ad0b674 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/io.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5p6442/include/mach/io.h + * + * Copyright 2008-2010 Ben Dooks + * + * Default IO routines for S5P6442 + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s5p6442/include/mach/timex.h b/arch/arm/mach-s5p6442/include/mach/timex.h new file mode 100644 index 0000000000000..ff8f2fcadeb77 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s5p6442/include/mach/timex.h + * + * Copyright (c) 2003-2010 Simtec Electronics + * Ben Dooks + * + * S5P6442 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h new file mode 100644 index 0000000000000..be3333688c20d --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5p6442/include/mach/vmalloc.h + * + * Copyright 2010 Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S5P6442 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ -- GitLab From 550db7f155c9e51288fbe114fbb33d7a044d8a75 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:19:26 +0900 Subject: [PATCH 256/370] ARM: S5P6442: Update Kconfig and Makefiles Updates arch/arm Kconfig and Makefile for building the S5P6442 support. Also modifies the plat-s5p Kconfig file to include the support for plat-s5p for S5P6442. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 12 +++++++++++- arch/arm/Makefile | 1 + arch/arm/plat-s5p/Kconfig | 2 +- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fd4882e61dd51..ac5f74b0f03ec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,14 @@ config ARCH_S5P6440 help Samsung S5P6440 CPU based systems +config ARCH_S5P6442 + bool "Samsung S5P6442" + select CPU_V6 + select GENERIC_GPIO + select HAVE_CLK + help + Samsung S5P6442 CPU based systems + config ARCH_S5PC1XX bool "Samsung S5PC1XX" select GENERIC_GPIO @@ -816,6 +824,8 @@ endif source "arch/arm/mach-s5p6440/Kconfig" +source "arch/arm/mach-s5p6442/Kconfig" + source "arch/arm/plat-stmp3xxx/Kconfig" if ARCH_S5PC1XX @@ -1096,7 +1106,7 @@ source kernel/Kconfig.preempt config HZ int default 128 if ARCH_L7200 - default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 + default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default 100 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 13c5c2be31ade..fc8cc4ba0fbd7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -162,6 +162,7 @@ machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S5P6440) := s5p6440 +machine-$(CONFIG_ARCH_S5P6442) := s5p6442 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index e5d1305764a38..7cf7f5e2c5fdf 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -7,7 +7,7 @@ config PLAT_S5P bool - depends on ARCH_S5P6440 + depends on (ARCH_S5P6440 || ARCH_S5P6442) default y select ARM_VIC select NO_IOPORT -- GitLab From 461859db1f367200602d81c9352e2477a6187814 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:21:16 +0900 Subject: [PATCH 257/370] ARM: S5P6442: Add SMDK6442 board support file This patch adds SMDK6442 board support file. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/Makefile | 1 + arch/arm/mach-s5p6442/mach-smdk6442.c | 91 +++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm/mach-s5p6442/mach-smdk6442.c diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index 501d2510a9a2d..dde39a6ce6bcc 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o # machine support +obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c new file mode 100644 index 0000000000000..0d63371ce07cf --- /dev/null +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -0,0 +1,91 @@ +/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, +}; + +static struct platform_device *smdk6442_devices[] __initdata = { +}; + +static void __init smdk6442_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs)); +} + +static void __init smdk6442_machine_init(void) +{ + platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); +} + +MACHINE_START(SMDK6442, "SMDK6442") + /* Maintainer: Kukjin Kim */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5p6442_init_irq, + .map_io = smdk6442_map_io, + .init_machine = smdk6442_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END -- GitLab From 7f7035f21c10d83994e045a98c0906781dba02d3 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:22:47 +0900 Subject: [PATCH 258/370] ARM: S5P6442: Add S5P6442 configuration file This patch adds S5P6442 default configuration file. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/configs/s5p6442_defconfig | 883 +++++++++++++++++++++++++++++ 1 file changed, 883 insertions(+) create mode 100644 arch/arm/configs/s5p6442_defconfig diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig new file mode 100644 index 0000000000000..74e20bfc04874 --- /dev/null +++ b/arch/arm/configs/s5p6442_defconfig @@ -0,0 +1,883 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc4 +# Mon Jan 25 08:50:28 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +CONFIG_ARCH_S5P6442=y +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SAMSUNG=y +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIOLIB_4BIT=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +# CONFIG_S3C_ADC is not set + +# +# Power management +# +CONFIG_PLAT_S3C=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +CONFIG_PLAT_S5P=y +CONFIG_CPU_S5P6442=y +CONFIG_MACH_SMDK6442=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=3 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S5PV210=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set +CONFIG_DEBUG_S3C_UART=1 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y -- GitLab From 03843a1294073c19783b43f60f3a455dd0672685 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:23:40 +0900 Subject: [PATCH 259/370] ARM: S5P6442: Add serial port support This patch adds UART serial port support for S5P6442. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5p/dev-uart.c | 2 ++ drivers/serial/Kconfig | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c index 23c75316d4917..a89331ef4ae17 100644 --- a/arch/arm/plat-s5p/dev-uart.c +++ b/arch/arm/plat-s5p/dev-uart.c @@ -95,6 +95,7 @@ static struct resource s5p_uart2_resource[] = { }; static struct resource s5p_uart3_resource[] = { +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 [0] = { .start = S5P_PA_UART3, .end = S5P_PA_UART3 + S5P_SZ_UART, @@ -115,6 +116,7 @@ static struct resource s5p_uart3_resource[] = { .end = IRQ_S5P_UART_ERR3, .flags = IORESOURCE_IRQ, }, +#endif }; struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b2157c36566dc..86590e9a92f5a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -551,7 +551,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" - depends on SERIAL_SAMSUNG && CPU_S5PV210 + depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) select SERIAL_SAMSUNG_UARTS_4 default y help -- GitLab From 1088f336ccc73feaaff2f95eec6fb5b6e7e94337 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 24 Feb 2010 01:46:10 +0000 Subject: [PATCH 260/370] ARM: SAMSUNG: Fix UART number for S5P6442 The recent changes in the UART code mean that we need to ensure that the 4 UART case is only selected if S5PV210 is being compiled. Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 86590e9a92f5a..c53e13a260845 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -552,7 +552,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) - select SERIAL_SAMSUNG_UARTS_4 + select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210 default y help Serial port support for Samsung's S5P Family of SoC's -- GitLab From c2b2c645dbeecb3433021ea71c6bbed70a1e9db6 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 12 Feb 2010 10:38:50 +0000 Subject: [PATCH 261/370] ARM: SMDK2443: Enable AC97 device Add AC97 controller to platform devices and initialize the AC97 gpios. Signed-off-by: Jassi Brar Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/mach-smdk2443.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index d65afdee59c5e..e2e362bda9b7e 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -106,6 +106,9 @@ static struct platform_device *smdk2443_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_hsmmc0, +#ifdef CONFIG_SND_SOC_SMDK2443_WM9710 + &s3c_device_ac97, +#endif }; static void __init smdk2443_map_io(void) @@ -118,6 +121,11 @@ static void __init smdk2443_map_io(void) static void __init smdk2443_machine_init(void) { s3c_i2c0_set_platdata(NULL); + +#ifdef CONFIG_SND_SOC_SMDK2443_WM9710 + s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0); +#endif + platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); smdk_machine_init(); } -- GitLab From bc449e53121681d16fbefb9c14d28b0638ae33db Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 12 Feb 2010 10:38:52 +0000 Subject: [PATCH 262/370] ARM: S3C2443: GPIO: Correct AC97 pin defines GPIO_E-[5,9] pin functionality was defined incorrectly. The patch corrects and adds missing pins. Signed-off-by: Jassi Brar Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index ebc85c6dadbf3..fd672f330bf2a 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -406,31 +406,31 @@ #define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) +#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) #define S3C2410_GPE6_SDCMD (0x02 << 12) #define S3C2443_GPE6_SD1_CMD (0x02 << 12) -#define S3C2443_GPE6_AC_BITCLK (0x03 << 12) +#define S3C2443_GPE6_AC_SDI (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) -#define S3C2443_GPE7_AC_SDI (0x03 << 14) +#define S3C2443_GPE7_AC_SDO (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) -#define S3C2443_GPE8_AC_SDO (0x03 << 16) +#define S3C2443_GPE8_AC_SYNC (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) -#define S3C2443_GPE9_AC_SYNC (0x03 << 18) +#define S3C2443_GPE9_AC_nRESET (0x03 << 18) #define S3C2400_GPE9_nXDACK1 (0x02 << 18) #define S3C2400_GPE9_nXBACK (0x03 << 18) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) -#define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) -- GitLab From 60f9101a8881797fecd89450b8a8d17a440e6281 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 17 Feb 2010 18:19:29 +0000 Subject: [PATCH 263/370] ARM: SMDK6410: Add initial support for WM1192-EV1 PMIC board The Wolfson Microelectronics 1192-EV1 is a plug in module for the SMDK6410 providing power using a WM8312 PMIC. This patch provides initial hookup sufficient to initialise the board, though not all features are fully described yet. As part of this supplies for the system that are provided as a single supply by one of the currently merged PMIC boards are factored out so they can be reused between different regulators. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c64xx/Kconfig | 15 ++ arch/arm/mach-s3c64xx/include/mach/irqs.h | 2 + arch/arm/mach-s3c64xx/mach-smdk6410.c | 256 +++++++++++++++++----- 3 files changed, 218 insertions(+), 55 deletions(-) diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 44cdd80ea107b..959df3840de5a 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -144,6 +144,21 @@ config SMDK6410_WM1190_EV1 detected at runtime so the the resulting kernel can be used with or without the 1190-EV1 fitted. +config SMDK6410_WM1192_EV1 + bool "Support Wolfson Microelectronics 1192-EV1 PMIC card" + depends on MACH_SMDK6410 + select REGULATOR + select REGULATOR_WM831X + select S3C24XX_GPIO_EXTRA64 + select MFD_WM831X + help + The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC + daughtercard for the Samsung SMDK6410 reference platform. + Enabling this option will build support for this module into + the kernel. The presence of the daughtercard will be + detected at runtime so the the resulting kernel can be used + with or without the 1192-EV1 fitted. + config MACH_NCP bool "NCP" select CPU_S3C6410 diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 44bb3e491b5c9..e9ab4ac0b9a82 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -200,6 +200,8 @@ #ifdef CONFIG_SMDK6410_WM1190_EV1 #define IRQ_BOARD_NR 64 +#elif defined(CONFIG_SMDK6410_WM1192_EV1) +#define IRQ_BOARD_NR 64 #else #define IRQ_BOARD_NR 16 #endif diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index fdf8f7539a120..cf2327f0bf77d 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -32,6 +32,10 @@ #include #endif +#ifdef CONFIG_SMDK6410_WM1192_EV1 +#include +#endif + #include