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Unverified Commit 55de0f31 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO



CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent b1a1ad4b
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