arm64: dts: ti: k3-am64-main: Make CPSW traffic coherent

commit d0b81e87e17cf25f60a6e54467fa191b10f40565 from
git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git



Set ASEL to 15 so that CPSW DMA channel participates in Coherency and
thus avoid need to cache maintenance for SKBs. This improves
bidirectional TCP performance by up to 100Mbps (on 1G link)

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Xulin Sun <xulin.sun@windriver.com>