ASoC: cs42l42: Add PLL ratio table values

Add 4.8Mhz 9.6Mhz and 19.2MHz SCLK values
for MCLK 12MHz and 12.288MHz requested by Intel.

Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230524125236.57149-1-vitalyr@opensource.cirrus.com


Signed-off-by: Mark Brown <broonie@kernel.org>