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Commit 8ba595b6 authored by Rick Chen's avatar Rick Chen Committed by Andes
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riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL



The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: default avatarRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
parent 43a0832b
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